+ CPURV_HAS_ZICOND

compiler/riscv/nrvutil.pas

@@ -81,8 +81,8 @@ implementation
             attr_arch:=attr_arch+'_d2p2';
           if CPURV_HAS_COMPACT in cpu_capabilities[current_settings.cputype] then
             attr_arch:=attr_arch+'_c2p0';
-{          if CPURV_HAS_ICOND in cpu_capabilities[current_settings.cputype] then
-            attr_arch:=attr_arch+'_zicond1p0'; }
+          if CPURV_HAS_ZICOND in cpu_capabilities[current_settings.cputype] then
+            attr_arch:=attr_arch+'_zicond1p0';
           if CPURV_HAS_CSR_INSTRUCTIONS in cpu_capabilities[current_settings.cputype] then
             attr_arch:=attr_arch+'_zicrs2p0';
           if CPURV_HAS_FETCH_FENCE in cpu_capabilities[current_settings.cputype] then

compiler/riscv32/cpuinfo.pas

@@ -224,7 +224,8 @@ Const
        CPURV_HAS_ZFINX,
        CPURV_HAS_ZDINX,
        CPURV_HAS_ZHINX,
-       CPURV_HAS_ZHINXMIN
+       CPURV_HAS_ZHINXMIN,
+       CPURV_HAS_ZICOND
       );
 
  const

compiler/riscv64/cpuinfo.pas

@@ -142,7 +142,8 @@ Const
        CPURV_HAS_ZFINX,
        CPURV_HAS_ZDINX,
        CPURV_HAS_ZHINX,
-       CPURV_HAS_ZHINXMIN
+       CPURV_HAS_ZHINXMIN,
+       CPURV_HAS_ZICOND
       );
 
  const