* Risc-V 32 has also a GC variant

compiler/riscv/agrvgas.pas

@@ -233,8 +233,8 @@ unit agrvgas;
       const
         arch_str: array[boolean,tcputype] of string[10] = (
 {$ifdef RISCV32}
-          ('','rv32imac','rv32ima','rv32im','rv32i','rv32e','rv32imc','rv32ec'),
-          ('','rv32imafdc','rv32imafd','rv32imfd','rv32ifd','rv32efd','rv32imcfd','rv32ecfd')
+          ('','rv32imac','rv32ima','rv32im','rv32i','rv32e','rv32imc','rv32ec','rv32gc'),
+          ('','rv32imafdc','rv32imafd','rv32imfd','rv32ifd','rv32efd','rv32imcfd','rv32ecfd','rv32gc')
 {$endif RISCV32}
 {$ifdef RISCV64}
           ('','rv64imac','rv64ima','rv64im','rv64i','rv64gc'),

compiler/riscv32/cpuinfo.pas

@@ -41,7 +41,8 @@ Type
        cpu_rv32i,
        cpu_rv32e,
        cpu_rv32imc,
-       cpu_rv32ec
+       cpu_rv32ec,
+       cpu_rv32gc
       );
 
    tfputype =
@@ -172,7 +173,8 @@ Const
      'RV32I',
      'RV32E',
      'RV32IMC',
-     'RV32EC'
+     'RV32EC',
+     'RV32GC'
    );
 
    fputypestr : array[tfputype] of string[8] = (         
@@ -214,7 +216,8 @@ Const
        { cpu_rv32i     } [],
        { cpu_rv32e     } [CPURV_HAS_16REGISTERS],
        { cpu_rv32imc   } [CPURV_HAS_MUL,CPURV_HAS_COMPACT],
-       { cpu_rv32ec    } [CPURV_HAS_16REGISTERS,CPURV_HAS_COMPACT]
+       { cpu_rv32ec    } [CPURV_HAS_16REGISTERS,CPURV_HAS_COMPACT],
+       { cpu_rv32gc    } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT]
      );
 
 Implementation