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@@ -26,7 +26,7 @@ unit nwasminl;
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interface
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uses
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- node,ncginl;
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+ node,ncginl,cpubase;
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type
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@@ -52,6 +52,7 @@ interface
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procedure second_unreachable;
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procedure second_throw_fpcexception;
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procedure second_atomic_fence;
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+ procedure second_atomic_rmw_x_y(op: TAsmOp);
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protected
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function first_sqr_real: tnode; override;
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public
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@@ -66,7 +67,6 @@ implementation
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uses
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ninl,ncal,compinnr,
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- cpubase,
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aasmbase,aasmdata,aasmcpu,
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cgbase,cgutils,
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hlcgobj,hlcgcpu,
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@@ -404,6 +404,35 @@ implementation
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end;
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+ procedure twasminlinenode.second_atomic_rmw_x_y(op: TAsmOp);
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+ begin
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+ secondpass(tcallparanode(tcallparanode(left).right).left);
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+ hlcg.location_force_reg(current_asmdata.CurrAsmList,
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+ tcallparanode(tcallparanode(left).right).left.location,
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+ tcallparanode(tcallparanode(left).right).left.resultdef,
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+ tcallparanode(tcallparanode(left).right).left.resultdef,false);
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+ thlcgwasm(hlcg).a_load_reg_stack(current_asmdata.CurrAsmList,
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+ tcallparanode(tcallparanode(left).right).left.resultdef,
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+ tcallparanode(tcallparanode(left).right).left.location.register);
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+
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+ secondpass(tcallparanode(left).left);
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+ hlcg.location_force_reg(current_asmdata.CurrAsmList,
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+ tcallparanode(left).left.location,
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+ tcallparanode(left).left.resultdef,
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+ tcallparanode(left).left.resultdef,false);
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+ thlcgwasm(hlcg).a_load_reg_stack(current_asmdata.CurrAsmList,
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+ tcallparanode(left).left.resultdef,
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+ tcallparanode(left).left.location.register);
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+
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+ current_asmdata.CurrAsmList.Concat(taicpu.op_const(op,0));
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+ thlcgwasm(hlcg).decstack(current_asmdata.CurrAsmList,1);
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+
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+ location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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+ location.register:=hlcg.getregisterfordef(current_asmdata.CurrAsmList,resultdef);
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+ thlcgwasm(hlcg).a_load_stack_loc(current_asmdata.CurrAsmList,resultdef,location);
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+ end;
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+
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+
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function twasminlinenode.first_sqr_real: tnode;
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begin
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expectloc:=LOC_FPUREGISTER;
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@@ -450,6 +479,57 @@ implementation
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CheckParameters(0);
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resultdef:=voidtype;
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end;
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+
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+ in_wasm32_i32_atomic_rmw8_add_u,
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+ in_wasm32_i32_atomic_rmw16_add_u,
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+ in_wasm32_i32_atomic_rmw_add,
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+ in_wasm32_i32_atomic_rmw8_sub_u,
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+ in_wasm32_i32_atomic_rmw16_sub_u,
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+ in_wasm32_i32_atomic_rmw_sub,
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+ in_wasm32_i32_atomic_rmw8_and_u,
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+ in_wasm32_i32_atomic_rmw16_and_u,
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+ in_wasm32_i32_atomic_rmw_and,
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+ in_wasm32_i32_atomic_rmw8_or_u,
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+ in_wasm32_i32_atomic_rmw16_or_u,
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+ in_wasm32_i32_atomic_rmw_or,
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+ in_wasm32_i32_atomic_rmw8_xor_u,
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+ in_wasm32_i32_atomic_rmw16_xor_u,
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+ in_wasm32_i32_atomic_rmw_xor,
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+ in_wasm32_i32_atomic_rmw8_xchg_u,
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+ in_wasm32_i32_atomic_rmw16_xchg_u,
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+ in_wasm32_i32_atomic_rmw_xchg:
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+ begin
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+ CheckParameters(2);
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+ resultdef:=u32inttype;
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+ end;
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+ in_wasm32_i64_atomic_rmw8_add_u,
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+ in_wasm32_i64_atomic_rmw16_add_u,
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+ in_wasm32_i64_atomic_rmw32_add_u,
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+ in_wasm32_i64_atomic_rmw_add,
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+ in_wasm32_i64_atomic_rmw8_sub_u,
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+ in_wasm32_i64_atomic_rmw16_sub_u,
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+ in_wasm32_i64_atomic_rmw32_sub_u,
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+ in_wasm32_i64_atomic_rmw_sub,
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+ in_wasm32_i64_atomic_rmw8_and_u,
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+ in_wasm32_i64_atomic_rmw16_and_u,
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+ in_wasm32_i64_atomic_rmw32_and_u,
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+ in_wasm32_i64_atomic_rmw_and,
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+ in_wasm32_i64_atomic_rmw8_or_u,
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+ in_wasm32_i64_atomic_rmw16_or_u,
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+ in_wasm32_i64_atomic_rmw32_or_u,
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+ in_wasm32_i64_atomic_rmw_or,
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+ in_wasm32_i64_atomic_rmw8_xor_u,
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+ in_wasm32_i64_atomic_rmw16_xor_u,
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+ in_wasm32_i64_atomic_rmw32_xor_u,
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+ in_wasm32_i64_atomic_rmw_xor,
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+ in_wasm32_i64_atomic_rmw8_xchg_u,
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+ in_wasm32_i64_atomic_rmw16_xchg_u,
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+ in_wasm32_i64_atomic_rmw32_xchg_u,
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+ in_wasm32_i64_atomic_rmw_xchg:
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+ begin
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+ CheckParameters(2);
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+ resultdef:=u64inttype;
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+ end;
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else
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Result:=inherited pass_typecheck_cpu;
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end;
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@@ -469,6 +549,49 @@ implementation
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in_wasm32_throw_fpcexception,
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in_wasm32_atomic_fence:
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expectloc:=LOC_VOID;
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+ in_wasm32_i32_atomic_rmw8_add_u,
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+ in_wasm32_i32_atomic_rmw16_add_u,
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+ in_wasm32_i32_atomic_rmw_add,
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+ in_wasm32_i64_atomic_rmw8_add_u,
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+ in_wasm32_i64_atomic_rmw16_add_u,
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+ in_wasm32_i64_atomic_rmw32_add_u,
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+ in_wasm32_i64_atomic_rmw_add,
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+ in_wasm32_i32_atomic_rmw8_sub_u,
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+ in_wasm32_i32_atomic_rmw16_sub_u,
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+ in_wasm32_i32_atomic_rmw_sub,
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+ in_wasm32_i64_atomic_rmw8_sub_u,
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+ in_wasm32_i64_atomic_rmw16_sub_u,
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+ in_wasm32_i64_atomic_rmw32_sub_u,
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+ in_wasm32_i64_atomic_rmw_sub,
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+ in_wasm32_i32_atomic_rmw8_and_u,
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+ in_wasm32_i32_atomic_rmw16_and_u,
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+ in_wasm32_i32_atomic_rmw_and,
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+ in_wasm32_i64_atomic_rmw8_and_u,
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+ in_wasm32_i64_atomic_rmw16_and_u,
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+ in_wasm32_i64_atomic_rmw32_and_u,
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+ in_wasm32_i64_atomic_rmw_and,
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+ in_wasm32_i32_atomic_rmw8_or_u,
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+ in_wasm32_i32_atomic_rmw16_or_u,
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+ in_wasm32_i32_atomic_rmw_or,
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+ in_wasm32_i64_atomic_rmw8_or_u,
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+ in_wasm32_i64_atomic_rmw16_or_u,
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+ in_wasm32_i64_atomic_rmw32_or_u,
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+ in_wasm32_i64_atomic_rmw_or,
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+ in_wasm32_i32_atomic_rmw8_xor_u,
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+ in_wasm32_i32_atomic_rmw16_xor_u,
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+ in_wasm32_i32_atomic_rmw_xor,
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+ in_wasm32_i64_atomic_rmw8_xor_u,
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+ in_wasm32_i64_atomic_rmw16_xor_u,
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+ in_wasm32_i64_atomic_rmw32_xor_u,
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+ in_wasm32_i64_atomic_rmw_xor,
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+ in_wasm32_i32_atomic_rmw8_xchg_u,
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+ in_wasm32_i32_atomic_rmw16_xchg_u,
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+ in_wasm32_i32_atomic_rmw_xchg,
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+ in_wasm32_i64_atomic_rmw8_xchg_u,
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+ in_wasm32_i64_atomic_rmw16_xchg_u,
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+ in_wasm32_i64_atomic_rmw32_xchg_u,
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+ in_wasm32_i64_atomic_rmw_xchg:
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+ expectloc:=LOC_REGISTER;
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else
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Result:=inherited first_cpu;
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end;
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@@ -492,6 +615,90 @@ implementation
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second_throw_fpcexception;
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in_wasm32_atomic_fence:
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second_atomic_fence;
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+ in_wasm32_i32_atomic_rmw8_add_u:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw8_add_u);
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+ in_wasm32_i32_atomic_rmw16_add_u:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw16_add_u);
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+ in_wasm32_i32_atomic_rmw_add:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw_add);
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+ in_wasm32_i64_atomic_rmw8_add_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw8_add_u);
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+ in_wasm32_i64_atomic_rmw16_add_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw16_add_u);
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+ in_wasm32_i64_atomic_rmw32_add_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw32_add_u);
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+ in_wasm32_i64_atomic_rmw_add:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw_add);
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+ in_wasm32_i32_atomic_rmw8_sub_u:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw8_sub_u);
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+ in_wasm32_i32_atomic_rmw16_sub_u:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw16_sub_u);
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+ in_wasm32_i32_atomic_rmw_sub:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw_sub);
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+ in_wasm32_i64_atomic_rmw8_sub_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw8_sub_u);
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+ in_wasm32_i64_atomic_rmw16_sub_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw16_sub_u);
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+ in_wasm32_i64_atomic_rmw32_sub_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw32_sub_u);
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+ in_wasm32_i64_atomic_rmw_sub:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw_sub);
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+ in_wasm32_i32_atomic_rmw8_and_u:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw8_and_u);
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+ in_wasm32_i32_atomic_rmw16_and_u:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw16_and_u);
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+ in_wasm32_i32_atomic_rmw_and:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw_and);
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+ in_wasm32_i64_atomic_rmw8_and_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw8_and_u);
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+ in_wasm32_i64_atomic_rmw16_and_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw16_and_u);
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+ in_wasm32_i64_atomic_rmw32_and_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw32_and_u);
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+ in_wasm32_i64_atomic_rmw_and:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw_and);
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+ in_wasm32_i32_atomic_rmw8_or_u:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw8_or_u);
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+ in_wasm32_i32_atomic_rmw16_or_u:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw16_or_u);
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+ in_wasm32_i32_atomic_rmw_or:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw_or);
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+ in_wasm32_i64_atomic_rmw8_or_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw8_or_u);
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+ in_wasm32_i64_atomic_rmw16_or_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw16_or_u);
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+ in_wasm32_i64_atomic_rmw32_or_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw32_or_u);
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+ in_wasm32_i64_atomic_rmw_or:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw_or);
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+ in_wasm32_i32_atomic_rmw8_xor_u:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw8_xor_u);
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+ in_wasm32_i32_atomic_rmw16_xor_u:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw16_xor_u);
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+ in_wasm32_i32_atomic_rmw_xor:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw_xor);
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+ in_wasm32_i64_atomic_rmw8_xor_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw8_xor_u);
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+ in_wasm32_i64_atomic_rmw16_xor_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw16_xor_u);
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+ in_wasm32_i64_atomic_rmw32_xor_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw32_xor_u);
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+ in_wasm32_i64_atomic_rmw_xor:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw_xor);
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+ in_wasm32_i32_atomic_rmw8_xchg_u:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw8_xchg_u);
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+ in_wasm32_i32_atomic_rmw16_xchg_u:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw16_xchg_u);
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+ in_wasm32_i32_atomic_rmw_xchg:
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+ second_atomic_rmw_x_y(a_i32_atomic_rmw_xchg);
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+ in_wasm32_i64_atomic_rmw8_xchg_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw8_xchg_u);
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+ in_wasm32_i64_atomic_rmw16_xchg_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw16_xchg_u);
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+ in_wasm32_i64_atomic_rmw32_xchg_u:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw32_xchg_u);
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+ in_wasm32_i64_atomic_rmw_xchg:
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+ second_atomic_rmw_x_y(a_i64_atomic_rmw_xchg);
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else
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inherited pass_generate_code_cpu;
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end;
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