* add memory barrier prototypes + implementation for i386 and sparc + use lwsync for powerpc64

git-svn-id: trunk@8240 -

compiler/sparc/cpugas.pas

@@ -208,7 +208,11 @@ implementation
            id     : as_gas;
            idtxt  : 'AS';
            asmbin : 'as';
+{$ifdef FPC_SPARC_V8_ONLY}
            asmcmd : '-o $OBJ $ASM';
+{$else}
+           asmcmd : '-Av9 -o $OBJ $ASM';
+{$endif}
            supported_target : system_any;
            flags : [af_allowdirect,af_needar,af_smartlink_sections];
            labelprefix : '.L';

compiler/sparc/opcode.inc

@@ -69,5 +69,7 @@ A_tst,
 { Internal instructions }
 A_FMOVd,
 A_FABSd,
-A_FABSq
-
+A_FABSq,
+{ Memory barrier instructions }
+A_STBAR,
+A_MEMBAR

compiler/sparc/strinst.inc

@@ -66,4 +66,7 @@
           'tst',
           { internal instructions }
           'fmovd',
-          'fabsd','fabsq'
+          'fabsd','fabsq',
+          { memory barrier instructions }
+          'stbar',
+          'membar'

rtl/i386/i386.inc

@@ -1334,3 +1334,32 @@ asm
 end;
 
 {$endif darwin}
+
+{$ifndef FPC_SYSTEM_HAS_MEM_BARRIER}
+{$define FPC_SYSTEM_HAS_MEM_BARRIER}
+
+procedure ReadBarrier;assembler;nostackframe;{$ifdef SYSTEMINLINE}inline;{$endif}
+asm
+  lock
+  addl $0,0(%esp)
+  { alternative: lfence on SSE capable CPUs }
+end;
+
+procedure ReadDependencyBarrier;{$ifdef SYSTEMINLINE}inline;{$endif}
+begin
+  { reads imply barrier on earlier reads depended on }
+end;
+
+procedure ReadWriteBarrier;assembler;nostackframe;{$ifdef SYSTEMINLINE}inline;{$endif}
+asm
+  lock
+  addl $0,0(%esp)
+  { alternative: mfence on SSE capable CPUs }
+end;
+
+procedure WriteBarrier;assembler;nostackframe;{$ifdef SYSTEMINLINE}inline;{$endif}
+asm
+  { no write reordering on intel CPUs (yet) }
+end;
+
+{$endif}

rtl/inc/generic.inc

@@ -1580,6 +1580,10 @@ procedure ReadBarrier;{$ifdef SYSTEMINLINE}inline;{$endif}
 begin
 end;
 
+procedure ReadDependencyBarrier;{$ifdef SYSTEMINLINE}inline;{$endif}
+begin
+end;
+
 procedure ReadWriteBarrier;{$ifdef SYSTEMINLINE}inline;{$endif}
 begin
 end;

rtl/inc/systemh.inc

@@ -432,6 +432,10 @@ procedure MoveChar0(const buf1;var buf2;len:SizeInt);
 function  IndexChar0(const buf;len:SizeInt;b:char):SizeInt;
 function  CompareChar0(const buf1,buf2;len:SizeInt):SizeInt;{$ifdef INLINEGENERICS}inline;{$endif}
 procedure prefetch(const mem);[internproc:fpc_in_prefetch_var];
+procedure ReadBarrier;{$ifdef INLINEGENERICS}inline;{$endif}
+procedure ReadDependencyBarrier;{$ifdef INLINEGENERICS}inline;{$endif}
+procedure ReadWriteBarrier;{$ifdef INLINEGENERICS}inline;{$endif}
+procedure WriteBarrier;{$ifdef INLINEGENERICS}inline;{$endif}
 
 {$ifdef INTERNALMOVEFILLCHAR}
 var

rtl/powerpc/powerpc.inc

@@ -1262,6 +1262,11 @@ asm
   sync
 end;
 
+procedure ReadDependencyBarrier;{$ifdef SYSTEMINLINE}inline;{$endif}
+begin
+  { reads imply barrier on earlier reads depended on }
+end;
+
 procedure ReadWriteBarrier;assembler;nostackframe;{$ifdef SYSTEMINLINE}inline;{$endif}
 asm
   sync

rtl/powerpc64/powerpc64.inc

@@ -842,7 +842,12 @@ end;
 
 procedure ReadBarrier;assembler;nostackframe;{$ifdef SYSTEMINLINE}inline;{$endif}
 asm
-  sync
+  lwsync
+end;
+
+procedure ReadDependencyBarrier;{$ifdef SYSTEMINLINE}inline;{$endif}
+asm
+  { reads imply barrier on earlier reads depended on }
 end;
 
 procedure ReadWriteBarrier;assembler;nostackframe;{$ifdef SYSTEMINLINE}inline;{$endif}

rtl/sparc/sparc.inc

@@ -507,3 +507,43 @@ asm
   or %g1,%lo(fpc_system_lock), %g1
   stb %g0,[%g1]
 end;
+
+{$ifndef FPC_SYSTEM_HAS_MEM_BARRIER}
+{$define FPC_SYSTEM_HAS_MEM_BARRIER}
+
+const
+  LoadLoad   = $01;
+  StoreLoad  = $02;
+  LoadStore  = $04;
+  StoreStore = $08;
+  LookAside  = $10;
+  MemIssue   = $20;
+  Sync       = $40;
+
+procedure ReadBarrier;assembler;nostackframe;{$ifdef SYSTEMINLINE}inline;{$endif}
+asm
+  ba,pt .L1
+  membar LoadLoad
+.L1:
+end;
+
+procedure ReadDependencyBarrier;{$ifdef SYSTEMINLINE}inline;{$endif}
+begin
+  { reads imply barrier on earlier reads depended on }
+end;
+
+procedure ReadWriteBarrier;assembler;nostackframe;{$ifdef SYSTEMINLINE}inline;{$endif}
+asm
+  ba,pt .L1
+  membar LoadLoad + LoadStore + StoreLoad + StoreStore
+.L1:
+end;
+
+procedure WriteBarrier;assembler;nostackframe;{$ifdef SYSTEMINLINE}inline;{$endif}
+asm
+  ba,pt .L1
+  stbar
+.L1:
+end;
+
+{$endif}

rtl/x86_64/x86_64.inc

@@ -617,3 +617,28 @@ begin
   softfloat_exception_flags:=0;
   softfloat_exception_mask:=float_flag_underflow or float_flag_inexact or float_flag_denormal;
 end;
+
+{$ifndef FPC_SYSTEM_HAS_MEM_BARRIER}
+{$define FPC_SYSTEM_HAS_MEM_BARRIER}
+
+procedure ReadBarrier;assembler;nostackframe;{$ifdef SYSTEMINLINE}inline;{$endif}
+asm
+  lfence
+end;
+
+procedure ReadDependencyBarrier;{$ifdef SYSTEMINLINE}inline;{$endif}
+asm
+  { reads imply barrier on earlier reads depended on }
+end;
+
+procedure ReadWriteBarrier;assembler;nostackframe;{$ifdef SYSTEMINLINE}inline;{$endif}
+asm
+  mfence
+end;
+
+procedure WriteBarrier;assembler;nostackframe;{$ifdef SYSTEMINLINE}inline;{$endif}
+asm
+  { no write reordering on intel CPUs (yet) }
+end;
+
+{$endif}