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@@ -9602,7 +9602,11 @@ unit aoptx86;
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function TX86AsmOptimizer.OptPass1Movx(var p : tai) : boolean;
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var
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hp1,hp2: tai;
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- reg_and_hp1_is_instr: Boolean;
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+ reg_and_hp1_is_instr, RegUsed, AndTest: Boolean;
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+ NewSize: TOpSize;
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+ NewRegSize: TSubRegister;
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+ Limit: TCgInt;
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+ SwapOper: POper;
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begin
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result:=false;
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reg_and_hp1_is_instr:=(taicpu(p).oper[1]^.typ = top_reg) and
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@@ -9678,8 +9682,11 @@ unit aoptx86;
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DebugMsg(SPeepholeOptimization + 'var3',p);
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RemoveCurrentP(p, hp1);
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RemoveInstruction(hp2);
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- end
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- else if reg_and_hp1_is_instr and
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+ Result := True;
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+ Exit;
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+ end;
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+
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+ if reg_and_hp1_is_instr and
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(taicpu(hp1).opcode = A_MOV) and
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MatchOpType(taicpu(hp1),top_reg,top_reg) and
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(MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[0]^)
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@@ -9716,9 +9723,12 @@ unit aoptx86;
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{$endif x86_64}
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taicpu(p).loadreg(1,taicpu(hp1).oper[1]^.reg);
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RemoveInstruction(hp1);
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+ Result := True;
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+ Exit;
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end;
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- end
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- else if reg_and_hp1_is_instr and
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+ end;
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+
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+ if reg_and_hp1_is_instr and
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((taicpu(hp1).opcode=A_MOV) or
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(taicpu(hp1).opcode=A_ADD) or
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(taicpu(hp1).opcode=A_SUB) or
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@@ -9727,56 +9737,225 @@ unit aoptx86;
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(taicpu(hp1).opcode=A_XOR) or
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(taicpu(hp1).opcode=A_AND)
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) and
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- MatchOpType(taicpu(hp1),top_reg,top_reg) and
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- (((taicpu(p).opsize in [S_BW,S_BL,S_WL{$ifdef x86_64},S_BQ,S_WQ,S_LQ{$endif x86_64}]) and
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- (taicpu(hp1).opsize=S_B)) or
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- ((taicpu(p).opsize in [S_WL{$ifdef x86_64},S_WQ,S_LQ{$endif x86_64}]) and
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- (taicpu(hp1).opsize=S_W))
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+ (taicpu(hp1).oper[1]^.typ = top_reg) then
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+ begin
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+ AndTest := (taicpu(hp1).opcode=A_AND) and
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+ GetNextInstruction(hp1, hp2) and
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+ (hp2.typ = ait_instruction) and
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+ (
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+ (
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+ (taicpu(hp2).opcode=A_TEST) and
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+ MatchOperand(taicpu(hp2).oper[0]^, taicpu(hp1).oper[1]^.reg) and
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+ MatchOperand(taicpu(hp2).oper[1]^, taicpu(hp1).oper[1]^.reg)
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+ ) or
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+ (
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+ (taicpu(hp2).opcode=A_CMP) and
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+ MatchOperand(taicpu(hp2).oper[0]^, 0) and
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+ MatchOperand(taicpu(hp2).oper[1]^, taicpu(hp1).oper[1]^.reg)
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+ )
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+ );
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+
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+ if (taicpu(hp1).oper[0]^.typ = top_reg) and
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+ (((taicpu(p).opsize in [S_BW,S_BL,S_WL{$ifdef x86_64},S_BQ,S_WQ,S_LQ{$endif x86_64}]) and
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+ (taicpu(hp1).opsize=S_B)) or
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+ ((taicpu(p).opsize in [S_WL{$ifdef x86_64},S_WQ,S_LQ{$endif x86_64}]) and
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+ (taicpu(hp1).opsize=S_W))
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{$ifdef x86_64}
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- or ((taicpu(p).opsize=S_LQ) and
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- (taicpu(hp1).opsize=S_L))
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+ or ((taicpu(p).opsize=S_LQ) and
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+ (taicpu(hp1).opsize=S_L))
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{$endif x86_64}
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- ) and
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- SuperRegistersEqual(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[0]^.reg) then
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- begin
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- { change
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- movx %reg1,%reg2
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- mov %reg2,%reg3
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- dealloc %reg2
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+ ) and
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+ SuperRegistersEqual(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[0]^.reg) then
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+ begin
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+ { change
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+ movx %reg1,%reg2
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+ op %reg2,%reg3
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+ dealloc %reg2
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- into
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+ into
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- mov %reg1,%reg3
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+ op %reg1,%reg3
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- if the second mov accesses only the bits stored in reg1
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- }
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- TransferUsedRegs(TmpUsedRegs);
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- UpdateUsedRegs(TmpUsedRegs, tai(p.next));
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- if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs)) then
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- begin
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- DebugMsg(SPeepholeOptimization + 'MovxOp2Op',p);
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- if taicpu(p).oper[0]^.typ=top_reg then
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+ if the second op accesses only the bits stored in reg1
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+ }
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+ TransferUsedRegs(TmpUsedRegs);
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+ UpdateUsedRegs(TmpUsedRegs, tai(p.next));
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+ if AndTest then
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begin
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- case taicpu(hp1).opsize of
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- S_B:
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- taicpu(hp1).loadreg(0,newreg(R_INTREGISTER,getsupreg(taicpu(p).oper[0]^.reg),R_SUBL));
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- S_W:
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- taicpu(hp1).loadreg(0,newreg(R_INTREGISTER,getsupreg(taicpu(p).oper[0]^.reg),R_SUBW));
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- S_L:
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- taicpu(hp1).loadreg(0,newreg(R_INTREGISTER,getsupreg(taicpu(p).oper[0]^.reg),R_SUBD));
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- else
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- Internalerror(2020102301);
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+ UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
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+ RegUsed := RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp2,TmpUsedRegs);
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+ end
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+ else
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+ RegUsed := RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs);
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+
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+ if not RegUsed then
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'MovxOp2Op',p);
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+ if taicpu(p).oper[0]^.typ=top_reg then
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+ begin
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+ case taicpu(hp1).opsize of
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+ S_B:
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+ taicpu(hp1).loadreg(0,newreg(R_INTREGISTER,getsupreg(taicpu(p).oper[0]^.reg),R_SUBL));
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+ S_W:
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+ taicpu(hp1).loadreg(0,newreg(R_INTREGISTER,getsupreg(taicpu(p).oper[0]^.reg),R_SUBW));
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+ S_L:
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+ taicpu(hp1).loadreg(0,newreg(R_INTREGISTER,getsupreg(taicpu(p).oper[0]^.reg),R_SUBD));
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+ else
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+ Internalerror(2020102301);
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+ end;
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+ AllocRegBetween(taicpu(hp1).oper[0]^.reg,p,hp1,UsedRegs);
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+ end
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+ else
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+ taicpu(hp1).loadref(0,taicpu(p).oper[0]^.ref^);
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+ RemoveCurrentP(p);
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+ if AndTest then
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+ RemoveInstruction(hp2);
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+ result:=true;
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+ exit;
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+ end;
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+ end
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+ else if (taicpu(p).oper[1]^.reg = taicpu(hp1).oper[1]^.reg) and
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+ (
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+ { Bitwise operations only }
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+ (taicpu(hp1).opcode=A_AND) or
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+ (taicpu(hp1).opcode=A_TEST) or
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+ (
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+ (taicpu(hp1).oper[0]^.typ = top_const) and
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+ (
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+ (taicpu(hp1).opcode=A_OR) or
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+ (taicpu(hp1).opcode=A_XOR)
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+ )
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+ )
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+ ) and
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+ (
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+ (taicpu(hp1).oper[0]^.typ = top_const) or
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+ MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[1]^.reg) or
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+ not RegInOp(taicpu(p).oper[1]^.reg, taicpu(hp1).oper[0]^)
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+ ) then
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+ begin
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+ { change
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+ movx %reg2,%reg2
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+ op const,%reg2
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+
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+ into
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+ op const,%reg2 (smaller version)
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+ movx %reg2,%reg2
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+
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+ also change
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+ movx %reg1,%reg2
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+ and/test (oper),%reg2
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+ dealloc %reg2
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+
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+ into
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+
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+ and/test (oper),%reg1
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+ }
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+ case taicpu(p).opsize of
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+ S_BW, S_BL{$ifdef x86_64}, S_BQ{$endif x86_64}:
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+ begin
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+ NewSize := S_B;
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+ NewRegSize := R_SUBL;
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+ Limit := $FF;
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end;
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- AllocRegBetween(taicpu(hp1).oper[0]^.reg,p,hp1,UsedRegs);
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+ S_WL{$ifdef x86_64}, S_WQ{$endif x86_64}:
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+ begin
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+ NewSize := S_W;
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+ NewRegSize := R_SUBW;
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+ Limit := $FFFF;
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+ end;
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+{$ifdef x86_64}
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+ S_LQ:
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+ begin
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+ NewSize := S_L;
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+ NewRegSize := R_SUBD;
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+ Limit := $FFFFFFFF;
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+ end;
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+{$endif x86_64}
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+ else
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+ Internalerror(2021120302);
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+ end;
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+
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+ TransferUsedRegs(TmpUsedRegs);
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+ UpdateUsedRegs(TmpUsedRegs, tai(p.next));
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+ if AndTest then
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+ begin
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+ UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
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+ RegUsed := RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp2,TmpUsedRegs);
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end
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else
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- taicpu(hp1).loadref(0,taicpu(p).oper[0]^.ref^);
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- RemoveCurrentP(p);
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- result:=true;
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- exit;
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+ RegUsed := RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs);
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+
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+ if
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+ (
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+ (taicpu(p).opcode = A_MOVZX) and
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+ (
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+ (taicpu(hp1).opcode=A_AND) or
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+ (taicpu(hp1).opcode=A_TEST)
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+ ) and
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+ not (
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+ { If both are references, then the final instruction will have
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+ both operands as references, which is not allowed }
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+ (taicpu(p).oper[0]^.typ = top_ref) and
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+ (taicpu(hp1).oper[0]^.typ = top_ref)
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+ ) and
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+ not RegUsed
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+ ) or
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+ (
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+ (
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+ SuperRegistersEqual(taicpu(p).oper[0]^.reg, taicpu(p).oper[1]^.reg) or
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+ not RegUsed
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+ ) and
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+ (taicpu(p).oper[0]^.typ = top_reg) and
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+ SuperRegistersEqual(taicpu(p).oper[0]^.reg, taicpu(p).oper[1]^.reg) and
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+ (taicpu(hp1).oper[0]^.typ = top_const) and
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+ ((taicpu(hp1).oper[0]^.val and Limit) = taicpu(hp1).oper[0]^.val)
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+ ) then
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'MovxOp2Op 2',p);
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+
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+ if AndTest and not RegUsed then
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+ taicpu(hp1).opcode := A_TEST;
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+
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+ taicpu(hp1).opsize := NewSize;
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+
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+ case taicpu(hp1).oper[0]^.typ of
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+ top_reg:
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+ setsubreg(taicpu(hp1).oper[0]^.reg, NewRegSize);
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+ top_const:
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+ { For the AND/TEST case }
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+ taicpu(hp1).oper[0]^.val := taicpu(hp1).oper[0]^.val and Limit;
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+ else
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+ ;
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+ end;
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+
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+ taicpu(hp1).loadoper(1, taicpu(p).oper[0]^);
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+ if (taicpu(hp1).opcode = A_TEST) and (taicpu(hp1).oper[0]^.typ = top_ref) then
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+ begin
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+ { For TEST, make sure the reference is the second operand }
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+ SwapOper := taicpu(hp1).oper[0];
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+ taicpu(hp1).oper[0] := taicpu(hp1).oper[1];
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+ taicpu(hp1).oper[1] := SwapOper;
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+ end;
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+
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+ if AndTest then
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+ RemoveInstruction(hp2);
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+
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+ if RegUsed then
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+ begin
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+ AsmL.Remove(p);
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+ AsmL.InsertAfter(p, hp1);
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+ p := hp1;
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+ end
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+ else
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+ RemoveCurrentP(p, hp1);
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+
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+ result:=true;
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+ exit;
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+ end;
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end;
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- end
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- else if reg_and_hp1_is_instr and
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+ end;
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+
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+ if reg_and_hp1_is_instr and
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(taicpu(p).oper[0]^.typ = top_reg) and
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(
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(taicpu(hp1).opcode = A_SHL) or (taicpu(hp1).opcode = A_SAL)
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@@ -9853,8 +10032,183 @@ unit aoptx86;
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DebugMsg(SPeepholeOptimization + 'MovsSar2SarMovs', hp1);
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Result := True;
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- end
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- else if taicpu(p).opcode=A_MOVZX then
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+ end;
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+
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+ if reg_and_hp1_is_instr and
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+ (taicpu(p).oper[0]^.typ = top_reg) and
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+ SuperRegistersEqual(taicpu(p).oper[0]^.reg, taicpu(p).oper[1]^.reg) and
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+ (
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+ (taicpu(hp1).opcode = taicpu(p).opcode)
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+ or ((taicpu(p).opcode = A_MOVZX) and ((taicpu(hp1).opcode = A_MOVSX){$ifdef x86_64} or (taicpu(hp1).opcode = A_MOVSXD){$endif x86_64}))
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+{$ifdef x86_64}
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+ or ((taicpu(p).opcode = A_MOVSX) and (taicpu(hp1).opcode = A_MOVSXD))
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+{$endif x86_64}
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+ ) then
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+ begin
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+ if MatchOpType(taicpu(hp1), top_reg, top_reg) and
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+ (taicpu(p).oper[1]^.reg = taicpu(hp1).oper[0]^.reg) and
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+ SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, taicpu(hp1).oper[1]^.reg) then
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+ begin
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+ {
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+ For example:
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+ movzbw %al,%ax
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+ movzwl %ax,%eax
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+
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+ Compress into:
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+ movzbl %al,%eax
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+ }
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+ RegUsed := False;
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+ case taicpu(p).opsize of
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+ S_BW:
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+ case taicpu(hp1).opsize of
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+ S_WL:
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+ begin
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+ taicpu(p).opsize := S_BL;
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+ RegUsed := True;
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+ end;
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+{$ifdef x86_64}
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+ S_WQ:
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+ begin
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+ if taicpu(p).opcode = A_MOVZX then
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+ taicpu(p).opsize := S_BL
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+ else
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+ taicpu(p).opsize := S_BQ;
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+ RegUsed := True;
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+ end;
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+{$endif x86_64}
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+ else
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+ ;
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+ end;
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+{$ifdef x86_64}
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+ S_BL:
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+ case taicpu(hp1).opsize of
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+ S_LQ:
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+ begin
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+ if taicpu(p).opcode = A_MOVZX then
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+ taicpu(p).opsize := S_BL
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+ else
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+ taicpu(p).opsize := S_BQ;
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+ RegUsed := True;
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+ end;
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+ else
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+ ;
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+ end;
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+ S_WL:
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+ case taicpu(hp1).opsize of
|
|
|
+ S_LQ:
|
|
|
+ begin
|
|
|
+ if taicpu(p).opcode = A_MOVZX then
|
|
|
+ taicpu(p).opsize := S_WL
|
|
|
+ else
|
|
|
+ taicpu(p).opsize := S_WQ;
|
|
|
+ RegUsed := True;
|
|
|
+ end;
|
|
|
+ else
|
|
|
+ ;
|
|
|
+ end;
|
|
|
+{$endif x86_64}
|
|
|
+ else
|
|
|
+ ;
|
|
|
+ end;
|
|
|
+
|
|
|
+ if RegUsed then
|
|
|
+ begin
|
|
|
+ DebugMsg(SPeepholeOptimization + 'MovxMovx2Movx', p);
|
|
|
+ taicpu(p).oper[1]^.reg := taicpu(hp1).oper[1]^.reg;
|
|
|
+ RemoveInstruction(hp1);
|
|
|
+ Result := True;
|
|
|
+ Exit;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+ if (taicpu(hp1).opsize = taicpu(p).opsize) and
|
|
|
+ not RegInInstruction(taicpu(p).oper[1]^.reg, hp1) and
|
|
|
+ GetNextInstruction(hp1, hp2) and
|
|
|
+ MatchInstruction(hp2, [A_AND, A_OR, A_XOR, A_TEST], []) and
|
|
|
+ (
|
|
|
+ ((taicpu(hp2).opsize = S_W) and (taicpu(p).opsize = S_BW)) or
|
|
|
+ ((taicpu(hp2).opsize = S_L) and (taicpu(p).opsize in [S_BL, S_WL]))
|
|
|
+{$ifdef x86_64}
|
|
|
+ or ((taicpu(hp2).opsize = S_Q) and (taicpu(p).opsize in [S_BL, S_BQ, S_WL, S_WQ, S_LQ]))
|
|
|
+{$endif x86_64}
|
|
|
+ ) and
|
|
|
+ MatchOpType(taicpu(hp2), top_reg, top_reg) and
|
|
|
+ (
|
|
|
+ (
|
|
|
+ (taicpu(hp2).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) and
|
|
|
+ (taicpu(hp2).oper[1]^.reg = taicpu(p).oper[1]^.reg)
|
|
|
+ ) or
|
|
|
+ (
|
|
|
+ { Only allow the operands in reverse order for TEST instructions }
|
|
|
+ (taicpu(hp2).opcode = A_TEST) and
|
|
|
+ (taicpu(hp2).oper[0]^.reg = taicpu(p).oper[1]^.reg) and
|
|
|
+ (taicpu(hp2).oper[1]^.reg = taicpu(hp1).oper[1]^.reg)
|
|
|
+ )
|
|
|
+ ) then
|
|
|
+ begin
|
|
|
+ {
|
|
|
+ For example:
|
|
|
+ movzbl %al,%eax
|
|
|
+ movzbl (ref),%edx
|
|
|
+ andl %edx,%eax
|
|
|
+ (%edx deallocated)
|
|
|
+
|
|
|
+ Change to:
|
|
|
+ andb (ref),%al
|
|
|
+ movzbl %al,%eax
|
|
|
+
|
|
|
+ Rules are:
|
|
|
+ - First two instructions have the same opcode and opsize
|
|
|
+ - First instruction's operands are the same super-register
|
|
|
+ - Second instruction operates on a different register
|
|
|
+ - Third instruction is AND, OR, XOR or TEST
|
|
|
+ - Third instruction's operands are the destination registers of the first two instructions
|
|
|
+ - Third instruction writes to the destination register of the first instruction (except with TEST)
|
|
|
+ - Second instruction's destination register is deallocated afterwards
|
|
|
+ }
|
|
|
+ TransferUsedRegs(TmpUsedRegs);
|
|
|
+ UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
|
|
|
+ UpdateUsedRegs(TmpUsedRegs, tai(hp1.Next));
|
|
|
+ if not RegUsedAfterInstruction(taicpu(hp1).oper[1]^.reg, hp2, TmpUsedRegs) then
|
|
|
+ begin
|
|
|
+ case taicpu(p).opsize of
|
|
|
+ S_BW, S_BL{$ifdef x86_64}, S_BQ{$endif x86_64}:
|
|
|
+ NewSize := S_B;
|
|
|
+ S_WL{$ifdef x86_64}, S_WQ{$endif x86_64}:
|
|
|
+ NewSize := S_W;
|
|
|
+{$ifdef x86_64}
|
|
|
+ S_LQ:
|
|
|
+ NewSize := S_L;
|
|
|
+{$endif x86_64}
|
|
|
+ else
|
|
|
+ InternalError(2021120301);
|
|
|
+ end;
|
|
|
+
|
|
|
+ taicpu(hp2).loadoper(0, taicpu(hp1).oper[0]^);
|
|
|
+ taicpu(hp2).loadreg(1, taicpu(p).oper[0]^.reg);
|
|
|
+ taicpu(hp2).opsize := NewSize;
|
|
|
+
|
|
|
+ RemoveInstruction(hp1);
|
|
|
+
|
|
|
+ { With TEST, it's best to keep the MOVX instruction at the top }
|
|
|
+ if (taicpu(hp2).opcode <> A_TEST) then
|
|
|
+ begin
|
|
|
+ DebugMsg(SPeepholeOptimization + 'MovxMovxTest2MovxTest', p);
|
|
|
+ asml.Remove(p);
|
|
|
+ { If the third instruction uses the flags, the MOVX instruction won't modify then }
|
|
|
+ asml.InsertAfter(p, hp2);
|
|
|
+ p := hp2;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ DebugMsg(SPeepholeOptimization + 'MovxMovxOp2OpMovx', p);
|
|
|
+
|
|
|
+ Result := True;
|
|
|
+ Exit;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+ if taicpu(p).opcode=A_MOVZX then
|
|
|
begin
|
|
|
{ removes superfluous And's after movzx's }
|
|
|
if reg_and_hp1_is_instr and
|
|
|
@@ -10103,6 +10457,7 @@ unit aoptx86;
|
|
|
hp1, hp2 : tai;
|
|
|
MaskLength : Cardinal;
|
|
|
MaskedBits : TCgInt;
|
|
|
+ ActiveReg : TRegister;
|
|
|
begin
|
|
|
Result:=false;
|
|
|
|
|
|
@@ -10316,6 +10671,119 @@ unit aoptx86;
|
|
|
else
|
|
|
;
|
|
|
end;
|
|
|
+ end
|
|
|
+ else if MatchOperand(taicpu(p).oper[0]^, taicpu(p).oper[1]^.reg) and
|
|
|
+ not RegInUsedRegs(NR_DEFAULTFLAGS, UsedRegs) then
|
|
|
+ begin
|
|
|
+{$ifdef x86_64}
|
|
|
+ if (taicpu(p).opsize = S_Q) then
|
|
|
+ begin
|
|
|
+ { Never necessary }
|
|
|
+ DebugMsg(SPeepholeOptimization + 'Andq2Nop', p);
|
|
|
+ RemoveCurrentP(p, hp1);
|
|
|
+ Result := True;
|
|
|
+ Exit;
|
|
|
+ end;
|
|
|
+{$endif x86_64}
|
|
|
+ { Forward check to determine necessity of and %reg,%reg }
|
|
|
+ TransferUsedRegs(TmpUsedRegs);
|
|
|
+ UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
|
|
|
+
|
|
|
+ { Saves on a bunch of dereferences }
|
|
|
+ ActiveReg := taicpu(p).oper[1]^.reg;
|
|
|
+
|
|
|
+ case taicpu(hp1).opcode of
|
|
|
+ A_MOV, A_MOVZX, A_MOVSX{$ifdef x86_64}, A_MOVSXD{$endif x86_64}:
|
|
|
+
|
|
|
+ if (
|
|
|
+ (taicpu(hp1).oper[0]^.typ <> top_ref) or
|
|
|
+ not RegInRef(ActiveReg, taicpu(hp1).oper[0]^.ref^)
|
|
|
+ ) and
|
|
|
+ (
|
|
|
+ (taicpu(hp1).opcode <> A_MOV) or
|
|
|
+ (taicpu(hp1).oper[1]^.typ <> top_ref) or
|
|
|
+ not RegInRef(ActiveReg, taicpu(hp1).oper[1]^.ref^)
|
|
|
+ ) and
|
|
|
+ not (
|
|
|
+ { If mov %reg,%reg is present, remove that instruction instead in OptPass1MOV }
|
|
|
+ (taicpu(hp1).opcode = A_MOV) and
|
|
|
+ MatchOperand(taicpu(hp1).oper[0]^, ActiveReg) and
|
|
|
+ MatchOperand(taicpu(hp1).oper[1]^, ActiveReg)
|
|
|
+ ) and
|
|
|
+ (
|
|
|
+ (
|
|
|
+ (taicpu(hp1).oper[0]^.typ = top_reg) and
|
|
|
+ (taicpu(hp1).oper[0]^.reg = ActiveReg) and
|
|
|
+ SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, taicpu(hp1).oper[1]^.reg)
|
|
|
+ ) or
|
|
|
+ (
|
|
|
+{$ifdef x86_64}
|
|
|
+ (
|
|
|
+ { If we read from the register, make sure it's not dependent on the upper 32 bits }
|
|
|
+ (taicpu(hp1).oper[0]^.typ <> top_reg) or
|
|
|
+ not SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, ActiveReg) or
|
|
|
+ (GetSubReg(taicpu(hp1).oper[0]^.reg) <> R_SUBQ)
|
|
|
+ ) and
|
|
|
+{$endif x86_64}
|
|
|
+ not RegUsedAfterInstruction(ActiveReg, hp1, TmpUsedRegs)
|
|
|
+ )
|
|
|
+ ) then
|
|
|
+ begin
|
|
|
+ DebugMsg(SPeepholeOptimization + 'AndMovx2Movx', p);
|
|
|
+ RemoveCurrentP(p, hp1);
|
|
|
+ Result := True;
|
|
|
+ Exit;
|
|
|
+ end;
|
|
|
+ A_ADD,
|
|
|
+ A_AND,
|
|
|
+ A_BSF,
|
|
|
+ A_BSR,
|
|
|
+ A_BTC,
|
|
|
+ A_BTR,
|
|
|
+ A_BTS,
|
|
|
+ A_OR,
|
|
|
+ A_SUB,
|
|
|
+ A_XOR:
|
|
|
+ { Register is written to, so this will clear the upper 32 bits (2-operand instructions) }
|
|
|
+ if (
|
|
|
+ (taicpu(hp1).oper[0]^.typ <> top_ref) or
|
|
|
+ not RegInRef(ActiveReg, taicpu(hp1).oper[0]^.ref^)
|
|
|
+ ) and
|
|
|
+ MatchOperand(taicpu(hp1).oper[1]^, ActiveReg) then
|
|
|
+ begin
|
|
|
+ DebugMsg(SPeepholeOptimization + 'AndOp2Op 2', p);
|
|
|
+ RemoveCurrentP(p, hp1);
|
|
|
+ Result := True;
|
|
|
+ Exit;
|
|
|
+ end;
|
|
|
+ A_CMP,
|
|
|
+ A_TEST:
|
|
|
+ if (
|
|
|
+ (taicpu(hp1).oper[0]^.typ <> top_ref) or
|
|
|
+ not RegInRef(ActiveReg, taicpu(hp1).oper[0]^.ref^)
|
|
|
+ ) and
|
|
|
+ MatchOperand(taicpu(hp1).oper[1]^, ActiveReg) and
|
|
|
+ not RegUsedAfterInstruction(ActiveReg, hp1, TmpUsedRegs) then
|
|
|
+ begin
|
|
|
+ DebugMsg(SPeepholeOptimization + 'AND; CMP/TEST -> CMP/TEST', p);
|
|
|
+ RemoveCurrentP(p, hp1);
|
|
|
+ Result := True;
|
|
|
+ Exit;
|
|
|
+ end;
|
|
|
+ A_BSWAP,
|
|
|
+ A_NEG,
|
|
|
+ A_NOT:
|
|
|
+ { Register is written to, so this will clear the upper 32 bits (1-operand instructions) }
|
|
|
+ if MatchOperand(taicpu(hp1).oper[0]^, ActiveReg) then
|
|
|
+ begin
|
|
|
+ DebugMsg(SPeepholeOptimization + 'AndOp2Op 1', p);
|
|
|
+ RemoveCurrentP(p, hp1);
|
|
|
+ Result := True;
|
|
|
+ Exit;
|
|
|
+ end;
|
|
|
+ else
|
|
|
+ ;
|
|
|
+ end;
|
|
|
end;
|
|
|
|
|
|
if (taicpu(hp1).is_jmp) and
|
J. Gareth "Curious Kit" Moreton