* fixed dword -> qword/int64 type cast on x86_64

compiler/x86/cgx86.pas

@@ -601,9 +601,28 @@ unit cgx86;
 {$ifdef x86_64}
         { zero extensions to 64 bit on the x86_64 are simply done by writting to the lower 32 bit
           which clears the upper 64 bit too, so it could be that s is S_L while the reg is
-          64 bit (FK) }
+          64 bit (FK) 
+          but we shouldn't allow the reg. allocator to remove the instruction in this case (FK)
+        }
         if s in [S_BL,S_WL,S_L] then
-          reg2:=makeregsize(list,reg2,OS_32);
+          begin          
+            reg2:=makeregsize(list,reg2,OS_32);
+            list.concat(taicpu.op_reg_reg(op,s,reg1,reg2));
+            if fromsize<tosize then
+              begin
+                case s of
+                  S_BL:
+                    list.concat(taicpu.op_const_reg(A_AND,S_L,$ff,reg2));
+                  S_WL:
+                    list.concat(taicpu.op_const_reg(A_AND,S_L,$ffff,reg2));
+                  S_L:
+                    list.concat(taicpu.op_const_reg(A_AND,S_L,$ffffffff,reg2));
+                  else
+                    internalerror(200502051);
+                end;                
+              end;
+          end
+        else
 {$endif x86_64}
         if (reg1<>reg2) then
           begin
@@ -1740,7 +1759,10 @@ unit cgx86;
 end.
 {
   $Log$
-  Revision 1.142  2005-01-25 18:48:15  peter
+  Revision 1.143  2005-02-05 18:08:48  florian
+    * fixed dword -> qword/int64 type cast on x86_64
+
+  Revision 1.142  2005/01/25 18:48:15  peter
     * tf_pic_uses_got added
 
   Revision 1.141  2005/01/08 16:00:55  florian