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+{
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+Register definitions and utility code for stellaris
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+Preliminary startup code
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+Geoffrey Barton 2010 08 01 [email protected]
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+based on stm32f103 created by Jeppe Johansen 2009 - [email protected]
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+}
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+unit stellaris;
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+
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+{$goto on}
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+
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+interface
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+
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+type
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+ TBitvector32 = bitpacked array[0..31] of 0..1;
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+
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+{$PACKRECORDS 4}
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+const
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+PeripheralBase = $40000000;
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+PPBbase = $E0000fff;
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+APBbase = PeripheralBase;
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+AHBbase = PeripheralBase+$54000;
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+portAoffset=APBbase+$4000;
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+portBoffset=APBbase+$5000;
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+portCoffset=APBbase+$6000;
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+portDoffset=APBbase+$7000;
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+portEoffset=APBbase+$24000;
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+portFoffset=APBbase+$25000;
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+portGoffset=APBbase+$26000;
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+portHoffset=APBbase+$27000;
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+portJoffset=APBbase+$3d000;
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+sysconoffset=APBbase+$fe000;
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+
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+
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+type
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+TgpioPort=record
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+ data:array[0..255] of dword;dir,is,ibe,iev,im,ris,mis,icr,
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+ afsel:dword;dummy1:array[0..54] of dword;dr2r,dr4r,dr8r,odr,pur,pdr,slr,den,lock,cr,amsel,pctl:dword;
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+ end;
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+Tsyscon=record
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+ did0,did1,dc0,res0c,dc1,dc2,dc3,dc4,dc5,dc6,dc7,dc8,borc,res34,res38,res3c,
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+ src0,src1,src2,res4c,ris,imc,misc,resc,rcc,pllcfg,res68,gpiohbctl,rcc2,res74,res78,moscctl:dword;res80:array[0..31] of dword;rcgc0,
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+ rcgc1,rcgc2,res10,scgc0,scgc1,scgc2,
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+ res11,dcgc0,dcgc1,dcgc2,res12c,res130,res134,res138,res13c,res140,dsplpclk,res13,res14,res15,piosccal,
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+ i2smclk,res174,res178,res17c,res180,res184,res188,res18c,dc9,res194,res198,res19c,nvmstat:dword;
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+ end;
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+
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+{$ALIGN 4}
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+var
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+
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+ PortA :Tgpioport absolute portAoffset;
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+ PortB :Tgpioport absolute portBoffset;
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+ PortC :Tgpioport absolute portCoffset;
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+ PortD :Tgpioport absolute portDoffset;
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+ PortE :Tgpioport absolute portEoffset;
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+ PortF :Tgpioport absolute portFoffset;
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+ PortG :Tgpioport absolute portGoffset;
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+ PortH :Tgpioport absolute portHoffset;
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+ PortJ :Tgpioport absolute portJoffset;
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+
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+ syscon :Tsyscon absolute sysconoffset;
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+ rcgc0 :dword absolute (sysconoffset+$100);
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+ rcgc1 :dword absolute (sysconoffset+$104);
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+ rcgc2 :dword absolute (sysconoffset+$108);
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+
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+var
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+NMI_Handler,
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+HardFault_Handler,
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+MemManage_Handler,
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+BusFault_Handler,
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+UsageFault_Handler,
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+SWI_Handler,
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+DebugMonitor_Handler,
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+PendingSV_Handler,
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+Systick_Handler,UART0intvector: pointer;
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+
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+implementation
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+
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+var
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+ _data: record end; external name '_data';
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+ _edata: record end; external name '_edata';
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+ _etext: record end; external name '_etext';
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+ _bss_start: record end; external name '_bss_start';
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+ _bss_end: record end; external name '_bss_end';
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+ _stack_top: record end; external name '_stack_top';
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+
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+procedure PASCALMAIN; external name 'PASCALMAIN';
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+
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+procedure _FPC_haltproc; assembler; nostackframe; public name '_haltproc';
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+asm
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+.Lhalt:
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+ b .Lhalt
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+end;
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+
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+procedure _FPC_start; assembler; nostackframe;
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+label _start;
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+asm
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+ .init
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+ .align 16
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+
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+ .long _stack_top // First entry in NVIC table is the new stack pointer
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+ .long _start+1 //gjb changed from stm32f version to avoid invstate error when interrupt fires
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+ //b _start // Reset
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+ .long _start+1
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+ //b .LNMI_Addr // Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector.
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+ .long _start+1
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+ //b .LHardFault_Addr // All class of fault
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+ .long _start+1
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+ //b .LMemManage_Addr // Memory management
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+ .long _start+1
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+ //b .LBusFault_Addr // Pre-fetch fault, memory access fault
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+ .long _start+1
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+ //b .LUsageFault_Addr // Undefined instruction or illegal state
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+ .long _start+1
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+ //nop // Reserved
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+ .long _start+1
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+ //nop // Reserved
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+ .long _start+1
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+ //nop // Reserved
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+ .long _start+1
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+ //nop // Reserved
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+ .long _start+1
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+ //b .LSWI_Addr // Software Interrupt vector now SVC
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+ .long _start+1
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+ //b .LDebugMonitor_Addr // Debug Monitor
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+ .long _start+1
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+ //nop // Reserved
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+ .long _start+1
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+ //b .LPendingSV_Addr // Pendable request for system service
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+ .long _start+1
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+ //b .LSystick_Addr // System tick timer
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+ //16
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+ .long .LDefaultHandler+1 //GPIOA #0
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+ .long .LDefaultHandler+1 //GPIOB
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+ .long .LDefaultHandler+1 //GPIOC
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+ .long .LDefaultHandler+1 //GPIOD
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+ .long .LDefaultHandler+1 //GPIOE
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+ .long .LUART0handler+1 //.LDefaultHandler+1 //UART0
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+ .long .LDefaultHandler+1 //UART1
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+ .long .LDefaultHandler+1 //SSI0
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+ //24
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+ .long .LDefaultHandler+1 //I2C0 #8
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+ .long .LDefaultHandler+1 //PWMF
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+ .long .LDefaultHandler+1 //PWMG0
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+ .long .LDefaultHandler+1 //PWMG1
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+ .long .LDefaultHandler+1 //PWMG2
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+ .long .LDefaultHandler+1 //QEI0
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+ .long .LDefaultHandler+1 //ADC0S0
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+ .long .LDefaultHandler+1 //ADC0S1
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+ //32
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+ .long .LDefaultHandler+1 //ADC0S2 #16
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+ .long .LDefaultHandler+1 //ADC0S3
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+ .long .LDefaultHandler+1 //WDGTimer01
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+ .long .LDefaultHandler+1 //T0A
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+ .long .LDefaultHandler+1 //T0B
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+ .long .LDefaultHandler+1 //T1A
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+ .long .LDefaultHandler+1 //T1B
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+ .long .LDefaultHandler+1 //T2A
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+ //40
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+ .long .LDefaultHandler+1 //T2B #24
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+ .long .LDefaultHandler+1 //COMP0
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+ .long .LDefaultHandler+1 //COMP1
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+ .long .LDefaultHandler+1 //COMP2
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+ .long .LDefaultHandler+1 //SYSCON
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+ .long .LDefaultHandler+1 //FLASH
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+ .long .LDefaultHandler+1 //GPIOF
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+ .long .LDefaultHandler+1 //GPIOG
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+ //48
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+ .long .LDefaultHandler+1 //GPIOH #32
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+ .long .LDefaultHandler+1 //UART2
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+ .long .LDefaultHandler+1 //SSI1
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+ .long .LDefaultHandler+1 //T3A
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+ .long .LDefaultHandler+1 //T3B
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+ .long .LDefaultHandler+1 //I2C1
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+ .long .LDefaultHandler+1 //QEI1
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+ .long .LDefaultHandler+1 //CAN0
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+ //56
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+ .long .LDefaultHandler+1 //CAN1 #40
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+ .long .LDefaultHandler+1 //res
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+ .long .LDefaultHandler+1 //ETH
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+ .long .LDefaultHandler+1 //res
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+ .long .LDefaultHandler+1 //USB
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+ .long .LDefaultHandler+1 //PWMG3
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+ .long .LDefaultHandler+1 //UDMAS
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+ .long .LDefaultHandler+1 //UDMAE
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+ //64
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+ .long .LDefaultHandler+1 //ADC1S0 #48
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+ .long .LDefaultHandler+1 //ADC1S1
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+ .long .LDefaultHandler+1 //ADC1S2
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+ .long .LDefaultHandler+1 //ADC1S3
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+ .long .LDefaultHandler+1 //I2S0
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+ .long .LDefaultHandler+1 //EPI
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+ .long .LDefaultHandler+1 //GPIOJ
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+ .long .LDefaultHandler+1 //res #55
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+
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+.LNMI_Addr:
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+ ldr r0,.L1
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+ ldr pc,[r0]
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+.LHardFault_Addr:
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+ ldr r0,.L2
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+ ldr pc,[r0]
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+.LMemManage_Addr:
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+ ldr r0,.L3
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+ ldr pc,[r0]
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+.LBusFault_Addr:
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+ ldr r0,.L4
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+ ldr pc,[r0]
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+.LUsageFault_Addr:
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+ ldr r0,.L5
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+ ldr pc,[r0]
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+.LSWI_Addr:
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+ ldr r0,.L6
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+ ldr pc,[r0]
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+.LDebugMonitor_Addr:
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+ ldr r0,.L7
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+ ldr pc,[r0]
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+.LPendingSV_Addr:
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+ ldr r0,.L8
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+ ldr pc,[r0]
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+.LSystick_Addr:
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+ ldr r0,.L9
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+ ldr pc,[r0]
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+.LUART0handler:
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+ ldr r0,.L10
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+ ldr pc,[r0]
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+.L1:
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+ .long NMI_Handler
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+.L2:
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+ .long HardFault_Handler
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+.L3:
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+ .long MemManage_Handler
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+.L4:
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+ .long BusFault_Handler
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+.L5:
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+ .long UsageFault_Handler
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+.L6:
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+ .long SWI_Handler
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+.L7:
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+ .long DebugMonitor_Handler
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+.L8:
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+ .long PendingSV_Handler
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+.L9:
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+ .long Systick_Handler
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+.L10:
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+ .long UART0IntVector
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+
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+ .globl _start
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+ .text
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+_start:
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+
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+ // Copy initialized data to ram
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+ ldr r1,.L_etext
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+ ldr r2,.L_data
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+ ldr r3,.L_edata
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+.Lcopyloop:
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+ cmp r2,r3
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+ ittt ls
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+ ldrls r0,[r1],#4
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+ strls r0,[r2],#4
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+ bls .Lcopyloop
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+
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+ // clear onboard ram
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+ ldr r1,.L_bss_start
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+ ldr r2,.L_bss_end
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+ mov r0,#0
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+.Lzeroloop:
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+ cmp r1,r2
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+ itt ls
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+ strls r0,[r1],#4
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+ bls .Lzeroloop
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+
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+ b PASCALMAIN
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+ b _FPC_haltproc
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+
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+.L_bss_start:
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+ .long _bss_start
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+.L_bss_end:
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+ .long _bss_end
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+.L_etext:
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+ .long _etext
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+.L_data:
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+ .long _data
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+.L_edata:
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+ .long _edata
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+.LDefaultHandlerAddr:
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+ .long .LDefaultHandler
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+ // default irq handler just returns
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+.LDefaultHandler:
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+ mov pc,r14
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+end;
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+
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+end.
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+
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florian