* nppcinl is currently the same for ppc32 and ppc64

git-svn-id: trunk@5405 -

.gitattributes

@@ -312,7 +312,6 @@ compiler/powerpc/itcpugas.pas svneol=native#text/plain
 compiler/powerpc/nppcadd.pas svneol=native#text/plain
 compiler/powerpc/nppccal.pas svneol=native#text/plain
 compiler/powerpc/nppccnv.pas svneol=native#text/plain
-compiler/powerpc/nppcinl.pas svneol=native#text/plain
 compiler/powerpc/nppcmat.pas svneol=native#text/plain
 compiler/powerpc/nppcset.pas svneol=native#text/plain
 compiler/powerpc/rappc.pas svneol=native#text/plain
@@ -348,7 +347,6 @@ compiler/powerpc64/itcpugas.pas svneol=native#text/plain
 compiler/powerpc64/nppcadd.pas svneol=native#text/plain
 compiler/powerpc64/nppccal.pas svneol=native#text/plain
 compiler/powerpc64/nppccnv.pas svneol=native#text/plain
-compiler/powerpc64/nppcinl.pas svneol=native#text/plain
 compiler/powerpc64/nppcld.pas svneol=native#text/plain
 compiler/powerpc64/nppcmat.pas svneol=native#text/plain
 compiler/powerpc64/nppcset.pas svneol=native#text/plain
@@ -382,6 +380,7 @@ compiler/ppcgen/aasmcpu.pas svneol=native#text/plain
 compiler/ppcgen/cgppc.pas svneol=native#text/plain
 compiler/ppcgen/ngppcadd.pas svneol=native#text/plain
 compiler/ppcgen/ngppccnv.pas svneol=native#text/plain
+compiler/ppcgen/ngppcinl.pas svneol=native#text/plain
 compiler/ppheap.pas svneol=native#text/plain
 compiler/ppu.pas svneol=native#text/plain
 compiler/procinfo.pas svneol=native#text/plain

compiler/powerpc64/nppcinl.pas

@@ -1,152 +0,0 @@
-{
-    Copyright (c) 1998-2002 by Florian Klaempfl
-
-    Generate i386 inline nodes
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
- ****************************************************************************
-}
-unit nppcinl;
-
-{$I fpcdefs.inc}
-
-interface
-
-uses
-  node, ninl, ncginl;
-
-type
-  tppcinlinenode = class(tcginlinenode)
-    { first pass override
-      so that the code generator will actually generate
-      these nodes.
-    }
-    function first_abs_real: tnode; override;
-    function first_sqr_real: tnode; override;
-
-    { trunc/round/frac?/int can't be inlined? }
-
-    procedure second_abs_real; override;
-    procedure second_sqr_real; override;
-    procedure second_prefetch; override;
-  private
-    procedure load_fpu_location;
-  end;
-
-implementation
-
-uses
-  cutils, globals, verbose,
-  aasmtai,aasmdata, aasmcpu,
-  symconst, symdef,
-  defutil,
-  cgbase, pass_2,
-  cpubase, ncgutil,
-  cgutils, cgobj, rgobj;
-
-{*****************************************************************************
-                              TPPCINLINENODE
-*****************************************************************************}
-
-function tppcinlinenode.first_abs_real: tnode;
-begin
-  expectloc := LOC_FPUREGISTER;
-  registersint := left.registersint;
-  registersfpu := max(left.registersfpu, 1);
-  first_abs_real := nil;
-end;
-
-function tppcinlinenode.first_sqr_real: tnode;
-begin
-  expectloc := LOC_FPUREGISTER;
-  registersint := left.registersint;
-  registersfpu := max(left.registersfpu, 1);
-  first_sqr_real := nil;
-end;
-
-{ load the FPU into the an fpu register }
-
-procedure tppcinlinenode.load_fpu_location;
-begin
-  location_reset(location, LOC_FPUREGISTER, def_cgsize(resultdef));
-  secondpass(left);
-  location_force_fpureg(current_asmdata.CurrAsmList, left.location, true);
-  location_copy(location, left.location);
-  if (location.loc = LOC_CFPUREGISTER) then
-  begin
-    location.loc := LOC_FPUREGISTER;
-    location.register := cg.getfpuregister(current_asmdata.CurrAsmList, OS_F64);
-  end;
-end;
-
-procedure tppcinlinenode.second_abs_real;
-begin
-  location.loc := LOC_FPUREGISTER;
-  load_fpu_location;
-  current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FABS, location.register,
-    left.location.register));
-end;
-
-procedure tppcinlinenode.second_sqr_real;
-var
-  op : TAsmOp;
-begin
-  location.loc := LOC_FPUREGISTER;
-  load_fpu_location;
-  if (left.location.size = OS_F32) then
-    op := A_FMULS
-  else
-    op := A_FMUL;
-
-  current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op, location.register,
-    left.location.register, left.location.register));
-end;
-
-procedure tppcinlinenode.second_prefetch;
-var
-  r: tregister;
-begin
-  secondpass(left);
-  case left.location.loc of
-    LOC_CREFERENCE,
-      LOC_REFERENCE:
-      begin
-        r := cg.getintregister(current_asmdata.CurrAsmList, OS_ADDR);
-        if (left.location.reference.offset = 0) and
-          not assigned(left.location.reference.symbol) then
-        begin
-          if (left.location.reference.index = NR_NO) then
-            current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_DCBT, 0,
-              left.location.reference.base))
-          else
-            current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_DCBT,
-              left.location.reference.base, left.location.reference.index));
-        end
-        else
-        begin
-          cg.a_loadaddr_ref_reg(current_asmdata.CurrAsmList, left.location.reference, r);
-          current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_DCBT, 0, r));
-        end;
-      end;
-  else
-    internalerror(200402021);
-  end;
-end;
-
-begin
-  cinlinenode := tppcinlinenode;
-end.
-

compiler/powerpc/nppcinl.pas → compiler/ppcgen/ngppcinl.pas

@@ -1,7 +1,7 @@
 {
     Copyright (c) 1998-2002 by Florian Klaempfl
 
-    Generate i386 inline nodes
+    Generate PowerPC32/64 inline nodes
 
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
@@ -19,7 +19,7 @@
 
  ****************************************************************************
 }
-unit nppcinl;
+unit ngppcinl;
 
 {$i fpcdefs.inc}
 
@@ -29,7 +29,7 @@ interface
        node,ninl,ncginl;
 
     type
-       tppcinlinenode = class(tcginlinenode)
+       tgppcinlinenode = class(tcginlinenode)
           { first pass override
             so that the code generator will actually generate
             these nodes.
@@ -39,7 +39,7 @@ interface
           procedure second_abs_real; override;
           procedure second_sqr_real; override;
           procedure second_prefetch;override;
-       private
+       protected
           procedure load_fpu_location;
        end;
 
@@ -56,10 +56,10 @@ implementation
 
 
 {*****************************************************************************
-                              TPPCINLINENODE
+                              tgppcinlinenode
 *****************************************************************************}
 
-     function tppcinlinenode.first_abs_real : tnode;
+     function tgppcinlinenode.first_abs_real : tnode;
       begin
         expectloc:=LOC_FPUREGISTER;
         registersint:=left.registersint;
@@ -70,7 +70,7 @@ implementation
         first_abs_real := nil;
       end;
 
-     function tppcinlinenode.first_sqr_real : tnode;
+     function tgppcinlinenode.first_sqr_real : tnode;
       begin
         expectloc:=LOC_FPUREGISTER;
         registersint:=left.registersint;
@@ -81,21 +81,19 @@ implementation
         first_sqr_real := nil;
       end;
 
+
        { load the FPU into the an fpu register }
-       procedure tppcinlinenode.load_fpu_location;
+       procedure tgppcinlinenode.load_fpu_location;
          begin
            location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
            secondpass(left);
            location_force_fpureg(current_asmdata.CurrAsmList,left.location,true);
-           location_copy(location,left.location);
-           if (location.loc = LOC_CFPUREGISTER) then
-             begin
-               location.loc := LOC_FPUREGISTER;
-               location.register := cg.getfpuregister(current_asmdata.CurrAsmList,OS_F64);
-             end;
+           location.loc := LOC_FPUREGISTER;
+           location.register := cg.getfpuregister(current_asmdata.CurrAsmList,OS_F64);
          end;
 
-     procedure tppcinlinenode.second_abs_real;
+
+     procedure tgppcinlinenode.second_abs_real;
        begin
          location.loc:=LOC_FPUREGISTER;
          load_fpu_location;
@@ -103,7 +101,7 @@ implementation
            left.location.register));
        end;
 
-     procedure tppcinlinenode.second_sqr_real;
+     procedure tgppcinlinenode.second_sqr_real;
        var
          op: tasmop;
        begin
@@ -118,7 +116,7 @@ implementation
        end;
 
 
-     procedure tppcinlinenode.second_prefetch;
+     procedure tgppcinlinenode.second_prefetch;
        var
          r: tregister;
        begin
@@ -147,6 +145,7 @@ implementation
          end;
        end;
 
+
 begin
-   cinlinenode:=tppcinlinenode;
+   cinlinenode:=tgppcinlinenode;
 end.