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@@ -5038,16 +5038,18 @@ unit aoptx86;
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function TX86AsmOptimizer.OptPass1Movx(var p : tai) : boolean;
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var
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hp1,hp2: tai;
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+ reg_and_hp1_is_instr: Boolean;
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begin
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result:=false;
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- if (taicpu(p).oper[1]^.typ = top_reg) and
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- GetNextInstruction(p,hp1) and
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- (hp1.typ = ait_instruction) and
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- IsFoldableArithOp(taicpu(hp1),taicpu(p).oper[1]^.reg) and
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- GetNextInstruction(hp1,hp2) and
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- MatchInstruction(hp2,A_MOV,[]) and
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- (taicpu(hp2).oper[0]^.typ = top_reg) and
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- OpsEqual(taicpu(hp2).oper[1]^,taicpu(p).oper[0]^) and
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+ reg_and_hp1_is_instr:=(taicpu(p).oper[1]^.typ = top_reg) and
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+ GetNextInstruction(p,hp1) and
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+ (hp1.typ = ait_instruction);
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+ if reg_and_hp1_is_instr and
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+ IsFoldableArithOp(taicpu(hp1),taicpu(p).oper[1]^.reg) and
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+ GetNextInstruction(hp1,hp2) and
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+ MatchInstruction(hp2,A_MOV,[]) and
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+ (taicpu(hp2).oper[0]^.typ = top_reg) and
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+ OpsEqual(taicpu(hp2).oper[1]^,taicpu(p).oper[0]^) and
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{$ifdef i386}
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{ not all registers have byte size sub registers on i386 }
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((taicpu(hp2).opsize<>S_B) or (getsupreg(taicpu(hp1).oper[0]^.reg) in [RS_EAX, RS_EBX, RS_ECX, RS_EDX])) and
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@@ -5105,12 +5107,9 @@ unit aoptx86;
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else if taicpu(p).opcode=A_MOVZX then
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begin
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{ removes superfluous And's after movzx's }
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- if (taicpu(p).oper[1]^.typ = top_reg) and
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- GetNextInstruction(p, hp1) and
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- (tai(hp1).typ = ait_instruction) and
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+ if reg_and_hp1_is_instr and
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(taicpu(hp1).opcode = A_AND) and
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- (taicpu(hp1).oper[0]^.typ = top_const) and
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- (taicpu(hp1).oper[1]^.typ = top_reg) and
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+ MatchOpType(taicpu(hp1),top_const,top_reg) and
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(taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
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begin
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case taicpu(p).opsize Of
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@@ -5144,8 +5143,7 @@ unit aoptx86;
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end;
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{ changes some movzx constructs to faster synonyms (all examples
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are given with eax/ax, but are also valid for other registers)}
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- if (taicpu(p).oper[1]^.typ = top_reg) then
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- if (taicpu(p).oper[0]^.typ = top_reg) then
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+ if MatchOpType(taicpu(p),top_reg,top_reg) then
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begin
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case taicpu(p).opsize of
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{ Technically, movzbw %al,%ax cannot be encoded in 32/64-bit mode
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@@ -5176,8 +5174,7 @@ unit aoptx86;
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GetNextInstruction(p, hp1) and
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(tai(hp1).typ = ait_instruction) and
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(taicpu(hp1).opcode = A_AND) and
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- (taicpu(hp1).oper[0]^.typ = top_const) and
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- (taicpu(hp1).oper[1]^.typ = top_reg) and
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+ MatchOpType(taicpu(hp1),top_const,top_reg) and
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(taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
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{ Change "movzbw %reg1, %reg2; andw $const, %reg2"
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to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
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@@ -5214,8 +5211,7 @@ unit aoptx86;
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GetNextInstruction(p, hp1) and
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(tai(hp1).typ = ait_instruction) and
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(taicpu(hp1).opcode = A_AND) and
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- (taicpu(hp1).oper[0]^.typ = top_const) and
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- (taicpu(hp1).oper[1]^.typ = top_reg) and
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+ MatchOpType(taicpu(hp1),top_const,top_reg) and
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(taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
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{ Change "movzbl %reg1, %reg2; andl $const, %reg2"
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to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
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florian