 florian
|
971d97c179
+ RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0
|
6 months ago |
|
florian
|
1202b2612f
+ RiscV: make use of the fl* rd,symbol,rd pseudoinstruction
|
6 months ago |
|
florian
|
c3110dfaa9
+ RiscV: make use of the fneg.* instruction
|
7 months ago |
|
florian
|
2c5a070959
+ random bits for quad support on RiscV
|
7 months ago |
|
florian
|
6ef37d999a
+ Risc-V: instructions of B extension
|
1 year ago |
|
florian
|
ec3a04da9b
+ forgotten pseudo-instructions added
|
3 years ago |
|
florian
|
eaeb8b70ff
+ added Risc-V register information file generation to the compiler Makefile
|
3 years ago |
|
florian
|
4556cb35d1
+ completed Risc-V 64 pseudo instructions
|
3 years ago |
|
florian
|
6a00f9f403
* unified Risc-V 32 and 64 cpubase.pas
|
3 years ago |
|
florian
|
09587d0c1b
* standard Risc-V pseudo instructions for Risc-V 32 completed
|
3 years ago |
|
florian
|
b29b81ae7b
* pseudo instructions for flag handling
|
3 years ago |
|
florian
|
9ccdf2b3bf
* RiscV: unified itcpugas.pas
|
4 years ago |
