 florian
|
1802a8c493
+ apply OptPass1Data to variable shifting/rotating operations as well
|
6 months ago |
|
florian
|
6cd75b75c3
* apply OptPass1Data to UDIV/SDIV as well
|
6 months ago |
 Sven/Sarah Barth
|
bb27442b19
* when removing the STP FP,LR and MOV FP,SP instructions, also remove the corresponding SEH directives if available
|
9 months ago |
 J. Gareth "Curious Kit" Moreton
|
2a50d5abf8
* ARMv7A / A64: Constant writes to memory merged to larger forms where possible
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3 years ago |
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florian
|
4fea0e355e
+ apply OptPass1FData on FRINT*
|
11 months ago |
|
florian
|
f81ce16d2a
+ AArch64: apply OptPass1FData also to FCSEL
|
11 months ago |
|
J. Gareth "Curious Kit" Moreton
|
9ee1821622
* arm / a64: Extended the AND; CMP -> ANDS family of optimisations to catch BIC as well as AND
|
1 year ago |
|
J. Gareth "Curious Kit" Moreton
|
99851f22f5
* a64: New B -> RET peephole optimisation
|
1 year ago |
|
J. Gareth "Curious Kit" Moreton
|
a907eb49c9
* a64: Several secondary peephole optimizations that clean up CSEL instructions
|
1 year ago |
|
J. Gareth "Curious Kit" Moreton
|
ef1cb852a8
* a64: New CSEL block optimisations ported over from x86 CMOV block optimisations
|
1 year ago |
|
J. Gareth "Curious Kit" Moreton
|
bf29f2051c
* arm/a64: Added new TST post-peephole optimisation to replace previous AND/CMP/B(c) optimisation
|
1 year ago |
|
J. Gareth "Curious Kit" Moreton
|
b18c10d0d8
* arm/a64: New "OptPass2TST" routine to catch "TST; B.c; AND -> ANDS; B.c" optimisation
|
1 year ago |
|
J. Gareth "Curious Kit" Moreton
|
9f19f582c4
* arm/a64: New AND/CMP -> TST or ANDS optimisation
|
1 year ago |
|
J. Gareth "Curious Kit" Moreton
|
38d2f3d58c
* a64: Renamed OptPostCMP/And to PostPeepholeOptCMP/AND for internal consistency
|
1 year ago |
|
J. Gareth "Curious Kit" Moreton
|
72081c803e
* a64: SkipAligns calls removed.
|
1 year ago |
|
J. Gareth "Curious Kit" Moreton
|
82a8640111
* a64: New conditional branch to CSET peephole optimisation
|
3 years ago |
 Pierre Muller
|
cd8aa3f0e0
Avoid generation of invalid 'cb(n)z sp,label' instruction
|
2 years ago |
|
florian
|
3a11ee9a14
* apply OptPass1Data to neg as well
|
2 years ago |
|
florian
|
5cbb36f218
* factor out TARMAsmOptimizer.USxtOp2Op
|
2 years ago |
|
florian
|
ed7b0c5e68
* AArch64: extended SxtwMov2Data to CMP and CMN
|
2 years ago |
|
florian
|
ad1c19864d
* small refactoring
|
2 years ago |
|
florian
|
9adcc891cf
+ Aarch64: SxtwOp2Op optimization
|
2 years ago |
|
florian
|
29495c9ba5
* refactor TCpuAsmOptimizer.OptPass1SXTW
|
2 years ago |
|
florian
|
fd94b6db91
* fix for TCpuAsmOptimizer.OptPass1SXTW
|
3 years ago |
|
florian
|
8a0498622b
+ AArchz64: TCpuAsmOptimizer.OptPass1SXTW
|
3 years ago |
|
florian
|
5a60eac0c8
+ MovzMovz2Movz optimization
|
3 years ago |
|
J. Gareth "Curious Kit" Moreton
|
d6ff4ed967
* arm/a64: New sbfx/ubfx -> mov optimisation
|
3 years ago |
|
J. Gareth "Curious Kit" Moreton
|
637645b6d6
* a64: New movz reg,#0 -> mov reg,xzr (or wzr) optimisation
|
3 years ago |
|
florian
|
81fd3e2748
* more readable fix for the missing ait_instruction check
|
3 years ago |
|
J. Gareth "Curious Kit" Moreton
|
27db63969a
* a64: Fix where hp1's was assumed to be an instruction and not actually checked
|
3 years ago |
