 sergei
|
e4fea2ebc8
* Dummy implementations of a_bit_scan_reg_reg and g_stackpointer_alloc in tcg, removes the need to override these methods in every descendant code generator solely to avoid "constructing a class with abstract method" warning.
|
11 years ago |
 Jeppe Johansen
|
a1197460e1
Constrained a number of optimizations and updated reference offsets for ARM Thumb.
|
11 years ago |
 masta
|
0cb1a129b3
{ARM} Implement usage of generic division-by-const optimization
|
11 years ago |
 Károly Balogh
|
af95876eba
arm: an attempt to improve the a_op_const_ref patch in r27881
|
11 years ago |
|
Károly Balogh
|
5b262df7d0
arm: have a CPU specific op_const_ref, so the reference doesn't get fixed up both in a_load_reg_ref and a_load_ref_reg
|
11 years ago |
 florian
|
8dfcc2b399
* do not reuse tmp. registers in tbasecgarm.handle_load_store
|
11 years ago |
|
florian
|
9464dad2b4
* handle vldr/vstr references with offsets correctly
|
11 years ago |
|
florian
|
686a2d2f3f
+ Support omitting the frame pointer on arm even in procedures with incoming parameters
|
11 years ago |
|
florian
|
6deb0b35b5
* handle fpu_vfpv3_d16 properly for thumb2
|
11 years ago |
|
masta
|
2d2cab0e7a
Fix some internalerror codes in the ARM CG
|
11 years ago |
|
sergei
|
9c1f917e3a
* a_call_ref functionality cannot be implemented efficiently at code generator level, because references need specific preparations at earlier points. Moved this support to tcgcallnode and its x86 descendants, and got rid of all ifdef's around.
|
11 years ago |
|
Jeppe Johansen
|
07b2982e77
Don't do ARM FoldShiftLdrStr peephole optimization if there's an offset in the reference.
|
11 years ago |
|
masta
|
0736bf4ded
Try to change typical constant AND-masking operations into shifts for ARM
|
11 years ago |
 nickysn
|
85dd9e5789
+ added a size parameter to optimize_op_const and do a sign extension of the 'a' parameter up from the specified size, so that things like (i and $ffffffff) get optimized away the same way as (i and -1)
|
11 years ago |
|
masta
|
3ab665e554
Try to split constant XORs into two shiftimms on ARM.
|
11 years ago |
|
masta
|
f8889e3d6d
Use optimize_op_const in ARM cg
|
11 years ago |
|
florian
|
561ec1f782
* unified internal errors
|
11 years ago |
|
florian
|
4d5119bf1c
* fixes several issues which cause warnings by the dfa code when using it to detect uninitialized variables
|
11 years ago |
 Jonas Maebe
|
555634b755
* (re)set upper bits of register when appropriate for all operations in
|
11 years ago |
|
florian
|
8fb7cf822b
* unified internal errors
|
12 years ago |
|
florian
|
e0f48b9f02
* calculate stack correction on exit correctly if stack parameters are passed
|
12 years ago |
|
florian
|
36e6f99843
* fix tthumbcgarm.g_flags2reg, mov reg,#imm for thumb updates the flags
|
12 years ago |
|
florian
|
e2ec3bbcb0
* do shifts for sign/zero extensions correctly
|
12 years ago |
|
florian
|
333e84202f
* fixed a_load_reg_reg for thumb
|
12 years ago |
|
Károly Balogh
|
86cb4d0c12
use a TSuperRegister instead of an aint
|
12 years ago |
|
Károly Balogh
|
c677f1fd69
trying harder to follow the code style (no functional changes)
|
12 years ago |
|
Károly Balogh
|
cb4d01627f
save an extra reg if it's required to keep 64bit stack alignment on ARM
|
12 years ago |
|
florian
|
d4968e054b
+ arm: tsettings.instructionset
|
12 years ago |
|
florian
|
f34bee1df7
* arm thumb does not support ror reg1,reg2,#imm
|
12 years ago |
|
florian
|
3ebe708574
* do not use r13/r15 for certain data processing operations
|
12 years ago |
