 J. Gareth "Curious Kit" Moreton
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a907eb49c9
* a64: Several secondary peephole optimizations that clean up CSEL instructions
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1 year ago |
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J. Gareth "Curious Kit" Moreton
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ef1cb852a8
* a64: New CSEL block optimisations ported over from x86 CMOV block optimisations
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1 year ago |
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J. Gareth "Curious Kit" Moreton
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bf29f2051c
* arm/a64: Added new TST post-peephole optimisation to replace previous AND/CMP/B(c) optimisation
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1 year ago |
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J. Gareth "Curious Kit" Moreton
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b18c10d0d8
* arm/a64: New "OptPass2TST" routine to catch "TST; B.c; AND -> ANDS; B.c" optimisation
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1 year ago |
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J. Gareth "Curious Kit" Moreton
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9f19f582c4
* arm/a64: New AND/CMP -> TST or ANDS optimisation
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1 year ago |
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J. Gareth "Curious Kit" Moreton
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38d2f3d58c
* a64: Renamed OptPostCMP/And to PostPeepholeOptCMP/AND for internal consistency
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1 year ago |
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J. Gareth "Curious Kit" Moreton
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72081c803e
* a64: SkipAligns calls removed.
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1 year ago |
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J. Gareth "Curious Kit" Moreton
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82a8640111
* a64: New conditional branch to CSET peephole optimisation
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3 years ago |
 Pierre Muller
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cd8aa3f0e0
Avoid generation of invalid 'cb(n)z sp,label' instruction
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2 years ago |
 florian
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3a11ee9a14
* apply OptPass1Data to neg as well
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2 years ago |
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florian
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5cbb36f218
* factor out TARMAsmOptimizer.USxtOp2Op
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2 years ago |
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florian
|
ed7b0c5e68
* AArch64: extended SxtwMov2Data to CMP and CMN
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2 years ago |
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florian
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ad1c19864d
* small refactoring
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2 years ago |
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florian
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9adcc891cf
+ Aarch64: SxtwOp2Op optimization
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2 years ago |
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florian
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29495c9ba5
* refactor TCpuAsmOptimizer.OptPass1SXTW
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2 years ago |
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florian
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fd94b6db91
* fix for TCpuAsmOptimizer.OptPass1SXTW
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2 years ago |
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florian
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8a0498622b
+ AArchz64: TCpuAsmOptimizer.OptPass1SXTW
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2 years ago |
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florian
|
5a60eac0c8
+ MovzMovz2Movz optimization
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2 years ago |
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J. Gareth "Curious Kit" Moreton
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d6ff4ed967
* arm/a64: New sbfx/ubfx -> mov optimisation
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3 years ago |
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J. Gareth "Curious Kit" Moreton
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637645b6d6
* a64: New movz reg,#0 -> mov reg,xzr (or wzr) optimisation
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3 years ago |
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florian
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81fd3e2748
* more readable fix for the missing ait_instruction check
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3 years ago |
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J. Gareth "Curious Kit" Moreton
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27db63969a
* a64: Fix where hp1's was assumed to be an instruction and not actually checked
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3 years ago |
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florian
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e8da1d081a
+ Aarch64: MovOp2AddUtxw optimization
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3 years ago |
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florian
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a362c93f73
* Aarch64: operations affect always the full 64 bit register, so
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3 years ago |
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florian
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fcdbb31ec4
* AArch64: TCpuAsmOptimizer.RegLoadedWithNewValue: check if p.ops=0
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3 years ago |
|
Pierre Muller
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7778d20003
Avoid range check error in TCpuAsmOptimizer.OptPostAnd method
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3 years ago |
|
florian
|
2e8c99947a
* define DEBUG_AOPTCPU if EXTDEBUG is used
|
3 years ago |
|
florian
|
cc5ee6b868
+ comments
|
3 years ago |
|
florian
|
39164ad732
* cleanup
|
3 years ago |
|
florian
|
c1d8e32eae
+ Aarch64: Ldr<Postfix>Mov2Ldr<Postfix> optimization
|
3 years ago |
