 florian
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94d7a02fae
* modified patch by Gareth Moreton to pool TmpUsedRegs in the assembler optimizers, resolves #34679
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6 years ago |
 yury
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92e579a294
* Improved the comment.
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6 years ago |
|
yury
|
fdcb12d9f6
* ARM: Remove preindexing and postindexing for LDR in some cases when removing superfluous MOVs. It fixes crash when calling Format() if rtl is compiled with -O3.
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6 years ago |
 Jonas Maebe
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122d0d36d6
+ volatile() expression that marks an expression as volatile
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6 years ago |
 pierre
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aebc8527ef
Also disable range checking in arm/aoptcpu unit
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6 years ago |
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florian
|
9f16c34329
+ initial work for tls-based threadvar support on arm-linux
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6 years ago |
|
pierre
|
fbffd2a38f
Fix typecast in FindRegDeAlloc call
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6 years ago |
 Jeppe Johansen
|
09a8cafcd7
Restricted MlaCmp>Mlas optimization to only work in ARM mode.
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8 years ago |
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florian
|
4868b83157
* do not generate always debug messages in the arm assembler optimizer
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8 years ago |
|
yury
|
3bedccf946
* ARM scheduler need to move register de-allocs located before the instruction. Also preserve order of allocs and de-allocs.
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8 years ago |
|
yury
|
fe0e30030f
* In ARM scheduler move all needed additional items with an instruction:
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8 years ago |
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Jonas Maebe
|
38fd0efa3b
* don't conditionalise BL on ARM, because it may have to be converted to
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9 years ago |
|
florian
|
73aeea73ed
+ VOpVMov2VOp optimization
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9 years ago |
|
florian
|
1266491085
o refactored some peephole optimizer code:
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9 years ago |
|
Jeppe Johansen
|
803f402bf8
Fix minor bug in peephole optimizer.
|
9 years ago |
|
yury
|
432248cbf1
* Removed lot of unused vars.
|
10 years ago |
|
yury
|
df9d6db398
* Fixed instruction re-scheduler for ARM in case of PIC.
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10 years ago |
|
Jeppe Johansen
|
9e5979e8be
Implemented UAL syntax support in the ARM assembler reader. Can be toggled with a field for now, but not implemented yet. Still using pre-UAL syntax for now.
|
10 years ago |
|
Jeppe Johansen
|
3bc1db9612
Fixed breakage in the ARM peephole optimizer indirectly brought to light by r29189.
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10 years ago |
|
Jeppe Johansen
|
d04e988ff1
Make sure optimizer don't generate invalid assembler forms (LDRD and STRD).
|
10 years ago |
|
Jeppe Johansen
|
d3e91bb60c
Fixed issue #26965. The peephole optimization didn't move a potential register deallocation to after the ldr instruction causing mov's to be removed.
|
10 years ago |
 sergei
|
a3c439c60f
- No longer insert BlockStart markers into asmlists. The presence of these markers disrupts peephole optimizations and require additional checks all over the place, causing various workarounds/hacks (like TAsmList.Create_without_marker) to start building up.
|
11 years ago |
 masta
|
7e22bd53b6
Changed ARMs StrLdr2StrMov peephole optimizer look further ahead
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11 years ago |
|
masta
|
bfa85218fa
Introduce TCpuAsmOptimizer.GetNextInstructionUsingRef
|
11 years ago |
|
masta
|
d1c5f89976
Make Next an Out-parameter in ARMs GetNextInstructionUsingReg
|
11 years ago |
|
masta
|
7a0c79de60
Fix for AndLsl2Lsl in ARM Peephole optimizer
|
11 years ago |
|
masta
|
85d208fea4
Fix ARM LoadScheduler in case of Pre/PostIndexed addressing
|
11 years ago |
|
Jeppe Johansen
|
857a849173
Added an additional check to the MulAdd2MLA optimization. The operands of the multiplication weren't checked.
|
11 years ago |
|
Jeppe Johansen
|
a1197460e1
Constrained a number of optimizations and updated reference offsets for ARM Thumb.
|
11 years ago |
|
florian
|
23c8517418
* applying opXYX2opsXY to ADD makes no sense on thumb-2 (at least as far as I can see)
|
11 years ago |
