; ; Table of assembler instructions for Free Pascal ; adapted from Netwide Assembler by Florian Klaempfl ; ; ; The Netwide Assembler is copyright (C) 1996 Simon Tatham and ; Julian Hall. All rights reserved. The software is ; redistributable under the licence given in the file "Licence" ; distributed in the NASM archive. ; ; Format of file: all four fields must be present on every functional ; line. Hence `void' for no-operand instructions, and `\0' for such ; as EQU. If the last three fields are all `ignore', no action is ; taken except to register the opcode as being present. ; ; ; 'ignore' means no instruc ; 'void' means instruc with zero operands ; ; Third field has a first byte indicating how to ; put together the bits, and then some codes ; that may be used at will (see assemble.c) ; ; \1 - 24 bit pc-rel offset [B, BL] ; \2 - 24 bit imm value [SWI] ; \3 - 3 byte code [BX] ; ; \4 - reg,reg,reg [AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC] ; \5 - reg,reg,reg,reg [-"-] ; \6 - reg,reg,reg,#imm [-"-] ; \7 - reg,reg,#imm [-"-] ; ; \x8 - reg,reg [MOV,MVN] ; \x9 - reg,reg,reg [-"-] ; \xA - reg,reg,#imm [-"-] ; \xB - reg,#imm [-"-] ; ; \xC - reg,reg [CMP,CMN,TEQ,TST] ; \xD - reg,reg,reg [-"-] ; \xE - reg,reg,#imm [-"-] ; \xF - reg,#imm [-"-] ; [ADCcc] reg32,reg32,reg32 \4\x0\xA0 ARM7 reg32,reg32,reg32,reg32 \5\x0\xA0 ARM7 reg32,reg32,reg32,imm \6\x0\xA0 ARM7 reg32,reg32,imm \7\x2\xA0 ARM7 [ADDcc] reg32,reg32,reg32 \4\x0\x80 ARM7 reg32,reg32,reg32,reg32 \5\x0\x80 ARM7 reg32,reg32,reg32,imm \6\x0\x80 ARM7 reg32,reg32,imm \7\x2\x80 ARM7 [ANDcc] reg32,reg32,reg32 \4\x0\x00 ARM7 reg32,reg32,reg32,reg32 \5\x0\x00 ARM7 reg32,reg32,reg32,imm \6\x0\x00 ARM7 reg32,reg32,imm \7\x2\x00 ARM7 [Bcc] mem32 \1\x0A ARM7 imm32 \1\x0A ARM7 [BICcc] reg32,reg32,reg32 \4\x1\xC0 ARM7 reg32,reg32,reg32,reg32 \5\x1\xC0 ARM7 reg32,reg32,reg32,imm \6\x1\xC0 ARM7 reg32,reg32,imm \7\x3\xC0 ARM7 [BLcc] mem32 \1\x0B ARM7 imm32 \1\x0B ARM7 [BXcc] reg32 \3\x01\x2F\xFF\x10 ARM7 [CDP] reg8,reg8 \300\1\x10\101 8086 [CMNcc] reg32,reg32 \xC\x1\x60 ARM7 reg32,reg32,reg32 \xD\x1\x60 ARM7 reg32,reg32,imm \xE\x1\x60 ARM7 reg32,imm \xF\x3\x60 ARM7 [CMPcc] reg32,reg32 \xC\x1\x40 ARM7 reg32,reg32,reg32 \xD\x1\x40 ARM7 reg32,reg32,imm \xE\x1\x40 ARM7 reg32,imm \xF\x3\x40 ARM7 [DCB] ignore ignore ignore [DCD] ignore ignore ignore [DCW] ignore ignore ignore [DQ] ignore ignore ignore [DT] ignore ignore ignore [EORcc] reg32,reg32,reg32 \4\x0\x20 ARM7 reg32,reg32,reg32,reg32 \5\x0\x20 ARM7 reg32,reg32,reg32,imm \6\x0\x20 ARM7 reg32,reg32,imm \7\x2\x20 ARM7 [LDC] reg32,reg32 \321\300\1\x11\101 ARM7 [LDMDAcc] reg32,reglist \x26\x81 ARM7 [LDMDBcc] reg32,reglist \x26\x91 ARM7 [LDMEAcc] reg32,reglist \x26\x91 ARM7 [LDMEDcc] reg32,reglist \x26\x99 ARM7 [LDMFAcc] reg32,reglist \x26\x81 ARM7 [LDMFDcc] reg32,reglist \x26\x89 ARM7 [LDMIAcc] reg32,reglist \x26\x89 ARM7 [LDMIBcc] reg32,reglist \x26\x99 ARM7 [LDRcc] reg32,imm32 \x17\x05\x10 ARM7 reg32,reg32 \x18\x04\x10 ARM7 reg32,reg32,imm32 \x19\x04\x10 ARM7 reg32,reg32,reg32 \x20\x06\x10 ARM7 reg32,reg32,reg32,imm32 \x21\x06\x10 ARM7 [LDRHcc] reg32,imm32 \x22\x50\xB0 ARM7 reg32,reg32 \x23\x50\xB0 ARM7 reg32,reg32,imm32 \x24\x50\xB0 ARM7 reg32,reg32,reg32 \x25\x10\xB0 ARM7 [LDRSBcc] reg32,imm32 \x22\x50\xD0 ARM7 reg32,reg32 \x23\x50\xD0 ARM7 reg32,reg32,imm32 \x24\x50\xD0 ARM7 reg32,reg32,reg32 \x25\x10\xD0 ARM7 [LDRSHcc] reg32,imm32 \x22\x50\xF0 ARM7 reg32,reg32 \x23\x50\xF0 ARM7 reg32,reg32,imm32 \x24\x50\xF0 ARM7 reg32,reg32,reg32 \x25\x10\xF0 ARM7 [MCR] reg32,mem32 \320\301\1\x13\110 8086 [MLAcc] reg32,reg32,reg32,reg32 \x15\x00\x20\x90 ARM7 [MOVcc] reg32,reg32 \x8\x1\xA0 ARM7 reg32,reg32,reg32 \x9\x1\xA0 ARM7 reg32,reg32,imm \xA\x1\xA0 ARM7 reg32,imm \xB\x3\xA0 ARM7 [MRC] reg32,reg32 \321\301\1\x13\110 ARM7 [MRScc] reg32,reg32 \x10\x01\x0F ARM7 [MSRcc] reg32,reg32 \x11\x01\x29\xF0 ARM7 regf,reg32 \x12\x01\x28\xF0 ARM7 regf,imm \x13\x03\x28\xF0 ARM7 [MULcc] reg32,reg32,reg32 \x14\x00\x00\x90 ARM7 [MVNcc] reg32,reg32 \x8\x1\xE0 ARM7 reg32,reg32,reg32 \x9\x1\xE0 ARM7 reg32,reg32,imm \xA\x1\xE0 ARM7 reg32,imm \xB\x3\xE0 ARM7 [ORRcc] reg32,reg32,reg32 \4\x1\x80 ARM7 reg32,reg32,reg32,reg32 \5\x1\x80 ARM7 reg32,reg32,reg32,imm \6\x1\x80 ARM7 reg32,reg32,imm \7\x3\x80 ARM7 [RSBcc] reg32,reg32,reg32 \4\x0\x60 ARM7 reg32,reg32,reg32,reg32 \5\x0\x60 ARM7 reg32,reg32,reg32,imm \6\x0\x60 ARM7 reg32,reg32,imm \7\x2\x60 ARM7 [RSCcc] reg32,reg32,reg32 \4\x0\xE0 ARM7 reg32,reg32,reg32,reg32 \5\x0\xE0 ARM7 reg32,reg32,reg32,imm \6\x0\xE0 ARM7 reg32,reg32,imm \7\x2\xE0 ARM7 [SBCcc] reg32,reg32,reg32 \4\x0\xC0 ARM7 reg32,reg32,reg32,reg32 \5\x0\xC0 ARM7 reg32,reg32,reg32,imm \6\x0\xC0 ARM7 reg32,reg32,imm \7\x2\xC0 ARM7 [SMLALcc] reg32,reg32,reg32,reg32 \x16\x00\xE0\x90 ARM7 [SMULLcc] reg32,reg32,reg32,reg32 \x16\x00\xC0\x90 ARM7 [STMDAcc] reg32,reglist \x26\x80 ARM7 [STMDBcc] reg32,reglist \x26\x90 ARM7 [STMEAcc] reg32,reglist \x26\x88 ARM7 [STMEDcc] reg32,reglist \x26\x80 ARM7 [STMFAcc] reg32,reglist \x26\x98 ARM7 [STMFDcc] reg32,reglist \x26\x90 ARM7 [STMIAcc] reg32,reglist \x26\x88 ARM7 [STMIBcc] reg32,reglist \x26\x98 ARM7 [STRcc] reg32,imm32 \x17\x05\x00 ARM7 reg32,reg32 \x18\x04\x00 ARM7 reg32,reg32,imm32 \x19\x04\x00 ARM7 reg32,reg32,reg32 \x20\x06\x00 ARM7 reg32,reg32,reg32,imm32 \x21\x06\x00 ARM7 ; A dummy since it is parsed as STR{cond}H [STRHcc] reg32,imm32 \x22\x40\xB0 ARM7 reg32,reg32 \x23\x40\xB0 ARM7 reg32,reg32,imm32 \x24\x40\xB0 ARM7 reg32,reg32,reg32 \x25\x00\xB0 ARM7 [SUBcc] reg32,reg32,reg32 \4\x0\x40 ARM7 reg32,reg32,reg32,reg32 \5\x0\x40 ARM7 reg32,reg32,reg32,imm \6\x0\x40 ARM7 reg32,reg32,imm \7\x2\x40 ARM7 [SWIcc] imm \2\x0F 8086 [SWPcc] reg32,reg32,reg32 \x27\x01\x90 ARM7 [TEQcc] reg32,reg32 \xC\x1\x20 ARM7 reg32,reg32,reg32 \xD\x1\x20 ARM7 reg32,reg32,imm \xE\x1\x20 ARM7 reg32,imm \xF\x3\x20 ARM7 [TSTcc] reg32,reg32 \xC\x1\x00 ARM7 reg32,reg32,reg32 \xD\x1\x00 ARM7 reg32,reg32,imm \xE\x1\x00 ARM7 reg32,imm \xF\x3\x00 ARM7 [UMLALcc] reg32,reg32,reg32,reg32 \x16\x00\xA0\x90 ARM7 [UMULLcc] reg32,reg32,reg32,reg32 \x16\x00\x80\x90 ARM7