popt386.pas 99 KB

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  1. {
  2. $Id$
  3. Copyright (c) 1998-2000 by Florian Klaempfl and Jonas Maebe
  4. This unit contains the peephole optimizer.
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. Unit POpt386;
  19. Interface
  20. Uses Aasm;
  21. Procedure PeepHoleOptPass1(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  22. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  23. Implementation
  24. Uses
  25. globtype,systems,
  26. globals,verbose,hcodegen,
  27. {$ifdef finaldestdebug}
  28. cobjects,
  29. {$endif finaldestdebug}
  30. cpubase,cpuasm,DAOpt386,tgeni386;
  31. Function RegUsedAfterInstruction(Reg: TRegister; p: Pai; Var UsedRegs: TRegSet): Boolean;
  32. Begin
  33. reg := reg32(reg);
  34. UpdateUsedRegs(UsedRegs, Pai(p^.Next));
  35. RegUsedAfterInstruction :=
  36. (Reg in UsedRegs) and
  37. (not(getNextInstruction(p,p)) or
  38. not(regLoadedWithNewValue(reg,false,p)));
  39. End;
  40. function doFpuLoadStoreOpt(asmL: paasmoutput; var p: pai): boolean;
  41. { returns true if a "continue" should be done after this optimization }
  42. var hp1, hp2: pai;
  43. begin
  44. doFpuLoadStoreOpt := false;
  45. if (paicpu(p)^.oper[0].typ = top_ref) and
  46. getNextInstruction(p, hp1) and
  47. (hp1^.typ = ait_instruction) and
  48. (((paicpu(hp1)^.opcode = A_FLD) and
  49. (paicpu(p)^.opcode = A_FSTP)) or
  50. ((paicpu(p)^.opcode = A_FISTP) and
  51. (paicpu(hp1)^.opcode = A_FILD))) and
  52. (paicpu(hp1)^.oper[0].typ = top_ref) and
  53. (paicpu(hp1)^.opsize = Paicpu(p)^.opsize) and
  54. refsEqual(paicpu(p)^.oper[0].ref^, paicpu(hp1)^.oper[0].ref^) then
  55. begin
  56. if getNextInstruction(hp1, hp2) and
  57. (hp2^.typ = ait_instruction) and
  58. ((paicpu(hp2)^.opcode = A_LEAVE) or
  59. (paicpu(hp2)^.opcode = A_RET)) and
  60. (paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) and
  61. (paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) and
  62. (paicpu(p)^.oper[0].ref^.Index = R_NO) then
  63. begin
  64. asmL^.remove(p);
  65. asmL^.remove(hp1);
  66. dispose(p, done);
  67. dispose(hp1, done);
  68. p := hp2;
  69. removeLastDeallocForFuncRes(asmL, p);
  70. doFPULoadStoreOpt := true;
  71. end
  72. else
  73. { fst can't store an extended value! }
  74. if (paicpu(p)^.opsize <> S_FX) and
  75. (paicpu(p)^.opsize <> S_IQ) then
  76. begin
  77. if (paicpu(p)^.opcode = A_FSTP) then
  78. paicpu(p)^.opcode := A_FST
  79. else Paicpu(p)^.opcode := A_FIST;
  80. asmL^.remove(hp1);
  81. dispose(hp1, done)
  82. end
  83. end;
  84. end;
  85. Procedure PeepHoleOptPass1(Asml: PAasmOutput; BlockStart, BlockEnd: Pai);
  86. {First pass of peepholeoptimizations}
  87. Var
  88. l,l1 : longint;
  89. p,hp1,hp2 : pai;
  90. hp3,hp4: pai;
  91. TmpRef: TReference;
  92. UsedRegs, TmpUsedRegs: TRegSet;
  93. TmpBool1, TmpBool2: Boolean;
  94. Function SkipLabels(hp: Pai; var hp2: pai): boolean;
  95. {skips all labels and returns the next "real" instruction}
  96. Begin
  97. While assigned(hp^.next) and
  98. (pai(hp^.next)^.typ In SkipInstr + [ait_label,ait_align]) Do
  99. hp := pai(hp^.next);
  100. If assigned(hp^.next) Then
  101. Begin
  102. SkipLabels := True;
  103. hp2 := pai(hp^.next)
  104. End
  105. Else
  106. Begin
  107. hp2 := hp;
  108. SkipLabels := False
  109. End;
  110. End;
  111. Procedure GetFinalDestination(AsmL: PAAsmOutput; hp: paicpu);
  112. {traces sucessive jumps to their final destination and sets it, e.g.
  113. je l1 je l3
  114. <code> <code>
  115. l1: becomes l1:
  116. je l2 je l3
  117. <code> <code>
  118. l2: l2:
  119. jmp l3 jmp l3}
  120. Var p1, p2: pai;
  121. l: pasmlabel;
  122. Function FindAnyLabel(hp: pai; var l: pasmlabel): Boolean;
  123. Begin
  124. FindAnyLabel := false;
  125. While assigned(hp^.next) and
  126. (pai(hp^.next)^.typ In (SkipInstr+[ait_align])) Do
  127. hp := pai(hp^.next);
  128. If assigned(hp^.next) and
  129. (pai(hp^.next)^.typ = ait_label) Then
  130. Begin
  131. FindAnyLabel := true;
  132. l := pai_label(hp^.next)^.l;
  133. End
  134. End;
  135. Begin
  136. If (pasmlabel(hp^.oper[0].sym)^.labelnr >= LoLab) and
  137. (pasmlabel(hp^.oper[0].sym)^.labelnr <= HiLab) and {range check, a jump can go past an assembler block!}
  138. Assigned(LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj) Then
  139. Begin
  140. p1 := LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj; {the jump's destination}
  141. SkipLabels(p1,p1);
  142. If (pai(p1)^.typ = ait_instruction) and
  143. (paicpu(p1)^.is_jmp) Then
  144. If { the next instruction after the label where the jump hp arrives}
  145. { is unconditional or of the same type as hp, so continue }
  146. (paicpu(p1)^.condition in [C_None,hp^.condition]) or
  147. { the next instruction after the label where the jump hp arrives}
  148. { is the opposite of hp (so this one is never taken), but after }
  149. { that one there is a branch that will be taken, so perform a }
  150. { little hack: set p1 equal to this instruction (that's what the}
  151. { last SkipLabels is for, only works with short bool evaluation)}
  152. ((paicpu(p1)^.condition = inverse_cond[hp^.condition]) and
  153. SkipLabels(p1,p2) and
  154. (p2^.typ = ait_instruction) and
  155. (paicpu(p2)^.is_jmp) and
  156. (paicpu(p2)^.condition in [C_None,hp^.condition]) and
  157. SkipLabels(p1,p1)) Then
  158. Begin
  159. GetFinalDestination(asml, paicpu(p1));
  160. Dec(pasmlabel(hp^.oper[0].sym)^.refs);
  161. hp^.oper[0].sym:=paicpu(p1)^.oper[0].sym;
  162. inc(pasmlabel(hp^.oper[0].sym)^.refs);
  163. End
  164. Else
  165. If (paicpu(p1)^.condition = inverse_cond[hp^.condition]) then
  166. if not FindAnyLabel(p1,l) then
  167. begin
  168. {$ifdef finaldestdebug}
  169. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  170. strpnew('previous label inserted'))));
  171. {$endif finaldestdebug}
  172. getlabel(l);
  173. insertllitem(asml,p1,p1^.next,new(pai_label,init(l)));
  174. dec(pasmlabel(paicpu(hp)^.oper[0].sym)^.refs);
  175. hp^.oper[0].sym := l;
  176. inc(l^.refs);
  177. { this won't work, since the new label isn't in the labeltable }
  178. { so it will fail the rangecheck. Labeltable should become a }
  179. { hashtable to support this: }
  180. { GetFinalDestination(asml, hp); }
  181. end
  182. else
  183. begin
  184. {$ifdef finaldestdebug}
  185. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  186. strpnew('next label reused'))));
  187. {$endif finaldestdebug}
  188. inc(l^.refs);
  189. hp^.oper[0].sym := l;
  190. GetFinalDestination(asml, hp);
  191. end;
  192. End;
  193. End;
  194. Function DoSubAddOpt(var p: Pai): Boolean;
  195. Begin
  196. DoSubAddOpt := False;
  197. If GetLastInstruction(p, hp1) And
  198. (hp1^.typ = ait_instruction) And
  199. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) then
  200. Case Paicpu(hp1)^.opcode Of
  201. A_DEC:
  202. If (Paicpu(hp1)^.oper[0].typ = top_reg) And
  203. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) Then
  204. Begin
  205. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+1);
  206. AsmL^.Remove(hp1);
  207. Dispose(hp1, Done)
  208. End;
  209. A_SUB:
  210. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  211. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  212. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  213. Begin
  214. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+Paicpu(hp1)^.oper[0].val);
  215. AsmL^.Remove(hp1);
  216. Dispose(hp1, Done)
  217. End;
  218. A_ADD:
  219. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  220. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  221. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  222. Begin
  223. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  224. AsmL^.Remove(hp1);
  225. Dispose(hp1, Done);
  226. If (Paicpu(p)^.oper[0].val = 0) Then
  227. Begin
  228. hp1 := Pai(p^.next);
  229. AsmL^.Remove(p);
  230. Dispose(p, Done);
  231. If Not GetLastInstruction(hp1, p) Then
  232. p := hp1;
  233. DoSubAddOpt := True;
  234. End
  235. End;
  236. End;
  237. End;
  238. Begin
  239. P := BlockStart;
  240. UsedRegs := [];
  241. While (P <> BlockEnd) Do
  242. Begin
  243. UpDateUsedRegs(UsedRegs, Pai(p^.next));
  244. Case P^.Typ Of
  245. ait_instruction:
  246. Begin
  247. { Handle Jmp Optimizations }
  248. if Paicpu(p)^.is_jmp then
  249. begin
  250. {the following if-block removes all code between a jmp and the next label,
  251. because it can never be executed}
  252. If (paicpu(p)^.opcode = A_JMP) Then
  253. Begin
  254. While GetNextInstruction(p, hp1) and
  255. ((hp1^.typ <> ait_label) or
  256. { skip unused labels, they're not referenced anywhere }
  257. labelCanBeSkipped(pai_label(hp1))) Do
  258. If not(hp1^.typ in ([ait_label,ait_align]+skipinstr)) Then
  259. Begin
  260. AsmL^.Remove(hp1);
  261. Dispose(hp1, done);
  262. End
  263. else break;
  264. End;
  265. If GetNextInstruction(p, hp1) then
  266. Begin
  267. if FindLabel(pasmlabel(paicpu(p)^.oper[0].sym), hp1) then
  268. Begin
  269. hp2:=pai(hp1^.next);
  270. asml^.remove(p);
  271. dispose(p,done);
  272. p:=hp2;
  273. continue;
  274. end
  275. Else
  276. Begin
  277. if hp1^.typ = ait_label then
  278. SkipLabels(hp1,hp1);
  279. If (pai(hp1)^.typ=ait_instruction) and
  280. (paicpu(hp1)^.opcode=A_JMP) and
  281. GetNextInstruction(hp1, hp2) And
  282. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym), hp2)
  283. Then
  284. Begin
  285. if paicpu(p)^.opcode=A_Jcc then
  286. paicpu(p)^.condition:=inverse_cond[paicpu(p)^.condition]
  287. else
  288. begin
  289. If (LabDif <> 0) Then
  290. GetFinalDestination(asml, paicpu(p));
  291. p:=pai(p^.next);
  292. continue;
  293. end;
  294. Dec(pai_label(hp2)^.l^.refs);
  295. paicpu(p)^.oper[0].sym:=paicpu(hp1)^.oper[0].sym;
  296. Inc(paicpu(p)^.oper[0].sym^.refs);
  297. asml^.remove(hp1);
  298. dispose(hp1,done);
  299. If (LabDif <> 0) Then
  300. GetFinalDestination(asml, paicpu(p));
  301. end
  302. else
  303. If (LabDif <> 0) Then
  304. GetFinalDestination(asml, paicpu(p));
  305. end;
  306. end;
  307. end
  308. else
  309. { All other optimizes }
  310. begin
  311. For l := 0 to 2 Do
  312. If (Paicpu(p)^.oper[l].typ = top_ref) Then
  313. With Paicpu(p)^.oper[l].ref^ Do
  314. Begin
  315. If (base = R_NO) And
  316. (index <> R_NO) And
  317. (scalefactor in [0,1])
  318. Then
  319. Begin
  320. base := index;
  321. index := R_NO
  322. End
  323. End;
  324. Case Paicpu(p)^.opcode Of
  325. A_AND:
  326. Begin
  327. If (Paicpu(p)^.oper[0].typ = top_const) And
  328. (Paicpu(p)^.oper[1].typ = top_reg) And
  329. GetNextInstruction(p, hp1) And
  330. (Pai(hp1)^.typ = ait_instruction) And
  331. (Paicpu(hp1)^.opcode = A_AND) And
  332. (Paicpu(hp1)^.oper[0].typ = top_const) And
  333. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  334. (Paicpu(hp1)^.oper[1].reg = Paicpu(hp1)^.oper[1].reg)
  335. Then
  336. {change "and const1, reg; and const2, reg" to "and (const1 and const2), reg"}
  337. Begin
  338. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val And Paicpu(hp1)^.oper[0].val);
  339. AsmL^.Remove(hp1);
  340. Dispose(hp1, Done)
  341. End
  342. Else
  343. {change "and x, reg; jxx" to "test x, reg", if reg is deallocated before the
  344. jump, but only if it's a conditional jump (PFV) }
  345. If (Paicpu(p)^.oper[1].typ = top_reg) And
  346. GetNextInstruction(p, hp1) And
  347. (hp1^.typ = ait_instruction) And
  348. (Paicpu(hp1)^.is_jmp) and
  349. (Paicpu(hp1)^.opcode<>A_JMP) and
  350. Not(Paicpu(p)^.oper[1].reg in UsedRegs) Then
  351. Paicpu(p)^.opcode := A_TEST;
  352. End;
  353. A_CMP:
  354. Begin
  355. If (Paicpu(p)^.oper[0].typ = top_const) And
  356. (Paicpu(p)^.oper[1].typ in [top_reg,top_ref]) And
  357. (Paicpu(p)^.oper[0].val = 0) Then
  358. If GetNextInstruction(p, hp1) And
  359. (hp1^.typ = ait_instruction) And
  360. (Paicpu(hp1)^.is_jmp) and
  361. (paicpu(hp1)^.opcode=A_Jcc) and
  362. (paicpu(hp1)^.condition in [C_LE,C_BE]) and
  363. GetNextInstruction(hp1,hp2) and
  364. (hp2^.typ = ait_instruction) and
  365. (Paicpu(hp2)^.opcode = A_DEC) And
  366. OpsEqual(Paicpu(hp2)^.oper[0],Paicpu(p)^.oper[1]) And
  367. GetNextInstruction(hp2, hp3) And
  368. (hp3^.typ = ait_instruction) and
  369. (Paicpu(hp3)^.is_jmp) and
  370. (Paicpu(hp3)^.opcode = A_JMP) And
  371. GetNextInstruction(hp3, hp4) And
  372. FindLabel(PAsmLabel(paicpu(hp1)^.oper[0].sym),hp4)
  373. Then
  374. Begin
  375. Paicpu(hp2)^.Opcode := A_SUB;
  376. Paicpu(hp2)^.Loadoper(1,Paicpu(hp2)^.oper[0]);
  377. Paicpu(hp2)^.LoadConst(0,1);
  378. Paicpu(hp2)^.ops:=2;
  379. Paicpu(hp3)^.Opcode := A_Jcc;
  380. Case paicpu(hp1)^.condition of
  381. C_LE: Paicpu(hp3)^.condition := C_GE;
  382. C_BE: Paicpu(hp3)^.condition := C_AE;
  383. End;
  384. AsmL^.Remove(p);
  385. AsmL^.Remove(hp1);
  386. Dispose(p, Done);
  387. Dispose(hp1, Done);
  388. p := hp2;
  389. continue;
  390. End
  391. Else
  392. {change "cmp $0, %reg" to "test %reg, %reg"}
  393. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  394. Begin
  395. Paicpu(p)^.opcode := A_TEST;
  396. Paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  397. End;
  398. End;
  399. A_FLD:
  400. Begin
  401. If (Paicpu(p)^.oper[0].typ = top_reg) And
  402. GetNextInstruction(p, hp1) And
  403. (hp1^.typ = Ait_Instruction) And
  404. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  405. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  406. (Paicpu(hp1)^.oper[0].reg = R_ST) And
  407. (Paicpu(hp1)^.oper[1].reg = R_ST1) Then
  408. { change to
  409. fld reg fxxx reg,st
  410. fxxxp st, st1 (hp1)
  411. Remark: non commutative operations must be reversed!
  412. }
  413. begin
  414. Case Paicpu(hp1)^.opcode Of
  415. A_FMULP,A_FADDP,
  416. A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  417. begin
  418. Case Paicpu(hp1)^.opcode Of
  419. A_FADDP: Paicpu(hp1)^.opcode := A_FADD;
  420. A_FMULP: Paicpu(hp1)^.opcode := A_FMUL;
  421. A_FSUBP: Paicpu(hp1)^.opcode := A_FSUBR;
  422. A_FSUBRP: Paicpu(hp1)^.opcode := A_FSUB;
  423. A_FDIVP: Paicpu(hp1)^.opcode := A_FDIVR;
  424. A_FDIVRP: Paicpu(hp1)^.opcode := A_FDIV;
  425. End;
  426. Paicpu(hp1)^.oper[0].reg := Paicpu(p)^.oper[0].reg;
  427. Paicpu(hp1)^.oper[1].reg := R_ST;
  428. AsmL^.Remove(p);
  429. Dispose(p, Done);
  430. p := hp1;
  431. Continue;
  432. end;
  433. end;
  434. end
  435. else
  436. If (Paicpu(p)^.oper[0].typ = top_ref) And
  437. GetNextInstruction(p, hp2) And
  438. (hp2^.typ = Ait_Instruction) And
  439. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  440. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  441. (Paicpu(p)^.opsize in [S_FS, S_FL]) And
  442. (Paicpu(hp2)^.oper[0].reg = R_ST) And
  443. (Paicpu(hp2)^.oper[1].reg = R_ST1) Then
  444. If GetLastInstruction(p, hp1) And
  445. (hp1^.typ = Ait_Instruction) And
  446. ((Paicpu(hp1)^.opcode = A_FLD) Or
  447. (Paicpu(hp1)^.opcode = A_FST)) And
  448. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  449. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  450. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^) Then
  451. If ((Paicpu(hp2)^.opcode = A_FMULP) Or
  452. (Paicpu(hp2)^.opcode = A_FADDP)) Then
  453. { change to
  454. fld/fst mem1 (hp1) fld/fst mem1
  455. fld mem1 (p) fadd/
  456. faddp/ fmul st, st
  457. fmulp st, st1 (hp2) }
  458. Begin
  459. AsmL^.Remove(p);
  460. Dispose(p, Done);
  461. p := hp1;
  462. If (Paicpu(hp2)^.opcode = A_FADDP) Then
  463. Paicpu(hp2)^.opcode := A_FADD
  464. Else
  465. Paicpu(hp2)^.opcode := A_FMUL;
  466. Paicpu(hp2)^.oper[1].reg := R_ST;
  467. End
  468. Else
  469. { change to
  470. fld/fst mem1 (hp1) fld/fst mem1
  471. fld mem1 (p) fld st}
  472. Begin
  473. Paicpu(p)^.changeopsize(S_FL);
  474. Paicpu(p)^.loadreg(0,R_ST);
  475. End
  476. Else
  477. Begin
  478. Case Paicpu(hp2)^.opcode Of
  479. A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  480. { change to
  481. fld/fst mem1 (hp1) fld/fst mem1
  482. fld mem2 (p) fxxx mem2
  483. fxxxp st, st1 (hp2) }
  484. Begin
  485. Case Paicpu(hp2)^.opcode Of
  486. A_FADDP: Paicpu(p)^.opcode := A_FADD;
  487. A_FMULP: Paicpu(p)^.opcode := A_FMUL;
  488. A_FSUBP: Paicpu(p)^.opcode := A_FSUBR;
  489. A_FSUBRP: Paicpu(p)^.opcode := A_FSUB;
  490. A_FDIVP: Paicpu(p)^.opcode := A_FDIVR;
  491. A_FDIVRP: Paicpu(p)^.opcode := A_FDIV;
  492. End;
  493. AsmL^.Remove(hp2);
  494. Dispose(hp2, Done)
  495. End
  496. End
  497. End
  498. End;
  499. A_FSTP,A_FISTP:
  500. if doFpuLoadStoreOpt(asmL,p) then
  501. continue;
  502. A_IMUL:
  503. {changes certain "imul const, %reg"'s to lea sequences}
  504. Begin
  505. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  506. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  507. (Paicpu(p)^.opsize = S_L) Then
  508. If (Paicpu(p)^.oper[0].val = 1) Then
  509. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  510. {remove "imul $1, reg"}
  511. Begin
  512. hp1 := Pai(p^.Next);
  513. AsmL^.Remove(p);
  514. Dispose(p, Done);
  515. p := hp1;
  516. Continue;
  517. End
  518. Else
  519. {change "imul $1, reg1, reg2" to "mov reg1, reg2"}
  520. Begin
  521. hp1 := New(Paicpu, Op_Reg_Reg(A_MOV, S_L, Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[2].reg));
  522. InsertLLItem(AsmL, p^.previous, p^.next, hp1);
  523. Dispose(p, Done);
  524. p := hp1;
  525. End
  526. Else If
  527. ((Paicpu(p)^.oper[2].typ = Top_Reg) or
  528. (Paicpu(p)^.oper[2].typ = Top_None)) And
  529. (aktoptprocessor < ClassP6) And
  530. (Paicpu(p)^.oper[0].val <= 12) And
  531. Not(CS_LittleSize in aktglobalswitches) And
  532. (Not(GetNextInstruction(p, hp1)) Or
  533. {GetNextInstruction(p, hp1) And}
  534. Not((Pai(hp1)^.typ = ait_instruction) And
  535. ((paicpu(hp1)^.opcode=A_Jcc) and
  536. (paicpu(hp1)^.condition in [C_O,C_NO]))))
  537. Then
  538. Begin
  539. Reset_reference(tmpref);
  540. Case Paicpu(p)^.oper[0].val Of
  541. 3: Begin
  542. {imul 3, reg1, reg2 to
  543. lea (reg1,reg1,2), reg2
  544. imul 3, reg1 to
  545. lea (reg1,reg1,2), reg1}
  546. TmpRef.base := Paicpu(p)^.oper[1].reg;
  547. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  548. TmpRef.ScaleFactor := 2;
  549. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  550. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  551. Else
  552. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  553. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  554. Dispose(p, Done);
  555. p := hp1;
  556. End;
  557. 5: Begin
  558. {imul 5, reg1, reg2 to
  559. lea (reg1,reg1,4), reg2
  560. imul 5, reg1 to
  561. lea (reg1,reg1,4), reg1}
  562. TmpRef.base := Paicpu(p)^.oper[1].reg;
  563. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  564. TmpRef.ScaleFactor := 4;
  565. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  566. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  567. Else
  568. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  569. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  570. Dispose(p, Done);
  571. p := hp1;
  572. End;
  573. 6: Begin
  574. {imul 6, reg1, reg2 to
  575. lea (,reg1,2), reg2
  576. lea (reg2,reg1,4), reg2
  577. imul 6, reg1 to
  578. lea (reg1,reg1,2), reg1
  579. add reg1, reg1}
  580. If (aktoptprocessor <= Class386)
  581. Then
  582. Begin
  583. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  584. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  585. Then
  586. Begin
  587. TmpRef.base := Paicpu(p)^.oper[2].reg;
  588. TmpRef.ScaleFactor := 4;
  589. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  590. End
  591. Else
  592. Begin
  593. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  594. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  595. End;
  596. InsertLLItem(AsmL,p, p^.next, hp1);
  597. Reset_reference(tmpref);
  598. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  599. TmpRef.ScaleFactor := 2;
  600. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  601. Then
  602. Begin
  603. TmpRef.base := R_NO;
  604. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
  605. Paicpu(p)^.oper[2].reg));
  606. End
  607. Else
  608. Begin
  609. TmpRef.base := Paicpu(p)^.oper[1].reg;
  610. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  611. End;
  612. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  613. Dispose(p, Done);
  614. p := Pai(hp1^.next);
  615. End
  616. End;
  617. 9: Begin
  618. {imul 9, reg1, reg2 to
  619. lea (reg1,reg1,8), reg2
  620. imul 9, reg1 to
  621. lea (reg1,reg1,8), reg1}
  622. TmpRef.base := Paicpu(p)^.oper[1].reg;
  623. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  624. TmpRef.ScaleFactor := 8;
  625. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  626. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  627. Else
  628. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  629. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  630. Dispose(p, Done);
  631. p := hp1;
  632. End;
  633. 10: Begin
  634. {imul 10, reg1, reg2 to
  635. lea (reg1,reg1,4), reg2
  636. add reg2, reg2
  637. imul 10, reg1 to
  638. lea (reg1,reg1,4), reg1
  639. add reg1, reg1}
  640. If (aktoptprocessor <= Class386) Then
  641. Begin
  642. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  643. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  644. Paicpu(p)^.oper[2].reg,Paicpu(p)^.oper[2].reg))
  645. Else
  646. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  647. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  648. InsertLLItem(AsmL,p, p^.next, hp1);
  649. TmpRef.base := Paicpu(p)^.oper[1].reg;
  650. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  651. TmpRef.ScaleFactor := 4;
  652. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  653. Then
  654. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg))
  655. Else
  656. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  657. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  658. Dispose(p, Done);
  659. p := Pai(hp1^.next);
  660. End
  661. End;
  662. 12: Begin
  663. {imul 12, reg1, reg2 to
  664. lea (,reg1,4), reg2
  665. lea (,reg1,8) reg2
  666. imul 12, reg1 to
  667. lea (reg1,reg1,2), reg1
  668. lea (,reg1,4), reg1}
  669. If (aktoptprocessor <= Class386)
  670. Then
  671. Begin
  672. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  673. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  674. Begin
  675. TmpRef.base := Paicpu(p)^.oper[2].reg;
  676. TmpRef.ScaleFactor := 8;
  677. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  678. End
  679. Else
  680. Begin
  681. TmpRef.base := R_NO;
  682. TmpRef.ScaleFactor := 4;
  683. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  684. End;
  685. InsertLLItem(AsmL,p, p^.next, hp1);
  686. Reset_reference(tmpref);
  687. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  688. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  689. Begin
  690. TmpRef.base := R_NO;
  691. TmpRef.ScaleFactor := 4;
  692. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  693. End
  694. Else
  695. Begin
  696. TmpRef.base := Paicpu(p)^.oper[1].reg;
  697. TmpRef.ScaleFactor := 2;
  698. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  699. End;
  700. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  701. Dispose(p, Done);
  702. p := Pai(hp1^.next);
  703. End
  704. End
  705. End;
  706. End;
  707. End;
  708. A_LEA:
  709. Begin
  710. {removes seg register prefixes from LEA operations, as they
  711. don't do anything}
  712. Paicpu(p)^.oper[0].ref^.Segment := R_NO;
  713. {changes "lea (%reg1), %reg2" into "mov %reg1, %reg2"}
  714. If (Paicpu(p)^.oper[0].ref^.Base In [R_EAX..R_EDI]) And
  715. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  716. (Not(Assigned(Paicpu(p)^.oper[0].ref^.Symbol))) Then
  717. If (Paicpu(p)^.oper[0].ref^.Base <> Paicpu(p)^.oper[1].reg)
  718. and (Paicpu(p)^.oper[0].ref^.Offset = 0)
  719. Then
  720. Begin
  721. hp1 := New(Paicpu, op_reg_reg(A_MOV, S_L,Paicpu(p)^.oper[0].ref^.Base,
  722. Paicpu(p)^.oper[1].reg));
  723. InsertLLItem(AsmL,p^.previous,p^.next, hp1);
  724. Dispose(p, Done);
  725. p := hp1;
  726. Continue;
  727. End
  728. Else
  729. if (Paicpu(p)^.oper[0].ref^.Offset = 0) then
  730. Begin
  731. hp1 := Pai(p^.Next);
  732. AsmL^.Remove(p);
  733. Dispose(p, Done);
  734. p := hp1;
  735. Continue;
  736. End
  737. else
  738. with Paicpu(p)^.oper[0].ref^ do
  739. if (Base = Paicpu(p)^.oper[1].reg) then
  740. begin
  741. l := offset+offsetfixup;
  742. case l of
  743. 1,-1:
  744. begin
  745. if l = 1 then
  746. paicpu(p)^.opcode := A_INC
  747. else paicpu(p)^.opcode := A_DEC;
  748. paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  749. paicpu(p)^.ops := 1;
  750. end;
  751. else
  752. begin
  753. paicpu(p)^.opcode := A_ADD;
  754. paicpu(p)^.loadconst(0,offset+offsetfixup);
  755. end;
  756. end;
  757. end;
  758. End;
  759. A_MOV:
  760. Begin
  761. TmpUsedRegs := UsedRegs;
  762. If (Paicpu(p)^.oper[1].typ = top_reg) And
  763. (Paicpu(p)^.oper[1].reg In [R_EAX, R_EBX, R_EDX, R_EDI]) And
  764. GetNextInstruction(p, hp1) And
  765. (Pai(hp1)^.typ = ait_instruction) And
  766. (Paicpu(hp1)^.opcode = A_MOV) And
  767. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  768. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  769. Then
  770. {we have "mov x, %treg; mov %treg, y}
  771. If not(RegUsedAfterInstruction(Paicpu(p)^.oper[1].reg, hp1, TmpUsedRegs)) then
  772. {we've got "mov x, %treg; mov %treg, y; with %treg is not used after }
  773. Case Paicpu(p)^.oper[0].typ Of
  774. top_reg:
  775. Begin
  776. { change "mov %reg, %treg; mov %treg, y"
  777. to "mov %reg, y" }
  778. Paicpu(p)^.LoadOper(1,Paicpu(hp1)^.oper[1]);
  779. AsmL^.Remove(hp1);
  780. Dispose(hp1, Done);
  781. continue;
  782. End;
  783. top_ref:
  784. If (Paicpu(hp1)^.oper[1].typ = top_reg) Then
  785. Begin
  786. { change "mov mem, %treg; mov %treg, %reg"
  787. to "mov mem, %reg" }
  788. Paicpu(p)^.Loadoper(1,Paicpu(hp1)^.oper[1]);
  789. AsmL^.Remove(hp1);
  790. Dispose(hp1, Done);
  791. continue;
  792. End;
  793. End
  794. Else
  795. Else
  796. {Change "mov %reg1, %reg2; xxx %reg2, ???" to
  797. "mov %reg1, %reg2; xxx %reg1, ???" to avoid a write/read
  798. penalty}
  799. If (Paicpu(p)^.oper[0].typ = top_reg) And
  800. (Paicpu(p)^.oper[1].typ = top_reg) And
  801. GetNextInstruction(p,hp1) And
  802. (Pai(hp1)^.typ = ait_instruction) And
  803. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  804. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  805. Then
  806. {we have "mov %reg1, %reg2; XXX %reg2, ???"}
  807. Begin
  808. If ((Paicpu(hp1)^.opcode = A_OR) Or
  809. (Paicpu(hp1)^.opcode = A_TEST)) And
  810. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  811. (Paicpu(hp1)^.oper[0].reg = Paicpu(hp1)^.oper[1].reg)
  812. Then
  813. {we have "mov %reg1, %reg2; test/or %reg2, %reg2"}
  814. Begin
  815. TmpUsedRegs := UsedRegs;
  816. { reg1 will be used after the first instruction, }
  817. { so update the allocation info }
  818. allocRegBetween(asmL,paicpu(p)^.oper[0].reg,p,hp1);
  819. If GetNextInstruction(hp1, hp2) And
  820. (hp2^.typ = ait_instruction) And
  821. paicpu(hp2)^.is_jmp and
  822. Not(RegUsedAfterInstruction(Paicpu(hp1)^.oper[0].reg, hp1, TmpUsedRegs))
  823. Then
  824. {change "mov %reg1, %reg2; test/or %reg2, %reg2; jxx" to
  825. "test %reg1, %reg1; jxx"}
  826. Begin
  827. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  828. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  829. AsmL^.Remove(p);
  830. Dispose(p, done);
  831. p := hp1;
  832. continue
  833. End
  834. Else
  835. {change "mov %reg1, %reg2; test/or %reg2, %reg2" to
  836. "mov %reg1, %reg2; test/or %reg1, %reg1"}
  837. Begin
  838. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  839. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  840. End;
  841. End
  842. { Else
  843. If (Paicpu(p^.next)^.opcode
  844. In [A_PUSH, A_OR, A_XOR, A_AND, A_TEST])}
  845. {change "mov %reg1, %reg2; push/or/xor/... %reg2, ???" to
  846. "mov %reg1, %reg2; push/or/xor/... %reg1, ???"}
  847. End
  848. Else
  849. {leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
  850. x >= RetOffset) as it doesn't do anything (it writes either to a
  851. parameter or to the temporary storage room for the function
  852. result)}
  853. If GetNextInstruction(p, hp1) And
  854. (Pai(hp1)^.typ = ait_instruction)
  855. Then
  856. If ((Paicpu(hp1)^.opcode = A_LEAVE) Or
  857. (Paicpu(hp1)^.opcode = A_RET)) And
  858. (Paicpu(p)^.oper[1].typ = top_ref) And
  859. (Paicpu(p)^.oper[1].ref^.base = procinfo^.FramePointer) And
  860. (Paicpu(p)^.oper[1].ref^.offset >= procinfo^.Return_Offset) And
  861. (Paicpu(p)^.oper[1].ref^.index = R_NO) And
  862. (Paicpu(p)^.oper[0].typ = top_reg)
  863. Then
  864. Begin
  865. AsmL^.Remove(p);
  866. Dispose(p, done);
  867. p := hp1;
  868. RemoveLastDeallocForFuncRes(asmL,p);
  869. End
  870. Else
  871. If (Paicpu(p)^.oper[0].typ = top_reg) And
  872. (Paicpu(p)^.oper[1].typ = top_ref) And
  873. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) And
  874. (Paicpu(hp1)^.opcode = A_CMP) And
  875. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  876. RefsEqual(Paicpu(p)^.oper[1].ref^, Paicpu(hp1)^.oper[1].ref^) Then
  877. {change "mov reg1, mem1; cmp x, mem1" to "mov reg, mem1; cmp x, reg1"}
  878. begin
  879. Paicpu(hp1)^.loadreg(1,Paicpu(p)^.oper[0].reg);
  880. allocRegBetween(asmL,paicpu(p)^.oper[0].reg,p,hp1);
  881. end;
  882. { Next instruction is also a MOV ? }
  883. If GetNextInstruction(p, hp1) And
  884. (pai(hp1)^.typ = ait_instruction) and
  885. (Paicpu(hp1)^.opcode = A_MOV) and
  886. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize)
  887. Then
  888. Begin
  889. If (Paicpu(hp1)^.oper[0].typ = Paicpu(p)^.oper[1].typ) and
  890. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[0].typ)
  891. Then
  892. {mov reg1, mem1 or mov mem1, reg1
  893. mov mem2, reg2 mov reg2, mem2}
  894. Begin
  895. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  896. {mov reg1, mem1 or mov mem1, reg1
  897. mov mem2, reg1 mov reg2, mem1}
  898. Begin
  899. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[1]) Then
  900. { Removes the second statement from
  901. mov reg1, mem1/reg2
  902. mov mem1/reg2, reg1 }
  903. Begin
  904. if (paicpu(p)^.oper[0].typ = top_reg) then
  905. AllocRegBetween(asmL,paicpu(p)^.oper[0].reg,p,hp1);
  906. AsmL^.remove(hp1);
  907. Dispose(hp1,done);
  908. End
  909. Else
  910. Begin
  911. TmpUsedRegs := UsedRegs;
  912. UpdateUsedRegs(TmpUsedRegs, Pai(hp1^.next));
  913. If (Paicpu(p)^.oper[0].typ = top_reg) And
  914. { mov reg1, mem1
  915. mov mem2, reg1 }
  916. GetNextInstruction(hp1, hp2) And
  917. (hp2^.typ = ait_instruction) And
  918. (Paicpu(hp2)^.opcode = A_CMP) And
  919. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  920. (Paicpu(hp2)^.oper[0].typ = TOp_Ref) And
  921. (Paicpu(hp2)^.oper[1].typ = TOp_Reg) And
  922. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(p)^.oper[1].ref^) And
  923. (Paicpu(hp2)^.oper[1].reg = Paicpu(p)^.oper[0].reg) And
  924. Not(RegUsedAfterInstruction(Paicpu(p)^.oper[0].reg, hp2, TmpUsedRegs)) Then
  925. { change to
  926. mov reg1, mem1 mov reg1, mem1
  927. mov mem2, reg1 cmp reg1, mem2
  928. cmp mem1, reg1 }
  929. Begin
  930. AsmL^.Remove(hp2);
  931. Dispose(hp2, Done);
  932. Paicpu(hp1)^.opcode := A_CMP;
  933. Paicpu(hp1)^.loadref(1,newreference(Paicpu(hp1)^.oper[0].ref^));
  934. Paicpu(hp1)^.loadreg(0,Paicpu(p)^.oper[0].reg);
  935. End;
  936. End;
  937. End
  938. Else
  939. Begin
  940. tmpUsedRegs := UsedRegs;
  941. If GetNextInstruction(hp1, hp2) And
  942. (Paicpu(p)^.oper[0].typ = top_ref) And
  943. (Paicpu(p)^.oper[1].typ = top_reg) And
  944. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  945. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  946. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  947. (Pai(hp2)^.typ = ait_instruction) And
  948. (Paicpu(hp2)^.opcode = A_MOV) And
  949. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  950. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  951. (Paicpu(hp2)^.oper[0].typ = top_ref) And
  952. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(hp1)^.oper[1].ref^) Then
  953. If not regInRef(Paicpu(hp2)^.oper[1].reg,Paicpu(hp2)^.oper[0].ref^) and
  954. (Paicpu(p)^.oper[1].reg in [R_DI,R_EDI]) and
  955. not(RegUsedAfterInstruction(R_EDI,hp1,tmpUsedRegs)) Then
  956. { mov mem1, %edi
  957. mov %edi, mem2
  958. mov mem2, reg2
  959. to:
  960. mov mem1, reg2
  961. mov reg2, mem2}
  962. Begin
  963. Paicpu(p)^.Loadoper(1,Paicpu(hp2)^.oper[1]);
  964. Paicpu(hp1)^.loadoper(0,Paicpu(hp2)^.oper[1]);
  965. AsmL^.Remove(hp2);
  966. Dispose(hp2,Done);
  967. End
  968. Else
  969. If (Paicpu(p)^.oper[1].reg <> Paicpu(hp2)^.oper[1].reg) And
  970. not(RegInRef(Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[0].ref^)) And
  971. not(RegInRef(Paicpu(hp2)^.oper[1].reg,Paicpu(hp2)^.oper[0].ref^))
  972. Then
  973. { mov mem1, reg1 mov mem1, reg1
  974. mov reg1, mem2 mov reg1, mem2
  975. mov mem2, reg2 mov mem2, reg1
  976. to: to:
  977. mov mem1, reg1 mov mem1, reg1
  978. mov mem1, reg2 mov reg1, mem2
  979. mov reg1, mem2
  980. or (if mem1 depends on reg1
  981. and/or if mem2 depends on reg2)
  982. to:
  983. mov mem1, reg1
  984. mov reg1, mem2
  985. mov reg1, reg2
  986. }
  987. Begin
  988. Paicpu(hp1)^.LoadRef(0,newreference(Paicpu(p)^.oper[0].ref^));
  989. Paicpu(hp1)^.LoadReg(1,Paicpu(hp2)^.oper[1].reg);
  990. Paicpu(hp2)^.LoadRef(1,newreference(Paicpu(hp2)^.oper[0].ref^));
  991. Paicpu(hp2)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  992. allocRegBetween(asmL,paicpu(p)^.oper[1].reg,p,hp2);
  993. if (paicpu(p)^.oper[0].ref^.base in (usableregs+[R_EDI])) then
  994. allocRegBetween(asmL,paicpu(p)^.oper[0].ref^.base,p,hp2);
  995. if (paicpu(p)^.oper[0].ref^.index in (usableregs+[R_EDI])) then
  996. allocRegBetween(asmL,paicpu(p)^.oper[0].ref^.index,p,hp2);
  997. End
  998. Else
  999. If (Paicpu(hp1)^.Oper[0].reg <> Paicpu(hp2)^.Oper[1].reg) Then
  1000. begin
  1001. Paicpu(hp2)^.LoadReg(0,Paicpu(hp1)^.Oper[0].reg);
  1002. allocRegBetween(asmL,paicpu(p)^.oper[1].reg,p,hp2);
  1003. end
  1004. else
  1005. begin
  1006. asmL^.Remove(hp2);
  1007. dispose(hp2, done);
  1008. end
  1009. End;
  1010. End
  1011. Else
  1012. (* {movl [mem1],reg1
  1013. movl [mem1],reg2
  1014. to:
  1015. movl [mem1],reg1
  1016. movl reg1,reg2 }
  1017. If (Paicpu(p)^.oper[0].typ = top_ref) and
  1018. (Paicpu(p)^.oper[1].typ = top_reg) and
  1019. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1020. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1021. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1022. RefsEqual(TReference(Paicpu(p)^.oper[0]^),Paicpu(hp1)^.oper[0]^.ref^) and
  1023. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.base) and
  1024. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.index) then
  1025. Paicpu(hp1)^.LoadReg(0,Paicpu(p)^.oper[1].reg)
  1026. Else*)
  1027. { movl const1,[mem1]
  1028. movl [mem1],reg1
  1029. to:
  1030. movl const1,reg1
  1031. movl reg1,[mem1] }
  1032. If (Paicpu(p)^.oper[0].typ = top_const) and
  1033. (Paicpu(p)^.oper[1].typ = top_ref) and
  1034. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1035. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1036. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1037. RefsEqual(Paicpu(hp1)^.oper[0].ref^,Paicpu(p)^.oper[1].ref^) then
  1038. Begin
  1039. allocregbetween(asml,Paicpu(hp1)^.oper[1].reg,p,hp1);
  1040. { allocregbetween doesn't insert this because at }
  1041. { this time, no regalloc info is available in }
  1042. { the optinfo field, so do it manually (JM) }
  1043. hp2 := new(paiRegalloc,alloc(Paicpu(hp1)^.oper[1].reg));
  1044. insertllitem(asml,p^.previous,p,hp2);
  1045. Paicpu(hp1)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1046. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[1].ref^));
  1047. Paicpu(p)^.LoadReg(1,Paicpu(hp1)^.oper[0].reg);
  1048. End
  1049. End;
  1050. End;
  1051. A_MOVZX:
  1052. Begin
  1053. {removes superfluous And's after movzx's}
  1054. If (Paicpu(p)^.oper[1].typ = top_reg) And
  1055. GetNextInstruction(p, hp1) And
  1056. (Pai(hp1)^.typ = ait_instruction) And
  1057. (Paicpu(hp1)^.opcode = A_AND) And
  1058. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1059. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1060. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1061. Then
  1062. Case Paicpu(p)^.opsize Of
  1063. S_BL, S_BW:
  1064. If (Paicpu(hp1)^.oper[0].val = $ff) Then
  1065. Begin
  1066. AsmL^.Remove(hp1);
  1067. Dispose(hp1, Done);
  1068. End;
  1069. S_WL:
  1070. If (Paicpu(hp1)^.oper[0].val = $ffff) Then
  1071. Begin
  1072. AsmL^.Remove(hp1);
  1073. Dispose(hp1, Done);
  1074. End;
  1075. End;
  1076. {changes some movzx constructs to faster synonims (all examples
  1077. are given with eax/ax, but are also valid for other registers)}
  1078. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1079. If (Paicpu(p)^.oper[0].typ = top_reg) Then
  1080. Case Paicpu(p)^.opsize of
  1081. S_BW:
  1082. Begin
  1083. If (Paicpu(p)^.oper[0].reg = Reg16ToReg8(Paicpu(p)^.oper[1].reg)) And
  1084. Not(CS_LittleSize In aktglobalswitches)
  1085. Then
  1086. {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
  1087. Begin
  1088. Paicpu(p)^.opcode := A_AND;
  1089. Paicpu(p)^.changeopsize(S_W);
  1090. Paicpu(p)^.LoadConst(0,$ff);
  1091. End
  1092. Else
  1093. If GetNextInstruction(p, hp1) And
  1094. (Pai(hp1)^.typ = ait_instruction) And
  1095. (Paicpu(hp1)^.opcode = A_AND) And
  1096. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1097. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1098. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1099. Then
  1100. {Change "movzbw %reg1, %reg2; andw $const, %reg2"
  1101. to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
  1102. Begin
  1103. Paicpu(p)^.opcode := A_MOV;
  1104. Paicpu(p)^.changeopsize(S_W);
  1105. Paicpu(p)^.LoadReg(0,Reg8ToReg16(Paicpu(p)^.oper[0].reg));
  1106. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1107. End;
  1108. End;
  1109. S_BL:
  1110. Begin
  1111. If (Paicpu(p)^.oper[0].reg = Reg32ToReg8(Paicpu(p)^.oper[1].reg)) And
  1112. Not(CS_LittleSize in aktglobalswitches)
  1113. Then
  1114. {Change "movzbl %al, %eax" to "andl $0x0ffh, %eax"}
  1115. Begin
  1116. Paicpu(p)^.opcode := A_AND;
  1117. Paicpu(p)^.changeopsize(S_L);
  1118. Paicpu(p)^.loadconst(0,$ff)
  1119. End
  1120. Else
  1121. If GetNextInstruction(p, hp1) And
  1122. (Pai(hp1)^.typ = ait_instruction) And
  1123. (Paicpu(hp1)^.opcode = A_AND) And
  1124. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1125. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1126. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1127. Then
  1128. {Change "movzbl %reg1, %reg2; andl $const, %reg2"
  1129. to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
  1130. Begin
  1131. Paicpu(p)^.opcode := A_MOV;
  1132. Paicpu(p)^.changeopsize(S_L);
  1133. Paicpu(p)^.LoadReg(0,Reg8ToReg32(Paicpu(p)^.oper[0].reg));
  1134. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1135. End
  1136. End;
  1137. S_WL:
  1138. Begin
  1139. If (Paicpu(p)^.oper[0].reg = Reg32ToReg16(Paicpu(p)^.oper[1].reg)) And
  1140. Not(CS_LittleSize In aktglobalswitches)
  1141. Then
  1142. {Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax"}
  1143. Begin
  1144. Paicpu(p)^.opcode := A_AND;
  1145. Paicpu(p)^.changeopsize(S_L);
  1146. Paicpu(p)^.LoadConst(0,$ffff);
  1147. End
  1148. Else
  1149. If GetNextInstruction(p, hp1) And
  1150. (Pai(hp1)^.typ = ait_instruction) And
  1151. (Paicpu(hp1)^.opcode = A_AND) And
  1152. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1153. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1154. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1155. Then
  1156. {Change "movzwl %reg1, %reg2; andl $const, %reg2"
  1157. to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
  1158. Begin
  1159. Paicpu(p)^.opcode := A_MOV;
  1160. Paicpu(p)^.changeopsize(S_L);
  1161. Paicpu(p)^.LoadReg(0,Reg16ToReg32(Paicpu(p)^.oper[0].reg));
  1162. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1163. End;
  1164. End;
  1165. End
  1166. Else
  1167. If (Paicpu(p)^.oper[0].typ = top_ref) Then
  1168. Begin
  1169. If GetNextInstruction(p, hp1) And
  1170. (Pai(hp1)^.typ = ait_instruction) And
  1171. (Paicpu(hp1)^.opcode = A_AND) And
  1172. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1173. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1174. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  1175. Begin
  1176. Paicpu(p)^.opcode := A_MOV;
  1177. Case Paicpu(p)^.opsize Of
  1178. S_BL:
  1179. Begin
  1180. Paicpu(p)^.changeopsize(S_L);
  1181. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1182. End;
  1183. S_WL:
  1184. Begin
  1185. Paicpu(p)^.changeopsize(S_L);
  1186. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1187. End;
  1188. S_BW:
  1189. Begin
  1190. Paicpu(p)^.changeopsize(S_W);
  1191. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1192. End;
  1193. End;
  1194. End;
  1195. End;
  1196. End;
  1197. A_POP:
  1198. Begin
  1199. if target_info.target=target_i386_go32v2 then
  1200. begin
  1201. { Transform a series of pop/pop/pop/push/push/push to }
  1202. { 'movl x(%esp),%reg' for go32v2 (not for the rest, }
  1203. { because I'm not sure whether they can cope with }
  1204. { 'movl x(%esp),%reg' with x > 0, I believe we had }
  1205. { such a problem when using esp as frame pointer (JM) }
  1206. if (Paicpu(p)^.oper[0].typ = top_reg) then
  1207. begin
  1208. hp1 := p;
  1209. hp2 := p;
  1210. l := 0;
  1211. while getNextInstruction(hp1,hp1) and
  1212. (hp1^.typ = ait_instruction) and
  1213. (paicpu(hp1)^.opcode = A_POP) and
  1214. (paicpu(hp1)^.oper[0].typ = top_reg) do
  1215. begin
  1216. hp2 := hp1;
  1217. inc(l,4);
  1218. end;
  1219. getLastInstruction(p,hp3);
  1220. l1 := 0;
  1221. while (hp2 <> hp3) and
  1222. assigned(hp1) and
  1223. (hp1^.typ = ait_instruction) and
  1224. (paicpu(hp1)^.opcode = A_PUSH) and
  1225. (paicpu(hp1)^.oper[0].typ = top_reg) and
  1226. (paicpu(hp1)^.oper[0].reg = paicpu(hp2)^.oper[0].reg) do
  1227. begin
  1228. { change it to a two op operation }
  1229. paicpu(hp2)^.oper[1].typ:=top_none;
  1230. paicpu(hp2)^.ops:=2;
  1231. paicpu(hp2)^.opcode := A_MOV;
  1232. paicpu(hp2)^.Loadoper(1,paicpu(hp1)^.oper[0]);
  1233. reset_reference(tmpref);
  1234. tmpRef.base := stack_pointer;
  1235. tmpRef.offset := l;
  1236. paicpu(hp2)^.loadRef(0,newReference(tmpRef));
  1237. hp4 := hp1;
  1238. getNextInstruction(hp1,hp1);
  1239. asmL^.remove(hp4);
  1240. dispose(hp4,done);
  1241. getLastInstruction(hp2,hp2);
  1242. dec(l,4);
  1243. inc(l1);
  1244. end;
  1245. if l <> -4 then
  1246. begin
  1247. inc(l,4);
  1248. for l1 := l1 downto 1 do
  1249. begin
  1250. getNextInstruction(hp2,hp2);
  1251. dec(paicpu(hp2)^.oper[0].ref^.offset,l);
  1252. end
  1253. end
  1254. end
  1255. end
  1256. else
  1257. begin
  1258. if (Paicpu(p)^.oper[0].typ = top_reg) And
  1259. GetNextInstruction(p, hp1) And
  1260. (pai(hp1)^.typ=ait_instruction) and
  1261. (Paicpu(hp1)^.opcode=A_PUSH) and
  1262. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  1263. (Paicpu(hp1)^.oper[0].reg=Paicpu(p)^.oper[0].reg) then
  1264. Begin
  1265. { change it to a two op operation }
  1266. Paicpu(p)^.oper[1].typ:=top_none;
  1267. Paicpu(p)^.ops:=2;
  1268. Paicpu(p)^.opcode := A_MOV;
  1269. Paicpu(p)^.Loadoper(1,Paicpu(p)^.oper[0]);
  1270. Reset_reference(tmpref);
  1271. TmpRef.base := R_ESP;
  1272. Paicpu(p)^.LoadRef(0,newReference(TmpRef));
  1273. AsmL^.Remove(hp1);
  1274. Dispose(hp1, Done)
  1275. End;
  1276. end;
  1277. end;
  1278. A_PUSH:
  1279. Begin
  1280. If (Paicpu(p)^.opsize = S_W) And
  1281. (Paicpu(p)^.oper[0].typ = Top_Const) And
  1282. GetNextInstruction(p, hp1) And
  1283. (Pai(hp1)^.typ = ait_instruction) And
  1284. (Paicpu(hp1)^.opcode = A_PUSH) And
  1285. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1286. (Paicpu(hp1)^.opsize = S_W) Then
  1287. Begin
  1288. Paicpu(p)^.changeopsize(S_L);
  1289. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val shl 16 + word(Paicpu(hp1)^.oper[0].val));
  1290. AsmL^.Remove(hp1);
  1291. Dispose(hp1, Done)
  1292. End;
  1293. End;
  1294. A_SHL, A_SAL:
  1295. Begin
  1296. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  1297. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  1298. (Paicpu(p)^.opsize = S_L) And
  1299. (Paicpu(p)^.oper[0].val <= 3)
  1300. {Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement}
  1301. Then
  1302. Begin
  1303. TmpBool1 := True; {should we check the next instruction?}
  1304. TmpBool2 := False; {have we found an add/sub which could be
  1305. integrated in the lea?}
  1306. Reset_reference(tmpref);
  1307. TmpRef.index := Paicpu(p)^.oper[1].reg;
  1308. TmpRef.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1309. While TmpBool1 And
  1310. GetNextInstruction(p, hp1) And
  1311. (Pai(hp1)^.typ = ait_instruction) And
  1312. ((Paicpu(hp1)^.opcode = A_ADD) Or
  1313. (Paicpu(hp1)^.opcode = A_SUB)) And
  1314. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1315. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Do
  1316. Begin
  1317. TmpBool1 := False;
  1318. If (Paicpu(hp1)^.oper[0].typ = Top_Const)
  1319. Then
  1320. Begin
  1321. TmpBool1 := True;
  1322. TmpBool2 := True;
  1323. If Paicpu(hp1)^.opcode = A_ADD Then
  1324. Inc(TmpRef.offset, Paicpu(hp1)^.oper[0].val)
  1325. Else
  1326. Dec(TmpRef.offset, Paicpu(hp1)^.oper[0].val);
  1327. AsmL^.Remove(hp1);
  1328. Dispose(hp1, Done);
  1329. End
  1330. Else
  1331. If (Paicpu(hp1)^.oper[0].typ = Top_Reg) And
  1332. (Paicpu(hp1)^.opcode = A_ADD) And
  1333. (TmpRef.base = R_NO) Then
  1334. Begin
  1335. TmpBool1 := True;
  1336. TmpBool2 := True;
  1337. TmpRef.base := Paicpu(hp1)^.oper[0].reg;
  1338. AsmL^.Remove(hp1);
  1339. Dispose(hp1, Done);
  1340. End;
  1341. End;
  1342. If TmpBool2 Or
  1343. ((aktoptprocessor < ClassP6) And
  1344. (Paicpu(p)^.oper[0].val <= 3) And
  1345. Not(CS_LittleSize in aktglobalswitches))
  1346. Then
  1347. Begin
  1348. If Not(TmpBool2) And
  1349. (Paicpu(p)^.oper[0].val = 1)
  1350. Then
  1351. Begin
  1352. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1353. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg))
  1354. End
  1355. Else hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
  1356. Paicpu(p)^.oper[1].reg));
  1357. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1358. Dispose(p, Done);
  1359. p := hp1;
  1360. End;
  1361. End
  1362. Else
  1363. If (aktoptprocessor < ClassP6) And
  1364. (Paicpu(p)^.oper[0].typ = top_const) And
  1365. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1366. If (Paicpu(p)^.oper[0].val = 1)
  1367. Then
  1368. {changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
  1369. but faster on a 486, and pairable in both U and V pipes on the Pentium
  1370. (unlike shl, which is only pairable in the U pipe)}
  1371. Begin
  1372. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1373. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1374. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1375. Dispose(p, done);
  1376. p := hp1;
  1377. End
  1378. Else If (Paicpu(p)^.opsize = S_L) and
  1379. (Paicpu(p)^.oper[0].val<= 3) Then
  1380. {changes "shl $2, %reg" to "lea (,%reg,4), %reg"
  1381. "shl $3, %reg" to "lea (,%reg,8), %reg}
  1382. Begin
  1383. Reset_reference(tmpref);
  1384. TmpRef.index := Paicpu(p)^.oper[1].reg;
  1385. TmpRef.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1386. hp1 := new(Paicpu,op_ref_reg(A_LEA,S_L,newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  1387. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1388. Dispose(p, done);
  1389. p := hp1;
  1390. End
  1391. End;
  1392. A_SAR, A_SHR:
  1393. {changes the code sequence
  1394. shr/sar const1, x
  1395. shl const2, x
  1396. to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
  1397. Begin
  1398. If GetNextInstruction(p, hp1) And
  1399. (pai(hp1)^.typ = ait_instruction) and
  1400. (Paicpu(hp1)^.opcode = A_SHL) and
  1401. (Paicpu(p)^.oper[0].typ = top_const) and
  1402. (Paicpu(hp1)^.oper[0].typ = top_const) and
  1403. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  1404. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[1].typ) And
  1405. OpsEqual(Paicpu(hp1)^.oper[1], Paicpu(p)^.oper[1])
  1406. Then
  1407. If (Paicpu(p)^.oper[0].val > Paicpu(hp1)^.oper[0].val) And
  1408. Not(CS_LittleSize In aktglobalswitches)
  1409. Then
  1410. { shr/sar const1, %reg
  1411. shl const2, %reg
  1412. with const1 > const2 }
  1413. Begin
  1414. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  1415. Paicpu(hp1)^.opcode := A_AND;
  1416. l := (1 shl (Paicpu(hp1)^.oper[0].val)) - 1;
  1417. Case Paicpu(p)^.opsize Of
  1418. S_L: Paicpu(hp1)^.LoadConst(0,l Xor longint(-1));
  1419. S_B: Paicpu(hp1)^.LoadConst(0,l Xor $ff);
  1420. S_W: Paicpu(hp1)^.LoadConst(0,l Xor $ffff);
  1421. End;
  1422. End
  1423. Else
  1424. If (Paicpu(p)^.oper[0].val<Paicpu(hp1)^.oper[0].val) And
  1425. Not(CS_LittleSize In aktglobalswitches)
  1426. Then
  1427. { shr/sar const1, %reg
  1428. shl const2, %reg
  1429. with const1 < const2 }
  1430. Begin
  1431. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val-Paicpu(p)^.oper[0].val);
  1432. Paicpu(p)^.opcode := A_AND;
  1433. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1434. Case Paicpu(p)^.opsize Of
  1435. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1436. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1437. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1438. End;
  1439. End
  1440. Else
  1441. { shr/sar const1, %reg
  1442. shl const2, %reg
  1443. with const1 = const2 }
  1444. if (Paicpu(p)^.oper[0].val = Paicpu(hp1)^.oper[0].val) then
  1445. Begin
  1446. Paicpu(p)^.opcode := A_AND;
  1447. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1448. Case Paicpu(p)^.opsize Of
  1449. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1450. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1451. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1452. End;
  1453. AsmL^.remove(hp1);
  1454. dispose(hp1, done);
  1455. End;
  1456. End;
  1457. A_SETcc :
  1458. { changes
  1459. setcc (funcres) setcc reg
  1460. movb (funcres), reg to leave/ret
  1461. leave/ret }
  1462. Begin
  1463. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1464. GetNextInstruction(p, hp1) And
  1465. GetNextInstruction(hp1, hp2) And
  1466. (hp2^.typ = ait_instruction) And
  1467. ((Paicpu(hp2)^.opcode = A_LEAVE) or
  1468. (Paicpu(hp2)^.opcode = A_RET)) And
  1469. (Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
  1470. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  1471. (Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) And
  1472. (hp1^.typ = ait_instruction) And
  1473. (Paicpu(hp1)^.opcode = A_MOV) And
  1474. (Paicpu(hp1)^.opsize = S_B) And
  1475. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1476. RefsEqual(Paicpu(hp1)^.oper[0].ref^, Paicpu(p)^.oper[0].ref^) Then
  1477. Begin
  1478. Paicpu(p)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1479. AsmL^.Remove(hp1);
  1480. Dispose(hp1, Done)
  1481. End
  1482. End;
  1483. A_SUB:
  1484. { * change "subl $2, %esp; pushw x" to "pushl x"}
  1485. { * change "sub/add const1, reg" or "dec reg" followed by
  1486. "sub const2, reg" to one "sub ..., reg" }
  1487. Begin
  1488. If (Paicpu(p)^.oper[0].typ = top_const) And
  1489. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1490. If (Paicpu(p)^.oper[0].val = 2) And
  1491. (Paicpu(p)^.oper[1].reg = R_ESP) and
  1492. { Don't do the sub/push optimization if the sub }
  1493. { comes from setting up the stack frame (JM) }
  1494. (not getLastInstruction(p,hp1) or
  1495. (hp1^.typ <> ait_instruction) or
  1496. (paicpu(hp1)^.opcode <> A_MOV) or
  1497. (paicpu(hp1)^.oper[0].typ <> top_reg) or
  1498. (paicpu(hp1)^.oper[0].reg <> R_ESP) or
  1499. (paicpu(hp1)^.oper[1].typ <> top_reg) or
  1500. (paicpu(hp1)^.oper[1].reg <> R_EBP)) then
  1501. Begin
  1502. hp1 := Pai(p^.next);
  1503. While Assigned(hp1) And
  1504. (Pai(hp1)^.typ In [ait_instruction]+SkipInstr) And
  1505. Not((Pai(hp1)^.typ = ait_instruction) And
  1506. ((Paicpu(hp1)^.opcode = A_CALL) or
  1507. (Paicpu(hp1)^.opcode = A_PUSH) or
  1508. ((Paicpu(hp1)^.opcode = A_MOV) And
  1509. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  1510. (Paicpu(hp1)^.oper[1].ref^.base = R_ESP)))) do
  1511. hp1 := Pai(hp1^.next);
  1512. If Assigned(hp1) And
  1513. (Pai(hp1)^.typ = ait_instruction) And
  1514. (Paicpu(hp1)^.opcode = A_PUSH) And
  1515. (Paicpu(hp1)^.opsize = S_W)
  1516. Then
  1517. Begin
  1518. Paicpu(hp1)^.changeopsize(S_L);
  1519. if Paicpu(hp1)^.oper[0].typ=top_reg then
  1520. Paicpu(hp1)^.LoadReg(0,Reg16ToReg32(Paicpu(hp1)^.oper[0].reg));
  1521. hp1 := Pai(p^.next);
  1522. AsmL^.Remove(p);
  1523. Dispose(p, Done);
  1524. p := hp1;
  1525. Continue
  1526. End;
  1527. If DoSubAddOpt(p) Then continue;
  1528. End
  1529. Else If DoSubAddOpt(p) Then Continue
  1530. End;
  1531. A_XOR:
  1532. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1533. (Paicpu(p)^.oper[1].typ = top_reg) And
  1534. (Paicpu(p)^.oper[0].reg = Paicpu(p)^.oper[1].reg) then
  1535. { temporarily change this to 'mov reg,0' to make it easier }
  1536. { for the CSE. Will be changed back in pass 2 }
  1537. begin
  1538. paicpu(p)^.opcode := A_MOV;
  1539. paicpu(p)^.loadconst(0,0);
  1540. end;
  1541. End;
  1542. end; { if is_jmp }
  1543. End;
  1544. { ait_label:
  1545. Begin
  1546. If labelCanBeSkipped(pai_label(p))
  1547. Then
  1548. Begin
  1549. hp1 := Pai(p^.next);
  1550. AsmL^.Remove(p);
  1551. Dispose(p, Done);
  1552. p := hp1;
  1553. Continue
  1554. End;
  1555. End;}
  1556. End;
  1557. p:=pai(p^.next);
  1558. end;
  1559. end;
  1560. function isFoldableArithOp(hp1: paicpu; reg: tregister): boolean;
  1561. begin
  1562. IsFoldableArithOp := False;
  1563. case hp1^.opcode of
  1564. A_ADD,A_SUB,A_OR,A_XOR,A_AND,A_SHL,A_SHR,A_SAR:
  1565. isFoldableArithOp :=
  1566. (paicpu(hp1)^.oper[0].typ in [top_reg,top_const]) and
  1567. (paicpu(hp1)^.oper[1].typ = top_reg) and
  1568. (paicpu(hp1)^.oper[1].reg = reg);
  1569. A_INC,A_DEC:
  1570. isFoldableArithOp :=
  1571. (paicpu(hp1)^.oper[0].typ = top_reg) and
  1572. (paicpu(hp1)^.oper[0].reg = reg);
  1573. end;
  1574. end;
  1575. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  1576. function CanBeCMOV(p : pai) : boolean;
  1577. begin
  1578. CanBeCMOV:=assigned(p) and (p^.typ=ait_instruction) and
  1579. (paicpu(p)^.opcode=A_MOV) and
  1580. (paicpu(p)^.opsize in [S_L,S_W]) and
  1581. (paicpu(p)^.oper[0].typ in [top_reg,top_ref]) and
  1582. (paicpu(p)^.oper[1].typ in [top_reg,top_ref]);
  1583. end;
  1584. var
  1585. p,hp1,hp2: pai;
  1586. {$ifdef USECMOV}
  1587. l : longint;
  1588. condition : tasmcond;
  1589. hp3: pai;
  1590. {$endif USECMOV}
  1591. UsedRegs, TmpUsedRegs: TRegSet;
  1592. Begin
  1593. P := BlockStart;
  1594. UsedRegs := [];
  1595. While (P <> BlockEnd) Do
  1596. Begin
  1597. UpdateUsedRegs(UsedRegs, Pai(p^.next));
  1598. Case P^.Typ Of
  1599. Ait_Instruction:
  1600. Begin
  1601. Case Paicpu(p)^.opcode Of
  1602. A_CALL:
  1603. If (AktOptProcessor < ClassP6) And
  1604. GetNextInstruction(p, hp1) And
  1605. (hp1^.typ = ait_instruction) And
  1606. (paicpu(hp1)^.opcode = A_JMP) Then
  1607. Begin
  1608. Inc(paicpu(hp1)^.oper[0].sym^.refs);
  1609. hp2 := New(Paicpu,op_sym(A_PUSH,S_L,paicpu(hp1)^.oper[0].sym));
  1610. InsertLLItem(AsmL, p^.previous, p, hp2);
  1611. Paicpu(p)^.opcode := A_JMP;
  1612. AsmL^.Remove(hp1);
  1613. Dispose(hp1, Done)
  1614. End;
  1615. {$ifdef USECMOV}
  1616. A_Jcc:
  1617. if (aktspecificoptprocessor=ClassP6) then
  1618. begin
  1619. { check for
  1620. jCC xxx
  1621. <several movs>
  1622. xxx:
  1623. }
  1624. l:=0;
  1625. GetNextInstruction(p, hp1);
  1626. while assigned(hp1) And
  1627. CanBeCMOV(hp1) do
  1628. begin
  1629. inc(l);
  1630. GetNextInstruction(hp1,hp1);
  1631. end;
  1632. if assigned(hp1) then
  1633. begin
  1634. if FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym),hp1) then
  1635. begin
  1636. if (l<=4) and (l>0) then
  1637. begin
  1638. condition:=inverse_cond[paicpu(p)^.condition];
  1639. GetNextInstruction(p,hp1);
  1640. asml^.remove(p);
  1641. dispose(p,done);
  1642. p:=hp1;
  1643. repeat
  1644. paicpu(hp1)^.opcode:=A_CMOVcc;
  1645. paicpu(hp1)^.condition:=condition;
  1646. GetNextInstruction(hp1,hp1);
  1647. until not(assigned(hp1)) or
  1648. not(CanBeCMOV(hp1));
  1649. asml^.remove(hp1);
  1650. dispose(hp1,done);
  1651. continue;
  1652. end;
  1653. end
  1654. else
  1655. begin
  1656. { check further for
  1657. jCC xxx
  1658. <several movs>
  1659. jmp yyy
  1660. xxx:
  1661. <several movs>
  1662. yyy:
  1663. }
  1664. { hp2 points to jmp xxx }
  1665. hp2:=hp1;
  1666. { skip hp1 to xxx }
  1667. GetNextInstruction(hp1, hp1);
  1668. if assigned(hp2) and
  1669. assigned(hp1) and
  1670. (l<=3) and
  1671. (hp2^.typ=ait_instruction) and
  1672. (paicpu(hp2)^.is_jmp) and
  1673. (paicpu(hp2)^.condition=C_None) and
  1674. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym),hp1) then
  1675. begin
  1676. l:=0;
  1677. while assigned(hp1) And
  1678. CanBeCMOV(hp1) do
  1679. begin
  1680. inc(l);
  1681. GetNextInstruction(hp1, hp1);
  1682. end;
  1683. end;
  1684. {
  1685. if assigned(hp1) and
  1686. FindLabel(PAsmLabel(paicpu(hp2)^.oper[0].sym),hp1) then
  1687. begin
  1688. condition:=inverse_cond[paicpu(p)^.condition];
  1689. GetNextInstruction(p,hp1);
  1690. asml^.remove(p);
  1691. dispose(p,done);
  1692. p:=hp1;
  1693. repeat
  1694. paicpu(hp1)^.opcode:=A_CMOVcc;
  1695. paicpu(hp1)^.condition:=condition;
  1696. GetNextInstruction(hp1,hp1);
  1697. until not(assigned(hp1)) or
  1698. not(CanBeCMOV(hp1));
  1699. hp2:=hp1^.next;
  1700. condition:=inverse_cond[condition];
  1701. asml^.remove(hp1^.next)
  1702. dispose(hp1^.next,done);
  1703. asml^.remove(hp1);
  1704. dispose(hp1,done);
  1705. continue;
  1706. end;
  1707. }
  1708. end;
  1709. end;
  1710. end;
  1711. {$endif USECMOV}
  1712. A_FSTP,A_FISTP:
  1713. if doFpuLoadStoreOpt(asmL,p) then
  1714. continue;
  1715. A_IMUL:
  1716. begin
  1717. if ((paicpu(p)^.oper[0].typ = top_const) or
  1718. (paicpu(p)^.oper[0].typ = top_symbol)) and
  1719. (paicpu(p)^.oper[1].typ = top_reg) and
  1720. ((paicpu(p)^.oper[2].typ = top_none) or
  1721. ((paicpu(p)^.oper[2].typ = top_reg) and
  1722. (paicpu(p)^.oper[2].reg = paicpu(p)^.oper[1].reg))) and
  1723. getLastInstruction(p,hp1) and
  1724. (hp1^.typ = ait_instruction) and
  1725. (paicpu(hp1)^.opcode = A_MOV) and
  1726. (paicpu(hp1)^.oper[0].typ = top_reg) and
  1727. (paicpu(hp1)^.oper[1].typ = top_reg) and
  1728. (paicpu(hp1)^.oper[1].reg = paicpu(p)^.oper[1].reg) then
  1729. { change "mov reg1,reg2; imul y,reg2" to "imul y,reg1,reg2" }
  1730. begin
  1731. paicpu(p)^.ops := 3;
  1732. paicpu(p)^.loadreg(1,paicpu(hp1)^.oper[0].reg);
  1733. paicpu(p)^.loadreg(2,paicpu(hp1)^.oper[1].reg);
  1734. asmL^.remove(hp1);
  1735. dispose(hp1,done);
  1736. end;
  1737. end;
  1738. A_MOV:
  1739. Begin
  1740. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1741. (Paicpu(p)^.oper[1].typ = top_reg) And
  1742. GetNextInstruction(p, hp1) And
  1743. (hp1^.typ = ait_Instruction) And
  1744. ((Paicpu(hp1)^.opcode = A_MOV) or
  1745. (Paicpu(hp1)^.opcode = A_MOVZX) or
  1746. (Paicpu(hp1)^.opcode = A_MOVSX)) And
  1747. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1748. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1749. ((Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Or
  1750. (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg)) And
  1751. (Reg32(Paicpu(hp1)^.oper[1].reg) = Paicpu(p)^.oper[1].reg) Then
  1752. {mov reg1, reg2
  1753. mov/zx/sx (reg2, ..), reg2 to mov/zx/sx (reg1, ..), reg2}
  1754. Begin
  1755. If (Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Then
  1756. Paicpu(hp1)^.oper[0].ref^.Base := Paicpu(p)^.oper[0].reg;
  1757. If (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg) Then
  1758. Paicpu(hp1)^.oper[0].ref^.Index := Paicpu(p)^.oper[0].reg;
  1759. AsmL^.Remove(p);
  1760. Dispose(p, Done);
  1761. p := hp1;
  1762. Continue;
  1763. End
  1764. Else If (Paicpu(p)^.oper[0].typ = top_ref) And
  1765. GetNextInstruction(p,hp1) And
  1766. (hp1^.typ = ait_instruction) And
  1767. IsFoldableArithOp(paicpu(hp1),Paicpu(p)^.oper[1].reg) And
  1768. GetNextInstruction(hp1,hp2) And
  1769. (hp2^.typ = ait_instruction) And
  1770. (Paicpu(hp2)^.opcode = A_MOV) And
  1771. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  1772. (Paicpu(hp2)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  1773. (Paicpu(hp2)^.oper[1].typ = top_ref) Then
  1774. Begin
  1775. TmpUsedRegs := UsedRegs;
  1776. UpdateUsedRegs(TmpUsedRegs,Pai(hp1^.next));
  1777. If (RefsEqual(Paicpu(hp2)^.oper[1].ref^, Paicpu(p)^.oper[0].ref^) And
  1778. Not(RegUsedAfterInstruction(Paicpu(p)^.oper[1].reg,
  1779. hp2, TmpUsedRegs)))
  1780. Then
  1781. { change mov (ref), reg }
  1782. { add/sub/or/... reg2/$const, reg }
  1783. { mov reg, (ref) }
  1784. { # release reg }
  1785. { to add/sub/or/... reg2/$const, (ref) }
  1786. Begin
  1787. case paicpu(hp1)^.opcode of
  1788. A_INC,A_DEC:
  1789. paicpu(hp1)^.LoadRef(0,newreference(Paicpu(p)^.oper[0].ref^))
  1790. else
  1791. paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[0].ref^));
  1792. end;
  1793. AsmL^.Remove(p);
  1794. AsmL^.Remove(hp2);
  1795. Dispose(p,done);
  1796. Dispose(hp2,Done);
  1797. p := hp1
  1798. End;
  1799. End
  1800. else if (Paicpu(p)^.oper[0].typ = Top_Const) And
  1801. (Paicpu(p)^.oper[0].val = 0) And
  1802. (Paicpu(p)^.oper[1].typ = Top_Reg) Then
  1803. { change "mov $0, %reg" into "xor %reg, %reg" }
  1804. Begin
  1805. Paicpu(p)^.opcode := A_XOR;
  1806. Paicpu(p)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  1807. End
  1808. End;
  1809. A_MOVZX:
  1810. Begin
  1811. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1812. If (Paicpu(p)^.oper[0].typ = top_reg)
  1813. Then
  1814. Case Paicpu(p)^.opsize of
  1815. S_BL:
  1816. Begin
  1817. If IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1818. Not(CS_LittleSize in aktglobalswitches) And
  1819. (aktoptprocessor = ClassP5)
  1820. Then
  1821. {Change "movzbl %reg1, %reg2" to
  1822. "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
  1823. PentiumMMX}
  1824. Begin
  1825. hp1 := New(Paicpu, op_reg_reg(A_XOR, S_L,
  1826. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1827. InsertLLItem(AsmL,p^.previous, p, hp1);
  1828. Paicpu(p)^.opcode := A_MOV;
  1829. Paicpu(p)^.changeopsize(S_B);
  1830. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1831. End;
  1832. End;
  1833. End
  1834. Else
  1835. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1836. (Paicpu(p)^.oper[0].ref^.base <> Paicpu(p)^.oper[1].reg) And
  1837. (Paicpu(p)^.oper[0].ref^.index <> Paicpu(p)^.oper[1].reg) And
  1838. Not(CS_LittleSize in aktglobalswitches) And
  1839. IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1840. (aktoptprocessor = ClassP5) And
  1841. (Paicpu(p)^.opsize = S_BL)
  1842. Then
  1843. {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
  1844. Pentium and PentiumMMX}
  1845. Begin
  1846. hp1 := New(Paicpu,op_reg_reg(A_XOR, S_L, Paicpu(p)^.oper[1].reg,
  1847. Paicpu(p)^.oper[1].reg));
  1848. Paicpu(p)^.opcode := A_MOV;
  1849. Paicpu(p)^.changeopsize(S_B);
  1850. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1851. InsertLLItem(AsmL,p^.previous, p, hp1);
  1852. End;
  1853. End;
  1854. A_TEST, A_OR:
  1855. {removes the line marked with (x) from the sequence
  1856. And/or/xor/add/sub/... $x, %y
  1857. test/or %y, %y (x)
  1858. j(n)z _Label
  1859. as the first instruction already adjusts the ZF}
  1860. Begin
  1861. If OpsEqual(Paicpu(p)^.oper[0],Paicpu(p)^.oper[1]) Then
  1862. If GetLastInstruction(p, hp1) And
  1863. (pai(hp1)^.typ = ait_instruction) Then
  1864. Case Paicpu(hp1)^.opcode Of
  1865. A_ADD, A_SUB, A_OR, A_XOR, A_AND, A_SHL, A_SHR:
  1866. Begin
  1867. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  1868. Begin
  1869. hp1 := pai(p^.next);
  1870. asml^.remove(p);
  1871. dispose(p, done);
  1872. p := pai(hp1);
  1873. continue
  1874. End;
  1875. End;
  1876. A_DEC, A_INC, A_NEG:
  1877. Begin
  1878. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[0]) Then
  1879. Begin
  1880. Case Paicpu(hp1)^.opcode Of
  1881. A_DEC, A_INC:
  1882. {replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag}
  1883. Begin
  1884. Case Paicpu(hp1)^.opcode Of
  1885. A_DEC: Paicpu(hp1)^.opcode := A_SUB;
  1886. A_INC: Paicpu(hp1)^.opcode := A_ADD;
  1887. End;
  1888. Paicpu(hp1)^.Loadoper(1,Paicpu(hp1)^.oper[0]);
  1889. Paicpu(hp1)^.LoadConst(0,1);
  1890. Paicpu(hp1)^.ops:=2;
  1891. End
  1892. End;
  1893. hp1 := pai(p^.next);
  1894. asml^.remove(p);
  1895. dispose(p, done);
  1896. p := pai(hp1);
  1897. continue
  1898. End;
  1899. End
  1900. End
  1901. End;
  1902. End;
  1903. End;
  1904. End;
  1905. p := Pai(p^.next)
  1906. End;
  1907. End;
  1908. End.
  1909. {
  1910. $Log$
  1911. Revision 1.10 2000-08-18 10:09:13 jonas
  1912. * fix for web bug1099 (merged from fixes branch)
  1913. Revision 1.9 2000/08/05 13:33:08 peter
  1914. * $ifdef go32v2 -> target_info.target=go32v2
  1915. Revision 1.8 2000/08/05 10:35:51 jonas
  1916. * readded l1 variable (between ifdef go32v2 to avoid hints/notes)
  1917. Revision 1.7 2000/08/04 22:00:52 peter
  1918. * merges from fixes
  1919. Revision 1.6 2000/07/31 08:44:05 jonas
  1920. - removed imul support from -dfoldarithops since "imull [reg32],[mem32]"
  1921. doesn't exist (merged from fixes branch)
  1922. Revision 1.5 2000/07/28 13:56:23 jonas
  1923. * fixed bug in shr/shl optimization when -Og is used (merged from fixes
  1924. branch)
  1925. Revision 1.4 2000/07/21 15:19:55 jonas
  1926. * daopt386: changes to getnextinstruction/getlastinstruction so they
  1927. ignore labels who have is_addr set
  1928. + daopt386/csopt386: remove loads of registers which are overwritten
  1929. before their contents are used (especially usefull for removing superfluous
  1930. maybe_loadesi outputs and push/pops transformed by below optimization
  1931. + popt386: transform pop/pop/pop/.../push/push/push to sequences of
  1932. 'movl x(%esp),%reg' (only active when compiling a go32v2 compiler
  1933. currently because I don't know whether it's safe to do this under Win32/
  1934. Linux (because of problems we had when using esp as frame pointer on
  1935. those os'es)
  1936. Revision 1.3 2000/07/14 05:11:49 michael
  1937. + Patch to 1.1
  1938. Revision 1.2 2000/07/13 11:32:45 michael
  1939. + removed logs
  1940. }