cgcpu.pas 52 KB

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  1. {******************************************************************************
  2. $Id$
  3. Copyright (c) 1998-2000 by Florian Klaempfl
  4. This program is free software;you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation;either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY;without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program;if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. *****************************************************************************}
  16. UNIT cgcpu;
  17. {This unit implements the code generator for the SPARC architecture}
  18. {$INCLUDE fpcdefs.inc}
  19. INTERFACE
  20. USES
  21. cginfo,cgbase,cgobj,cg64f32,
  22. aasmbase,aasmtai,aasmcpu,
  23. cpubase,cpuinfo,cpupara,
  24. node,symconst;
  25. TYPE
  26. TCgSparc=CLASS(tcg)
  27. {This method is used to pass a parameter, which is located in a register, to a
  28. routine. It should give the parameter to the routine, as required by the
  29. specific processor ABI. It is overriden for each CPU target.
  30. Size : is the size of the operand in the register
  31. r : is the register source of the operand
  32. LocPara : is the location where the parameter will be stored}
  33. procedure a_param_reg(list:TAasmOutput;sz:tcgsize;r:tregister;const LocPara:TParaLocation);override;
  34. {passes a parameter which is a constant to a function}
  35. procedure a_param_const(list:TAasmOutput;size:tcgsize;a:aword;CONST LocPara:TParaLocation);override;
  36. procedure a_param_ref(list:TAasmOutput;sz:tcgsize;CONST r:TReference;CONST LocPara:TParaLocation);override;
  37. procedure a_paramaddr_ref(list:TAasmOutput;CONST r:TReference;CONST LocPara:TParaLocation);override;
  38. procedure a_call_name(list:TAasmOutput;CONST s:string);override;
  39. procedure a_call_ref(list:TAasmOutput;CONST ref:TReference);override;
  40. procedure a_call_reg(list:TAasmOutput;Reg:TRegister);override;
  41. {Branch Instruction}
  42. procedure a_jmp_always(List:TAasmOutput;l:TAsmLabel);override;
  43. {General purpose instyructions}
  44. procedure a_op_const_reg(list:TAasmOutput;Op:TOpCG;a:AWord;reg:TRegister);override;
  45. procedure a_op_const_ref(list:TAasmOutput;Op:TOpCG;size:TCGSize;a:AWord;CONST ref:TReference);override;
  46. procedure a_op_reg_reg(list:TAasmOutput;Op:TOpCG;size:TCGSize;src, dst:TRegister);override;
  47. procedure a_op_ref_reg(list:TAasmOutput;Op:TOpCG;size:TCGSize;CONST ref:TReference;reg:TRegister);override;
  48. procedure a_op_reg_ref(list:TAasmOutput;Op:TOpCG;size:TCGSize;reg:TRegister;CONST ref:TReference);override;
  49. procedure a_op_const_reg_reg(list:TAasmOutput;op:TOpCg;size:tcgsize;a:aword;src, dst:tregister);override;
  50. procedure a_op_reg_reg_reg(list:TAasmOutput;op:TOpCg;size:tcgsize;src1, src2, dst:tregister);override;
  51. { move instructions }
  52. procedure a_load_const_reg(list:TAasmOutput;size:tcgsize;a:aword;reg:tregister);override;
  53. procedure a_load_const_ref(list:TAasmOutput;size:tcgsize;a:aword;CONST ref:TReference);override;
  54. procedure a_load_reg_ref(list:TAasmOutput;size:tcgsize;reg:tregister;CONST ref:TReference);override;
  55. procedure a_load_ref_reg(list:TAasmOutput;size:tcgsize;CONST ref:TReference;reg:tregister);override;
  56. procedure a_load_reg_reg(list:TAasmOutput;fromsize,tosize:tcgsize;reg1,reg2:tregister);override;
  57. procedure a_loadaddr_ref_reg(list:TAasmOutput;CONST ref:TReference;r:tregister);override;
  58. { fpu move instructions }
  59. procedure a_loadfpu_reg_reg(list:TAasmOutput;reg1, reg2:tregister);override;
  60. procedure a_loadfpu_ref_reg(list:TAasmOutput;size:tcgsize;CONST ref:TReference;reg:tregister);override;
  61. procedure a_loadfpu_reg_ref(list:TAasmOutput;size:tcgsize;reg:tregister;CONST ref:TReference);override;
  62. { vector register move instructions }
  63. procedure a_loadmm_reg_reg(list:TAasmOutput;reg1, reg2:tregister);override;
  64. procedure a_loadmm_ref_reg(list:TAasmOutput;CONST ref:TReference;reg:tregister);override;
  65. procedure a_loadmm_reg_ref(list:TAasmOutput;reg:tregister;CONST ref:TReference);override;
  66. procedure a_parammm_reg(list:TAasmOutput;reg:tregister);override;
  67. { comparison operations }
  68. procedure a_cmp_const_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;a:aword;reg:tregister;l:tasmlabel);override;
  69. procedure a_cmp_const_ref_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;a:aword;CONST ref:TReference;l:tasmlabel);override;
  70. procedure a_cmp_reg_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;reg1,reg2:tregister;l:tasmlabel);override;
  71. procedure a_cmp_ref_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;CONST ref:TReference;reg:tregister;l:tasmlabel);override;
  72. procedure a_jmp_cond(list:TAasmOutput;cond:TOpCmp;l:tasmlabel);{ override;}
  73. procedure a_jmp_flags(list:TAasmOutput;CONST f:TResFlags;l:tasmlabel);override;
  74. procedure g_flags2reg(list:TAasmOutput;Size:TCgSize;CONST f:tresflags;reg:TRegister);override;
  75. procedure g_overflowCheck(List:TAasmOutput;const p:TNode);override;
  76. procedure g_stackframe_entry(list:TAasmOutput;localsize:LongInt);override;
  77. procedure g_restore_all_registers(list:TAasmOutput;selfused,accused,acchiused:boolean);override;
  78. procedure g_restore_frame_pointer(list:TAasmOutput);override;
  79. procedure g_return_from_proc(list:TAasmOutput;parasize:aword);override;
  80. procedure g_save_all_registers(list : taasmoutput);override;
  81. procedure g_save_standard_registers(list : taasmoutput; usedinproc : tregisterset);override;
  82. procedure g_concatcopy(list:TAasmOutput;CONST source,dest:TReference;len:aword;delsource,loadref:boolean);override;
  83. class function reg_cgsize(CONST reg:tregister):tcgsize;override;
  84. PRIVATE
  85. function IsSimpleRef(const ref:treference):boolean;
  86. procedure sizes2load(s1:tcgsize;s2:topsize;var op:tasmop;var s3:topsize);
  87. procedure floatload(list:TAasmOutput;t:tcgsize;CONST ref:TReference);
  88. procedure floatstore(list:TAasmOutput;t:tcgsize;CONST ref:TReference);
  89. procedure floatloadops(t:tcgsize;var op:tasmop;var s:topsize);
  90. procedure floatstoreops(t:tcgsize;var op:tasmop;var s:topsize);
  91. END;
  92. TCg64Sparc=class(tcg64f32)
  93. procedure a_op64_ref_reg(list:TAasmOutput;op:TOpCG;CONST ref:TReference;reg:TRegister64);override;
  94. procedure a_op64_reg_reg(list:TAasmOutput;op:TOpCG;regsrc,regdst:TRegister64);override;
  95. procedure a_op64_const_reg(list:TAasmOutput;op:TOpCG;value:qWord;regdst:TRegister64);override;
  96. procedure a_op64_const_ref(list:TAasmOutput;op:TOpCG;value:qWord;CONST ref:TReference);override;
  97. procedure get_64bit_ops(op:TOpCG;var op1,op2:TAsmOp);
  98. END;
  99. CONST
  100. TOpCG2AsmOp:ARRAY[topcg]OF TAsmOp=(A_NONE,A_ADD,A_AND,A_UDIV,A_SDIV,A_UMUL, A_SMUL, A_NEG,A_NOT,A_OR,A_not,A_not,A_not,A_SUB,A_XOR);
  101. TOpCmp2AsmCond:ARRAY[topcmp]OF TAsmCond=(C_NONE,C_E,C_G,C_L,C_GE,C_LE,C_NE,C_BE,C_B,C_AE,C_A);
  102. TCGSize2OpSize:ARRAY[tcgsize]OF TOpSize=(S_NO,S_B,S_W,S_SW,S_SW,S_B,S_W,S_SW,S_SW,S_FS,S_FD,S_FQ,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO);
  103. IMPLEMENTATION
  104. USES
  105. globtype,globals,verbose,systems,cutils,
  106. symdef,symsym,defutil,paramgr,
  107. rgobj,tgobj,rgcpu,cpupi;
  108. procedure TCgSparc.a_param_reg(list:TAasmOutput;sz:tcgsize;r:tregister;const LocPara:TParaLocation);
  109. var
  110. r2:Tregister;
  111. begin
  112. r2.enum:=R_G0;
  113. with list,LocPara do
  114. case Loc of
  115. LOC_REGISTER:
  116. case Sz of
  117. OS_8,OS_S8:
  118. Concat(taicpu.op_Reg_Const_Reg(A_AND,r,$FF,Register));
  119. OS_16,OS_S16:
  120. begin
  121. Concat(taicpu.op_Reg_Reg_Reg(A_AND,r,r2,Register));
  122. {This will put 00...00111 in the hiest 22 bits of the reg}
  123. Concat(taicpu.op_Reg_Const_Reg(A_SETHI,Register,$7,Register));
  124. end;
  125. OS_32,OS_S32:
  126. if r.enum<>Register.enum
  127. then
  128. Concat(taicpu.op_Reg_Reg_Reg(A_OR,r,r2,Register));
  129. else
  130. InternalError(2002032212);
  131. end;
  132. else
  133. InternalError(2002101002);
  134. end;
  135. end;
  136. procedure TCgSparc.a_param_const(list:TAasmOutput;size:tcgsize;a:aword;CONST LocPara:TParaLocation);
  137. var
  138. Ref:TReference;
  139. begin
  140. with List do
  141. case locpara.loc of
  142. LOC_REGISTER,LOC_CREGISTER:
  143. a_load_const_reg(list,size,a,locpara.register);
  144. LOC_REFERENCE:
  145. begin
  146. reference_reset(ref);
  147. ref.base:=locpara.reference.index;
  148. ref.offset:=locpara.reference.offset;
  149. a_load_const_ref(list,size,a,ref);
  150. end;
  151. else
  152. InternalError(2002122200);
  153. end;
  154. if locpara.sp_fixup<>0
  155. then
  156. InternalError(2002122201);
  157. end;
  158. procedure TCgSparc.a_param_ref(list:TAasmOutput;sz:TCgSize;const r:TReference;const LocPara:TParaLocation);
  159. var
  160. ref: treference;
  161. tmpreg:TRegister;
  162. begin
  163. with LocPara do
  164. case locpara.loc of
  165. LOC_REGISTER,LOC_CREGISTER:
  166. a_load_ref_reg(list,sz,r,Register);
  167. LOC_REFERENCE:
  168. begin
  169. {Code conventions need the parameters being allocated in %o6+92. See
  170. comment on g_stack_frame}
  171. if locpara.sp_fixup<92
  172. then
  173. InternalError(2002081104);
  174. reference_reset(ref);
  175. ref.base:=locpara.reference.index;
  176. ref.offset:=locpara.reference.offset;
  177. tmpreg := get_scratch_reg_int(list);
  178. a_load_ref_reg(list,sz,r,tmpreg);
  179. a_load_reg_ref(list,sz,tmpreg,ref);
  180. free_scratch_reg(list,tmpreg);
  181. end;
  182. LOC_FPUREGISTER,LOC_CFPUREGISTER:
  183. case sz of
  184. OS_32:
  185. a_loadfpu_ref_reg(list,OS_F32,r,locpara.register);
  186. OS_64:
  187. a_loadfpu_ref_reg(list,OS_F64,r,locpara.register);
  188. else
  189. internalerror(2002072801);
  190. end;
  191. else
  192. internalerror(2002081103);
  193. end;
  194. end;
  195. procedure TCgSparc.a_paramaddr_ref(list:TAasmOutput;CONST r:TReference;CONST LocPara:TParaLocation);
  196. VAR
  197. tmpreg:TRegister;
  198. BEGIN
  199. IF r.segment.enum<>R_NO
  200. THEN
  201. CGMessage(cg_e_cant_use_far_pointer_there);
  202. IF(r.base.enum=R_NO)AND(r.index.enum=R_NO)
  203. THEN
  204. list.concat(Taicpu.Op_sym_ofs(A_LD,S_SW,r.symbol,r.offset))
  205. ELSE IF(r.base.enum=R_NO)AND(r.index.enum<>R_NO)AND
  206. (r.offset=0)AND(r.scalefactor=0)AND(r.symbol=nil)
  207. THEN
  208. list.concat(Taicpu.Op_reg(A_LD,r.index))
  209. ELSE IF(r.base.enum<>R_NO)AND(r.index.enum=R_NO)AND
  210. (r.offset=0)AND(r.symbol=nil)
  211. THEN
  212. list.concat(Taicpu.Op_reg(A_LD,r.base))
  213. ELSE
  214. BEGIN
  215. tmpreg:=get_scratch_reg_address(list);
  216. a_loadaddr_ref_reg(list,r,tmpreg);
  217. list.concat(taicpu.op_reg(A_LD,tmpreg));
  218. free_scratch_reg(list,tmpreg);
  219. END;
  220. END;
  221. procedure TCgSparc.a_call_name(list:TAasmOutput;CONST s:string);
  222. BEGIN
  223. WITH List,objectlibrary DO
  224. BEGIN
  225. concat(taicpu.op_sym(A_CALL,S_SW,newasmsymbol(s)));
  226. concat(taicpu.op_none(A_NOP));
  227. END;
  228. END;
  229. procedure TCgSparc.a_call_ref(list:TAasmOutput;CONST ref:TReference);
  230. begin
  231. list.concat(taicpu.op_ref(A_CALL,ref));
  232. list.concat(taicpu.op_none(A_NOP));
  233. end;
  234. procedure TCgSparc.a_call_reg(list:TAasmOutput;Reg:TRegister);
  235. begin
  236. list.concat(taicpu.op_reg(A_JMPL,reg));
  237. if target_info.system=system_sparc_linux
  238. then
  239. list.concat(taicpu.op_none(A_NOP));
  240. procinfo.flags:=procinfo.flags or pi_do_call;
  241. end;
  242. {********************** branch instructions ********************}
  243. procedure TCgSparc.a_jmp_always(List:TAasmOutput;l:TAsmLabel);
  244. begin
  245. List.Concat(TAiCpu.op_sym(A_BA,S_NO,objectlibrary.newasmsymbol(l.name)));
  246. end;
  247. {********************** load instructions ********************}
  248. procedure TCgSparc.a_load_const_reg(list:TAasmOutput;size:TCGSize;a:aword;reg:TRegister);
  249. var r:Tregister;
  250. BEGIN
  251. r.enum:=R_G0;
  252. WITH List DO
  253. IF a<>0
  254. THEN{R_G0 is usually set to zero, so we use it}
  255. Concat(taicpu.op_reg_const_reg(A_OR,r,a,reg))
  256. ELSE{The is no A_MOV in sparc, that's why we use A_OR with help of R_G0}
  257. Concat(taicpu.op_reg_reg_reg(A_OR,r,r,reg));
  258. END;
  259. procedure TCgSparc.a_load_const_ref(list:TAasmOutput;size:tcgsize;a:aword;CONST ref:TReference);
  260. var r:Tregister;
  261. BEGIN
  262. r.enum:=R_G0;
  263. WITH List DO
  264. IF a=0
  265. THEN
  266. Concat(taicpu.op_reg_ref(A_ST,r,Ref))
  267. ELSE
  268. BEGIN
  269. r.enum:=R_G1;
  270. a_load_const_reg(list,size,a,r);
  271. a_load_reg_ref(list,size,r,Ref);
  272. END;
  273. END;
  274. procedure TCgSparc.a_load_reg_ref(list:TAasmOutput;size:TCGSize;reg:tregister;const Ref:TReference);
  275. var
  276. op:tasmop;
  277. begin
  278. case size of
  279. { signed integer registers }
  280. OS_S8:
  281. Op:=A_STB;{Store Signed Byte}
  282. OS_S16:
  283. Op:=A_STH;{Store Signed Halfword}
  284. OS_S32:
  285. Op:=A_ST;{Store Word}
  286. OS_S64:
  287. Op:=A_STD;{Store Double Word}
  288. { unsigned integer registers }
  289. //A_STSTUB;{Store-Store Unsigned Byte}
  290. OS_8:
  291. Op:=A_STB;{Store Unsigned Bye}
  292. OS_16:
  293. Op:=A_STH;{Store Unsigned Halfword}
  294. OS_32:
  295. Op:=A_ST;{Store Word}
  296. OS_64:
  297. Op:=A_STD;{Store Double Word}
  298. { floating-point real registers }
  299. OS_F32:
  300. Op:=A_STF;{Store Floating-point word}
  301. //A_STFSR
  302. OS_F64:
  303. Op:=A_STDF;{Store Double Floating-point word}
  304. //A_STC;{Store Coprocessor}
  305. //A_STCSR;
  306. //A_STDC;{Store Double Coprocessor}
  307. else
  308. InternalError(2002122100);
  309. end;
  310. with list do
  311. concat(taicpu.op_reg_ref(op,reg,ref));
  312. end;
  313. procedure TCgSparc.a_load_ref_reg(list:TAasmOutput;size:TCgSize;const ref:TReference;reg:tregister);
  314. var
  315. op:tasmop;
  316. begin
  317. case size of
  318. { signed integer registers }
  319. OS_S8:
  320. Op:=A_LDSB;{Load Signed Byte}
  321. OS_S16:
  322. Op:=A_LDSH;{Load Signed Halfword}
  323. OS_S32:
  324. Op:=A_LD;{Load Word}
  325. OS_S64:
  326. Op:=A_LDD;{Load Double Word}
  327. { unsigned integer registers }
  328. //A_LDSTUB;{Load-Store Unsigned Byte}
  329. OS_8:
  330. Op:=A_LDUB;{Load Unsigned Bye}
  331. OS_16:
  332. Op:=A_LDUH;{Load Unsigned Halfword}
  333. OS_32:
  334. Op:=A_LD;{Load Word}
  335. OS_64:
  336. Op:=A_LDD;{Load Double Word}
  337. { floating-point real registers }
  338. OS_F32:
  339. Op:=A_LDF;{Load Floating-point word}
  340. //A_LDFSR
  341. OS_F64:
  342. Op:=A_LDDF;{Load Double Floating-point word}
  343. //A_LDC;{Load Coprocessor}
  344. //A_LDCSR;
  345. //A_LDDC;{Load Double Coprocessor}
  346. else
  347. InternalError(2002122100);
  348. end;
  349. with list do
  350. concat(taicpu.op_ref_reg(op,ref,reg));
  351. end;
  352. procedure TCgSparc.a_load_reg_reg(list:TAasmOutput;fromsize,tosize:tcgsize;reg1,reg2:tregister);
  353. var
  354. op:tasmop;
  355. s:topsize;
  356. r:Tregister;
  357. begin
  358. r.enum:=R_G0;
  359. if(reg1.enum<>reg2.enum)or
  360. (tcgsize2size[tosize]<tcgsize2size[fromsize])or
  361. ((tcgsize2size[tosize] = tcgsize2size[fromsize])and
  362. (tosize <> fromsize)and
  363. not(fromsize in [OS_32,OS_S32]))
  364. then
  365. with list do
  366. case fromsize of
  367. OS_8,OS_S8,OS_16,OS_S16,OS_32,OS_S32:
  368. concat(taicpu.op_reg_reg_reg(A_OR,r,reg1,reg2));
  369. else internalerror(2002090901);
  370. end;
  371. end;
  372. { all fpu load routines expect that R_ST[0-7] means an fpu regvar and }
  373. { R_ST means "the current value at the top of the fpu stack" (JM) }
  374. procedure TCgSparc.a_loadfpu_reg_reg(list:TAasmOutput;reg1, reg2:tregister);
  375. begin
  376. { if NOT (reg1 IN [R_F0..R_F31]) then
  377. begin
  378. list.concat(taicpu.op_reg(A_NONE,S_NO,
  379. trgcpu(rg).correct_fpuregister(reg1,trgcpu(rg).fpuvaroffset)));
  380. inc(trgcpu(rg).fpuvaroffset);
  381. end;
  382. if NOT (reg2 IN [R_F0..R_F31]) then
  383. begin
  384. list.concat(taicpu.op_reg(A_JMPL,S_NO,
  385. trgcpu(rg).correct_fpuregister(reg2,trgcpu(rg).fpuvaroffset)));
  386. dec(trgcpu(rg).fpuvaroffset);
  387. end;}
  388. end;
  389. procedure TCgSparc.a_loadfpu_ref_reg(list:TAasmOutput;size:tcgsize;CONST ref:TReference;reg:tregister);
  390. begin
  391. floatload(list,size,ref);
  392. { if (reg <> R_ST) then
  393. a_loadfpu_reg_reg(list,R_ST,reg);}
  394. end;
  395. procedure TCgSparc.a_loadfpu_reg_ref(list:TAasmOutput;size:tcgsize;reg:tregister;CONST ref:TReference);
  396. begin
  397. { if reg <> R_ST then
  398. a_loadfpu_reg_reg(list,reg,R_ST);}
  399. floatstore(list,size,ref);
  400. end;
  401. procedure TCgSparc.a_loadmm_reg_reg(list:TAasmOutput;reg1, reg2:tregister);
  402. begin
  403. // list.concat(taicpu.op_reg_reg(A_NONEQ,S_NO,reg1,reg2));
  404. end;
  405. procedure TCgSparc.a_loadmm_ref_reg(list:TAasmOutput;CONST ref:TReference;reg:tregister);
  406. begin
  407. // list.concat(taicpu.op_ref_reg(A_NONEQ,S_NO,ref,reg));
  408. end;
  409. procedure TCgSparc.a_loadmm_reg_ref(list:TAasmOutput;reg:tregister;CONST ref:TReference);
  410. begin
  411. // list.concat(taicpu.op_reg_ref(A_NONEQ,S_NO,reg,ref));
  412. end;
  413. procedure TCgSparc.a_parammm_reg(list:TAasmOutput;reg:tregister);
  414. VAR
  415. href:TReference;
  416. BEGIN
  417. // list.concat(taicpu.op_const_reg(A_SUB,S_SW,8,R_RSP));
  418. // reference_reset_base(href,R_ESP,0);
  419. // list.concat(taicpu.op_reg_ref(A_NONEQ,S_NO,reg,href));
  420. END;
  421. procedure TCgSparc.a_op_const_reg(list:TAasmOutput;Op:TOpCG;a:AWord;reg:TRegister);
  422. var
  423. opcode:tasmop;
  424. power:LongInt;
  425. begin
  426. (* Case Op of
  427. OP_DIV, OP_IDIV:
  428. Begin
  429. if ispowerof2(a,power) then
  430. begin
  431. case op of
  432. OP_DIV:
  433. opcode := A_SHR;
  434. OP_IDIV:
  435. opcode := A_SAR;
  436. end;
  437. list.concat(taicpu.op_const_reg(opcode,S_SW,power,
  438. reg));
  439. exit;
  440. end;
  441. { the rest should be handled specifically in the code }
  442. { generator because of the silly register usage restraints }
  443. internalerror(200109224);
  444. End;
  445. OP_MUL,OP_IMUL:
  446. begin
  447. if not(cs_check_overflow in aktlocalswitches) and
  448. ispowerof2(a,power) then
  449. begin
  450. list.concat(taicpu.op_const_reg(A_SHL,S_SW,power,
  451. reg));
  452. exit;
  453. end;
  454. if op = OP_IMUL then
  455. list.concat(taicpu.op_const_reg(A_IMUL,S_SW,
  456. a,reg))
  457. else
  458. { OP_MUL should be handled specifically in the code }
  459. { generator because of the silly register usage restraints }
  460. internalerror(200109225);
  461. end;
  462. OP_ADD, OP_AND, OP_OR, OP_SUB, OP_XOR:
  463. if not(cs_check_overflow in aktlocalswitches) and
  464. (a = 1) and
  465. (op in [OP_ADD,OP_SUB]) then
  466. if op = OP_ADD then
  467. list.concat(taicpu.op_reg(A_INC,S_SW,reg))
  468. else
  469. list.concat(taicpu.op_reg(A_DEC,S_SW,reg))
  470. else if (a = 0) then
  471. if (op <> OP_AND) then
  472. exit
  473. else
  474. list.concat(taicpu.op_const_reg(A_NONE,S_SW,0,reg))
  475. else if (a = high(aword)) and
  476. (op in [OP_AND,OP_OR,OP_XOR]) then
  477. begin
  478. case op of
  479. OP_AND:
  480. exit;
  481. OP_OR:
  482. list.concat(taicpu.op_const_reg(A_NONE,S_SW,high(aword),reg));
  483. OP_XOR:
  484. list.concat(taicpu.op_reg(A_NOT,S_SW,reg));
  485. end
  486. end
  487. else
  488. list.concat(taicpu.op_const_reg(TOpCG2AsmOp[op],S_SW,
  489. a,reg));
  490. OP_SHL,OP_SHR,OP_SAR:
  491. begin
  492. if (a and 31) <> 0 Then
  493. list.concat(taicpu.op_const_reg(
  494. TOpCG2AsmOp[op],S_SW,a and 31,reg));
  495. if (a shr 5) <> 0 Then
  496. internalerror(68991);
  497. end
  498. else internalerror(68992);
  499. end;*)
  500. end;
  501. procedure TCgSparc.a_op_const_ref(list:TAasmOutput;Op:TOpCG;size:TCGSize;a:AWord;CONST ref:TReference);
  502. var
  503. opcode:tasmop;
  504. power:LongInt;
  505. begin
  506. (* Case Op of
  507. OP_DIV, OP_IDIV:
  508. Begin
  509. if ispowerof2(a,power) then
  510. begin
  511. case op of
  512. OP_DIV:
  513. opcode := A_SHR;
  514. OP_IDIV:
  515. opcode := A_SAR;
  516. end;
  517. list.concat(taicpu.op_const_ref(opcode,
  518. TCgSize2OpSize[size],power,ref));
  519. exit;
  520. end;
  521. { the rest should be handled specifically in the code }
  522. { generator because of the silly register usage restraints }
  523. internalerror(200109231);
  524. End;
  525. OP_MUL,OP_IMUL:
  526. begin
  527. if not(cs_check_overflow in aktlocalswitches) and
  528. ispowerof2(a,power) then
  529. begin
  530. list.concat(taicpu.op_const_ref(A_SHL,TCgSize2OpSize[size],
  531. power,ref));
  532. exit;
  533. end;
  534. { can't multiply a memory location directly with a CONSTant }
  535. if op = OP_IMUL then
  536. inherited a_op_const_ref(list,op,size,a,ref)
  537. else
  538. { OP_MUL should be handled specifically in the code }
  539. { generator because of the silly register usage restraints }
  540. internalerror(200109232);
  541. end;
  542. OP_ADD, OP_AND, OP_OR, OP_SUB, OP_XOR:
  543. if not(cs_check_overflow in aktlocalswitches) and
  544. (a = 1) and
  545. (op in [OP_ADD,OP_SUB]) then
  546. if op = OP_ADD then
  547. list.concat(taicpu.op_ref(A_INC,TCgSize2OpSize[size],ref))
  548. else
  549. list.concat(taicpu.op_ref(A_DEC,TCgSize2OpSize[size],ref))
  550. else if (a = 0) then
  551. if (op <> OP_AND) then
  552. exit
  553. else
  554. a_load_const_ref(list,size,0,ref)
  555. else if (a = high(aword)) and
  556. (op in [OP_AND,OP_OR,OP_XOR]) then
  557. begin
  558. case op of
  559. OP_AND:
  560. exit;
  561. OP_OR:
  562. list.concat(taicpu.op_const_ref(A_NONE,TCgSize2OpSize[size],high(aword),ref));
  563. OP_XOR:
  564. list.concat(taicpu.op_ref(A_NOT,TCgSize2OpSize[size],ref));
  565. end
  566. end
  567. else
  568. list.concat(taicpu.op_const_ref(TOpCG2AsmOp[op],
  569. TCgSize2OpSize[size],a,ref));
  570. OP_SHL,OP_SHR,OP_SAR:
  571. begin
  572. if (a and 31) <> 0 Then
  573. list.concat(taicpu.op_const_ref(
  574. TOpCG2AsmOp[op],TCgSize2OpSize[size],a and 31,ref));
  575. if (a shr 5) <> 0 Then
  576. internalerror(68991);
  577. end
  578. else internalerror(68992);
  579. end;*)
  580. end;
  581. procedure TCgSparc.a_op_reg_reg(list:TAasmOutput;Op:TOpCG;size:TCGSize;src, dst:TRegister);
  582. var
  583. regloadsize:tcgsize;
  584. dstsize:topsize;
  585. tmpreg:tregister;
  586. popecx:boolean;
  587. begin
  588. (* dstsize := S_Q{makeregsize(dst,size)};
  589. case op of
  590. OP_NEG,OP_NOT:
  591. begin
  592. if src <> R_NO then
  593. internalerror(200112291);
  594. list.concat(taicpu.op_reg(TOpCG2AsmOp[op],dstsize,dst));
  595. end;
  596. OP_MUL,OP_DIV,OP_IDIV:
  597. { special stuff, needs separate handling inside code }
  598. { generator }
  599. internalerror(200109233);
  600. OP_SHR,OP_SHL,OP_SAR:
  601. begin
  602. tmpreg := R_NO;
  603. { we need cl to hold the shift count, so if the destination }
  604. { is ecx, save it to a temp for now }
  605. if dst in [R_ECX,R_CX,R_CL] then
  606. begin
  607. case S_SW of
  608. S_B:regloadsize := OS_8;
  609. S_W:regloadsize := OS_16;
  610. else regloadsize := OS_32;
  611. end;
  612. tmpreg := get_scratch_reg(list);
  613. a_load_reg_reg(list,regloadsize,OS_32,src,tmpreg);
  614. end;
  615. if not(src in [R_ECX,R_CX,R_CL]) then
  616. begin
  617. { is ecx still free (it's also free if it was allocated }
  618. { to dst, since we've moved dst somewhere else already) }
  619. if not((dst = R_ECX) or
  620. ((R_ECX in rg.unusedregsint) and
  621. { this will always be true, it's just here to }
  622. { allocate ecx }
  623. (rg.getexplicitregisterint(list,R_ECX) = R_ECX))) then
  624. begin
  625. list.concat(taicpu.op_reg(A_NONE,S_SW,R_ECX));
  626. popecx := true;
  627. end;
  628. a_load_reg_reg(list,OS_8,OS_8,(src),R_CL);
  629. end
  630. else
  631. src := R_CL;
  632. { do the shift }
  633. if tmpreg = R_NO then
  634. list.concat(taicpu.op_reg_reg(TOpCG2AsmOp[op],dstsize,
  635. R_CL,dst))
  636. else
  637. begin
  638. list.concat(taicpu.op_reg_reg(TOpCG2AsmOp[op],S_SW,
  639. R_CL,tmpreg));
  640. { move result back to the destination }
  641. a_load_reg_reg(list,OS_32,OS_32,tmpreg,R_ECX);
  642. free_scratch_reg(list,tmpreg);
  643. end;
  644. if popecx then
  645. list.concat(taicpu.op_reg(A_POP,S_SW,R_ECX))
  646. else if not (dst in [R_ECX,R_CX,R_CL]) then
  647. rg.ungetregisterint(list,R_ECX);
  648. end;
  649. else
  650. begin
  651. if S_SW <> dstsize then
  652. internalerror(200109226);
  653. list.concat(taicpu.op_reg_reg(TOpCG2AsmOp[op],dstsize,
  654. src,dst));
  655. end;
  656. end;*)
  657. end;
  658. procedure TCgSparc.a_op_ref_reg(list:TAasmOutput;Op:TOpCG;size:TCGSize;CONST ref:TReference;reg:TRegister);
  659. var
  660. opsize:topsize;
  661. begin
  662. (* case op of
  663. OP_NEG,OP_NOT,OP_IMUL:
  664. begin
  665. inherited a_op_ref_reg(list,op,size,ref,reg);
  666. end;
  667. OP_MUL,OP_DIV,OP_IDIV:
  668. { special stuff, needs separate handling inside code }
  669. { generator }
  670. internalerror(200109239);
  671. else
  672. begin
  673. opsize := S_Q{makeregsize(reg,size)};
  674. list.concat(taicpu.op_ref_reg(TOpCG2AsmOp[op],opsize,ref,reg));
  675. end;
  676. end;*)
  677. end;
  678. procedure TCgSparc.a_op_reg_ref(list:TAasmOutput;Op:TOpCG;size:TCGSize;reg:TRegister;CONST ref:TReference);
  679. var
  680. opsize:topsize;
  681. begin
  682. (* case op of
  683. OP_NEG,OP_NOT:
  684. begin
  685. if reg <> R_NO then
  686. internalerror(200109237);
  687. list.concat(taicpu.op_ref(TOpCG2AsmOp[op],tcgsize2opsize[size],ref));
  688. end;
  689. OP_IMUL:
  690. begin
  691. { this one needs a load/imul/store, which is the default }
  692. inherited a_op_ref_reg(list,op,size,ref,reg);
  693. end;
  694. OP_MUL,OP_DIV,OP_IDIV:
  695. { special stuff, needs separate handling inside code }
  696. { generator }
  697. internalerror(200109238);
  698. else
  699. begin
  700. opsize := tcgsize2opsize[size];
  701. list.concat(taicpu.op_reg_ref(TOpCG2AsmOp[op],opsize,reg,ref));
  702. end;
  703. end;*)
  704. end;
  705. procedure TCgSparc.a_op_const_reg_reg(list:TAasmOutput;op:TOpCg;
  706. size:tcgsize;a:aword;src, dst:tregister);
  707. var
  708. tmpref:TReference;
  709. power:LongInt;
  710. opsize:topsize;
  711. begin
  712. opsize := S_SW;
  713. if (opsize <> S_SW) or
  714. not (size in [OS_32,OS_S32]) then
  715. begin
  716. inherited a_op_const_reg_reg(list,op,size,a,src,dst);
  717. exit;
  718. end;
  719. { if we get here, we have to do a 32 bit calculation, guaranteed }
  720. Case Op of
  721. OP_DIV, OP_IDIV, OP_MUL, OP_AND, OP_OR, OP_XOR, OP_SHL, OP_SHR,
  722. OP_SAR:
  723. { can't do anything special for these }
  724. inherited a_op_const_reg_reg(list,op,size,a,src,dst);
  725. OP_IMUL:
  726. begin
  727. if not(cs_check_overflow in aktlocalswitches) and
  728. ispowerof2(a,power) then
  729. { can be done with a shift }
  730. inherited a_op_const_reg_reg(list,op,size,a,src,dst);
  731. list.concat(taicpu.op_reg_const_reg(A_SMUL,src,a,dst));
  732. end;
  733. OP_ADD, OP_SUB:
  734. if (a = 0) then
  735. a_load_reg_reg(list,size,size,src,dst)
  736. else
  737. begin
  738. reference_reset(tmpref);
  739. tmpref.base := src;
  740. tmpref.offset := LongInt(a);
  741. if op = OP_SUB then
  742. tmpref.offset := -tmpref.offset;
  743. list.concat(taicpu.op_ref_reg(A_NONE,tmpref,dst));
  744. end
  745. else internalerror(200112302);
  746. end;
  747. end;
  748. procedure TCgSparc.a_op_reg_reg_reg(list:TAasmOutput;op:TOpCg;
  749. size:tcgsize;src1, src2, dst:tregister);
  750. var
  751. tmpref:TReference;
  752. opsize:topsize;
  753. begin
  754. opsize := S_SW;
  755. if (opsize <> S_SW) or
  756. (S_SW <> S_SW) or
  757. not (size in [OS_32,OS_S32]) then
  758. begin
  759. inherited a_op_reg_reg_reg(list,op,size,src1,src2,dst);
  760. exit;
  761. end;
  762. { if we get here, we have to do a 32 bit calculation, guaranteed }
  763. Case Op of
  764. OP_DIV, OP_IDIV, OP_MUL, OP_AND, OP_OR, OP_XOR, OP_SHL, OP_SHR,
  765. OP_SAR,OP_SUB,OP_NOT,OP_NEG:
  766. { can't do anything special for these }
  767. inherited a_op_reg_reg_reg(list,op,size,src1,src2,dst);
  768. OP_IMUL:
  769. list.concat(taicpu.op_reg_reg_reg(A_SMUL,src1,src2,dst));
  770. OP_ADD:
  771. begin
  772. reference_reset(tmpref);
  773. tmpref.base := src1;
  774. tmpref.index := src2;
  775. tmpref.scalefactor := 1;
  776. list.concat(taicpu.op_ref_reg(A_NONE,tmpref,dst));
  777. end
  778. else internalerror(200112303);
  779. end;
  780. end;
  781. {*************** compare instructructions ****************}
  782. procedure TCgSparc.a_cmp_const_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;a:aword;reg:tregister;
  783. l:tasmlabel);
  784. begin
  785. if (a = 0) then
  786. list.concat(taicpu.op_reg_reg(A_CMP,reg,reg))
  787. else
  788. list.concat(taicpu.op_const_reg(A_CMP,a,reg));
  789. a_jmp_cond(list,cmp_op,l);
  790. end;
  791. procedure TCgSparc.a_cmp_const_ref_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;a:aword;const ref:TReference;l:tasmlabel);
  792. begin
  793. with List do
  794. begin
  795. Concat(taicpu.op_const(A_LD,a));
  796. Concat(taicpu.op_ref(A_CMP,ref));
  797. end;
  798. a_jmp_cond(list,cmp_op,l);
  799. end;
  800. procedure TCgSparc.a_cmp_reg_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;
  801. reg1,reg2:tregister;l:tasmlabel);
  802. begin
  803. { if regsize(reg1) <> S_SW then
  804. internalerror(200109226);
  805. list.concat(taicpu.op_reg_reg(A_CMP,regsize(reg1),reg1,reg2));
  806. a_jmp_cond(list,cmp_op,l);}
  807. end;
  808. procedure TCgSparc.a_cmp_ref_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;CONST ref:TReference;reg:tregister;l:tasmlabel);
  809. var
  810. TempReg:TRegister;
  811. begin
  812. TempReg:=cg.get_scratch_reg_int(List);
  813. a_load_ref_reg(list,OS_32,Ref,TempReg);
  814. list.concat(taicpu.op_reg_reg(A_SUBcc,TempReg,Reg));
  815. a_jmp_cond(list,cmp_op,l);
  816. cg.free_scratch_reg(exprasmlist,TempReg);
  817. end;
  818. procedure TCgSparc.a_jmp_cond(list:TAasmOutput;cond:TOpCmp;l:tasmlabel);
  819. var
  820. ai:taicpu;
  821. begin
  822. if cond=OC_None then
  823. ai := Taicpu.Op_sym(A_JMPL,S_NO,l)
  824. else
  825. begin
  826. ai:=Taicpu.Op_sym(A_JMPL,S_NO,l);
  827. ai.SetCondition(TOpCmp2AsmCond[cond]);
  828. end;
  829. ai.is_jmp:=true;
  830. list.concat(ai);
  831. end;
  832. procedure TCgSparc.a_jmp_flags(list:TAasmOutput;CONST f:TResFlags;l:tasmlabel);
  833. var
  834. ai:taicpu;
  835. begin
  836. ai := Taicpu.op_sym(A_JMPL,S_NO,l);
  837. ai.SetCondition(flags_to_cond(f));
  838. ai.is_jmp := true;
  839. list.concat(ai);
  840. end;
  841. procedure TCgSparc.g_flags2reg(list:TAasmOutput;Size:TCgSize;CONST f:tresflags;reg:TRegister);
  842. VAR
  843. ai:taicpu;
  844. r,hreg:tregister;
  845. BEGIN
  846. r.enum:=R_PSR;
  847. hreg := rg.makeregsize(reg,OS_8);
  848. ai:=Taicpu.Op_reg_reg(A_RDPSR,r,hreg);
  849. ai.SetCondition(flags_to_cond(f));
  850. list.concat(ai);
  851. IF hreg.enum<>reg.enum
  852. THEN
  853. a_load_reg_reg(list,OS_32,OS_32,hreg,reg);
  854. END;
  855. procedure TCgSparc.g_overflowCheck(List:TAasmOutput;const p:TNode);
  856. var
  857. hl:TAsmLabel;
  858. r:Tregister;
  859. begin
  860. r.enum:=R_NONE;
  861. if not(cs_check_overflow in aktlocalswitches)
  862. then
  863. exit;
  864. objectlibrary.getlabel(hl);
  865. if not((p.resulttype.def.deftype=pointerdef) or
  866. ((p.resulttype.def.deftype=orddef) and
  867. (torddef(p.resulttype.def).typ in [u64bit,u16bit,u32bit,u8bit,uchar,
  868. bool8bit,bool16bit,bool32bit])))
  869. then
  870. begin
  871. list.concat(taicpu.op_reg(A_NONE,r));
  872. a_jmp_always(list,hl)
  873. end
  874. else
  875. a_jmp_cond(list,OC_NONE,hl);
  876. a_call_name(list,'FPC_OVERFLOW');
  877. a_label(list,hl);
  878. end;
  879. { *********** entry/exit code and address loading ************ }
  880. procedure TCgSparc.g_stackframe_entry(list:TAasmOutput;LocalSize:LongInt);
  881. var
  882. href:TReference;
  883. r:Tregister;
  884. i:integer;
  885. again:tasmlabel;
  886. begin
  887. {Althogh the SPARC architecture require only word alignment, software
  888. convention and the operating system require every stack frame to be double word
  889. aligned}
  890. LocalSize:=(LocalSize+7)and $FFFFFFF8;
  891. {Execute the SAVE instruction to get a new register window and create a new
  892. stack frame. In the "SAVE %i6,size,%i6" the first %i6 is related to the state
  893. before execution of the SAVE instrucion so it is the caller %i6, when the %i6
  894. after execution of that instruction is the called function stack pointer}
  895. r.enum:=stack_pointer_reg;
  896. with list do
  897. concat(Taicpu.Op_reg_const_reg(A_SAVE,r,-LocalSize,r));
  898. end;
  899. procedure TCgSparc.g_restore_all_registers(list:TaasmOutput;selfused,accused,acchiused:boolean);
  900. begin
  901. {$warning FIX ME TCgSparc.g_restore_all_registers}
  902. end;
  903. procedure TCgSparc.g_restore_frame_pointer(list:TAasmOutput);
  904. begin
  905. {This function intontionally does nothing as frame pointer is restored in the
  906. delay slot of the return instrucion done in g_return_from_proc}
  907. end;
  908. procedure TCgSparc.g_return_from_proc(list:TAasmOutput;parasize:aword);
  909. var r,r2:Tregister;
  910. begin
  911. {According to the SPARC ABI, the stack is cleared using the RESTORE instruction
  912. which is genereted in the g_restore_frame_pointer. Notice that SPARC has no
  913. RETURN instruction and that JMPL is used instead. The JMPL instrucion have one
  914. delay slot, so an inversion is possible such as
  915. JMPL %i7+8,%g0
  916. RESTORE %g0,0,%g0
  917. If no inversion we can use just
  918. RESTORE %g0,0,%g0
  919. JMPL %i7+8,%g0
  920. NOP}
  921. with list do
  922. begin
  923. {Return address is computed by adding 8 to the CALL address saved onto %i6}
  924. r.enum:=R_G0;
  925. r2.enum:=R_I7;
  926. concat(Taicpu.Op_caddr_reg(A_JMPL,r,8,r));
  927. {We use trivial restore in the delay slot of the JMPL instruction, as we
  928. already set result onto %i0}
  929. concat(Taicpu.Op_reg_const_reg(A_RESTORE,r,0,r));
  930. end
  931. end;
  932. procedure TCgSparc.g_save_all_registers(list : taasmoutput);
  933. begin
  934. {$warning FIX ME TCgSparc.g_save_all_registers}
  935. end;
  936. procedure TCgSparc.g_save_standard_registers(list : taasmoutput; usedinproc : tregisterset);
  937. begin
  938. {$warning FIX ME tcgppc.g_save_standard_registers}
  939. end;
  940. procedure TCgSparc.a_loadaddr_ref_reg(list:TAasmOutput;CONST ref:TReference;r:tregister);
  941. begin
  942. // list.concat(taicpu.op_ref_reg(A_LEA,S_SW,ref,r));
  943. end;
  944. { ************* 64bit operations ************ }
  945. procedure TCg64Sparc.get_64bit_ops(op:TOpCG;var op1,op2:TAsmOp);
  946. begin
  947. case op of
  948. OP_ADD :
  949. begin
  950. op1:=A_ADD;
  951. op2:=A_ADD;
  952. end;
  953. OP_SUB :
  954. begin
  955. op1:=A_SUB;
  956. op2:=A_SUB;
  957. end;
  958. OP_XOR :
  959. begin
  960. op1:=A_XOR;
  961. op2:=A_XOR;
  962. end;
  963. OP_OR :
  964. begin
  965. op1:=A_OR;
  966. op2:=A_OR;
  967. end;
  968. OP_AND :
  969. begin
  970. op1:=A_AND;
  971. op2:=A_AND;
  972. end;
  973. else
  974. internalerror(200203241);
  975. end;
  976. end;
  977. procedure TCg64Sparc.a_op64_ref_reg(list:TAasmOutput;op:TOpCG;CONST ref:TReference;reg:TRegister64);
  978. var
  979. op1,op2:TAsmOp;
  980. tempref:TReference;
  981. begin
  982. get_64bit_ops(op,op1,op2);
  983. list.concat(taicpu.op_ref_reg(op1,ref,reg.reglo));
  984. tempref:=ref;
  985. inc(tempref.offset,4);
  986. list.concat(taicpu.op_ref_reg(op2,tempref,reg.reghi));
  987. end;
  988. procedure TCg64Sparc.a_op64_reg_reg(list:TAasmOutput;op:TOpCG;regsrc,regdst:TRegister64);
  989. var
  990. op1,op2:TAsmOp;
  991. begin
  992. get_64bit_ops(op,op1,op2);
  993. list.concat(taicpu.op_reg_reg(op1,regsrc.reglo,regdst.reglo));
  994. list.concat(taicpu.op_reg_reg(op2,regsrc.reghi,regdst.reghi));
  995. end;
  996. procedure TCg64Sparc.a_op64_const_reg(list:TAasmOutput;op:TOpCG;value:qWord;regdst:TRegister64);
  997. var
  998. op1,op2:TAsmOp;
  999. begin
  1000. case op of
  1001. OP_AND,OP_OR,OP_XOR:
  1002. WITH cg DO
  1003. begin
  1004. a_op_const_reg(list,op,Lo(Value),regdst.reglo);
  1005. a_op_const_reg(list,op,Hi(Value),regdst.reghi);
  1006. end;
  1007. OP_ADD, OP_SUB:
  1008. begin
  1009. {can't use a_op_const_ref because this may use dec/inc}
  1010. get_64bit_ops(op,op1,op2);
  1011. list.concat(taicpu.op_const_reg(op1,Lo(Value),regdst.reglo));
  1012. list.concat(taicpu.op_const_reg(op2,Hi(Value),regdst.reghi));
  1013. end;
  1014. else
  1015. internalerror(200204021);
  1016. end;
  1017. end;
  1018. procedure TCg64Sparc.a_op64_const_ref(list:TAasmOutput;op:TOpCG;value:qWord;const ref:TReference);
  1019. var
  1020. op1,op2:TAsmOp;
  1021. tempref:TReference;
  1022. begin
  1023. case op of
  1024. OP_AND,OP_OR,OP_XOR:
  1025. with cg do
  1026. begin
  1027. a_op_const_ref(list,op,OS_32,Lo(Value),ref);
  1028. tempref:=ref;
  1029. inc(tempref.offset,4);
  1030. a_op_const_ref(list,op,OS_32,Hi(Value),tempref);
  1031. end;
  1032. OP_ADD, OP_SUB:
  1033. begin
  1034. get_64bit_ops(op,op1,op2);
  1035. { can't use a_op_const_ref because this may use dec/inc}
  1036. { list.concat(taicpu.op_const_ref(op1,Lo(Value),ref));
  1037. tempref:=ref;
  1038. inc(tempref.offset,4);
  1039. list.concat(taicpu.op_const_ref(op2,S_SW,Hi(Value),tempref));}
  1040. InternalError(2002102101);
  1041. end;
  1042. else
  1043. internalerror(200204022);
  1044. end;
  1045. end;
  1046. { ************* concatcopy ************ }
  1047. procedure TCgSparc.g_concatcopy(list:taasmoutput;const source,dest:treference;len:aword;delsource,loadref:boolean);
  1048. var
  1049. countreg: TRegister;
  1050. src, dst: TReference;
  1051. lab: tasmlabel;
  1052. count, count2: aword;
  1053. orgsrc, orgdst: boolean;
  1054. r:Tregister;
  1055. begin
  1056. {$ifdef extdebug}
  1057. if len > high(longint)
  1058. then
  1059. internalerror(2002072704);
  1060. {$endif extdebug}
  1061. { make sure short loads are handled as optimally as possible }
  1062. if not loadref then
  1063. if (len <= 8) and
  1064. (byte(len) in [1,2,4,8]) then
  1065. begin
  1066. if len < 8 then
  1067. begin
  1068. a_load_ref_ref(list,int_cgsize(len),source,dest);
  1069. if delsource then
  1070. reference_release(list,source);
  1071. end
  1072. else
  1073. begin
  1074. r.enum:=R_F0;
  1075. a_reg_alloc(list,r);
  1076. a_loadfpu_ref_reg(list,OS_F64,source,r);
  1077. if delsource then
  1078. reference_release(list,source);
  1079. a_loadfpu_reg_ref(list,OS_F64,r,dest);
  1080. a_reg_dealloc(list,r);
  1081. end;
  1082. exit;
  1083. end;
  1084. reference_reset(src);
  1085. reference_reset(dst);
  1086. { load the address of source into src.base }
  1087. if loadref then
  1088. begin
  1089. src.base := get_scratch_reg_address(list);
  1090. a_load_ref_reg(list,OS_32,source,src.base);
  1091. orgsrc := false;
  1092. end
  1093. else if not issimpleref(source) or
  1094. ((source.index.enum <> R_NO) and
  1095. ((source.offset + longint(len)) > high(smallint))) then
  1096. begin
  1097. src.base := get_scratch_reg_address(list);
  1098. a_loadaddr_ref_reg(list,source,src.base);
  1099. orgsrc := false;
  1100. end
  1101. else
  1102. begin
  1103. src := source;
  1104. orgsrc := true;
  1105. end;
  1106. if not orgsrc and delsource then
  1107. reference_release(list,source);
  1108. { load the address of dest into dst.base }
  1109. if not issimpleref(dest) or
  1110. ((dest.index.enum <> R_NO) and
  1111. ((dest.offset + longint(len)) > high(smallint))) then
  1112. begin
  1113. dst.base := get_scratch_reg_address(list);
  1114. a_loadaddr_ref_reg(list,dest,dst.base);
  1115. orgdst := false;
  1116. end
  1117. else
  1118. begin
  1119. dst := dest;
  1120. orgdst := true;
  1121. end;
  1122. count := len div 8;
  1123. if count > 4 then
  1124. { generate a loop }
  1125. begin
  1126. { the offsets are zero after the a_loadaddress_ref_reg and just }
  1127. { have to be set to 8. I put an Inc there so debugging may be }
  1128. { easier (should offset be different from zero here, it will be }
  1129. { easy to notice in the generated assembler }
  1130. inc(dst.offset,8);
  1131. inc(src.offset,8);
  1132. list.concat(taicpu.op_reg_const_reg(A_SUB,src.base,8,src.base));
  1133. list.concat(taicpu.op_reg_const_reg(A_SUB,dst.base,8,dst.base));
  1134. countreg := get_scratch_reg_int(list);
  1135. a_load_const_reg(list,OS_32,count,countreg);
  1136. { explicitely allocate R_O0 since it can be used safely here }
  1137. { (for holding date that's being copied) }
  1138. r.enum:=R_F0;
  1139. a_reg_alloc(list,r);
  1140. objectlibrary.getlabel(lab);
  1141. a_label(list, lab);
  1142. list.concat(taicpu.op_reg_const_reg(A_SUB,countreg,1,countreg));
  1143. list.concat(taicpu.op_reg_ref(A_LDF,r,src));
  1144. list.concat(taicpu.op_reg_ref(A_STD,r,dst));
  1145. //a_jmp(list,A_BC,C_NE,0,lab);
  1146. free_scratch_reg(list,countreg);
  1147. a_reg_dealloc(list,r);
  1148. len := len mod 8;
  1149. end;
  1150. count := len div 8;
  1151. if count > 0 then
  1152. { unrolled loop }
  1153. begin
  1154. r.enum:=R_F0;
  1155. a_reg_alloc(list,r);
  1156. for count2 := 1 to count do
  1157. begin
  1158. a_loadfpu_ref_reg(list,OS_F64,src,r);
  1159. a_loadfpu_reg_ref(list,OS_F64,r,dst);
  1160. inc(src.offset,8);
  1161. inc(dst.offset,8);
  1162. end;
  1163. a_reg_dealloc(list,r);
  1164. len := len mod 8;
  1165. end;
  1166. if (len and 4) <> 0 then
  1167. begin
  1168. r.enum:=R_O0;
  1169. a_reg_alloc(list,r);
  1170. a_load_ref_reg(list,OS_32,src,r);
  1171. a_load_reg_ref(list,OS_32,r,dst);
  1172. inc(src.offset,4);
  1173. inc(dst.offset,4);
  1174. a_reg_dealloc(list,r);
  1175. end;
  1176. { copy the leftovers }
  1177. if (len and 2) <> 0 then
  1178. begin
  1179. r.enum:=R_O0;
  1180. a_reg_alloc(list,r);
  1181. a_load_ref_reg(list,OS_16,src,r);
  1182. a_load_reg_ref(list,OS_16,r,dst);
  1183. inc(src.offset,2);
  1184. inc(dst.offset,2);
  1185. a_reg_dealloc(list,r);
  1186. end;
  1187. if (len and 1) <> 0 then
  1188. begin
  1189. r.enum:=R_O0;
  1190. a_reg_alloc(list,r);
  1191. a_load_ref_reg(list,OS_8,src,r);
  1192. a_load_reg_ref(list,OS_8,r,dst);
  1193. a_reg_dealloc(list,r);
  1194. end;
  1195. if orgsrc then
  1196. begin
  1197. if delsource then
  1198. reference_release(list,source);
  1199. end
  1200. else
  1201. free_scratch_reg(list,src.base);
  1202. if not orgdst then
  1203. free_scratch_reg(list,dst.base);
  1204. end;
  1205. function TCgSparc.reg_cgsize(CONST reg:tregister):tcgsize;
  1206. begin
  1207. result:=OS_32;
  1208. end;
  1209. {***************** This is private property, keep out! :) *****************}
  1210. function TCgSparc.IsSimpleRef(const ref:treference):boolean;
  1211. begin
  1212. if(ref.base.enum=R_NONE)and(ref.index.enum <> R_NO)
  1213. then
  1214. InternalError(2002100804);
  1215. result :=not(assigned(ref.symbol))and
  1216. (((ref.index.enum = R_NO) and
  1217. (ref.offset >= low(smallint)) and
  1218. (ref.offset <= high(smallint))) or
  1219. ((ref.index.enum <> R_NO) and
  1220. (ref.offset = 0)));
  1221. end;
  1222. procedure TCgSparc.sizes2load(s1:tcgsize;s2:topsize;var op:tasmop;var s3:topsize);
  1223. begin
  1224. case s2 of
  1225. S_B:
  1226. if S1 in [OS_8,OS_S8]
  1227. then
  1228. s3 := S_B
  1229. else
  1230. internalerror(200109221);
  1231. S_W:
  1232. case s1 of
  1233. OS_8,OS_S8:
  1234. s3 := S_B;
  1235. OS_16,OS_S16:
  1236. s3 := S_H;
  1237. else
  1238. internalerror(200109222);
  1239. end;
  1240. S_SW:
  1241. case s1 of
  1242. OS_8,OS_S8:
  1243. s3 := S_B;
  1244. OS_16,OS_S16:
  1245. s3 := S_H;
  1246. OS_32,OS_S32:
  1247. s3 := S_W;
  1248. else
  1249. internalerror(200109223);
  1250. end;
  1251. else internalerror(200109227);
  1252. end;
  1253. if s3 in [S_B,S_W,S_SW]
  1254. then
  1255. op := A_LD
  1256. { else if s3=S_DW
  1257. then
  1258. op:=A_LDD
  1259. else if s3 in [OS_8,OS_16,OS_32]
  1260. then
  1261. op := A_NONE}
  1262. else
  1263. op := A_NONE;
  1264. end;
  1265. procedure TCgSparc.floatloadops(t:tcgsize;VAR op:tasmop;VAR s:topsize);
  1266. BEGIN
  1267. (* case t of
  1268. OS_F32:begin
  1269. op:=A_FLD;
  1270. s:=S_FS;
  1271. end;
  1272. OS_F64:begin
  1273. op:=A_FLD;
  1274. { ???? }
  1275. s:=S_FL;
  1276. end;
  1277. OS_F80:begin
  1278. op:=A_FLD;
  1279. s:=S_FX;
  1280. end;
  1281. OS_C64:begin
  1282. op:=A_FILD;
  1283. s:=S_IQ;
  1284. end;
  1285. else internalerror(17);
  1286. end;*)
  1287. END;
  1288. procedure TCgSparc.floatload(list:TAasmOutput;t:tcgsize;CONST ref:TReference);
  1289. VAR
  1290. op:tasmop;
  1291. s:topsize;
  1292. BEGIN
  1293. floatloadops(t,op,s);
  1294. list.concat(Taicpu.Op_ref(op,ref));
  1295. { inc(trgcpu(rg).fpuvaroffset);}
  1296. END;
  1297. procedure TCgSparc.floatstoreops(t:tcgsize;var op:tasmop;var s:topsize);
  1298. BEGIN
  1299. { case t of
  1300. OS_F32:begin
  1301. op:=A_FSTP;
  1302. s:=S_FS;
  1303. end;
  1304. OS_F64:begin
  1305. op:=A_FSTP;
  1306. s:=S_FL;
  1307. end;
  1308. OS_F80:begin
  1309. op:=A_FSTP;
  1310. s:=S_FX;
  1311. end;
  1312. OS_C64:begin
  1313. op:=A_FISTP;
  1314. s:=S_IQ;
  1315. end;
  1316. else
  1317. internalerror(17);
  1318. end;}
  1319. end;
  1320. procedure TCgSparc.floatstore(list:TAasmOutput;t:tcgsize;CONST ref:TReference);
  1321. VAR
  1322. op:tasmop;
  1323. s:topsize;
  1324. BEGIN
  1325. floatstoreops(t,op,s);
  1326. list.concat(Taicpu.Op_ref(op,ref));
  1327. { dec(trgcpu(rg).fpuvaroffset);}
  1328. END;
  1329. BEGIN
  1330. cg:=TCgSparc.Create;
  1331. cg64:=TCg64Sparc.Create;
  1332. END.
  1333. {
  1334. $Log$
  1335. Revision 1.36 2003-01-22 22:30:03 mazen
  1336. - internal errors rmoved from a_loar_reg_reg when reg sizes differs from 32
  1337. Revision 1.35 2003/01/20 22:21:36 mazen
  1338. * many stuff related to RTL fixed
  1339. Revision 1.34 2003/01/08 18:43:58 daniel
  1340. * Tregister changed into a record
  1341. Revision 1.33 2003/01/07 22:03:40 mazen
  1342. * adding unequaln node support to sparc compiler
  1343. Revision 1.32 2003/01/06 22:51:47 mazen
  1344. * fixing bugs related to load_reg_ref
  1345. Revision 1.31 2003/01/05 21:32:35 mazen
  1346. * fixing several bugs compiling the RTL
  1347. Revision 1.30 2003/01/05 13:36:53 florian
  1348. * x86-64 compiles
  1349. + very basic support for float128 type (x86-64 only)
  1350. Revision 1.29 2002/12/25 20:59:49 mazen
  1351. - many emitXXX removed from cga.pas in order to remove that file.
  1352. Revision 1.28 2002/12/22 19:26:31 mazen
  1353. * many internal errors related to unimplemented nodes are fixed
  1354. Revision 1.27 2002/12/21 23:21:47 mazen
  1355. + added support for the shift nodes
  1356. + added debug output on screen with -an command line option
  1357. Revision 1.26 2002/11/25 19:21:49 mazen
  1358. * fixed support of nSparcInline
  1359. Revision 1.25 2002/11/25 17:43:28 peter
  1360. * splitted defbase in defutil,symutil,defcmp
  1361. * merged isconvertable and is_equal into compare_defs(_ext)
  1362. * made operator search faster by walking the list only once
  1363. Revision 1.24 2002/11/17 17:49:09 mazen
  1364. + return_result_reg and function_result_reg are now used, in all plateforms, to pass functions result between called function and its caller. See the explanation of each one
  1365. Revision 1.23 2002/11/10 19:07:46 mazen
  1366. * SPARC calling mechanism almost OK (as in GCC./mppcsparc )
  1367. Revision 1.22 2002/11/06 11:31:24 mazen
  1368. * op_reg_reg_reg don't need any more a TOpSize parameter
  1369. Revision 1.21 2002/11/05 16:15:00 mazen
  1370. *** empty log message ***
  1371. Revision 1.20 2002/11/03 20:22:40 mazen
  1372. * parameter handling updated
  1373. Revision 1.19 2002/10/28 20:59:17 mazen
  1374. * TOpSize values changed S_L --> S_SW
  1375. Revision 1.18 2002/10/22 13:43:01 mazen
  1376. - cga.pas redueced to an empty unit
  1377. Revision 1.17 2002/10/20 19:01:38 mazen
  1378. + op_raddr_reg and op_caddr_reg added to fix functions prologue
  1379. Revision 1.16 2002/10/13 21:46:07 mazen
  1380. * assembler output format fixed
  1381. Revision 1.15 2002/10/11 13:35:14 mazen
  1382. *** empty log message ***
  1383. Revision 1.14 2002/10/10 19:57:51 mazen
  1384. * Just to update repsitory
  1385. Revision 1.13 2002/10/10 15:10:39 mazen
  1386. * Internal error fixed, but usually i386 parameter model used
  1387. Revision 1.12 2002/10/08 17:17:03 mazen
  1388. *** empty log message ***
  1389. Revision 1.11 2002/10/07 20:33:04 mazen
  1390. word alignement modified in g_stack_frame
  1391. Revision 1.10 2002/10/04 21:57:42 mazen
  1392. * register allocation for parameters now done in cpupara, but InternalError(200109223) in cgcpu.pas:1053 is still not fixed du to location_force problem in ncgutils.pas:419
  1393. Revision 1.9 2002/10/02 22:20:28 mazen
  1394. + out registers allocator for the first 6 scalar parameters which must be passed into %o0..%o5
  1395. Revision 1.8 2002/10/01 21:35:58 mazen
  1396. + procedures exiting prologue added and stack frame now restored in the delay slot of the return (JMPL) instruction
  1397. Revision 1.7 2002/10/01 21:06:29 mazen
  1398. attinst.inc --> strinst.inc
  1399. Revision 1.6 2002/10/01 17:41:50 florian
  1400. * fixed log and id
  1401. }