cgcpu.pas 72 KB

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  1. {
  2. Copyright (c) 2008 by Florian Klaempfl
  3. Member of the Free Pascal development team
  4. This unit implements the code generator for the AVR
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. unit cgcpu;
  19. {$i fpcdefs.inc}
  20. interface
  21. uses
  22. globtype,symtype,symdef,
  23. cgbase,cgutils,cgobj,
  24. aasmbase,aasmcpu,aasmtai,aasmdata,
  25. parabase,
  26. cpubase,cpuinfo,node,cg64f32,rgcpu;
  27. type
  28. { tcgavr }
  29. tcgavr = class(tcg)
  30. { true, if the next arithmetic operation should modify the flags }
  31. cgsetflags : boolean;
  32. procedure init_register_allocators;override;
  33. procedure done_register_allocators;override;
  34. function getintregister(list:TAsmList;size:Tcgsize):Tregister;override;
  35. function getaddressregister(list:TAsmList):TRegister;override;
  36. procedure a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);override;
  37. procedure a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);override;
  38. procedure a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);override;
  39. procedure a_load_reg_cgpara(list : TAsmList; size : tcgsize;r : tregister; const cgpara : tcgpara);override;
  40. procedure a_call_name(list : TAsmList;const s : string; weak: boolean);override;
  41. procedure a_call_reg(list : TAsmList;reg: tregister);override;
  42. procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister); override;
  43. procedure a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src, dst : TRegister); override;
  44. procedure a_op_reg_reg_reg(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister); override;
  45. procedure a_op_const_reg_reg(list : TAsmList;op : TOpCg;size : tcgsize; a : tcgint;src,dst : tregister); override;
  46. { move instructions }
  47. procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);override;
  48. procedure a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
  49. procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
  50. procedure a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
  51. { fpu move instructions }
  52. procedure a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
  53. procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
  54. procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
  55. { comparison operations }
  56. procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
  57. l : tasmlabel);override;
  58. procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
  59. procedure a_jmp_name(list : TAsmList;const s : string); override;
  60. procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
  61. procedure a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel); override;
  62. procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  63. procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
  64. procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
  65. procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
  66. procedure g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);override;
  67. procedure g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  68. procedure g_overflowcheck(list: TAsmList; const l: tlocation; def: tdef); override;
  69. procedure g_save_registers(list : TAsmList);override;
  70. procedure g_restore_registers(list : TAsmList);override;
  71. procedure a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  72. procedure fixref(list : TAsmList;var ref : treference);
  73. function normalize_ref(list : TAsmList;ref : treference;
  74. tmpreg : tregister) : treference;
  75. procedure emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  76. procedure a_adjust_sp(list: TAsmList; value: longint);
  77. function GetLoad(const ref : treference) : tasmop;
  78. function GetStore(const ref: treference): tasmop;
  79. protected
  80. procedure a_op_reg_reg_internal(list: TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
  81. procedure a_op_const_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg, reghi: TRegister);
  82. end;
  83. tcg64favr = class(tcg64f32)
  84. procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  85. procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
  86. end;
  87. procedure create_codegen;
  88. const
  89. TOpCG2AsmOp: Array[topcg] of TAsmOp = (A_NONE,A_MOV,A_ADD,A_AND,A_NONE,
  90. A_NONE,A_MULS,A_MUL,A_NEG,A_COM,A_OR,
  91. A_ASR,A_LSL,A_LSR,A_SUB,A_EOR,A_ROL,A_ROR);
  92. implementation
  93. uses
  94. globals,verbose,systems,cutils,
  95. fmodule,
  96. symconst,symsym,symtable,
  97. tgobj,rgobj,
  98. procinfo,cpupi,
  99. paramgr;
  100. procedure tcgavr.init_register_allocators;
  101. begin
  102. inherited init_register_allocators;
  103. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  104. [RS_R18,RS_R19,RS_R20,RS_R21,RS_R22,RS_R23,RS_R24,RS_R25,
  105. RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,RS_R9,
  106. RS_R10,RS_R11,RS_R12,RS_R13,RS_R14,RS_R15,RS_R16,RS_R17],first_int_imreg,[]);
  107. end;
  108. procedure tcgavr.done_register_allocators;
  109. begin
  110. rg[R_INTREGISTER].free;
  111. // rg[R_ADDRESSREGISTER].free;
  112. inherited done_register_allocators;
  113. end;
  114. function tcgavr.getintregister(list: TAsmList; size: Tcgsize): Tregister;
  115. var
  116. tmp1,tmp2,tmp3 : TRegister;
  117. begin
  118. case size of
  119. OS_8,OS_S8:
  120. Result:=inherited getintregister(list, size);
  121. OS_16,OS_S16:
  122. begin
  123. Result:=inherited getintregister(list, OS_8);
  124. { ensure that the high register can be retrieved by
  125. GetNextReg
  126. }
  127. if inherited getintregister(list, OS_8)<>GetNextReg(Result) then
  128. internalerror(2011021331);
  129. end;
  130. OS_32,OS_S32:
  131. begin
  132. Result:=inherited getintregister(list, OS_8);
  133. tmp1:=inherited getintregister(list, OS_8);
  134. { ensure that the high register can be retrieved by
  135. GetNextReg
  136. }
  137. if tmp1<>GetNextReg(Result) then
  138. internalerror(2011021332);
  139. tmp2:=inherited getintregister(list, OS_8);
  140. { ensure that the upper register can be retrieved by
  141. GetNextReg
  142. }
  143. if tmp2<>GetNextReg(tmp1) then
  144. internalerror(2011021333);
  145. tmp3:=inherited getintregister(list, OS_8);
  146. { ensure that the upper register can be retrieved by
  147. GetNextReg
  148. }
  149. if tmp3<>GetNextReg(tmp2) then
  150. internalerror(2011021334);
  151. end;
  152. else
  153. internalerror(2011021330);
  154. end;
  155. end;
  156. function tcgavr.getaddressregister(list: TAsmList): TRegister;
  157. begin
  158. Result:=getintregister(list,OS_ADDR);
  159. end;
  160. procedure tcgavr.a_load_reg_cgpara(list : TAsmList;size : tcgsize;r : tregister;const cgpara : tcgpara);
  161. procedure load_para_loc(r : TRegister;paraloc : PCGParaLocation);
  162. var
  163. ref : treference;
  164. begin
  165. paramanager.allocparaloc(list,paraloc);
  166. case paraloc^.loc of
  167. LOC_REGISTER,LOC_CREGISTER:
  168. a_load_reg_reg(list,paraloc^.size,paraloc^.size,r,paraloc^.register);
  169. LOC_REFERENCE,LOC_CREFERENCE:
  170. begin
  171. reference_reset_base(ref,paraloc^.reference.index,paraloc^.reference.offset,2);
  172. a_load_reg_ref(list,paraloc^.size,paraloc^.size,r,ref);
  173. end;
  174. else
  175. internalerror(2002071004);
  176. end;
  177. end;
  178. var
  179. i, i2 : longint;
  180. hp : PCGParaLocation;
  181. begin
  182. { if use_push(cgpara) then
  183. begin
  184. if tcgsize2size[cgpara.Size] > 2 then
  185. begin
  186. if tcgsize2size[cgpara.Size] <> 4 then
  187. internalerror(2013031101);
  188. if cgpara.location^.Next = nil then
  189. begin
  190. if tcgsize2size[cgpara.location^.size] <> 4 then
  191. internalerror(2013031101);
  192. end
  193. else
  194. begin
  195. if tcgsize2size[cgpara.location^.size] <> 2 then
  196. internalerror(2013031101);
  197. if tcgsize2size[cgpara.location^.Next^.size] <> 2 then
  198. internalerror(2013031101);
  199. if cgpara.location^.Next^.Next <> nil then
  200. internalerror(2013031101);
  201. end;
  202. if tcgsize2size[cgpara.size]>cgpara.alignment then
  203. pushsize:=cgpara.size
  204. else
  205. pushsize:=int_cgsize(cgpara.alignment);
  206. pushsize2 := int_cgsize(tcgsize2size[pushsize] - 2);
  207. list.concat(taicpu.op_reg(A_PUSH,TCgsize2opsize[pushsize2],makeregsize(list,GetNextReg(r),pushsize2)));
  208. list.concat(taicpu.op_reg(A_PUSH,S_W,makeregsize(list,r,OS_16)));
  209. end
  210. else
  211. begin
  212. cgpara.check_simple_location;
  213. if tcgsize2size[cgpara.location^.size]>cgpara.alignment then
  214. pushsize:=cgpara.location^.size
  215. else
  216. pushsize:=int_cgsize(cgpara.alignment);
  217. list.concat(taicpu.op_reg(A_PUSH,TCgsize2opsize[pushsize],makeregsize(list,r,pushsize)));
  218. end;
  219. end
  220. else }
  221. begin
  222. if not(tcgsize2size[cgpara.Size] in [1..4]) then
  223. internalerror(2014011101);
  224. hp:=cgpara.location;
  225. i:=0;
  226. while i<tcgsize2size[cgpara.Size] do
  227. begin
  228. if not(assigned(hp)) then
  229. internalerror(2014011102);
  230. inc(i, tcgsize2size[hp^.Size]);
  231. if hp^.Loc=LOC_REGISTER then
  232. begin
  233. load_para_loc(r,hp);
  234. hp:=hp^.Next;
  235. r:=GetNextReg(r);
  236. end
  237. else
  238. begin
  239. load_para_loc(r,hp);
  240. for i2:=1 to tcgsize2size[hp^.Size] do
  241. r:=GetNextReg(r);
  242. hp:=hp^.Next;
  243. end;
  244. end;
  245. if assigned(hp) then
  246. internalerror(2014011103);
  247. end;
  248. end;
  249. procedure tcgavr.a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);
  250. var
  251. i : longint;
  252. hp : PCGParaLocation;
  253. begin
  254. if not(tcgsize2size[paraloc.Size] in [1..4]) then
  255. internalerror(2014011101);
  256. hp:=paraloc.location;
  257. for i:=1 to tcgsize2size[paraloc.Size] do
  258. begin
  259. if not(assigned(hp)) then
  260. internalerror(2014011105);
  261. case hp^.loc of
  262. LOC_REGISTER,LOC_CREGISTER:
  263. begin
  264. if (tcgsize2size[hp^.size]<>1) or
  265. (hp^.shiftval<>0) then
  266. internalerror(2015041101);
  267. a_load_const_reg(list,hp^.size,(a shr (8*(i-1))) and $ff,hp^.register);
  268. hp:=hp^.Next;
  269. end;
  270. LOC_REFERENCE,LOC_CREFERENCE:
  271. list.concat(taicpu.op_const(A_PUSH,(a shr (8*(i-1))) and $ff));
  272. else
  273. internalerror(2002071004);
  274. end;
  275. end;
  276. end;
  277. procedure tcgavr.a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);
  278. var
  279. tmpref, ref: treference;
  280. location: pcgparalocation;
  281. sizeleft: tcgint;
  282. begin
  283. location := paraloc.location;
  284. tmpref := r;
  285. sizeleft := paraloc.intsize;
  286. while assigned(location) do
  287. begin
  288. paramanager.allocparaloc(list,location);
  289. case location^.loc of
  290. LOC_REGISTER,LOC_CREGISTER:
  291. a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
  292. LOC_REFERENCE:
  293. begin
  294. reference_reset_base(ref,location^.reference.index,location^.reference.offset,paraloc.alignment);
  295. { doubles in softemu mode have a strange order of registers and references }
  296. if location^.size=OS_32 then
  297. g_concatcopy(list,tmpref,ref,4)
  298. else
  299. begin
  300. g_concatcopy(list,tmpref,ref,sizeleft);
  301. if assigned(location^.next) then
  302. internalerror(2005010710);
  303. end;
  304. end;
  305. LOC_VOID:
  306. begin
  307. // nothing to do
  308. end;
  309. else
  310. internalerror(2002081103);
  311. end;
  312. inc(tmpref.offset,tcgsize2size[location^.size]);
  313. dec(sizeleft,tcgsize2size[location^.size]);
  314. location := location^.next;
  315. end;
  316. end;
  317. procedure tcgavr.a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);
  318. var
  319. tmpreg: tregister;
  320. begin
  321. tmpreg:=getaddressregister(list);
  322. a_loadaddr_ref_reg(list,r,tmpreg);
  323. a_load_reg_cgpara(list,OS_ADDR,tmpreg,paraloc);
  324. end;
  325. procedure tcgavr.a_call_name(list : TAsmList;const s : string; weak: boolean);
  326. begin
  327. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  328. list.concat(taicpu.op_sym(A_CALL,current_asmdata.RefAsmSymbol(s)))
  329. else
  330. list.concat(taicpu.op_sym(A_RCALL,current_asmdata.RefAsmSymbol(s)));
  331. include(current_procinfo.flags,pi_do_call);
  332. end;
  333. procedure tcgavr.a_call_reg(list : TAsmList;reg: tregister);
  334. begin
  335. a_reg_alloc(list,NR_ZLO);
  336. a_reg_alloc(list,NR_ZHI);
  337. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZLO,reg));
  338. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZHI,GetHigh(reg)));
  339. list.concat(taicpu.op_none(A_ICALL));
  340. a_reg_dealloc(list,NR_ZLO);
  341. a_reg_dealloc(list,NR_ZHI);
  342. include(current_procinfo.flags,pi_do_call);
  343. end;
  344. procedure tcgavr.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister);
  345. begin
  346. if not(size in [OS_S8,OS_8,OS_S16,OS_16,OS_S32,OS_32]) then
  347. internalerror(2012102403);
  348. a_op_const_reg_internal(list,Op,size,a,reg,NR_NO);
  349. end;
  350. procedure tcgavr.a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src, dst : TRegister);
  351. begin
  352. if not(size in [OS_S8,OS_8,OS_S16,OS_16,OS_S32,OS_32]) then
  353. internalerror(2012102401);
  354. a_op_reg_reg_internal(list,Op,size,src,NR_NO,dst,NR_NO);
  355. end;
  356. procedure tcgavr.a_op_reg_reg_reg(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister);
  357. begin
  358. if (op in [OP_MUL,OP_IMUL]) and (size in [OS_16,OS_S16]) then
  359. begin
  360. getcpuregister(list,NR_R0);
  361. getcpuregister(list,NR_R1);
  362. list.concat(taicpu.op_reg_reg(A_MUL,src1,src2));
  363. emit_mov(list,dst,NR_R0);
  364. emit_mov(list,GetNextReg(dst),NR_R1);
  365. list.concat(taicpu.op_reg_reg(A_MUL,GetNextReg(src1),src2));
  366. list.concat(taicpu.op_reg_reg(A_ADD,GetNextReg(dst),NR_R0));
  367. list.concat(taicpu.op_reg_reg(A_MUL,src1,GetNextReg(src2)));
  368. list.concat(taicpu.op_reg_reg(A_ADD,GetNextReg(dst),NR_R0));
  369. ungetcpuregister(list,NR_R0);
  370. list.concat(taicpu.op_reg(A_CLR,NR_R1));
  371. ungetcpuregister(list,NR_R1);
  372. end
  373. else
  374. inherited a_op_reg_reg_reg(list,op,size,src1,src2,dst);
  375. end;
  376. procedure tcgavr.a_op_const_reg_reg(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister);
  377. begin
  378. if (op in [OP_MUL,OP_IMUL]) and (size in [OS_16,OS_S16]) and (a in [2,4,8]) then
  379. begin
  380. emit_mov(list,dst,src);
  381. emit_mov(list,GetNextReg(dst),GetNextReg(src));
  382. a:=a shr 1;
  383. while a>0 do
  384. begin
  385. list.concat(taicpu.op_reg(A_LSL,dst));
  386. list.concat(taicpu.op_reg(A_ROL,GetNextReg(dst)));
  387. a:=a shr 1;
  388. end;
  389. end
  390. else
  391. inherited a_op_const_reg_reg(list,op,size,a,src,dst);
  392. end;
  393. procedure tcgavr.a_op_reg_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
  394. var
  395. countreg,
  396. tmpreg: tregister;
  397. i : integer;
  398. instr : taicpu;
  399. paraloc1,paraloc2,paraloc3 : TCGPara;
  400. l1,l2 : tasmlabel;
  401. pd : tprocdef;
  402. procedure NextSrcDst;
  403. begin
  404. if i=5 then
  405. begin
  406. dst:=dsthi;
  407. src:=srchi;
  408. end
  409. else
  410. begin
  411. dst:=GetNextReg(dst);
  412. src:=GetNextReg(src);
  413. end;
  414. end;
  415. { iterates TmpReg through all registers of dst }
  416. procedure NextTmp;
  417. begin
  418. if i=5 then
  419. tmpreg:=dsthi
  420. else
  421. tmpreg:=GetNextReg(tmpreg);
  422. end;
  423. begin
  424. case op of
  425. OP_ADD:
  426. begin
  427. list.concat(taicpu.op_reg_reg(A_ADD,dst,src));
  428. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  429. begin
  430. for i:=2 to tcgsize2size[size] do
  431. begin
  432. NextSrcDst;
  433. list.concat(taicpu.op_reg_reg(A_ADC,dst,src));
  434. end;
  435. end;
  436. end;
  437. OP_SUB:
  438. begin
  439. list.concat(taicpu.op_reg_reg(A_SUB,dst,src));
  440. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  441. begin
  442. for i:=2 to tcgsize2size[size] do
  443. begin
  444. NextSrcDst;
  445. list.concat(taicpu.op_reg_reg(A_SBC,dst,src));
  446. end;
  447. end;
  448. end;
  449. OP_NEG:
  450. begin
  451. if src<>dst then
  452. begin
  453. if size in [OS_S64,OS_64] then
  454. begin
  455. a_load_reg_reg(list,OS_32,OS_32,src,dst);
  456. a_load_reg_reg(list,OS_32,OS_32,srchi,dsthi);
  457. end
  458. else
  459. a_load_reg_reg(list,size,size,src,dst);
  460. end;
  461. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  462. begin
  463. tmpreg:=GetNextReg(dst);
  464. for i:=2 to tcgsize2size[size] do
  465. begin
  466. list.concat(taicpu.op_reg(A_COM,tmpreg));
  467. NextTmp;
  468. end;
  469. list.concat(taicpu.op_reg(A_NEG,dst));
  470. tmpreg:=GetNextReg(dst);
  471. for i:=2 to tcgsize2size[size] do
  472. begin
  473. list.concat(taicpu.op_reg_const(A_SBCI,tmpreg,-1));
  474. NextTmp;
  475. end;
  476. end;
  477. end;
  478. OP_NOT:
  479. begin
  480. for i:=1 to tcgsize2size[size] do
  481. begin
  482. if src<>dst then
  483. a_load_reg_reg(list,OS_8,OS_8,src,dst);
  484. list.concat(taicpu.op_reg(A_COM,dst));
  485. NextSrcDst;
  486. end;
  487. end;
  488. OP_MUL,OP_IMUL:
  489. begin
  490. if size in [OS_8,OS_S8] then
  491. begin
  492. cg.a_reg_alloc(list,NR_R0);
  493. cg.a_reg_alloc(list,NR_R1);
  494. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src));
  495. list.concat(taicpu.op_reg(A_CLR,NR_R1));
  496. cg.a_reg_dealloc(list,NR_R1);
  497. list.concat(taicpu.op_reg_reg(A_MOV,dst,NR_R0));
  498. cg.a_reg_dealloc(list,NR_R0);
  499. end
  500. else if size=OS_16 then
  501. begin
  502. tmpreg:=getintregister(list,OS_16);
  503. emit_mov(list,tmpreg,dst);
  504. emit_mov(list,GetNextReg(tmpreg),GetNextReg(dst));
  505. list.concat(taicpu.op_reg_reg(A_MUL,tmpreg,src));
  506. emit_mov(list,dst,NR_R0);
  507. emit_mov(list,GetNextReg(dst),NR_R1);
  508. list.concat(taicpu.op_reg_reg(A_MUL,GetNextReg(tmpreg),src));
  509. list.concat(taicpu.op_reg_reg(A_ADD,GetNextReg(dst),NR_R0));
  510. list.concat(taicpu.op_reg_reg(A_MUL,tmpreg,GetNextReg(src)));
  511. list.concat(taicpu.op_reg_reg(A_ADD,GetNextReg(dst),NR_R0));
  512. list.concat(taicpu.op_reg(A_CLR,NR_R1));
  513. { keep code for muls with overflow checking
  514. pd:=search_system_proc('fpc_mul_word');
  515. paraloc1.init;
  516. paraloc2.init;
  517. paraloc3.init;
  518. paramanager.getintparaloc(list,pd,1,paraloc1);
  519. paramanager.getintparaloc(list,pd,2,paraloc2);
  520. paramanager.getintparaloc(list,pd,3,paraloc3);
  521. a_load_const_cgpara(list,OS_8,0,paraloc3);
  522. a_load_reg_cgpara(list,OS_16,src,paraloc2);
  523. a_load_reg_cgpara(list,OS_16,dst,paraloc1);
  524. paramanager.freecgpara(list,paraloc3);
  525. paramanager.freecgpara(list,paraloc2);
  526. paramanager.freecgpara(list,paraloc1);
  527. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  528. a_call_name(list,'FPC_MUL_WORD',false);
  529. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  530. cg.a_reg_alloc(list,NR_R24);
  531. cg.a_reg_alloc(list,NR_R25);
  532. cg.a_load_reg_reg(list,OS_8,OS_8,NR_R24,dst);
  533. cg.a_reg_dealloc(list,NR_R24);
  534. cg.a_load_reg_reg(list,OS_8,OS_8,NR_R25,GetNextReg(dst));
  535. cg.a_reg_dealloc(list,NR_R25);
  536. paraloc3.done;
  537. paraloc2.done;
  538. paraloc1.done;
  539. }
  540. end
  541. else
  542. internalerror(2011022002);
  543. end;
  544. OP_DIV,OP_IDIV:
  545. { special stuff, needs separate handling inside code }
  546. { generator }
  547. internalerror(2011022001);
  548. OP_SHR,OP_SHL,OP_SAR,OP_ROL,OP_ROR:
  549. begin
  550. current_asmdata.getjumplabel(l1);
  551. current_asmdata.getjumplabel(l2);
  552. countreg:=getintregister(list,OS_8);
  553. a_load_reg_reg(list,size,OS_8,src,countreg);
  554. list.concat(taicpu.op_reg(A_TST,countreg));
  555. a_jmp_flags(list,F_EQ,l2);
  556. cg.a_label(list,l1);
  557. case op of
  558. OP_SHR:
  559. list.concat(taicpu.op_reg(A_LSR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  560. OP_SHL:
  561. list.concat(taicpu.op_reg(A_LSL,dst));
  562. OP_SAR:
  563. list.concat(taicpu.op_reg(A_ASR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  564. OP_ROR:
  565. begin
  566. { load carry? }
  567. if not(size in [OS_8,OS_S8]) then
  568. begin
  569. list.concat(taicpu.op_none(A_CLC));
  570. list.concat(taicpu.op_reg_const(A_SBRC,src,0));
  571. list.concat(taicpu.op_none(A_SEC));
  572. end;
  573. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  574. end;
  575. OP_ROL:
  576. begin
  577. { load carry? }
  578. if not(size in [OS_8,OS_S8]) then
  579. begin
  580. list.concat(taicpu.op_none(A_CLC));
  581. list.concat(taicpu.op_reg_const(A_SBRC,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1),7));
  582. list.concat(taicpu.op_none(A_SEC));
  583. end;
  584. list.concat(taicpu.op_reg(A_ROL,dst))
  585. end;
  586. else
  587. internalerror(2011030901);
  588. end;
  589. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  590. begin
  591. for i:=2 to tcgsize2size[size] do
  592. begin
  593. case op of
  594. OP_ROR,
  595. OP_SHR:
  596. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  597. OP_ROL,
  598. OP_SHL:
  599. list.concat(taicpu.op_reg(A_ROL,GetOffsetReg64(dst,dsthi,i-1)));
  600. OP_SAR:
  601. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  602. else
  603. internalerror(2011030902);
  604. end;
  605. end;
  606. end;
  607. list.concat(taicpu.op_reg(A_DEC,countreg));
  608. a_jmp_flags(list,F_NE,l1);
  609. // keep registers alive
  610. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  611. cg.a_label(list,l2);
  612. end;
  613. OP_AND,OP_OR,OP_XOR:
  614. begin
  615. for i:=1 to tcgsize2size[size] do
  616. begin
  617. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src));
  618. NextSrcDst;
  619. end;
  620. end;
  621. else
  622. internalerror(2011022004);
  623. end;
  624. end;
  625. procedure tcgavr.a_op_const_reg_internal(list: TAsmList; Op: TOpCG;
  626. size: TCGSize; a: tcgint; reg, reghi: TRegister);
  627. var
  628. mask : qword;
  629. shift : byte;
  630. i : byte;
  631. tmpreg : tregister;
  632. tmpreg64 : tregister64;
  633. procedure NextReg;
  634. begin
  635. if i=5 then
  636. reg:=reghi
  637. else
  638. reg:=GetNextReg(reg);
  639. end;
  640. var
  641. curvalue : byte;
  642. begin
  643. optimize_op_const(size,op,a);
  644. mask:=$ff;
  645. shift:=0;
  646. case op of
  647. OP_NONE:
  648. begin
  649. { Opcode is optimized away }
  650. end;
  651. OP_MOVE:
  652. begin
  653. { Optimized, replaced with a simple load }
  654. a_load_const_reg(list,size,a,reg);
  655. end;
  656. OP_OR:
  657. begin
  658. for i:=1 to tcgsize2size[size] do
  659. begin
  660. list.concat(taicpu.op_reg_const(A_ORI,reg,(qword(a) and mask) shr shift));
  661. NextReg;
  662. mask:=mask shl 8;
  663. inc(shift,8);
  664. end;
  665. end;
  666. OP_AND:
  667. begin
  668. for i:=1 to tcgsize2size[size] do
  669. begin
  670. list.concat(taicpu.op_reg_const(A_ANDI,reg,(qword(a) and mask) shr shift));
  671. NextReg;
  672. mask:=mask shl 8;
  673. inc(shift,8);
  674. end;
  675. end;
  676. OP_SUB:
  677. begin
  678. list.concat(taicpu.op_reg_const(A_SUBI,reg,a and mask));
  679. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  680. begin
  681. for i:=2 to tcgsize2size[size] do
  682. begin
  683. NextReg;
  684. mask:=mask shl 8;
  685. inc(shift,8);
  686. curvalue:=(qword(a) and mask) shr shift;
  687. { decrease pressure on upper half of registers by using SBC ...,R1 instead
  688. of SBCI ...,0 }
  689. if curvalue=0 then
  690. list.concat(taicpu.op_reg_reg(A_SBC,reg,NR_R1))
  691. else
  692. list.concat(taicpu.op_reg_const(A_SBCI,reg,curvalue));
  693. end;
  694. end;
  695. end;
  696. OP_ADD:
  697. begin
  698. curvalue:=a and mask;
  699. if curvalue=0 then
  700. list.concat(taicpu.op_reg_reg(A_ADD,reg,NR_R1))
  701. else
  702. begin
  703. tmpreg:=getintregister(list,OS_8);
  704. a_load_const_reg(list,OS_8,curvalue,tmpreg);
  705. list.concat(taicpu.op_reg_reg(A_ADD,reg,tmpreg));
  706. end;
  707. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  708. begin
  709. for i:=2 to tcgsize2size[size] do
  710. begin
  711. NextReg;
  712. mask:=mask shl 8;
  713. inc(shift,8);
  714. curvalue:=(qword(a) and mask) shr shift;
  715. { decrease pressure on upper half of registers by using ADC ...,R1 instead
  716. of ADD ...,0 }
  717. if curvalue=0 then
  718. list.concat(taicpu.op_reg_reg(A_ADC,reg,NR_R1))
  719. else
  720. begin
  721. tmpreg:=getintregister(list,OS_8);
  722. a_load_const_reg(list,OS_8,curvalue,tmpreg);
  723. list.concat(taicpu.op_reg_reg(A_ADC,reg,tmpreg));
  724. end;
  725. end;
  726. end;
  727. end;
  728. else
  729. begin
  730. if size in [OS_64,OS_S64] then
  731. begin
  732. tmpreg64.reglo:=getintregister(list,OS_32);
  733. tmpreg64.reghi:=getintregister(list,OS_32);
  734. cg64.a_load64_const_reg(list,a,tmpreg64);
  735. cg64.a_op64_reg_reg(list,op,size,tmpreg64,joinreg64(reg,reghi));
  736. end
  737. else
  738. begin
  739. {$if 0}
  740. { code not working yet }
  741. if (op=OP_SAR) and (a=31) and (size in [OS_32,OS_S32]) then
  742. begin
  743. tmpreg:=reg;
  744. for i:=1 to 4 do
  745. begin
  746. list.concat(taicpu.op_reg_reg(A_MOV,tmpreg,NR_R1));
  747. tmpreg:=GetNextReg(tmpreg);
  748. end;
  749. end
  750. else
  751. {$endif}
  752. begin
  753. tmpreg:=getintregister(list,size);
  754. a_load_const_reg(list,size,a,tmpreg);
  755. a_op_reg_reg(list,op,size,tmpreg,reg);
  756. end;
  757. end;
  758. end;
  759. end;
  760. end;
  761. procedure tcgavr.a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);
  762. var
  763. mask : qword;
  764. shift : byte;
  765. i : byte;
  766. begin
  767. mask:=$ff;
  768. shift:=0;
  769. for i:=1 to tcgsize2size[size] do
  770. begin
  771. if ((qword(a) and mask) shr shift)=0 then
  772. emit_mov(list,reg,NR_R1)
  773. else
  774. list.concat(taicpu.op_reg_const(A_LDI,reg,(qword(a) and mask) shr shift));
  775. mask:=mask shl 8;
  776. inc(shift,8);
  777. reg:=GetNextReg(reg);
  778. end;
  779. end;
  780. function tcgavr.normalize_ref(list:TAsmList;ref: treference;tmpreg : tregister) : treference;
  781. procedure maybegetcpuregister(list:tasmlist;reg : tregister);
  782. begin
  783. { allocate the register only, if a cpu register is passed }
  784. if getsupreg(reg)<first_int_imreg then
  785. getcpuregister(list,reg);
  786. end;
  787. var
  788. tmpref : treference;
  789. l : tasmlabel;
  790. begin
  791. Result:=ref;
  792. if ref.addressmode<>AM_UNCHANGED then
  793. internalerror(2011021701);
  794. { Be sure to have a base register }
  795. if (ref.base=NR_NO) then
  796. begin
  797. { only symbol+offset? }
  798. if ref.index=NR_NO then
  799. exit;
  800. ref.base:=ref.index;
  801. ref.index:=NR_NO;
  802. end;
  803. if assigned(ref.symbol) or (ref.offset<>0) then
  804. begin
  805. reference_reset(tmpref,0);
  806. tmpref.symbol:=ref.symbol;
  807. tmpref.offset:=ref.offset;
  808. if assigned(ref.symbol) and (ref.symbol.typ in [AT_FUNCTION,AT_LABEL]) then
  809. tmpref.refaddr:=addr_lo8_gs
  810. else
  811. tmpref.refaddr:=addr_lo8;
  812. maybegetcpuregister(list,tmpreg);
  813. list.concat(taicpu.op_reg_ref(A_LDI,tmpreg,tmpref));
  814. if assigned(ref.symbol) and (ref.symbol.typ in [AT_FUNCTION,AT_LABEL]) then
  815. tmpref.refaddr:=addr_hi8_gs
  816. else
  817. tmpref.refaddr:=addr_hi8;
  818. maybegetcpuregister(list,GetNextReg(tmpreg));
  819. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(tmpreg),tmpref));
  820. if (ref.base<>NR_NO) then
  821. begin
  822. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
  823. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
  824. end;
  825. if (ref.index<>NR_NO) then
  826. begin
  827. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  828. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  829. end;
  830. ref.symbol:=nil;
  831. ref.offset:=0;
  832. ref.base:=tmpreg;
  833. ref.index:=NR_NO;
  834. end
  835. else if (ref.base<>NR_NO) and (ref.index<>NR_NO) then
  836. begin
  837. maybegetcpuregister(list,tmpreg);
  838. emit_mov(list,tmpreg,ref.base);
  839. maybegetcpuregister(list,GetNextReg(tmpreg));
  840. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  841. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  842. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  843. ref.base:=tmpreg;
  844. ref.index:=NR_NO;
  845. end
  846. else if (ref.base<>NR_NO) then
  847. begin
  848. maybegetcpuregister(list,tmpreg);
  849. emit_mov(list,tmpreg,ref.base);
  850. maybegetcpuregister(list,GetNextReg(tmpreg));
  851. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  852. ref.base:=tmpreg;
  853. ref.index:=NR_NO;
  854. end
  855. else if (ref.index<>NR_NO) then
  856. begin
  857. maybegetcpuregister(list,tmpreg);
  858. emit_mov(list,tmpreg,ref.index);
  859. maybegetcpuregister(list,GetNextReg(tmpreg));
  860. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
  861. ref.base:=tmpreg;
  862. ref.index:=NR_NO;
  863. end;
  864. Result:=ref;
  865. end;
  866. procedure tcgavr.a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);
  867. var
  868. href : treference;
  869. conv_done: boolean;
  870. tmpreg : tregister;
  871. i : integer;
  872. QuickRef : Boolean;
  873. begin
  874. QuickRef:=false;
  875. if not((Ref.addressmode=AM_UNCHANGED) and
  876. (Ref.symbol=nil) and
  877. ((Ref.base=NR_R28) or
  878. (Ref.base=NR_R29)) and
  879. (Ref.Index=NR_No) and
  880. (Ref.Offset in [0..64-tcgsize2size[tosize]])) and
  881. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  882. href:=normalize_ref(list,Ref,NR_R30)
  883. else
  884. begin
  885. QuickRef:=true;
  886. href:=Ref;
  887. end;
  888. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  889. internalerror(2011021307);
  890. conv_done:=false;
  891. if tosize<>fromsize then
  892. begin
  893. conv_done:=true;
  894. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  895. fromsize:=tosize;
  896. case fromsize of
  897. OS_8:
  898. begin
  899. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  900. href.addressmode:=AM_POSTINCREMENT;
  901. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  902. for i:=2 to tcgsize2size[tosize] do
  903. begin
  904. if QuickRef then
  905. inc(href.offset);
  906. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  907. href.addressmode:=AM_POSTINCREMENT
  908. else
  909. href.addressmode:=AM_UNCHANGED;
  910. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  911. end;
  912. end;
  913. OS_S8:
  914. begin
  915. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  916. href.addressmode:=AM_POSTINCREMENT;
  917. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  918. if tcgsize2size[tosize]>1 then
  919. begin
  920. tmpreg:=getintregister(list,OS_8);
  921. emit_mov(list,tmpreg,NR_R1);
  922. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  923. list.concat(taicpu.op_reg(A_COM,tmpreg));
  924. for i:=2 to tcgsize2size[tosize] do
  925. begin
  926. if QuickRef then
  927. inc(href.offset);
  928. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  929. href.addressmode:=AM_POSTINCREMENT
  930. else
  931. href.addressmode:=AM_UNCHANGED;
  932. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  933. end;
  934. end;
  935. end;
  936. OS_16:
  937. begin
  938. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  939. href.addressmode:=AM_POSTINCREMENT;
  940. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  941. if QuickRef then
  942. inc(href.offset)
  943. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  944. href.addressmode:=AM_POSTINCREMENT
  945. else
  946. href.addressmode:=AM_UNCHANGED;
  947. reg:=GetNextReg(reg);
  948. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  949. for i:=3 to tcgsize2size[tosize] do
  950. begin
  951. if QuickRef then
  952. inc(href.offset);
  953. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  954. href.addressmode:=AM_POSTINCREMENT
  955. else
  956. href.addressmode:=AM_UNCHANGED;
  957. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  958. end;
  959. end;
  960. OS_S16:
  961. begin
  962. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  963. href.addressmode:=AM_POSTINCREMENT;
  964. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  965. if QuickRef then
  966. inc(href.offset)
  967. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  968. href.addressmode:=AM_POSTINCREMENT
  969. else
  970. href.addressmode:=AM_UNCHANGED;
  971. reg:=GetNextReg(reg);
  972. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  973. if tcgsize2size[tosize]>2 then
  974. begin
  975. tmpreg:=getintregister(list,OS_8);
  976. emit_mov(list,tmpreg,NR_R1);
  977. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  978. list.concat(taicpu.op_reg(A_COM,tmpreg));
  979. for i:=3 to tcgsize2size[tosize] do
  980. begin
  981. if QuickRef then
  982. inc(href.offset);
  983. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  984. href.addressmode:=AM_POSTINCREMENT
  985. else
  986. href.addressmode:=AM_UNCHANGED;
  987. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  988. end;
  989. end;
  990. end;
  991. else
  992. conv_done:=false;
  993. end;
  994. end;
  995. if not conv_done then
  996. begin
  997. for i:=1 to tcgsize2size[fromsize] do
  998. begin
  999. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  1000. href.addressmode:=AM_POSTINCREMENT
  1001. else
  1002. href.addressmode:=AM_UNCHANGED;
  1003. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  1004. if QuickRef then
  1005. inc(href.offset);
  1006. reg:=GetNextReg(reg);
  1007. end;
  1008. end;
  1009. if not(QuickRef) then
  1010. begin
  1011. ungetcpuregister(list,href.base);
  1012. ungetcpuregister(list,GetNextReg(href.base));
  1013. end;
  1014. end;
  1015. procedure tcgavr.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;
  1016. const Ref : treference;reg : tregister);
  1017. var
  1018. href : treference;
  1019. conv_done: boolean;
  1020. tmpreg : tregister;
  1021. i : integer;
  1022. QuickRef : boolean;
  1023. begin
  1024. QuickRef:=false;
  1025. if not((Ref.addressmode=AM_UNCHANGED) and
  1026. (Ref.symbol=nil) and
  1027. ((Ref.base=NR_R28) or
  1028. (Ref.base=NR_R29)) and
  1029. (Ref.Index=NR_No) and
  1030. (Ref.Offset in [0..64-tcgsize2size[fromsize]])) and
  1031. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  1032. href:=normalize_ref(list,Ref,NR_R30)
  1033. else
  1034. begin
  1035. QuickRef:=true;
  1036. href:=Ref;
  1037. end;
  1038. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  1039. internalerror(2011021307);
  1040. conv_done:=false;
  1041. if tosize<>fromsize then
  1042. begin
  1043. conv_done:=true;
  1044. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  1045. fromsize:=tosize;
  1046. case fromsize of
  1047. OS_8:
  1048. begin
  1049. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1050. for i:=2 to tcgsize2size[tosize] do
  1051. begin
  1052. reg:=GetNextReg(reg);
  1053. emit_mov(list,reg,NR_R1);
  1054. end;
  1055. end;
  1056. OS_S8:
  1057. begin
  1058. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1059. tmpreg:=reg;
  1060. if tcgsize2size[tosize]>1 then
  1061. begin
  1062. reg:=GetNextReg(reg);
  1063. emit_mov(list,reg,NR_R1);
  1064. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  1065. list.concat(taicpu.op_reg(A_COM,reg));
  1066. tmpreg:=reg;
  1067. for i:=3 to tcgsize2size[tosize] do
  1068. begin
  1069. reg:=GetNextReg(reg);
  1070. emit_mov(list,reg,tmpreg);
  1071. end;
  1072. end;
  1073. end;
  1074. OS_16:
  1075. begin
  1076. if not(QuickRef) then
  1077. href.addressmode:=AM_POSTINCREMENT;
  1078. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1079. if QuickRef then
  1080. inc(href.offset);
  1081. href.addressmode:=AM_UNCHANGED;
  1082. reg:=GetNextReg(reg);
  1083. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1084. for i:=3 to tcgsize2size[tosize] do
  1085. begin
  1086. reg:=GetNextReg(reg);
  1087. emit_mov(list,reg,NR_R1);
  1088. end;
  1089. end;
  1090. OS_S16:
  1091. begin
  1092. if not(QuickRef) then
  1093. href.addressmode:=AM_POSTINCREMENT;
  1094. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1095. if QuickRef then
  1096. inc(href.offset);
  1097. href.addressmode:=AM_UNCHANGED;
  1098. reg:=GetNextReg(reg);
  1099. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1100. tmpreg:=reg;
  1101. reg:=GetNextReg(reg);
  1102. emit_mov(list,reg,NR_R1);
  1103. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  1104. list.concat(taicpu.op_reg(A_COM,reg));
  1105. tmpreg:=reg;
  1106. for i:=4 to tcgsize2size[tosize] do
  1107. begin
  1108. reg:=GetNextReg(reg);
  1109. emit_mov(list,reg,tmpreg);
  1110. end;
  1111. end;
  1112. else
  1113. conv_done:=false;
  1114. end;
  1115. end;
  1116. if not conv_done then
  1117. begin
  1118. for i:=1 to tcgsize2size[fromsize] do
  1119. begin
  1120. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  1121. href.addressmode:=AM_POSTINCREMENT
  1122. else
  1123. href.addressmode:=AM_UNCHANGED;
  1124. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1125. if QuickRef then
  1126. inc(href.offset);
  1127. reg:=GetNextReg(reg);
  1128. end;
  1129. end;
  1130. if not(QuickRef) then
  1131. begin
  1132. ungetcpuregister(list,href.base);
  1133. ungetcpuregister(list,GetNextReg(href.base));
  1134. end;
  1135. end;
  1136. procedure tcgavr.a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);
  1137. var
  1138. conv_done: boolean;
  1139. tmpreg : tregister;
  1140. i : integer;
  1141. begin
  1142. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  1143. internalerror(2011021310);
  1144. conv_done:=false;
  1145. if tosize<>fromsize then
  1146. begin
  1147. conv_done:=true;
  1148. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  1149. fromsize:=tosize;
  1150. case fromsize of
  1151. OS_8:
  1152. begin
  1153. emit_mov(list,reg2,reg1);
  1154. for i:=2 to tcgsize2size[tosize] do
  1155. begin
  1156. reg2:=GetNextReg(reg2);
  1157. emit_mov(list,reg2,NR_R1);
  1158. end;
  1159. end;
  1160. OS_S8:
  1161. begin
  1162. emit_mov(list,reg2,reg1);
  1163. if tcgsize2size[tosize]>1 then
  1164. begin
  1165. reg2:=GetNextReg(reg2);
  1166. emit_mov(list,reg2,NR_R1);
  1167. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  1168. list.concat(taicpu.op_reg(A_COM,reg2));
  1169. tmpreg:=reg2;
  1170. for i:=3 to tcgsize2size[tosize] do
  1171. begin
  1172. reg2:=GetNextReg(reg2);
  1173. emit_mov(list,reg2,tmpreg);
  1174. end;
  1175. end;
  1176. end;
  1177. OS_16:
  1178. begin
  1179. emit_mov(list,reg2,reg1);
  1180. reg1:=GetNextReg(reg1);
  1181. reg2:=GetNextReg(reg2);
  1182. emit_mov(list,reg2,reg1);
  1183. for i:=3 to tcgsize2size[tosize] do
  1184. begin
  1185. reg2:=GetNextReg(reg2);
  1186. emit_mov(list,reg2,NR_R1);
  1187. end;
  1188. end;
  1189. OS_S16:
  1190. begin
  1191. emit_mov(list,reg2,reg1);
  1192. reg1:=GetNextReg(reg1);
  1193. reg2:=GetNextReg(reg2);
  1194. emit_mov(list,reg2,reg1);
  1195. if tcgsize2size[tosize]>2 then
  1196. begin
  1197. reg2:=GetNextReg(reg2);
  1198. emit_mov(list,reg2,NR_R1);
  1199. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  1200. list.concat(taicpu.op_reg(A_COM,reg2));
  1201. tmpreg:=reg2;
  1202. for i:=4 to tcgsize2size[tosize] do
  1203. begin
  1204. reg2:=GetNextReg(reg2);
  1205. emit_mov(list,reg2,tmpreg);
  1206. end;
  1207. end;
  1208. end;
  1209. else
  1210. conv_done:=false;
  1211. end;
  1212. end;
  1213. if not conv_done and (reg1<>reg2) then
  1214. begin
  1215. for i:=1 to tcgsize2size[fromsize] do
  1216. begin
  1217. emit_mov(list,reg2,reg1);
  1218. reg1:=GetNextReg(reg1);
  1219. reg2:=GetNextReg(reg2);
  1220. end;
  1221. end;
  1222. end;
  1223. procedure tcgavr.a_loadfpu_reg_reg(list: TAsmList; fromsize,tosize: tcgsize; reg1, reg2: tregister);
  1224. begin
  1225. internalerror(2012010702);
  1226. end;
  1227. procedure tcgavr.a_loadfpu_ref_reg(list: TAsmList; fromsize,tosize: tcgsize; const ref: treference; reg: tregister);
  1228. begin
  1229. internalerror(2012010703);
  1230. end;
  1231. procedure tcgavr.a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference);
  1232. begin
  1233. internalerror(2012010704);
  1234. end;
  1235. { comparison operations }
  1236. procedure tcgavr.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;
  1237. cmp_op : topcmp;a : tcgint;reg : tregister;l : tasmlabel);
  1238. var
  1239. swapped : boolean;
  1240. tmpreg : tregister;
  1241. i : byte;
  1242. begin
  1243. if a=0 then
  1244. begin
  1245. swapped:=false;
  1246. { swap parameters? }
  1247. case cmp_op of
  1248. OC_GT:
  1249. begin
  1250. swapped:=true;
  1251. cmp_op:=OC_LT;
  1252. end;
  1253. OC_LTE:
  1254. begin
  1255. swapped:=true;
  1256. cmp_op:=OC_GTE;
  1257. end;
  1258. OC_BE:
  1259. begin
  1260. swapped:=true;
  1261. cmp_op:=OC_AE;
  1262. end;
  1263. OC_A:
  1264. begin
  1265. swapped:=true;
  1266. cmp_op:=OC_B;
  1267. end;
  1268. end;
  1269. if swapped then
  1270. list.concat(taicpu.op_reg_reg(A_CP,reg,NR_R1))
  1271. else
  1272. list.concat(taicpu.op_reg_reg(A_CP,NR_R1,reg));
  1273. for i:=2 to tcgsize2size[size] do
  1274. begin
  1275. reg:=GetNextReg(reg);
  1276. if swapped then
  1277. list.concat(taicpu.op_reg_reg(A_CPC,reg,NR_R1))
  1278. else
  1279. list.concat(taicpu.op_reg_reg(A_CPC,NR_R1,reg));
  1280. end;
  1281. a_jmp_cond(list,cmp_op,l);
  1282. end
  1283. else
  1284. inherited a_cmp_const_reg_label(list,size,cmp_op,a,reg,l);
  1285. end;
  1286. procedure tcgavr.a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;
  1287. cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
  1288. var
  1289. swapped : boolean;
  1290. tmpreg : tregister;
  1291. i : byte;
  1292. begin
  1293. swapped:=false;
  1294. { swap parameters? }
  1295. case cmp_op of
  1296. OC_GT:
  1297. begin
  1298. swapped:=true;
  1299. cmp_op:=OC_LT;
  1300. end;
  1301. OC_LTE:
  1302. begin
  1303. swapped:=true;
  1304. cmp_op:=OC_GTE;
  1305. end;
  1306. OC_BE:
  1307. begin
  1308. swapped:=true;
  1309. cmp_op:=OC_AE;
  1310. end;
  1311. OC_A:
  1312. begin
  1313. swapped:=true;
  1314. cmp_op:=OC_B;
  1315. end;
  1316. end;
  1317. if swapped then
  1318. begin
  1319. tmpreg:=reg1;
  1320. reg1:=reg2;
  1321. reg2:=tmpreg;
  1322. end;
  1323. list.concat(taicpu.op_reg_reg(A_CP,reg2,reg1));
  1324. for i:=2 to tcgsize2size[size] do
  1325. begin
  1326. reg1:=GetNextReg(reg1);
  1327. reg2:=GetNextReg(reg2);
  1328. list.concat(taicpu.op_reg_reg(A_CPC,reg2,reg1));
  1329. end;
  1330. a_jmp_cond(list,cmp_op,l);
  1331. end;
  1332. procedure tcgavr.a_jmp_name(list : TAsmList;const s : string);
  1333. var
  1334. ai : taicpu;
  1335. begin
  1336. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  1337. ai:=taicpu.op_sym(A_JMP,current_asmdata.RefAsmSymbol(s))
  1338. else
  1339. ai:=taicpu.op_sym(A_RJMP,current_asmdata.RefAsmSymbol(s));
  1340. ai.is_jmp:=true;
  1341. list.concat(ai);
  1342. end;
  1343. procedure tcgavr.a_jmp_always(list : TAsmList;l: tasmlabel);
  1344. var
  1345. ai : taicpu;
  1346. begin
  1347. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  1348. ai:=taicpu.op_sym(A_JMP,l)
  1349. else
  1350. ai:=taicpu.op_sym(A_RJMP,l);
  1351. ai.is_jmp:=true;
  1352. list.concat(ai);
  1353. end;
  1354. procedure tcgavr.a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel);
  1355. var
  1356. ai : taicpu;
  1357. begin
  1358. ai:=setcondition(taicpu.op_sym(A_BRxx,l),flags_to_cond(f));
  1359. ai.is_jmp:=true;
  1360. list.concat(ai);
  1361. end;
  1362. procedure tcgavr.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
  1363. var
  1364. l : TAsmLabel;
  1365. tmpflags : TResFlags;
  1366. begin
  1367. current_asmdata.getjumplabel(l);
  1368. {
  1369. if flags_to_cond(f) then
  1370. begin
  1371. tmpflags:=f;
  1372. inverse_flags(tmpflags);
  1373. emit_mov(reg,NR_R1);
  1374. a_jmp_flags(list,tmpflags,l);
  1375. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1376. end
  1377. else
  1378. }
  1379. begin
  1380. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1381. a_jmp_flags(list,f,l);
  1382. emit_mov(list,reg,NR_R1);
  1383. end;
  1384. cg.a_label(list,l);
  1385. end;
  1386. procedure tcgavr.a_adjust_sp(list : TAsmList; value : longint);
  1387. var
  1388. i : integer;
  1389. begin
  1390. case value of
  1391. 0:
  1392. ;
  1393. {-14..-1:
  1394. begin
  1395. if ((-value) mod 2)<>0 then
  1396. list.concat(taicpu.op_reg(A_PUSH,NR_R0));
  1397. for i:=1 to (-value) div 2 do
  1398. list.concat(taicpu.op_const(A_RCALL,0));
  1399. end;
  1400. 1..7:
  1401. begin
  1402. for i:=1 to value do
  1403. list.concat(taicpu.op_reg(A_POP,NR_R0));
  1404. end;}
  1405. else
  1406. begin
  1407. list.concat(taicpu.op_reg_const(A_SUBI,NR_R28,lo(word(-value))));
  1408. list.concat(taicpu.op_reg_const(A_SBCI,NR_R29,hi(word(-value))));
  1409. // get SREG
  1410. list.concat(taicpu.op_reg_const(A_IN,NR_R0,NIO_SREG));
  1411. // block interrupts
  1412. list.concat(taicpu.op_none(A_CLI));
  1413. // write high SP
  1414. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_HI,NR_R29));
  1415. // release interrupts
  1416. list.concat(taicpu.op_const_reg(A_OUT,NIO_SREG,NR_R0));
  1417. // write low SP
  1418. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_LO,NR_R28));
  1419. end;
  1420. end;
  1421. end;
  1422. function tcgavr.GetLoad(const ref: treference) : tasmop;
  1423. begin
  1424. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1425. result:=A_LDS
  1426. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1427. result:=A_LDD
  1428. else
  1429. result:=A_LD;
  1430. end;
  1431. function tcgavr.GetStore(const ref: treference) : tasmop;
  1432. begin
  1433. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1434. result:=A_STS
  1435. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1436. result:=A_STD
  1437. else
  1438. result:=A_ST;
  1439. end;
  1440. procedure tcgavr.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
  1441. var
  1442. regs : tcpuregisterset;
  1443. reg : tsuperregister;
  1444. begin
  1445. if not(nostackframe) then
  1446. begin
  1447. { save int registers,
  1448. but only if the procedure returns }
  1449. if not(po_noreturn in current_procinfo.procdef.procoptions) then
  1450. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall)
  1451. else
  1452. regs:=[];
  1453. { if the framepointer is potentially used, save it always because we need a proper stack frame,
  1454. even if the procedure never returns, the procedure could be e.g. a nested one accessing
  1455. an outer stackframe }
  1456. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1457. regs:=regs+[RS_R28,RS_R29];
  1458. for reg:=RS_R31 downto RS_R0 do
  1459. if reg in regs then
  1460. list.concat(taicpu.op_reg(A_PUSH,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1461. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1462. begin
  1463. list.concat(taicpu.op_reg_const(A_IN,NR_R28,NIO_SP_LO));
  1464. list.concat(taicpu.op_reg_const(A_IN,NR_R29,NIO_SP_HI));
  1465. end
  1466. else
  1467. { the framepointer cannot be omitted on avr because sp
  1468. is not a register but part of the i/o map
  1469. }
  1470. internalerror(2011021901);
  1471. a_adjust_sp(list,-localsize);
  1472. end;
  1473. end;
  1474. procedure tcgavr.g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean);
  1475. var
  1476. regs : tcpuregisterset;
  1477. reg : TSuperRegister;
  1478. LocalSize : longint;
  1479. begin
  1480. { every byte counts for avr, so if a subroutine is marked as non-returning, we do
  1481. not generate any exit code, so we really trust the noreturn directive
  1482. }
  1483. if po_noreturn in current_procinfo.procdef.procoptions then
  1484. exit;
  1485. if not(nostackframe) then
  1486. begin
  1487. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1488. begin
  1489. LocalSize:=current_procinfo.calc_stackframe_size;
  1490. a_adjust_sp(list,LocalSize);
  1491. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1492. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1493. regs:=regs+[RS_R28,RS_R29];
  1494. for reg:=RS_R0 to RS_R31 do
  1495. if reg in regs then
  1496. list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1497. end
  1498. else
  1499. { the framepointer cannot be omitted on avr because sp
  1500. is not a register but part of the i/o map
  1501. }
  1502. internalerror(2011021902);
  1503. end;
  1504. list.concat(taicpu.op_none(A_RET));
  1505. end;
  1506. procedure tcgavr.a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);
  1507. var
  1508. tmpref : treference;
  1509. begin
  1510. if ref.addressmode<>AM_UNCHANGED then
  1511. internalerror(2011021701);
  1512. if assigned(ref.symbol) or (ref.offset<>0) then
  1513. begin
  1514. reference_reset(tmpref,0);
  1515. tmpref.symbol:=ref.symbol;
  1516. tmpref.offset:=ref.offset;
  1517. if assigned(ref.symbol) and (ref.symbol.typ in [AT_FUNCTION,AT_LABEL]) then
  1518. tmpref.refaddr:=addr_lo8_gs
  1519. else
  1520. tmpref.refaddr:=addr_lo8;
  1521. list.concat(taicpu.op_reg_ref(A_LDI,r,tmpref));
  1522. if assigned(ref.symbol) and (ref.symbol.typ in [AT_FUNCTION,AT_LABEL]) then
  1523. tmpref.refaddr:=addr_hi8_gs
  1524. else
  1525. tmpref.refaddr:=addr_hi8;
  1526. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(r),tmpref));
  1527. if (ref.base<>NR_NO) then
  1528. begin
  1529. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.base));
  1530. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.base)));
  1531. end;
  1532. if (ref.index<>NR_NO) then
  1533. begin
  1534. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1535. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1536. end;
  1537. end
  1538. else if (ref.base<>NR_NO)then
  1539. begin
  1540. emit_mov(list,r,ref.base);
  1541. emit_mov(list,GetNextReg(r),GetNextReg(ref.base));
  1542. if (ref.index<>NR_NO) then
  1543. begin
  1544. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1545. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1546. end;
  1547. end
  1548. else if (ref.index<>NR_NO) then
  1549. begin
  1550. emit_mov(list,r,ref.index);
  1551. emit_mov(list,GetNextReg(r),GetNextReg(ref.index));
  1552. end;
  1553. end;
  1554. procedure tcgavr.fixref(list : TAsmList;var ref : treference);
  1555. begin
  1556. internalerror(2011021320);
  1557. end;
  1558. procedure tcgavr.g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  1559. var
  1560. paraloc1,paraloc2,paraloc3 : TCGPara;
  1561. pd : tprocdef;
  1562. begin
  1563. pd:=search_system_proc('MOVE');
  1564. paraloc1.init;
  1565. paraloc2.init;
  1566. paraloc3.init;
  1567. paramanager.getintparaloc(list,pd,1,paraloc1);
  1568. paramanager.getintparaloc(list,pd,2,paraloc2);
  1569. paramanager.getintparaloc(list,pd,3,paraloc3);
  1570. a_load_const_cgpara(list,OS_SINT,len,paraloc3);
  1571. a_loadaddr_ref_cgpara(list,dest,paraloc2);
  1572. a_loadaddr_ref_cgpara(list,source,paraloc1);
  1573. paramanager.freecgpara(list,paraloc3);
  1574. paramanager.freecgpara(list,paraloc2);
  1575. paramanager.freecgpara(list,paraloc1);
  1576. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1577. a_call_name_static(list,'FPC_MOVE');
  1578. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1579. paraloc3.done;
  1580. paraloc2.done;
  1581. paraloc1.done;
  1582. end;
  1583. procedure tcgavr.g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);
  1584. var
  1585. countreg,tmpreg : tregister;
  1586. srcref,dstref : treference;
  1587. copysize,countregsize : tcgsize;
  1588. l : TAsmLabel;
  1589. i : longint;
  1590. SrcQuickRef, DestQuickRef : Boolean;
  1591. begin
  1592. if len>16 then
  1593. begin
  1594. current_asmdata.getjumplabel(l);
  1595. reference_reset(srcref,0);
  1596. reference_reset(dstref,0);
  1597. srcref.base:=NR_R30;
  1598. srcref.addressmode:=AM_POSTINCREMENT;
  1599. dstref.base:=NR_R26;
  1600. dstref.addressmode:=AM_POSTINCREMENT;
  1601. copysize:=OS_8;
  1602. if len<256 then
  1603. countregsize:=OS_8
  1604. else if len<65536 then
  1605. countregsize:=OS_16
  1606. else
  1607. internalerror(2011022007);
  1608. countreg:=getintregister(list,countregsize);
  1609. a_load_const_reg(list,countregsize,len,countreg);
  1610. a_loadaddr_ref_reg(list,source,NR_R30);
  1611. tmpreg:=getaddressregister(list);
  1612. a_loadaddr_ref_reg(list,dest,tmpreg);
  1613. { X is used for spilling code so we can load it
  1614. only by a push/pop sequence, this can be
  1615. optimized later on by the peephole optimizer
  1616. }
  1617. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1618. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1619. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1620. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1621. cg.a_label(list,l);
  1622. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1623. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1624. list.concat(taicpu.op_reg(A_DEC,countreg));
  1625. a_jmp_flags(list,F_NE,l);
  1626. // keep registers alive
  1627. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  1628. end
  1629. else
  1630. begin
  1631. SrcQuickRef:=false;
  1632. DestQuickRef:=false;
  1633. if not((source.addressmode=AM_UNCHANGED) and
  1634. (source.symbol=nil) and
  1635. ((source.base=NR_R28) or
  1636. (source.base=NR_R29)) and
  1637. (source.Index=NR_NO) and
  1638. (source.Offset in [0..64-len])) and
  1639. not((source.Base=NR_NO) and (source.Index=NR_NO)) then
  1640. srcref:=normalize_ref(list,source,NR_R30)
  1641. else
  1642. begin
  1643. SrcQuickRef:=true;
  1644. srcref:=source;
  1645. end;
  1646. if not((dest.addressmode=AM_UNCHANGED) and
  1647. (dest.symbol=nil) and
  1648. ((dest.base=NR_R28) or
  1649. (dest.base=NR_R29)) and
  1650. (dest.Index=NR_No) and
  1651. (dest.Offset in [0..64-len])) and
  1652. not((dest.Base=NR_NO) and (dest.Index=NR_NO)) then
  1653. begin
  1654. if not(SrcQuickRef) then
  1655. begin
  1656. tmpreg:=getaddressregister(list);
  1657. dstref:=normalize_ref(list,dest,tmpreg);
  1658. { X is used for spilling code so we can load it
  1659. only by a push/pop sequence, this can be
  1660. optimized later on by the peephole optimizer
  1661. }
  1662. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1663. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1664. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1665. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1666. dstref.base:=NR_R26;
  1667. end
  1668. else
  1669. dstref:=normalize_ref(list,dest,NR_R30);
  1670. end
  1671. else
  1672. begin
  1673. DestQuickRef:=true;
  1674. dstref:=dest;
  1675. end;
  1676. for i:=1 to len do
  1677. begin
  1678. if not(SrcQuickRef) and (i<len) then
  1679. srcref.addressmode:=AM_POSTINCREMENT
  1680. else
  1681. srcref.addressmode:=AM_UNCHANGED;
  1682. if not(DestQuickRef) and (i<len) then
  1683. dstref.addressmode:=AM_POSTINCREMENT
  1684. else
  1685. dstref.addressmode:=AM_UNCHANGED;
  1686. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1687. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1688. if SrcQuickRef then
  1689. inc(srcref.offset);
  1690. if DestQuickRef then
  1691. inc(dstref.offset);
  1692. end;
  1693. if not(SrcQuickRef) then
  1694. begin
  1695. ungetcpuregister(list,srcref.base);
  1696. ungetcpuregister(list,GetNextReg(srcref.base));
  1697. end;
  1698. end;
  1699. end;
  1700. procedure tcgavr.g_overflowCheck(list : TAsmList;const l : tlocation;def : tdef);
  1701. var
  1702. hl : tasmlabel;
  1703. ai : taicpu;
  1704. cond : TAsmCond;
  1705. begin
  1706. if not(cs_check_overflow in current_settings.localswitches) then
  1707. exit;
  1708. current_asmdata.getjumplabel(hl);
  1709. if not ((def.typ=pointerdef) or
  1710. ((def.typ=orddef) and
  1711. (torddef(def).ordtype in [u64bit,u16bit,u32bit,u8bit,uchar,
  1712. pasbool8,pasbool16,pasbool32,pasbool64]))) then
  1713. cond:=C_VC
  1714. else
  1715. cond:=C_CC;
  1716. ai:=Taicpu.Op_Sym(A_BRxx,hl);
  1717. ai.SetCondition(cond);
  1718. ai.is_jmp:=true;
  1719. list.concat(ai);
  1720. a_call_name(list,'FPC_OVERFLOW',false);
  1721. a_label(list,hl);
  1722. end;
  1723. procedure tcgavr.g_save_registers(list: TAsmList);
  1724. begin
  1725. { this is done by the entry code }
  1726. end;
  1727. procedure tcgavr.g_restore_registers(list: TAsmList);
  1728. begin
  1729. { this is done by the exit code }
  1730. end;
  1731. procedure tcgavr.a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  1732. var
  1733. ai1,ai2 : taicpu;
  1734. hl : TAsmLabel;
  1735. begin
  1736. ai1:=Taicpu.Op_sym(A_BRxx,l);
  1737. ai1.is_jmp:=true;
  1738. hl:=nil;
  1739. case cond of
  1740. OC_EQ:
  1741. ai1.SetCondition(C_EQ);
  1742. OC_GT:
  1743. begin
  1744. { emulate GT }
  1745. current_asmdata.getjumplabel(hl);
  1746. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1747. ai2.SetCondition(C_EQ);
  1748. ai2.is_jmp:=true;
  1749. list.concat(ai2);
  1750. ai1.SetCondition(C_GE);
  1751. end;
  1752. OC_LT:
  1753. ai1.SetCondition(C_LT);
  1754. OC_GTE:
  1755. ai1.SetCondition(C_GE);
  1756. OC_LTE:
  1757. begin
  1758. { emulate LTE }
  1759. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1760. ai2.SetCondition(C_EQ);
  1761. ai2.is_jmp:=true;
  1762. list.concat(ai2);
  1763. ai1.SetCondition(C_LT);
  1764. end;
  1765. OC_NE:
  1766. ai1.SetCondition(C_NE);
  1767. OC_BE:
  1768. begin
  1769. { emulate BE }
  1770. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1771. ai2.SetCondition(C_EQ);
  1772. ai2.is_jmp:=true;
  1773. list.concat(ai2);
  1774. ai1.SetCondition(C_LO);
  1775. end;
  1776. OC_B:
  1777. ai1.SetCondition(C_LO);
  1778. OC_AE:
  1779. ai1.SetCondition(C_SH);
  1780. OC_A:
  1781. begin
  1782. { emulate A (unsigned GT) }
  1783. current_asmdata.getjumplabel(hl);
  1784. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1785. ai2.SetCondition(C_EQ);
  1786. ai2.is_jmp:=true;
  1787. list.concat(ai2);
  1788. ai1.SetCondition(C_SH);
  1789. end;
  1790. else
  1791. internalerror(2011082501);
  1792. end;
  1793. list.concat(ai1);
  1794. if assigned(hl) then
  1795. a_label(list,hl);
  1796. end;
  1797. procedure tcgavr.emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  1798. var
  1799. instr: taicpu;
  1800. begin
  1801. instr:=taicpu.op_reg_reg(A_MOV,reg2,reg1);
  1802. list.Concat(instr);
  1803. { Notify the register allocator that we have written a move instruction so
  1804. it can try to eliminate it. }
  1805. add_move_instruction(instr);
  1806. end;
  1807. procedure tcg64favr.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
  1808. begin
  1809. if not(size in [OS_S64,OS_64]) then
  1810. internalerror(2012102402);
  1811. tcgavr(cg).a_op_reg_reg_internal(list,Op,size,regsrc.reglo,regsrc.reghi,regdst.reglo,regdst.reghi);
  1812. end;
  1813. procedure tcg64favr.a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);
  1814. begin
  1815. tcgavr(cg).a_op_const_reg_internal(list,Op,size,value,reg.reglo,reg.reghi);
  1816. end;
  1817. procedure create_codegen;
  1818. begin
  1819. cg:=tcgavr.create;
  1820. cg64:=tcg64favr.create;
  1821. end;
  1822. end.