cpubase.pas 35 KB

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  1. {
  2. $Id$
  3. Copyright (c) 1998-2002 by Florian Klaempfl
  4. Contains the base types for the PowerPC
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. { This Unit contains the base types for the PowerPC
  19. }
  20. unit cpubase;
  21. {$i fpcdefs.inc}
  22. interface
  23. uses
  24. strings,cutils,cclasses,aasmbase,cpuinfo,cgbase;
  25. {*****************************************************************************
  26. Assembler Opcodes
  27. *****************************************************************************}
  28. type
  29. TAsmOp=(A_None,
  30. { normal opcodes }
  31. a_add, a_add_, a_addo, a_addo_, a_addc, a_addc_, a_addco, a_addco_,
  32. a_adde, a_adde_, a_addeo, a_addeo_, a_addi, a_addic, a_addic_, a_addis,
  33. a_addme, a_addme_, a_addmeo, a_addmeo_, a_addze, a_addze_, a_addzeo,
  34. a_addzeo_, a_and, a_and_, a_andc, a_andc_, a_andi_, a_andis_, a_b,
  35. a_ba, a_bl, a_bla, a_bc, a_bca, a_bcl, a_bcla, a_bcctr, a_bcctrl, a_bclr,
  36. a_bclrl, a_cmp, a_cmpi, a_cmpl, a_cmpli, a_cntlzw, a_cntlzw_, a_crand,
  37. a_crandc, a_creqv, a_crnand, a_crnor, a_cror, a_crorc, a_crxor, a_dcba,
  38. a_dcbf, a_dcbi, a_dcbst, a_dcbt, a_dcbtst, a_dcbz, a_divw, a_divw_, a_divwo, a_divwo_,
  39. a_divwu, a_divwu_, a_divwuo, a_divwuo_, a_eciwx, a_ecowx, a_eieio, a_eqv,
  40. a_eqv_, a_extsb, a_extsb_, a_extsh, a_extsh_, a_fabs, a_fabs_, a_fadd,
  41. a_fadd_, a_fadds, a_fadds_, a_fcmpo, a_fcmpu, a_fctiw, a_fctw_, a_fctwz,
  42. a_fctwz_, a_fdiv, a_fdiv_, a_fdivs, a_fdivs_, a_fmadd, a_fmadd_, a_fmadds,
  43. a_fmadds_, a_fmr, a_fmsub, a_fmsub_, a_fmsubs, a_fmsubs_, a_fmul, a_fmul_,
  44. a_fmuls, a_fmuls_, a_fnabs, a_fnabs_, a_fneg, a_fneg_, a_fnmadd,
  45. a_fnmadd_, a_fnmadds, a_fnmadds_, a_fnmsub, a_fnmsub_, a_fnmsubs,
  46. a_fnmsubs_, a_fres, a_fres_, a_frsp, a_frsp_, a_frsqrte, a_frsqrte_,
  47. a_fsel, a_fsel_, a_fsqrt, a_fsqrt_, a_fsqrts, a_fsqrts_, a_fsub, a_fsub_,
  48. a_fsubs, a_fsubs_, a_icbi, a_isync, a_lbz, a_lbzu, a_lbzux, a_lbzx,
  49. a_lfd, a_lfdu, a_lfdux, a_lfdx, a_lfs, a_lfsu, a_lfsux, a_lfsx, a_lha,
  50. a_lhau, a_lhaux, a_lhax, a_hbrx, a_lhz, a_lhzu, a_lhzux, a_lhzx, a_lmw,
  51. a_lswi, a_lswx, a_lwarx, a_lwbrx, a_lwz, a_lwzu, a_lwzux, a_lwzx, a_mcrf,
  52. a_mcrfs, a_mcrxr, a_lcrxe, a_mfcr, a_mffs, a_maffs_, a_mfmsr, a_mfspr, a_mfsr,
  53. a_mfsrin, a_mftb, a_mtcrf, a_a_mtfd0, a_mtfsb1, a_mtfsf, a_mtfsf_,
  54. a_mtfsfi, a_mtfsfi_, a_mtmsr, a_mtspr, a_mtsr, a_mtsrin, a_mulhw,
  55. a_mulhw_, a_mulhwu, a_mulhwu_, a_mulli, a_mullw, a_mullw_, a_mullwo,
  56. a_mullwo_, a_nand, a_nand_, a_neg, a_neg_, a_nego, a_nego_, a_nor, a_nor_,
  57. a_or, a_or_, a_orc, a_orc_, a_ori, a_oris, a_rfi, a_rlwimi, a_rlwimi_,
  58. a_rlwinm, a_rlwinm_, a_rlwnm, a_sc, a_slw, a_slw_, a_sraw, a_sraw_,
  59. a_srawi, a_srawi_,a_srw, a_srw_, a_stb, a_stbu, a_stbux, a_stbx, a_stfd,
  60. a_stfdu, a_stfdux, a_stfdx, a_stfiwx, a_stfs, a_stfsu, a_stfsux, a_stfsx,
  61. a_sth, a_sthbrx, a_sthu, a_sthux, a_sthx, a_stmw, a_stswi, a_stswx, a_stw,
  62. a_stwbrx, a_stwcx_, a_stwu, a_stwux, a_stwx, a_subf, a_subf_, a_subfo,
  63. a_subfo_, a_subfc, a_subfc_, a_subfco, a_subfco_, a_subfe, a_subfe_,
  64. a_subfeo, a_subfeo_, a_subfic, a_subfme, a_subfme_, a_subfmeo, a_subfmeo_,
  65. a_subfze, a_subfze_, a_subfzeo, a_subfzeo_, a_sync, a_tlbia, a_tlbie,
  66. a_tlbsync, a_tw, a_twi, a_xor, a_xor_, a_xori, a_xoris,
  67. { simplified mnemonics }
  68. a_subi, a_subis, a_subic, a_subic_, a_sub, a_sub_, a_subo, a_subo_,
  69. a_subc, a_subc_, a_subco, a_subco_, a_cmpwi, a_cmpw, a_cmplwi, a_cmplw,
  70. a_extlwi, a_extlwi_, a_extrwi, a_extrwi_, a_inslwi, a_inslwi_, a_insrwi,
  71. a_insrwi_, a_rotlwi, a_rotlwi_, a_rotlw, a_rotlw_, a_slwi, a_slwi_,
  72. a_srwi, a_srwi_, a_clrlwi, a_clrlwi_, a_clrrwi, a_clrrwi_, a_clrslwi,
  73. a_clrslwi_, a_blr, a_bctr, a_blrl, a_bctrl, a_crset, a_crclr, a_crmove,
  74. a_crnot, a_mt {move to special prupose reg}, a_mf {move from special purpose reg},
  75. a_nop, a_li, a_lis, a_la, a_mr, a_mr_, a_not, a_mtcr, a_mtlr, a_mflr,
  76. a_mtctr, a_mfctr);
  77. {# This should define the array of instructions as string }
  78. op2strtable=array[tasmop] of string[8];
  79. Const
  80. {# First value of opcode enumeration }
  81. firstop = low(tasmop);
  82. {# Last value of opcode enumeration }
  83. lastop = high(tasmop);
  84. {*****************************************************************************
  85. Registers
  86. *****************************************************************************}
  87. type
  88. { Number of registers used for indexing in tables }
  89. tregisterindex=0..{$i rppcnor.inc}-1;
  90. totherregisterset = set of tregisterindex;
  91. const
  92. { Available Superregisters }
  93. {$i rppcsup.inc}
  94. { No Subregisters }
  95. R_SUBWHOLE=R_SUBNONE;
  96. { Available Registers }
  97. {$i rppccon.inc}
  98. { Integer Super registers first and last }
  99. first_int_imreg = $20;
  100. { Float Super register first and last }
  101. first_fpu_imreg = $20;
  102. { MM Super register first and last }
  103. first_mm_imreg = $20;
  104. {$warning TODO Calculate bsstart}
  105. regnumber_count_bsstart = 64;
  106. regnumber_table : array[tregisterindex] of tregister = (
  107. {$i rppcnum.inc}
  108. );
  109. regstabs_table : array[tregisterindex] of shortint = (
  110. {$i rppcstab.inc}
  111. );
  112. { registers which may be destroyed by calls }
  113. VOLATILE_INTREGISTERS = [RS_R3..RS_R12];
  114. {$warning FIXME!!}
  115. { FIXME: only R_F1..R_F8 under the SYSV ABI -> has to become a }
  116. { typed const (JM) }
  117. VOLATILE_FPUREGISTERS = [RS_F3..RS_F13];
  118. {*****************************************************************************
  119. Conditions
  120. *****************************************************************************}
  121. type
  122. TAsmCondFlag = (C_None { unconditional jumps },
  123. { conditions when not using ctr decrement etc }
  124. C_LT,C_LE,C_EQ,C_GE,C_GT,C_NL,C_NE,C_NG,C_SO,C_NS,C_UN,C_NU,
  125. { conditions when using ctr decrement etc }
  126. C_T,C_F,C_DNZ,C_DNZT,C_DNZF,C_DZ,C_DZT,C_DZF);
  127. TDirHint = (DH_None,DH_Minus,DH_Plus);
  128. const
  129. { these are in the XER, but when moved to CR_x they correspond with the }
  130. { bits below }
  131. C_OV = C_GT;
  132. C_CA = C_EQ;
  133. C_NO = C_NG;
  134. C_NC = C_NE;
  135. type
  136. TAsmCond = packed record
  137. dirhint : tdirhint;
  138. case simple: boolean of
  139. false: (BO, BI: byte);
  140. true: (
  141. cond: TAsmCondFlag;
  142. case byte of
  143. 0: ();
  144. { specifies in which part of the cr the bit has to be }
  145. { tested for blt,bgt,beq,..,bnu }
  146. 1: (cr: RS_CR0..RS_CR7);
  147. { specifies the bit to test for bt,bf,bdz,..,bdzf }
  148. 2: (crbit: byte)
  149. );
  150. end;
  151. const
  152. AsmCondFlag2BO: Array[C_T..C_DZF] of Byte =
  153. (12,4,16,8,0,18,10,2);
  154. AsmCondFlag2BOLT_NU: Array[C_LT..C_NU] of Byte =
  155. (12,4,12,4,12,4,4,4,12,4,12,4);
  156. AsmCondFlag2BI: Array[C_LT..C_NU] of Byte =
  157. (0,1,2,0,1,0,2,1,3,3,3,3);
  158. AsmCondFlagTF: Array[TAsmCondFlag] of Boolean =
  159. (false,true,false,true,false,true,false,false,false,true,false,true,false,
  160. true,false,false,true,false,false,true,false);
  161. AsmCondFlag2Str: Array[TAsmCondFlag] of string[4] = ({cf_none}'',
  162. { conditions when not using ctr decrement etc}
  163. 'lt','le','eq','ge','gt','nl','ne','ng','so','ns','un','nu',
  164. 't','f','dnz','dnzt','dnzf','dz','dzt','dzf');
  165. UpperAsmCondFlag2Str: Array[TAsmCondFlag] of string[4] = ({cf_none}'',
  166. { conditions when not using ctr decrement etc}
  167. 'LT','LE','EQ','GE','GT','NL','NE','NG','SO','NS','UN','NU',
  168. 'T','F','DNZ','DNZT','DNZF','DZ','DZT','DZF');
  169. const
  170. CondAsmOps=3;
  171. CondAsmOp:array[0..CondAsmOps-1] of TasmOp=(
  172. A_BC, A_TW, A_TWI
  173. );
  174. {*****************************************************************************
  175. Flags
  176. *****************************************************************************}
  177. type
  178. TResFlagsEnum = (F_EQ,F_NE,F_LT,F_LE,F_GT,F_GE,F_SO,F_FX,F_FEX,F_VX,F_OX);
  179. TResFlags = record
  180. cr: RS_CR0..RS_CR7;
  181. flag: TResFlagsEnum;
  182. end;
  183. (*
  184. const
  185. { arrays for boolean location conversions }
  186. flag_2_cond : array[TResFlags] of TAsmCond =
  187. (C_E,C_NE,C_LT,C_LE,C_GT,C_GE,???????????????);
  188. *)
  189. {*****************************************************************************
  190. Reference
  191. *****************************************************************************}
  192. type
  193. trefoptions=(ref_none,ref_parafixup,ref_localfixup,ref_selffixup);
  194. { since we have only 16 offsets, we need to be able to specify the high }
  195. { and low 16 bits of the address of a symbol }
  196. trefsymaddr = (refs_full,refs_ha,refs_l);
  197. { reference record }
  198. preference = ^treference;
  199. treference = packed record
  200. { base register, R_NO if none }
  201. base,
  202. { index register, R_NO if none }
  203. index : tregister;
  204. { offset, 0 if none }
  205. offset : longint;
  206. { symbol this reference refers to, nil if none }
  207. symbol : tasmsymbol;
  208. { used in conjunction with symbols and offsets: refs_full means }
  209. { means a full 32bit reference, refs_ha means the upper 16 bits }
  210. { and refs_l the lower 16 bits of the address }
  211. symaddr : trefsymaddr;
  212. { changed when inlining and possibly in other cases, don't }
  213. { set manually }
  214. offsetfixup : longint;
  215. { used in conjunction with the previous field }
  216. options : trefoptions;
  217. { alignment this reference is guaranteed to have }
  218. alignment : byte;
  219. end;
  220. { reference record }
  221. pparareference = ^tparareference;
  222. tparareference = packed record
  223. index : tregister;
  224. offset : aword;
  225. end;
  226. const
  227. symaddr2str: array[trefsymaddr] of string[3] = ('','@ha','@l');
  228. const
  229. { MacOS only. Whether the direct data area (TOC) directly contain
  230. global variables. Otherwise it contains pointers to global variables. }
  231. macos_direct_globals = false;
  232. {*****************************************************************************
  233. Operand Sizes
  234. *****************************************************************************}
  235. {*****************************************************************************
  236. Generic Location
  237. *****************************************************************************}
  238. type
  239. { tparamlocation describes where a parameter for a procedure is stored.
  240. References are given from the caller's point of view. The usual
  241. TLocation isn't used, because contains a lot of unnessary fields.
  242. }
  243. tparalocation = packed record
  244. size : TCGSize;
  245. { The location type where the parameter is passed, usually
  246. LOC_REFERENCE,LOC_REGISTER or LOC_FPUREGISTER
  247. }
  248. loc : TCGLoc;
  249. {Word alignment on stack 4 --> 32 bit}
  250. Alignment:Byte;
  251. case TCGLoc of
  252. LOC_REFERENCE : (reference : tparareference);
  253. LOC_FPUREGISTER, LOC_CFPUREGISTER, LOC_MMREGISTER, LOC_CMMREGISTER,
  254. LOC_REGISTER,LOC_CREGISTER : (
  255. case longint of
  256. 1 : (register,registerhigh : tregister);
  257. { overlay a registerlow }
  258. 2 : (registerlow : tregister);
  259. { overlay a 64 Bit register type }
  260. 3 : (reg64 : tregister64);
  261. 4 : (register64 : tregister64);
  262. );
  263. end;
  264. treglocation = packed record
  265. case longint of
  266. 1 : (register,registerhigh : tregister);
  267. { overlay a registerlow }
  268. 2 : (registerlow : tregister);
  269. { overlay a 64 Bit register type }
  270. 3 : (reg64 : tregister64);
  271. 4 : (register64 : tregister64);
  272. end;
  273. tlocation = packed record
  274. size : TCGSize;
  275. loc : tcgloc;
  276. case tcgloc of
  277. LOC_CREFERENCE,LOC_REFERENCE : (reference : treference);
  278. LOC_CONSTANT : (
  279. case longint of
  280. {$ifdef FPC_BIG_ENDIAN}
  281. 1 : (_valuedummy,value : AWord);
  282. {$else FPC_BIG_ENDIAN}
  283. 1 : (value : AWord);
  284. {$endif FPC_BIG_ENDIAN}
  285. { can't do this, this layout depends on the host cpu. Use }
  286. { lo(valueqword)/hi(valueqword) instead (JM) }
  287. { 2 : (valuelow, valuehigh:AWord); }
  288. { overlay a complete 64 Bit value }
  289. 3 : (valueqword : qword);
  290. );
  291. LOC_FPUREGISTER, LOC_CFPUREGISTER, LOC_MMREGISTER, LOC_CMMREGISTER,
  292. LOC_REGISTER,LOC_CREGISTER : (
  293. case longint of
  294. 1 : (registerlow,registerhigh : tregister);
  295. 2 : (register : tregister);
  296. { overlay a 64 Bit register type }
  297. 3 : (reg64 : tregister64);
  298. 4 : (register64 : tregister64);
  299. );
  300. LOC_FLAGS : (resflags : tresflags);
  301. end;
  302. {*****************************************************************************
  303. Constants
  304. *****************************************************************************}
  305. const
  306. max_operands = 5;
  307. (*
  308. {# Table of registers which can be allocated by the code generator
  309. internally, when generating the code.
  310. }
  311. { legend: }
  312. { xxxregs = set of all possibly used registers of that type in the code }
  313. { generator }
  314. { usableregsxxx = set of all 32bit components of registers that can be }
  315. { possible allocated to a regvar or using getregisterxxx (this }
  316. { excludes registers which can be only used for parameter }
  317. { passing on ABI's that define this) }
  318. { c_countusableregsxxx = amount of registers in the usableregsxxx set }
  319. maxintregs = 18;
  320. { to determine how many registers to use for regvars }
  321. maxintscratchregs = 3;
  322. usableregsint = [RS_R13..RS_R27];
  323. c_countusableregsint = 18;
  324. maxfpuregs = 31-14+1;
  325. usableregsfpu = [RS_F14..RS_F31];
  326. c_countusableregsfpu = 31-14+1;
  327. usableregsmm = [RS_M14..RS_M31];
  328. c_countusableregsmm = 31-14+1;
  329. { no distinction on this platform }
  330. maxaddrregs = 0;
  331. addrregs = [];
  332. usableregsaddr = [];
  333. c_countusableregsaddr = 0;
  334. firstsaveintreg = RS_R13;
  335. lastsaveintreg = RS_R31;
  336. firstsavefpureg = RS_F14;
  337. lastsavefpureg = RS_F31;
  338. { no altivec support yet. Need to override tcgobj.a_loadmm_* first in tcgppc }
  339. firstsavemmreg = RS_INVALID;
  340. lastsavemmreg = RS_INVALID;
  341. maxvarregs = 15;
  342. varregs : Array [1..maxvarregs] of Tsuperregister =
  343. (RS_R14,RS_R15,RS_R16,RS_R17,RS_R18,RS_R19,RS_R20,RS_R21,
  344. RS_R22,RS_R23,RS_R24,RS_R25,RS_R26,RS_R27,RS_R28);
  345. maxfpuvarregs = 31-14+1;
  346. fpuvarregs : Array [1..maxfpuvarregs] of Tsuperregister =
  347. (RS_F14,RS_F15,RS_F16,RS_F17,RS_F18,RS_F19,RS_F20,RS_F21,RS_F22,RS_F23,
  348. RS_F24,RS_F25,RS_F26,RS_F27,RS_F28,RS_F29,RS_F30,RS_F31);
  349. {
  350. // max_param_regs_int = 8;
  351. // param_regs_int: Array[1..max_param_regs_int] of Tsuperregister =
  352. // (R_3,R_4,R_5,R_6,R_7,R_8,R_9,R_10);
  353. // max_param_regs_fpu = 13;
  354. // param_regs_fpu: Array[1..max_param_regs_fpu] of Toldregister =
  355. // (RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7,RS_F8,RS_F9,RS_F10,RS_F11,RS_F12,RS_F13);
  356. max_param_regs_mm = 13;
  357. param_regs_mm: Array[1..max_param_regs_mm] of Toldregister =
  358. (R_M1,R_M2,R_M3,R_M4,R_M5,R_M6,R_M7,R_M8,R_M9,R_M10,R_M11,R_M12,R_M13);
  359. }
  360. *)
  361. {*****************************************************************************
  362. Default generic sizes
  363. *****************************************************************************}
  364. {# Defines the default address size for a processor, }
  365. OS_ADDR = OS_32;
  366. {# the natural int size for a processor, }
  367. OS_INT = OS_32;
  368. {# the maximum float size for a processor, }
  369. OS_FLOAT = OS_F64;
  370. {# the size of a vector register for a processor }
  371. OS_VECTOR = OS_M128;
  372. {*****************************************************************************
  373. GDB Information
  374. *****************************************************************************}
  375. {# Register indexes for stabs information, when some
  376. parameters or variables are stored in registers.
  377. Taken from rs6000.h (DBX_REGISTER_NUMBER)
  378. from GCC 3.x source code. PowerPC has 1:1 mapping
  379. according to the order of the registers defined
  380. in GCC
  381. }
  382. stab_regindex : array[tregisterindex] of shortint = (
  383. {$i rppcstab.inc}
  384. );
  385. {*****************************************************************************
  386. Generic Register names
  387. *****************************************************************************}
  388. {# Stack pointer register }
  389. NR_STACK_POINTER_REG = NR_R1;
  390. RS_STACK_POINTER_REG = RS_R1;
  391. {# Frame pointer register }
  392. NR_FRAME_POINTER_REG = NR_STACK_POINTER_REG;
  393. RS_FRAME_POINTER_REG = RS_STACK_POINTER_REG;
  394. {# Register for addressing absolute data in a position independant way,
  395. such as in PIC code. The exact meaning is ABI specific. For
  396. further information look at GCC source : PIC_OFFSET_TABLE_REGNUM
  397. Taken from GCC rs6000.h
  398. }
  399. {$warning As indicated in rs6000.h, but can't find it anywhere else!}
  400. NR_PIC_OFFSET_REG = NR_R30;
  401. { Results are returned in this register (32-bit values) }
  402. NR_FUNCTION_RETURN_REG = NR_R3;
  403. RS_FUNCTION_RETURN_REG = RS_R3;
  404. { Low part of 64bit return value }
  405. NR_FUNCTION_RETURN64_LOW_REG = NR_R4;
  406. RS_FUNCTION_RETURN64_LOW_REG = RS_R4;
  407. { High part of 64bit return value }
  408. NR_FUNCTION_RETURN64_HIGH_REG = NR_R3;
  409. RS_FUNCTION_RETURN64_HIGH_REG = RS_R3;
  410. { The value returned from a function is available in this register }
  411. NR_FUNCTION_RESULT_REG = NR_FUNCTION_RETURN_REG;
  412. RS_FUNCTION_RESULT_REG = RS_FUNCTION_RETURN_REG;
  413. { The lowh part of 64bit value returned from a function }
  414. NR_FUNCTION_RESULT64_LOW_REG = NR_FUNCTION_RETURN64_LOW_REG;
  415. RS_FUNCTION_RESULT64_LOW_REG = RS_FUNCTION_RETURN64_LOW_REG;
  416. { The high part of 64bit value returned from a function }
  417. NR_FUNCTION_RESULT64_HIGH_REG = NR_FUNCTION_RETURN64_HIGH_REG;
  418. RS_FUNCTION_RESULT64_HIGH_REG = RS_FUNCTION_RETURN64_HIGH_REG;
  419. NR_FPU_RESULT_REG = NR_F1;
  420. NR_MM_RESULT_REG = NR_M0;
  421. {*****************************************************************************
  422. GCC /ABI linking information
  423. *****************************************************************************}
  424. {# Registers which must be saved when calling a routine declared as
  425. cppdecl, cdecl, stdcall, safecall, palmossyscall. The registers
  426. saved should be the ones as defined in the target ABI and / or GCC.
  427. This value can be deduced from CALLED_USED_REGISTERS array in the
  428. GCC source.
  429. }
  430. std_saved_registers = [RS_R13..RS_R29];
  431. {# Required parameter alignment when calling a routine declared as
  432. stdcall and cdecl. The alignment value should be the one defined
  433. by GCC or the target ABI.
  434. The value of this constant is equal to the constant
  435. PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.
  436. }
  437. std_param_align = 4; { for 32-bit version only }
  438. {*****************************************************************************
  439. CPU Dependent Constants
  440. *****************************************************************************}
  441. LinkageAreaSizeAIX = 24;
  442. LinkageAreaSizeSYSV = 8;
  443. { offset in the linkage area for the saved stack pointer }
  444. LA_SP = 0;
  445. { offset in the linkage area for the saved conditional register}
  446. LA_CR_AIX = 4;
  447. { offset in the linkage area for the saved link register}
  448. LA_LR_AIX = 8;
  449. LA_LR_SYSV = 4;
  450. { offset in the linkage area for the saved RTOC register}
  451. LA_RTOC_AIX = 20;
  452. PARENT_FRAMEPOINTER_OFFSET = 12;
  453. NR_RTOC = NR_R2;
  454. {*****************************************************************************
  455. Helpers
  456. *****************************************************************************}
  457. function is_calljmp(o:tasmop):boolean;
  458. procedure inverse_flags(var r : TResFlags);
  459. procedure inverse_cond(const c: TAsmCond;var r : TAsmCond);
  460. function flags_to_cond(const f: TResFlags) : TAsmCond;
  461. procedure create_cond_imm(BO,BI:byte;var r : TAsmCond);
  462. procedure create_cond_norm(cond: TAsmCondFlag; cr: byte;var r : TasmCond);
  463. function cgsize2subreg(s:Tcgsize):Tsubregister;
  464. function findreg_by_number(r:Tregister):tregisterindex;
  465. function std_regnum_search(const s:string):Tregister;
  466. function std_regname(r:Tregister):string;
  467. function is_condreg(r : tregister):boolean;
  468. implementation
  469. uses
  470. rgBase,verbose;
  471. const
  472. std_regname_table : array[tregisterindex] of string[7] = (
  473. {$i rppcstd.inc}
  474. );
  475. regnumber_index : array[tregisterindex] of tregisterindex = (
  476. {$i rppcrni.inc}
  477. );
  478. std_regname_index : array[tregisterindex] of tregisterindex = (
  479. {$i rppcsri.inc}
  480. );
  481. {*****************************************************************************
  482. Helpers
  483. *****************************************************************************}
  484. function is_calljmp(o:tasmop):boolean;
  485. begin
  486. is_calljmp:=false;
  487. case o of
  488. A_B,A_BA,A_BL,A_BLA,A_BC,A_BCA,A_BCL,A_BCLA,A_BCCTR,A_BCCTRL,A_BCLR,
  489. A_BCLRL,A_TW,A_TWI: is_calljmp:=true;
  490. end;
  491. end;
  492. procedure inverse_flags(var r: TResFlags);
  493. const
  494. inv_flags: array[F_EQ..F_GE] of TResFlagsEnum =
  495. (F_NE,F_EQ,F_GE,F_GE,F_LE,F_LT);
  496. begin
  497. r.flag := inv_flags[r.flag];
  498. end;
  499. procedure inverse_cond(const c: TAsmCond;var r : TAsmCond);
  500. const
  501. inv_condflags:array[TAsmCondFlag] of TAsmCondFlag=(C_None,
  502. C_GE,C_GT,C_NE,C_LT,C_LE,C_LT,C_EQ,C_GT,C_NS,C_SO,C_NU,C_UN,
  503. C_F,C_T,C_DNZ,C_DNZF,C_DNZT,C_DZ,C_DZF,C_DZT);
  504. begin
  505. r := c;
  506. r.cond := inv_condflags[c.cond];
  507. end;
  508. function flags_to_cond(const f: TResFlags) : TAsmCond;
  509. const
  510. flag_2_cond: array[F_EQ..F_SO] of TAsmCondFlag =
  511. (C_EQ,C_NE,C_LT,C_LE,C_GT,C_GE,C_SO);
  512. begin
  513. if f.flag > high(flag_2_cond) then
  514. internalerror(200112301);
  515. result.simple := true;
  516. result.cr := f.cr;
  517. result.cond := flag_2_cond[f.flag];
  518. end;
  519. procedure create_cond_imm(BO,BI:byte;var r : TAsmCond);
  520. begin
  521. r.simple := false;
  522. r.bo := bo;
  523. r.bi := bi;
  524. end;
  525. procedure create_cond_norm(cond: TAsmCondFlag; cr: byte;var r : TasmCond);
  526. begin
  527. r.simple := true;
  528. r.cond := cond;
  529. case cond of
  530. C_NONE:;
  531. C_T..C_DZF: r.crbit := cr
  532. else r.cr := RS_CR0+cr;
  533. end;
  534. end;
  535. function is_condreg(r : tregister):boolean;
  536. var
  537. supreg: tsuperregister;
  538. begin
  539. result := false;
  540. if (getregtype(r) = R_SPECIALREGISTER) then
  541. begin
  542. supreg := getsupreg(r);
  543. result := (supreg >= RS_CR0) and (supreg <= RS_CR7);
  544. end;
  545. end;
  546. function cgsize2subreg(s:Tcgsize):Tsubregister;
  547. begin
  548. cgsize2subreg:=R_SUBWHOLE;
  549. end;
  550. function findreg_by_number(r:Tregister):tregisterindex;
  551. begin
  552. result:=rgBase.findreg_by_number_table(r,regnumber_index);
  553. end;
  554. function std_regnum_search(const s:string):Tregister;
  555. begin
  556. result:=regnumber_table[findreg_by_name_table(s,std_regname_table,std_regname_index)];
  557. end;
  558. function std_regname(r:Tregister):string;
  559. var
  560. p : tregisterindex;
  561. begin
  562. p:=findreg_by_number_table(r,regnumber_index);
  563. if p<>0 then
  564. result:=std_regname_table[p]
  565. else
  566. result:=generic_regname(r);
  567. end;
  568. end.
  569. {
  570. $Log$
  571. Revision 1.81 2003-12-16 21:49:47 florian
  572. * fixed ppc compilation
  573. Revision 1.80 2003/12/09 20:39:43 jonas
  574. * forgot call to cg.g_overflowcheck() in nppcadd
  575. * fixed overflow flag definition
  576. * fixed cg.g_overflowcheck() for signed numbers (jump over call to
  577. FPC_OVERFLOW if *no* overflow instead of if overflow :)
  578. Revision 1.79 2003/11/29 16:27:19 jonas
  579. * fixed several ppc assembler reader related problems
  580. * local vars in assembler procedures now start at offset 4
  581. * fixed second_int_to_bool (apparently an integer can be in LOC_JUMP??)
  582. Revision 1.78 2003/11/23 20:00:39 jonas
  583. * fixed is_condreg
  584. * fixed branch condition parsing in assembler reader
  585. Revision 1.77 2003/11/15 19:00:10 florian
  586. * fixed ppc assembler reader
  587. Revision 1.76 2003/11/12 16:05:40 florian
  588. * assembler readers OOPed
  589. + typed currency constants
  590. + typed 128 bit float constants if the CPU supports it
  591. Revision 1.75 2003/10/31 08:42:28 mazen
  592. * rgHelper renamed to rgBase
  593. * using findreg_by_<name|number>_table directly to decrease heap overheading
  594. Revision 1.74 2003/10/30 15:03:18 mazen
  595. * now uses standard routines in rgBase unit to search registers by number and by name
  596. Revision 1.73 2003/10/19 01:34:31 florian
  597. * some ppc stuff fixed
  598. * memory leak fixed
  599. Revision 1.72 2003/10/17 15:08:34 peter
  600. * commented out more obsolete constants
  601. Revision 1.71 2003/10/11 16:06:42 florian
  602. * fixed some MMX<->SSE
  603. * started to fix ppc, needs an overhaul
  604. + stabs info improve for spilling, not sure if it works correctly/completly
  605. - MMX_SUPPORT removed from Makefile.fpc
  606. Revision 1.70 2003/10/08 14:11:36 mazen
  607. + Alignement field added to TParaLocation (=4 as 32 bits archs)
  608. Revision 1.69 2003/10/01 20:34:49 peter
  609. * procinfo unit contains tprocinfo
  610. * cginfo renamed to cgbase
  611. * moved cgmessage to verbose
  612. * fixed ppc and sparc compiles
  613. Revision 1.68 2003/09/14 16:37:20 jonas
  614. * fixed some ppc problems
  615. Revision 1.67 2003/09/03 21:04:14 peter
  616. * some fixes for ppc
  617. Revision 1.66 2003/09/03 19:35:24 peter
  618. * powerpc compiles again
  619. Revision 1.65 2003/09/03 11:18:37 florian
  620. * fixed arm concatcopy
  621. + arm support in the common compiler sources added
  622. * moved some generic cg code around
  623. + tfputype added
  624. * ...
  625. Revision 1.64 2003/08/17 16:59:20 jonas
  626. * fixed regvars so they work with newra (at least for ppc)
  627. * fixed some volatile register bugs
  628. + -dnotranslation option for -dnewra, which causes the registers not to
  629. be translated from virtual to normal registers. Requires support in
  630. the assembler writer as well, which is only implemented in aggas/
  631. agppcgas currently
  632. Revision 1.63 2003/08/08 15:51:16 olle
  633. * merged macos entry/exit code generation into the general one.
  634. Revision 1.62 2003/07/23 11:00:09 jonas
  635. * "lastsaveintreg" is RS_R31 instead of RS_R27 with -dnewra, because
  636. there are no scratch regs anymore
  637. Revision 1.61 2003/07/06 20:25:03 jonas
  638. * fixed ppc compiler
  639. Revision 1.60 2003/07/06 15:28:24 jonas
  640. * VOLATILE_REGISTERS was wrong (it was more or less the inverted set
  641. of what it had to be :/ )
  642. Revision 1.59 2003/06/17 16:34:44 jonas
  643. * lots of newra fixes (need getfuncretparaloc implementation for i386)!
  644. * renamed all_intregisters to volatile_intregisters and made it
  645. processor dependent
  646. Revision 1.58 2003/06/14 22:32:43 jonas
  647. * ppc compiles with -dnewra, haven't tried to compile anything with it
  648. yet though
  649. Revision 1.57 2003/06/13 17:44:44 jonas
  650. + added supreg_name function
  651. Revision 1.56 2003/06/12 19:11:34 jonas
  652. - removed ALL_INTREGISTERS (only the one in rgobj is valid)
  653. Revision 1.55 2003/05/31 15:05:28 peter
  654. * FUNCTION_RESULT64_LOW/HIGH_REG added for int64 results
  655. Revision 1.54 2003/05/30 23:57:08 peter
  656. * more sparc cleanup
  657. * accumulator removed, splitted in function_return_reg (called) and
  658. function_result_reg (caller)
  659. Revision 1.53 2003/05/30 18:49:59 jonas
  660. * changed scratchregs from r28-r30 to r29-r31
  661. * made sure the regvar registers don't overlap with the scratchregs
  662. anymore
  663. Revision 1.52 2003/05/24 16:02:01 jonas
  664. * fixed endian problem with tlocation.value/valueqword fields
  665. Revision 1.51 2003/05/16 16:26:05 jonas
  666. * adapted for Peter's regvar fixes
  667. Revision 1.50 2003/05/15 22:14:43 florian
  668. * fixed last commit, changing lastsaveintreg to r31 caused some strange problems
  669. Revision 1.49 2003/05/15 21:37:00 florian
  670. * sysv entry code saves r13 now as well
  671. Revision 1.48 2003/04/23 12:35:35 florian
  672. * fixed several issues with powerpc
  673. + applied a patch from Jonas for nested function calls (PowerPC only)
  674. * ...
  675. Revision 1.47 2003/04/22 11:27:48 florian
  676. + added first_ and last_imreg
  677. Revision 1.46 2003/03/19 14:26:26 jonas
  678. * fixed R_TOC bugs introduced by new register allocator conversion
  679. Revision 1.45 2003/03/11 21:46:24 jonas
  680. * lots of new regallocator fixes, both in generic and ppc-specific code
  681. (ppc compiler still can't compile the linux system unit though)
  682. Revision 1.44 2003/02/19 22:00:16 daniel
  683. * Code generator converted to new register notation
  684. - Horribily outdated todo.txt removed
  685. Revision 1.43 2003/02/02 19:25:54 carl
  686. * Several bugfixes for m68k target (register alloc., opcode emission)
  687. + VIS target
  688. + Generic add more complete (still not verified)
  689. Revision 1.42 2003/01/16 11:31:28 olle
  690. + added new register constants
  691. + implemented register convertion proc
  692. Revision 1.41 2003/01/13 17:17:50 olle
  693. * changed global var access, TOC now contain pointers to globals
  694. * fixed handling of function pointers
  695. Revision 1.40 2003/01/09 15:49:56 daniel
  696. * Added register conversion
  697. Revision 1.39 2003/01/08 18:43:58 daniel
  698. * Tregister changed into a record
  699. Revision 1.38 2002/11/25 17:43:27 peter
  700. * splitted defbase in defutil,symutil,defcmp
  701. * merged isconvertable and is_equal into compare_defs(_ext)
  702. * made operator search faster by walking the list only once
  703. Revision 1.37 2002/11/24 14:28:56 jonas
  704. + some comments describing the fields of treference
  705. Revision 1.36 2002/11/17 18:26:16 mazen
  706. * fixed a compilation bug accmulator-->FUNCTION_RETURN_REG, in definition of return_result_reg
  707. Revision 1.35 2002/11/17 17:49:09 mazen
  708. + return_result_reg and FUNCTION_RESULT_REG are now used, in all plateforms, to pass functions result between called function and its caller. See the explanation of each one
  709. Revision 1.34 2002/09/17 18:54:06 jonas
  710. * a_load_reg_reg() now has two size parameters: source and dest. This
  711. allows some optimizations on architectures that don't encode the
  712. register size in the register name.
  713. Revision 1.33 2002/09/07 17:54:59 florian
  714. * first part of PowerPC fixes
  715. Revision 1.32 2002/09/07 15:25:14 peter
  716. * old logs removed and tabs fixed
  717. Revision 1.31 2002/09/01 21:04:49 florian
  718. * several powerpc related stuff fixed
  719. Revision 1.30 2002/08/18 22:16:15 florian
  720. + the ppc gas assembler writer adds now registers aliases
  721. to the assembler file
  722. Revision 1.29 2002/08/18 21:36:42 florian
  723. + handling of local variables in direct reader implemented
  724. Revision 1.28 2002/08/14 18:41:47 jonas
  725. - remove valuelow/valuehigh fields from tlocation, because they depend
  726. on the endianess of the host operating system -> difficult to get
  727. right. Use lo/hi(location.valueqword) instead (remember to use
  728. valueqword and not value!!)
  729. Revision 1.27 2002/08/13 21:40:58 florian
  730. * more fixes for ppc calling conventions
  731. Revision 1.26 2002/08/12 15:08:44 carl
  732. + stab register indexes for powerpc (moved from gdb to cpubase)
  733. + tprocessor enumeration moved to cpuinfo
  734. + linker in target_info is now a class
  735. * many many updates for m68k (will soon start to compile)
  736. - removed some ifdef or correct them for correct cpu
  737. Revision 1.25 2002/08/10 17:15:06 jonas
  738. * endianess fix
  739. Revision 1.24 2002/08/06 20:55:24 florian
  740. * first part of ppc calling conventions fix
  741. Revision 1.23 2002/08/04 12:57:56 jonas
  742. * more misc. fixes, mostly constant-related
  743. Revision 1.22 2002/07/27 19:57:18 jonas
  744. * some typo corrections in the instruction tables
  745. * renamed the m* registers to v*
  746. Revision 1.21 2002/07/26 12:30:51 jonas
  747. * fixed typo in instruction table (_subco_ -> a_subco)
  748. Revision 1.20 2002/07/25 18:04:10 carl
  749. + FPURESULTREG -> FPU_RESULT_REG
  750. Revision 1.19 2002/07/13 19:38:44 florian
  751. * some more generic calling stuff fixed
  752. Revision 1.18 2002/07/11 14:41:34 florian
  753. * start of the new generic parameter handling
  754. Revision 1.17 2002/07/11 07:35:36 jonas
  755. * some available registers fixes
  756. Revision 1.16 2002/07/09 19:45:01 jonas
  757. * unarynminus and shlshr node fixed for 32bit and smaller ordinals
  758. * small fixes in the assembler writer
  759. * changed scratch registers, because they were used by the linker (r11
  760. and r12) and by the abi under linux (r31)
  761. Revision 1.15 2002/07/07 09:44:31 florian
  762. * powerpc target fixed, very simple units can be compiled
  763. Revision 1.14 2002/05/18 13:34:26 peter
  764. * readded missing revisions
  765. Revision 1.12 2002/05/14 19:35:01 peter
  766. * removed old logs and updated copyright year
  767. Revision 1.11 2002/05/14 17:28:10 peter
  768. * synchronized cpubase between powerpc and i386
  769. * moved more tables from cpubase to cpuasm
  770. * tai_align_abstract moved to tainst, cpuasm must define
  771. the tai_align class now, which may be empty
  772. }