cpubase.pas 15 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl
  3. Contains the base types for the RiscV64
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. { This Unit contains the base types for the RiscV64
  18. }
  19. unit cpubase;
  20. {$I fpcdefs.inc}
  21. interface
  22. uses
  23. strings, globtype,
  24. cutils, cclasses, aasmbase, cpuinfo, cgbase;
  25. {*****************************************************************************
  26. Assembler Opcodes
  27. *****************************************************************************}
  28. type
  29. TAsmOp=(A_None,
  30. { Pseudo instructions }
  31. A_NOP,
  32. { normal opcodes }
  33. A_LUI,A_AUIPC,A_JAL,A_JALR,
  34. A_Bxx,A_LB,A_LH,A_LW,A_LBU,A_LHU,
  35. A_SB,A_SH,A_SW,
  36. A_ADDI,A_SLTI,A_SLTIU,
  37. A_XORI,A_ORI,A_ANDI,
  38. A_SLLI,A_SRLI,A_SRAI,
  39. A_ADD,A_SUB,A_SLL,A_SLT,A_SLTU,
  40. A_XOR,A_SRL,A_SRA,A_OR,A_AND,
  41. A_FENCE,A_FENCE_I,
  42. A_ECALL,A_EBREAK,
  43. A_CSRRW,A_CSRRS,A_CSRRC,A_CSRRWI,A_CSRRSI,A_CSRRCI,
  44. { 64-bit }
  45. A_ADDIW,A_SLLIW,A_SRLIW,A_SRAIW,
  46. A_ADDW,A_SLLW,A_SRLW,A_SUBW,A_SRAW,
  47. A_LD,A_SD,A_LWU,
  48. { M-extension }
  49. A_MUL,A_MULH,A_MULHSU,A_MULHU,
  50. A_DIV,A_DIVU,A_REM,A_REMU,
  51. { 64-bit }
  52. A_MULW,
  53. A_DIVW,A_DIVUW,A_REMW,A_REMUW,
  54. { A-extension }
  55. A_LR_W,A_SC_W,A_AMOSWAP_W,A_AMOADD_W,A_AMOXOR_W,A_AMOAND_W,
  56. A_AMOOR_W,A_AMOMIN_W,A_AMOMAX_W,A_AMOMINU_W,A_AMOMAXU_W,
  57. { 64-bit }
  58. A_LR_D,A_SC_D,A_AMOSWAP_D,A_AMOADD_D,A_AMOXOR_D,A_AMOAND_D,
  59. A_AMOOR_D,A_AMOMIN_D,A_AMOMAX_D,A_AMOMINU_D,A_AMOMAXU_D,
  60. { F-extension }
  61. A_FLW,A_FSW,
  62. A_FMADD_S,A_FMSUB_S,A_FNMSUB_S,A_FNMADD_S,
  63. A_FADD_S,A_FSUB_S,A_FMUL_S,A_FDIV_S,
  64. A_FSQRT_S,A_FSGNJ_S,A_FSGNJN_S,A_FSGNJX_S,
  65. A_FMIN_S,A_FMAX_S,
  66. A_FMV_X_S,A_FEQ_S,A_FLT_S,A_FLE_S,A_FCLASS_S,
  67. A_FCVT_W_S,A_FCVT_WU_S,A_FCVT_S_W,A_FCVT_S_WU,
  68. A_FMV_S_X,
  69. A_FRCSR,A_FRRM,A_FRFLAGS,A_FSCSR,A_FSRM,
  70. A_FSFLAGS,A_FSRMI,A_FSFLAGSI,
  71. { 64-bit }
  72. A_FCVT_L_S,A_FCVT_LU_S,
  73. A_FCVT_S_L,A_FCVT_S_LU,
  74. { D-extension }
  75. A_FLD,A_FSD,
  76. A_FMADD_D,A_FMSUB_D,A_FNMSUB_D,A_FNMADD_D,
  77. A_FADD_D,A_FSUB_D,A_FMUL_D,A_FDIV_D,
  78. A_FSQRT_D,A_FSGNJ_D,A_FSGNJN_D,A_FSGNJX_D,
  79. A_FMIN_D,A_FMAX_D,
  80. A_FEQ_D,A_FLT_D,A_FLE_D,A_FCLASS_D,
  81. A_FCVT_D_S,A_FCVT_S_D,
  82. A_FCVT_W_D,A_FCVT_WU_D,A_FCVT_D_W,A_FCVT_D_WU,
  83. { 64-bit }
  84. A_FCVT_L_D,A_FCVT_LU_D,A_FMV_X_D,
  85. A_FCVT_D_L,A_FCVT_D_LU,A_FMV_D_X,
  86. { Machine mode }
  87. A_MRET,A_HRET,A_SRET,A_URET,
  88. A_WFI,
  89. { Supervisor }
  90. A_SFENCE_VM
  91. );
  92. {# This should define the array of instructions as string }
  93. op2strtable = array[tasmop] of string[8];
  94. const
  95. {# First value of opcode enumeration }
  96. firstop = low(tasmop);
  97. {# Last value of opcode enumeration }
  98. lastop = high(tasmop);
  99. {*****************************************************************************
  100. Registers
  101. *****************************************************************************}
  102. type
  103. { Number of registers used for indexing in tables }
  104. tregisterindex=0..{$i rrv32nor.inc}-1;
  105. totherregisterset = set of tregisterindex;
  106. const
  107. maxvarregs = 32-6; { 32 int registers - r0 - stackpointer - r2 - 3 scratch registers }
  108. maxfpuvarregs = 28; { 32 fpuregisters - some scratch registers (minimally 2) }
  109. { Available Superregisters }
  110. {$i rrv32sup.inc}
  111. { No Subregisters }
  112. R_SUBWHOLE=R_SUBNONE;
  113. { Available Registers }
  114. {$i rrv32con.inc}
  115. { Integer Super registers first and last }
  116. first_int_imreg = $20;
  117. { Float Super register first and last }
  118. first_fpu_imreg = $20;
  119. { MM Super register first and last }
  120. first_mm_imreg = $20;
  121. { TODO: Calculate bsstart}
  122. regnumber_count_bsstart = 64;
  123. regnumber_table : array[tregisterindex] of tregister = (
  124. {$i rrv32num.inc}
  125. );
  126. regstabs_table : array[tregisterindex] of shortint = (
  127. {$i rrv32sta.inc}
  128. );
  129. regdwarf_table : array[tregisterindex] of shortint = (
  130. {$i rrv32dwa.inc}
  131. );
  132. {*****************************************************************************
  133. Operands
  134. *****************************************************************************}
  135. type
  136. TMemoryOrderingFlag = (moRl, moAq);
  137. TMemoryOrdering = set of TMemoryOrderingFlag;
  138. TFenceFlag = (ffI, ffO, ffR, ffW);
  139. TFenceFlags = set of TFenceFlag;
  140. TRoundingMode = (RM_Default,
  141. RM_RNE,
  142. RM_RTZ,
  143. RM_RDN,
  144. RM_RUP,
  145. RM_RMM);
  146. const
  147. roundingmode2str : array[TRoundingMode] of string[3] = ('',
  148. 'rne','rtz','rdn','rup','rmm');
  149. {*****************************************************************************
  150. Conditions
  151. *****************************************************************************}
  152. type
  153. TAsmCond = (C_None { unconditional jumps },
  154. C_LT,C_LTU,C_GE,C_GEU,C_NE,C_EQ);
  155. const
  156. cond2str: Array[TAsmCond] of string[4] = ({cf_none}'',
  157. { conditions when not using ctr decrement etc}
  158. 'lt','ltu','ge','geu','ne','eq');
  159. uppercond2str: Array[TAsmCond] of string[4] = ({cf_none}'',
  160. { conditions when not using ctr decrement etc}
  161. 'LT','LTU','GE','GEU','NE','EQ');
  162. {*****************************************************************************
  163. Flags
  164. *****************************************************************************}
  165. type
  166. TResFlagsEnum = (F_EQ,F_NE,F_LT,F_LTU,F_GE,F_GEU);
  167. {*****************************************************************************
  168. Reference
  169. *****************************************************************************}
  170. {*****************************************************************************
  171. Operand Sizes
  172. *****************************************************************************}
  173. {*****************************************************************************
  174. Constants
  175. *****************************************************************************}
  176. const
  177. max_operands = 5;
  178. {*****************************************************************************
  179. Default generic sizes
  180. *****************************************************************************}
  181. {# Defines the default address size for a processor, }
  182. OS_ADDR = OS_64;
  183. {# the natural int size for a processor,
  184. has to match osuinttype/ossinttype as initialized in psystem }
  185. OS_INT = OS_64;
  186. OS_SINT = OS_S64;
  187. {# the maximum float size for a processor, }
  188. OS_FLOAT = OS_F64;
  189. {# the size of a vector register for a processor }
  190. OS_VECTOR = OS_M128;
  191. {*****************************************************************************
  192. GDB Information
  193. *****************************************************************************}
  194. stab_regindex: array[tregisterindex] of shortint = (
  195. {$I rrv32sta.inc}
  196. );
  197. {*****************************************************************************
  198. Generic Register names
  199. *****************************************************************************}
  200. {# Stack pointer register }
  201. NR_STACK_POINTER_REG = NR_X2;
  202. RS_STACK_POINTER_REG = RS_X2;
  203. {# Frame pointer register }
  204. NR_FRAME_POINTER_REG = NR_X8;
  205. RS_FRAME_POINTER_REG = RS_X8;
  206. NR_PIC_OFFSET_REG = NR_X3;
  207. { Return address of a function }
  208. NR_RETURN_ADDRESS_REG = NR_X1;
  209. RS_RETURN_ADDRESS_REG = RS_X1;
  210. { Results are returned in this register (32-bit values) }
  211. NR_FUNCTION_RETURN_REG = NR_X10;
  212. RS_FUNCTION_RETURN_REG = RS_X10;
  213. { Low part of 64bit return value }
  214. NR_FUNCTION_RETURN64_LOW_REG = NR_X10;
  215. RS_FUNCTION_RETURN64_LOW_REG = RS_X10;
  216. { High part of 64bit return value }
  217. NR_FUNCTION_RETURN64_HIGH_REG = NR_X11;
  218. RS_FUNCTION_RETURN64_HIGH_REG = RS_X11;
  219. { The value returned from a function is available in this register }
  220. NR_FUNCTION_RESULT_REG = NR_FUNCTION_RETURN_REG;
  221. RS_FUNCTION_RESULT_REG = RS_FUNCTION_RETURN_REG;
  222. { The lowh part of 64bit value returned from a function }
  223. NR_FUNCTION_RESULT64_LOW_REG = NR_FUNCTION_RETURN64_LOW_REG;
  224. RS_FUNCTION_RESULT64_LOW_REG = RS_FUNCTION_RETURN64_LOW_REG;
  225. { The high part of 64bit value returned from a function }
  226. NR_FUNCTION_RESULT64_HIGH_REG = NR_FUNCTION_RETURN64_HIGH_REG;
  227. RS_FUNCTION_RESULT64_HIGH_REG = RS_FUNCTION_RETURN64_HIGH_REG;
  228. NR_FPU_RESULT_REG = NR_F10;
  229. NR_MM_RESULT_REG = NR_NO;
  230. NR_DEFAULTFLAGS = NR_NO;
  231. RS_DEFAULTFLAGS = RS_NO;
  232. {*****************************************************************************
  233. GCC /ABI linking information
  234. *****************************************************************************}
  235. {# Registers which must be saved when calling a routine declared as
  236. cppdecl, cdecl, stdcall, safecall, palmossyscall. The registers
  237. saved should be the ones as defined in the target ABI and / or GCC.
  238. This value can be deduced from CALLED_USED_REGISTERS array in the
  239. GCC source.
  240. }
  241. saved_standard_registers: array[0..12] of tsuperregister = (
  242. RS_X2,
  243. RS_X8,RS_X9,
  244. RS_X18,RS_X19,
  245. RS_X20,RS_X21,RS_X22,RS_X23,RS_X24,RS_X25,RS_X26,RS_X27
  246. );
  247. { this is only for the generic code which is not used for this architecture }
  248. saved_address_registers : array[0..0] of tsuperregister = (RS_INVALID);
  249. saved_mm_registers : array[0..0] of tsuperregister = (RS_INVALID);
  250. {# Required parameter alignment when calling a routine declared as
  251. stdcall and cdecl. The alignment value should be the one defined
  252. by GCC or the target ABI.
  253. The value of this constant is equal to the constant
  254. PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.
  255. }
  256. std_param_align = 8; { for 32-bit version only }
  257. {*****************************************************************************
  258. CPU Dependent Constants
  259. *****************************************************************************}
  260. maxfpuregs = 8;
  261. {*****************************************************************************
  262. Helpers
  263. *****************************************************************************}
  264. function is_imm12(value: aint): boolean;
  265. function is_lui_imm(value: aint): boolean;
  266. function is_calljmp(o:tasmop):boolean;
  267. function cgsize2subreg(regtype: tregistertype; s:Tcgsize):Tsubregister;
  268. { Returns the tcgsize corresponding with the size of reg.}
  269. function reg_cgsize(const reg: tregister) : tcgsize;
  270. function findreg_by_number(r:Tregister):tregisterindex;
  271. function std_regnum_search(const s:string):Tregister;
  272. function std_regname(r:Tregister):string;
  273. function inverse_cond(const c: TAsmCond): Tasmcond; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  274. function dwarf_reg(r:tregister):shortint;
  275. function conditions_equal(const c1,c2: TAsmCond): boolean;
  276. implementation
  277. uses
  278. rgbase,verbose;
  279. const
  280. std_regname_table : TRegNameTable = (
  281. {$i rrv32std.inc}
  282. );
  283. regnumber_index : array[tregisterindex] of tregisterindex = (
  284. {$i rrv32rni.inc}
  285. );
  286. std_regname_index : array[tregisterindex] of tregisterindex = (
  287. {$i rrv32sri.inc}
  288. );
  289. {*****************************************************************************
  290. Helpers
  291. *****************************************************************************}
  292. function is_imm12(value: aint): boolean;
  293. begin
  294. result:=(value >= -2048) and (value <= 2047);
  295. end;
  296. function is_lui_imm(value: aint): boolean;
  297. begin
  298. result:=SarInt64((value and $FFFFF000) shl 32, 32) = value;
  299. end;
  300. function is_calljmp(o:tasmop):boolean;
  301. begin
  302. is_calljmp:=false;
  303. case o of
  304. A_JAL,A_JALR,A_Bxx:
  305. is_calljmp:=true;
  306. end;
  307. end;
  308. function inverse_cond(const c: TAsmCond): Tasmcond; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  309. const
  310. inv_condflags:array[TAsmCond] of TAsmCond=(C_None,
  311. C_GE,C_GEU,C_LT,C_LTU,C_EQ,C_NE);
  312. begin
  313. result := inv_condflags[c];
  314. end;
  315. function reg_cgsize(const reg: tregister): tcgsize;
  316. begin
  317. case getregtype(reg) of
  318. R_INTREGISTER :
  319. result:=OS_64;
  320. R_MMREGISTER:
  321. result:=OS_M128;
  322. R_FPUREGISTER:
  323. result:=OS_F64;
  324. else
  325. internalerror(200303181);
  326. end;
  327. end;
  328. function cgsize2subreg(regtype: tregistertype; s:Tcgsize):Tsubregister;
  329. begin
  330. cgsize2subreg:=R_SUBWHOLE;
  331. end;
  332. function findreg_by_number(r:Tregister):tregisterindex;
  333. begin
  334. result:=rgBase.findreg_by_number_table(r,regnumber_index);
  335. end;
  336. function std_regnum_search(const s:string):Tregister;
  337. begin
  338. result:=regnumber_table[findreg_by_name_table(s,std_regname_table,std_regname_index)];
  339. end;
  340. function std_regname(r:Tregister):string;
  341. var
  342. p : tregisterindex;
  343. begin
  344. p:=findreg_by_number_table(r,regnumber_index);
  345. if p<>0 then
  346. result:=std_regname_table[p]
  347. else
  348. result:=generic_regname(r);
  349. end;
  350. function dwarf_reg(r:tregister):shortint;
  351. begin
  352. result:=regdwarf_table[findreg_by_number(r)];
  353. if result=-1 then
  354. internalerror(200603251);
  355. end;
  356. function conditions_equal(const c1, c2: TAsmCond): boolean;
  357. begin
  358. result:=c1=c2;
  359. end;
  360. end.