cgcpu.pas 54 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl
  3. This unit implements the code generator for the SPARC
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit cgcpu;
  18. {$i fpcdefs.inc}
  19. interface
  20. uses
  21. globtype,parabase,
  22. cgbase,cgutils,cgobj,cg64f32,
  23. aasmbase,aasmtai,aasmdata,aasmcpu,
  24. cpubase,cpuinfo,
  25. node,symconst,SymType,symdef,
  26. rgcpu;
  27. type
  28. TCgSparc=class(tcg)
  29. protected
  30. function IsSimpleRef(const ref:treference):boolean;
  31. public
  32. procedure init_register_allocators;override;
  33. procedure done_register_allocators;override;
  34. function getfpuregister(list:TAsmList;size:Tcgsize):Tregister;override;
  35. { sparc special, needed by cg64 }
  36. procedure make_simple_ref(list:TAsmList;var ref: treference);
  37. procedure handle_load_store(list:TAsmList;isstore:boolean;op: tasmop;reg:tregister;ref: treference);
  38. procedure handle_reg_const_reg(list:TAsmList;op:Tasmop;src:tregister;a:aint;dst:tregister);
  39. { parameter }
  40. procedure a_param_const(list:TAsmList;size:tcgsize;a:aint;const paraloc:TCGPara);override;
  41. procedure a_param_ref(list:TAsmList;sz:tcgsize;const r:TReference;const paraloc:TCGPara);override;
  42. procedure a_paramaddr_ref(list:TAsmList;const r:TReference;const paraloc:TCGPara);override;
  43. procedure a_paramfpu_reg(list : TAsmList;size : tcgsize;const r : tregister;const paraloc : TCGPara);override;
  44. procedure a_paramfpu_ref(list : TAsmList;size : tcgsize;const ref : treference;const paraloc : TCGPara);override;
  45. procedure a_call_name(list:TAsmList;const s:string);override;
  46. procedure a_call_reg(list:TAsmList;Reg:TRegister);override;
  47. { General purpose instructions }
  48. procedure a_op_const_reg(list:TAsmList;Op:TOpCG;size:tcgsize;a:aint;reg:TRegister);override;
  49. procedure a_op_reg_reg(list:TAsmList;Op:TOpCG;size:TCGSize;src, dst:TRegister);override;
  50. procedure a_op_const_reg_reg(list:TAsmList;op:TOpCg;size:tcgsize;a:aint;src, dst:tregister);override;
  51. procedure a_op_reg_reg_reg(list:TAsmList;op:TOpCg;size:tcgsize;src1, src2, dst:tregister);override;
  52. procedure a_op_const_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; a: aint; src, dst: tregister;setflags : boolean;var ovloc : tlocation);override;
  53. procedure a_op_reg_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister;setflags : boolean;var ovloc : tlocation);override;
  54. { move instructions }
  55. procedure a_load_const_reg(list:TAsmList;size:tcgsize;a:aint;reg:tregister);override;
  56. procedure a_load_const_ref(list:TAsmList;size:tcgsize;a:aint;const ref:TReference);override;
  57. procedure a_load_reg_ref(list:TAsmList;FromSize,ToSize:TCgSize;reg:TRegister;const ref:TReference);override;
  58. procedure a_load_ref_reg(list:TAsmList;FromSize,ToSize:TCgSize;const ref:TReference;reg:tregister);override;
  59. procedure a_load_reg_reg(list:TAsmList;FromSize,ToSize:TCgSize;reg1,reg2:tregister);override;
  60. procedure a_loadaddr_ref_reg(list:TAsmList;const ref:TReference;r:tregister);override;
  61. { fpu move instructions }
  62. procedure a_loadfpu_reg_reg(list:TAsmList;size:tcgsize;reg1, reg2:tregister);override;
  63. procedure a_loadfpu_ref_reg(list:TAsmList;size:tcgsize;const ref:TReference;reg:tregister);override;
  64. procedure a_loadfpu_reg_ref(list:TAsmList;size:tcgsize;reg:tregister;const ref:TReference);override;
  65. { comparison operations }
  66. procedure a_cmp_const_reg_label(list:TAsmList;size:tcgsize;cmp_op:topcmp;a:aint;reg:tregister;l:tasmlabel);override;
  67. procedure a_cmp_reg_reg_label(list:TAsmList;size:tcgsize;cmp_op:topcmp;reg1,reg2:tregister;l:tasmlabel);override;
  68. procedure a_jmp_always(List:TAsmList;l:TAsmLabel);override;
  69. procedure a_jmp_name(list : TAsmList;const s : string);override;
  70. procedure a_jmp_cond(list:TAsmList;cond:TOpCmp;l:tasmlabel);{ override;}
  71. procedure a_jmp_flags(list:TAsmList;const f:TResFlags;l:tasmlabel);override;
  72. procedure g_flags2reg(list:TAsmList;Size:TCgSize;const f:tresflags;reg:TRegister);override;
  73. procedure g_overflowCheck(List:TAsmList;const Loc:TLocation;def:TDef);override;
  74. procedure g_overflowCheck_loc(List:TAsmList;const Loc:TLocation;def:TDef;ovloc : tlocation);override;
  75. procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
  76. procedure g_proc_exit(list : TAsmList;parasize:longint;nostackframe:boolean);override;
  77. procedure g_restore_standard_registers(list:TAsmList);override;
  78. procedure g_save_standard_registers(list : TAsmList);override;
  79. procedure g_concatcopy(list : TAsmList;const source,dest : treference;len : aint);override;
  80. procedure g_concatcopy_unaligned(list : TAsmList;const source,dest : treference;len : aint);override;
  81. procedure g_concatcopy_move(list : TAsmList;const source,dest : treference;len : aint);
  82. procedure g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);override;
  83. end;
  84. TCg64Sparc=class(tcg64f32)
  85. private
  86. procedure get_64bit_ops(op:TOpCG;var op1,op2:TAsmOp;checkoverflow : boolean);
  87. public
  88. procedure a_load64_reg_ref(list : TAsmList;reg : tregister64;const ref : treference);override;
  89. procedure a_load64_ref_reg(list : TAsmList;const ref : treference;reg : tregister64);override;
  90. procedure a_param64_ref(list : TAsmList;const r : treference;const paraloc : tcgpara);override;
  91. procedure a_op64_reg_reg(list:TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst:TRegister64);override;
  92. procedure a_op64_const_reg(list:TAsmList;op:TOpCG;size : tcgsize;value:int64;regdst:TRegister64);override;
  93. procedure a_op64_const_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64);override;
  94. procedure a_op64_reg_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64);override;
  95. procedure a_op64_const_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64;setflags : boolean;var ovloc : tlocation);override;
  96. procedure a_op64_reg_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64;setflags : boolean;var ovloc : tlocation);override;
  97. end;
  98. const
  99. TOpCG2AsmOp : array[topcg] of TAsmOp=(
  100. A_NONE,A_MOV,A_ADD,A_AND,A_UDIV,A_SDIV,A_SMUL,A_UMUL,A_NEG,A_NOT,A_OR,A_SRA,A_SLL,A_SRL,A_SUB,A_XOR
  101. );
  102. TOpCG2AsmOpWithFlags : array[topcg] of TAsmOp=(
  103. A_NONE,A_MOV,A_ADDcc,A_ANDcc,A_UDIVcc,A_SDIVcc,A_SMULcc,A_UMULcc,A_NEG,A_NOT,A_ORcc,A_SRA,A_SLL,A_SRL,A_SUBcc,A_XORcc
  104. );
  105. TOpCmp2AsmCond : array[topcmp] of TAsmCond=(C_NONE,
  106. C_E,C_G,C_L,C_GE,C_LE,C_NE,C_BE,C_B,C_AE,C_A
  107. );
  108. implementation
  109. uses
  110. globals,verbose,systems,cutils,
  111. paramgr,fmodule,
  112. tgobj,
  113. procinfo,cpupi;
  114. function TCgSparc.IsSimpleRef(const ref:treference):boolean;
  115. begin
  116. if (ref.base=NR_NO) and (ref.index<>NR_NO) then
  117. InternalError(2002100804);
  118. result :=not(assigned(ref.symbol))and
  119. (((ref.index = NR_NO) and
  120. (ref.offset >= simm13lo) and
  121. (ref.offset <= simm13hi)) or
  122. ((ref.index <> NR_NO) and
  123. (ref.offset = 0)));
  124. end;
  125. procedure tcgsparc.make_simple_ref(list:TAsmList;var ref: treference);
  126. var
  127. tmpreg : tregister;
  128. tmpref : treference;
  129. begin
  130. tmpreg:=NR_NO;
  131. { Be sure to have a base register }
  132. if (ref.base=NR_NO) then
  133. begin
  134. ref.base:=ref.index;
  135. ref.index:=NR_NO;
  136. end;
  137. if (cs_create_pic in aktmoduleswitches) and
  138. assigned(ref.symbol) then
  139. begin
  140. tmpreg:=GetIntRegister(list,OS_INT);
  141. reference_reset(tmpref);
  142. tmpref.symbol:=ref.symbol;
  143. tmpref.refaddr:=addr_pic;
  144. if not(pi_needs_got in current_procinfo.flags) then
  145. internalerror(200501161);
  146. tmpref.index:=current_procinfo.got;
  147. list.concat(taicpu.op_ref_reg(A_LD,tmpref,tmpreg));
  148. ref.symbol:=nil;
  149. if (ref.index<>NR_NO) then
  150. begin
  151. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.index,tmpreg));
  152. ref.index:=tmpreg;
  153. end
  154. else
  155. begin
  156. if ref.base<>NR_NO then
  157. ref.index:=tmpreg
  158. else
  159. ref.base:=tmpreg;
  160. end;
  161. end;
  162. { When need to use SETHI, do it first }
  163. if assigned(ref.symbol) or
  164. (ref.offset<simm13lo) or
  165. (ref.offset>simm13hi) then
  166. begin
  167. tmpreg:=GetIntRegister(list,OS_INT);
  168. reference_reset(tmpref);
  169. tmpref.symbol:=ref.symbol;
  170. tmpref.offset:=ref.offset;
  171. tmpref.refaddr:=addr_hi;
  172. list.concat(taicpu.op_ref_reg(A_SETHI,tmpref,tmpreg));
  173. if (ref.offset=0) and (ref.index=NR_NO) and
  174. (ref.base=NR_NO) then
  175. begin
  176. ref.refaddr:=addr_lo;
  177. end
  178. else
  179. begin
  180. { Load the low part is left }
  181. tmpref.refaddr:=addr_lo;
  182. list.concat(taicpu.op_reg_ref_reg(A_OR,tmpreg,tmpref,tmpreg));
  183. ref.offset:=0;
  184. { symbol is loaded }
  185. ref.symbol:=nil;
  186. end;
  187. if (ref.index<>NR_NO) then
  188. begin
  189. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.index,tmpreg));
  190. ref.index:=tmpreg;
  191. end
  192. else
  193. begin
  194. if ref.base<>NR_NO then
  195. ref.index:=tmpreg
  196. else
  197. ref.base:=tmpreg;
  198. end;
  199. end;
  200. if (ref.base<>NR_NO) then
  201. begin
  202. if (ref.index<>NR_NO) and
  203. ((ref.offset<>0) or assigned(ref.symbol)) then
  204. begin
  205. if tmpreg=NR_NO then
  206. tmpreg:=GetIntRegister(list,OS_INT);
  207. list.concat(taicpu.op_reg_reg_reg(A_ADD,ref.base,ref.index,tmpreg));
  208. ref.base:=tmpreg;
  209. ref.index:=NR_NO;
  210. end;
  211. end;
  212. end;
  213. procedure tcgsparc.handle_load_store(list:TAsmList;isstore:boolean;op: tasmop;reg:tregister;ref: treference);
  214. begin
  215. make_simple_ref(list,ref);
  216. if isstore then
  217. list.concat(taicpu.op_reg_ref(op,reg,ref))
  218. else
  219. list.concat(taicpu.op_ref_reg(op,ref,reg));
  220. end;
  221. procedure tcgsparc.handle_reg_const_reg(list:TAsmList;op:Tasmop;src:tregister;a:aint;dst:tregister);
  222. var
  223. tmpreg : tregister;
  224. begin
  225. if (a<simm13lo) or
  226. (a>simm13hi) then
  227. begin
  228. tmpreg:=GetIntRegister(list,OS_INT);
  229. a_load_const_reg(list,OS_INT,a,tmpreg);
  230. list.concat(taicpu.op_reg_reg_reg(op,src,tmpreg,dst));
  231. end
  232. else
  233. list.concat(taicpu.op_reg_const_reg(op,src,a,dst));
  234. end;
  235. {****************************************************************************
  236. Assembler code
  237. ****************************************************************************}
  238. procedure Tcgsparc.init_register_allocators;
  239. begin
  240. inherited init_register_allocators;
  241. if (cs_create_pic in aktmoduleswitches) and
  242. (pi_needs_got in current_procinfo.flags) then
  243. begin
  244. current_procinfo.got:=NR_L7;
  245. rg[R_INTREGISTER]:=Trgcpu.create(R_INTREGISTER,R_SUBD,
  246. [RS_O0,RS_O1,RS_O2,RS_O3,RS_O4,RS_O5,
  247. RS_L0,RS_L1,RS_L2,RS_L3,RS_L4,RS_L5,RS_L6],
  248. first_int_imreg,[]);
  249. end
  250. else
  251. rg[R_INTREGISTER]:=Trgcpu.create(R_INTREGISTER,R_SUBD,
  252. [RS_O0,RS_O1,RS_O2,RS_O3,RS_O4,RS_O5,
  253. RS_L0,RS_L1,RS_L2,RS_L3,RS_L4,RS_L5,RS_L6,RS_L7],
  254. first_int_imreg,[]);
  255. rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBFS,
  256. [RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7,
  257. RS_F8,RS_F9,RS_F10,RS_F11,RS_F12,RS_F13,RS_F14,RS_F15,
  258. RS_F16,RS_F17,RS_F18,RS_F19,RS_F20,RS_F21,RS_F22,RS_F23,
  259. RS_F24,RS_F25,RS_F26,RS_F27,RS_F28,RS_F29,RS_F30,RS_F31],
  260. first_fpu_imreg,[]);
  261. { needs at least one element for rgobj not to crash }
  262. rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBNONE,
  263. [RS_L0],first_mm_imreg,[]);
  264. end;
  265. procedure Tcgsparc.done_register_allocators;
  266. begin
  267. rg[R_INTREGISTER].free;
  268. rg[R_FPUREGISTER].free;
  269. inherited done_register_allocators;
  270. end;
  271. function tcgsparc.getfpuregister(list:TAsmList;size:Tcgsize):Tregister;
  272. begin
  273. if size=OS_F64 then
  274. result:=rg[R_FPUREGISTER].getregister(list,R_SUBFD)
  275. else
  276. result:=rg[R_FPUREGISTER].getregister(list,R_SUBFS);
  277. end;
  278. procedure TCgSparc.a_param_const(list:TAsmList;size:tcgsize;a:aint;const paraloc:TCGPara);
  279. var
  280. Ref:TReference;
  281. begin
  282. paraloc.check_simple_location;
  283. case paraloc.location^.loc of
  284. LOC_REGISTER,LOC_CREGISTER:
  285. a_load_const_reg(list,size,a,paraloc.location^.register);
  286. LOC_REFERENCE:
  287. begin
  288. { Code conventions need the parameters being allocated in %o6+92 }
  289. with paraloc.location^.Reference do
  290. begin
  291. if (Index=NR_SP) and (Offset<Target_info.first_parm_offset) then
  292. InternalError(2002081104);
  293. reference_reset_base(ref,index,offset);
  294. end;
  295. a_load_const_ref(list,size,a,ref);
  296. end;
  297. else
  298. InternalError(2002122200);
  299. end;
  300. end;
  301. procedure TCgSparc.a_param_ref(list:TAsmList;sz:TCgSize;const r:TReference;const paraloc:TCGPara);
  302. var
  303. ref: treference;
  304. tmpreg:TRegister;
  305. begin
  306. paraloc.check_simple_location;
  307. with paraloc.location^ do
  308. begin
  309. case loc of
  310. LOC_REGISTER,LOC_CREGISTER :
  311. a_load_ref_reg(list,sz,sz,r,Register);
  312. LOC_REFERENCE:
  313. begin
  314. { Code conventions need the parameters being allocated in %o6+92 }
  315. with Reference do
  316. begin
  317. if (Index=NR_SP) and (Offset<Target_info.first_parm_offset) then
  318. InternalError(2002081104);
  319. reference_reset_base(ref,index,offset);
  320. end;
  321. tmpreg:=GetIntRegister(list,OS_INT);
  322. a_load_ref_reg(list,sz,sz,r,tmpreg);
  323. a_load_reg_ref(list,sz,sz,tmpreg,ref);
  324. end;
  325. else
  326. internalerror(2002081103);
  327. end;
  328. end;
  329. end;
  330. procedure TCgSparc.a_paramaddr_ref(list:TAsmList;const r:TReference;const paraloc:TCGPara);
  331. var
  332. Ref:TReference;
  333. TmpReg:TRegister;
  334. begin
  335. paraloc.check_simple_location;
  336. with paraloc.location^ do
  337. begin
  338. case loc of
  339. LOC_REGISTER,LOC_CREGISTER:
  340. a_loadaddr_ref_reg(list,r,register);
  341. LOC_REFERENCE:
  342. begin
  343. reference_reset(ref);
  344. ref.base := reference.index;
  345. ref.offset := reference.offset;
  346. tmpreg:=GetAddressRegister(list);
  347. a_loadaddr_ref_reg(list,r,tmpreg);
  348. a_load_reg_ref(list,OS_ADDR,OS_ADDR,tmpreg,ref);
  349. end;
  350. else
  351. internalerror(2002080701);
  352. end;
  353. end;
  354. end;
  355. procedure tcgsparc.a_paramfpu_ref(list : TAsmList;size : tcgsize;const ref : treference;const paraloc : TCGPara);
  356. var
  357. href,href2 : treference;
  358. hloc : pcgparalocation;
  359. begin
  360. href:=ref;
  361. hloc:=paraloc.location;
  362. while assigned(hloc) do
  363. begin
  364. case hloc^.loc of
  365. LOC_REGISTER :
  366. a_load_ref_reg(list,hloc^.size,hloc^.size,href,hloc^.register);
  367. LOC_REFERENCE :
  368. begin
  369. reference_reset_base(href2,hloc^.reference.index,hloc^.reference.offset);
  370. a_load_ref_ref(list,hloc^.size,hloc^.size,href,href2);
  371. end;
  372. else
  373. internalerror(200408241);
  374. end;
  375. inc(href.offset,tcgsize2size[hloc^.size]);
  376. hloc:=hloc^.next;
  377. end;
  378. end;
  379. procedure tcgsparc.a_paramfpu_reg(list : TAsmList;size : tcgsize;const r : tregister;const paraloc : TCGPara);
  380. var
  381. href : treference;
  382. begin
  383. tg.GetTemp(list,TCGSize2Size[size],tt_normal,href);
  384. a_loadfpu_reg_ref(list,size,r,href);
  385. a_paramfpu_ref(list,size,href,paraloc);
  386. tg.Ungettemp(list,href);
  387. end;
  388. procedure TCgSparc.a_call_name(list:TAsmList;const s:string);
  389. begin
  390. list.concat(taicpu.op_sym(A_CALL,current_asmdata.RefAsmSymbol(s)));
  391. { Delay slot }
  392. list.concat(taicpu.op_none(A_NOP));
  393. end;
  394. procedure TCgSparc.a_call_reg(list:TAsmList;Reg:TRegister);
  395. begin
  396. list.concat(taicpu.op_reg(A_CALL,reg));
  397. { Delay slot }
  398. list.concat(taicpu.op_none(A_NOP));
  399. end;
  400. {********************** load instructions ********************}
  401. procedure TCgSparc.a_load_const_reg(list : TAsmList;size : TCGSize;a : aint;reg : TRegister);
  402. begin
  403. { we don't use the set instruction here because it could be evalutated to two
  404. instructions which would cause problems with the delay slot (FK) }
  405. if (a=0) then
  406. list.concat(taicpu.op_reg(A_CLR,reg))
  407. { sethi allows to set the upper 22 bit, so we'll take full advantage of it }
  408. else if (a and aint($1fff))=0 then
  409. list.concat(taicpu.op_const_reg(A_SETHI,a shr 10,reg))
  410. else if (a>=simm13lo) and (a<=simm13hi) then
  411. list.concat(taicpu.op_const_reg(A_MOV,a,reg))
  412. else
  413. begin
  414. list.concat(taicpu.op_const_reg(A_SETHI,a shr 10,reg));
  415. list.concat(taicpu.op_reg_const_reg(A_OR,reg,a and aint($3ff),reg));
  416. end;
  417. end;
  418. procedure TCgSparc.a_load_const_ref(list : TAsmList;size : tcgsize;a : aint;const ref : TReference);
  419. begin
  420. if a=0 then
  421. a_load_reg_ref(list,size,size,NR_G0,ref)
  422. else
  423. inherited a_load_const_ref(list,size,a,ref);
  424. end;
  425. procedure TCgSparc.a_load_reg_ref(list:TAsmList;FromSize,ToSize:TCGSize;reg:tregister;const Ref:TReference);
  426. var
  427. op : tasmop;
  428. begin
  429. if (TCGSize2Size[fromsize] >= TCGSize2Size[tosize]) then
  430. fromsize := tosize;
  431. case fromsize of
  432. { signed integer registers }
  433. OS_8,
  434. OS_S8:
  435. Op:=A_STB;
  436. OS_16,
  437. OS_S16:
  438. Op:=A_STH;
  439. OS_32,
  440. OS_S32:
  441. Op:=A_ST;
  442. else
  443. InternalError(2002122100);
  444. end;
  445. handle_load_store(list,true,op,reg,ref);
  446. end;
  447. procedure TCgSparc.a_load_ref_reg(list:TAsmList;FromSize,ToSize:TCgSize;const ref:TReference;reg:tregister);
  448. var
  449. op : tasmop;
  450. begin
  451. if (TCGSize2Size[fromsize] >= TCGSize2Size[tosize]) then
  452. fromsize := tosize;
  453. case fromsize of
  454. OS_S8:
  455. Op:=A_LDSB;{Load Signed Byte}
  456. OS_8:
  457. Op:=A_LDUB;{Load Unsigned Byte}
  458. OS_S16:
  459. Op:=A_LDSH;{Load Signed Halfword}
  460. OS_16:
  461. Op:=A_LDUH;{Load Unsigned Halfword}
  462. OS_S32,
  463. OS_32:
  464. Op:=A_LD;{Load Word}
  465. OS_S64,
  466. OS_64:
  467. Op:=A_LDD;{Load a Long Word}
  468. else
  469. InternalError(2002122101);
  470. end;
  471. handle_load_store(list,false,op,reg,ref);
  472. end;
  473. procedure TCgSparc.a_load_reg_reg(list:TAsmList;fromsize,tosize:tcgsize;reg1,reg2:tregister);
  474. var
  475. instr : taicpu;
  476. begin
  477. if (tcgsize2size[tosize]<tcgsize2size[fromsize]) or
  478. (
  479. (tcgsize2size[tosize] = tcgsize2size[fromsize]) and
  480. (tosize <> fromsize) and
  481. not(fromsize in [OS_32,OS_S32])
  482. ) then
  483. begin
  484. case tosize of
  485. OS_8 :
  486. a_op_const_reg_reg(list,OP_AND,tosize,$ff,reg1,reg2);
  487. OS_16 :
  488. a_op_const_reg_reg(list,OP_AND,tosize,$ffff,reg1,reg2);
  489. OS_32,
  490. OS_S32 :
  491. begin
  492. instr:=taicpu.op_reg_reg(A_MOV,reg1,reg2);
  493. list.Concat(instr);
  494. { Notify the register allocator that we have written a move instruction so
  495. it can try to eliminate it. }
  496. add_move_instruction(instr);
  497. end;
  498. OS_S8 :
  499. begin
  500. list.concat(taicpu.op_reg_const_reg(A_SLL,reg1,24,reg2));
  501. list.concat(taicpu.op_reg_const_reg(A_SRA,reg2,24,reg2));
  502. end;
  503. OS_S16 :
  504. begin
  505. list.concat(taicpu.op_reg_const_reg(A_SLL,reg1,16,reg2));
  506. list.concat(taicpu.op_reg_const_reg(A_SRA,reg2,16,reg2));
  507. end;
  508. else
  509. internalerror(2002090901);
  510. end;
  511. end
  512. else
  513. begin
  514. if reg1<>reg2 then
  515. begin
  516. { same size, only a register mov required }
  517. instr:=taicpu.op_reg_reg(A_MOV,reg1,reg2);
  518. list.Concat(instr);
  519. { Notify the register allocator that we have written a move instruction so
  520. it can try to eliminate it. }
  521. add_move_instruction(instr);
  522. end;
  523. end;
  524. end;
  525. procedure TCgSparc.a_loadaddr_ref_reg(list : TAsmList;const ref : TReference;r : tregister);
  526. var
  527. tmpref,href : treference;
  528. hreg,tmpreg : tregister;
  529. begin
  530. href:=ref;
  531. if (href.base=NR_NO) and (href.index<>NR_NO) then
  532. internalerror(200306171);
  533. if (cs_create_pic in aktmoduleswitches) and
  534. assigned(href.symbol) then
  535. begin
  536. tmpreg:=GetIntRegister(list,OS_ADDR);
  537. reference_reset(tmpref);
  538. tmpref.symbol:=href.symbol;
  539. tmpref.refaddr:=addr_pic;
  540. if not(pi_needs_got in current_procinfo.flags) then
  541. internalerror(200501161);
  542. tmpref.base:=current_procinfo.got;
  543. list.concat(taicpu.op_ref_reg(A_LD,tmpref,tmpreg));
  544. href.symbol:=nil;
  545. if (href.index<>NR_NO) then
  546. begin
  547. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,href.index,tmpreg));
  548. href.index:=tmpreg;
  549. end
  550. else
  551. begin
  552. if href.base<>NR_NO then
  553. href.index:=tmpreg
  554. else
  555. href.base:=tmpreg;
  556. end;
  557. end;
  558. { At least big offset (need SETHI), maybe base and maybe index }
  559. if assigned(href.symbol) or
  560. (href.offset<simm13lo) or
  561. (href.offset>simm13hi) then
  562. begin
  563. hreg:=GetAddressRegister(list);
  564. reference_reset(tmpref);
  565. tmpref.symbol := href.symbol;
  566. tmpref.offset := href.offset;
  567. tmpref.refaddr := addr_hi;
  568. list.concat(taicpu.op_ref_reg(A_SETHI,tmpref,hreg));
  569. { Only the low part is left }
  570. tmpref.refaddr:=addr_lo;
  571. list.concat(taicpu.op_reg_ref_reg(A_OR,hreg,tmpref,hreg));
  572. if href.base<>NR_NO then
  573. begin
  574. if href.index<>NR_NO then
  575. begin
  576. list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,href.base,hreg));
  577. list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,href.index,r));
  578. end
  579. else
  580. list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,href.base,r));
  581. end
  582. else
  583. begin
  584. if hreg<>r then
  585. a_load_reg_reg(list,OS_ADDR,OS_ADDR,hreg,r);
  586. end;
  587. end
  588. else
  589. { At least small offset, maybe base and maybe index }
  590. if href.offset<>0 then
  591. begin
  592. if href.base<>NR_NO then
  593. begin
  594. if href.index<>NR_NO then
  595. begin
  596. hreg:=GetAddressRegister(list);
  597. list.concat(taicpu.op_reg_const_reg(A_ADD,href.base,href.offset,hreg));
  598. list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,href.index,r));
  599. end
  600. else
  601. list.concat(taicpu.op_reg_const_reg(A_ADD,href.base,href.offset,r));
  602. end
  603. else
  604. list.concat(taicpu.op_const_reg(A_MOV,href.offset,r));
  605. end
  606. else
  607. { Both base and index }
  608. if href.index<>NR_NO then
  609. list.concat(taicpu.op_reg_reg_reg(A_ADD,href.base,href.index,r))
  610. else
  611. { Only base }
  612. if href.base<>NR_NO then
  613. a_load_reg_reg(list,OS_ADDR,OS_ADDR,href.base,r)
  614. else
  615. { only offset, can be generated by absolute }
  616. a_load_const_reg(list,OS_ADDR,href.offset,r);
  617. end;
  618. procedure TCgSparc.a_loadfpu_reg_reg(list:TAsmList;size:tcgsize;reg1, reg2:tregister);
  619. const
  620. FpuMovInstr : Array[OS_F32..OS_F64] of TAsmOp =
  621. (A_FMOVS,A_FMOVD);
  622. var
  623. instr : taicpu;
  624. begin
  625. if reg1<>reg2 then
  626. begin
  627. instr:=taicpu.op_reg_reg(fpumovinstr[size],reg1,reg2);
  628. list.Concat(instr);
  629. { Notify the register allocator that we have written a move instruction so
  630. it can try to eliminate it. }
  631. add_move_instruction(instr);
  632. end;
  633. end;
  634. procedure TCgSparc.a_loadfpu_ref_reg(list:TAsmList;size:tcgsize;const ref:TReference;reg:tregister);
  635. const
  636. FpuLoadInstr : Array[OS_F32..OS_F64] of TAsmOp =
  637. (A_LDF,A_LDDF);
  638. begin
  639. handle_load_store(list,false,fpuloadinstr[size],reg,ref);
  640. end;
  641. procedure TCgSparc.a_loadfpu_reg_ref(list:TAsmList;size:tcgsize;reg:tregister;const ref:TReference);
  642. const
  643. FpuLoadInstr : Array[OS_F32..OS_F64] of TAsmOp =
  644. (A_STF,A_STDF);
  645. begin
  646. handle_load_store(list,true,fpuloadinstr[size],reg,ref);
  647. end;
  648. procedure TCgSparc.a_op_const_reg(list:TAsmList;Op:TOpCG;size:tcgsize;a:aint;reg:TRegister);
  649. begin
  650. if Op in [OP_NEG,OP_NOT] then
  651. internalerror(200306011);
  652. if (a=0) then
  653. list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],reg,NR_G0,reg))
  654. else
  655. handle_reg_const_reg(list,TOpCG2AsmOp[op],reg,a,reg);
  656. end;
  657. procedure TCgSparc.a_op_reg_reg(list:TAsmList;Op:TOpCG;size:TCGSize;src, dst:TRegister);
  658. var
  659. a : aint;
  660. begin
  661. Case Op of
  662. OP_NEG :
  663. list.concat(taicpu.op_reg_reg(TOpCG2AsmOp[op],src,dst));
  664. OP_NOT :
  665. begin
  666. case size of
  667. OS_8 :
  668. a:=aint($ffffff00);
  669. OS_16 :
  670. a:=aint($ffff0000);
  671. else
  672. a:=0;
  673. end;
  674. handle_reg_const_reg(list,A_XNOR,src,a,dst);
  675. end;
  676. else
  677. list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],dst,src,dst));
  678. end;
  679. end;
  680. procedure TCgSparc.a_op_const_reg_reg(list:TAsmList;op:TOpCg;size:tcgsize;a:aint;src, dst:tregister);
  681. var
  682. power : longInt;
  683. begin
  684. case op of
  685. OP_MUL,
  686. OP_IMUL:
  687. begin
  688. if ispowerof2(a,power) then
  689. begin
  690. { can be done with a shift }
  691. inherited a_op_const_reg_reg(list,op,size,a,src,dst);
  692. exit;
  693. end;
  694. end;
  695. OP_SUB,
  696. OP_ADD :
  697. begin
  698. if (a=0) then
  699. begin
  700. a_load_reg_reg(list,size,size,src,dst);
  701. exit;
  702. end;
  703. end;
  704. end;
  705. handle_reg_const_reg(list,TOpCG2AsmOp[op],src,a,dst);
  706. end;
  707. procedure TCgSparc.a_op_reg_reg_reg(list:TAsmList;op:TOpCg;size:tcgsize;src1, src2, dst:tregister);
  708. begin
  709. list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],src2,src1,dst));
  710. end;
  711. procedure tcgsparc.a_op_const_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; a: aint; src, dst: tregister;setflags : boolean;var ovloc : tlocation);
  712. var
  713. power : longInt;
  714. tmpreg1,tmpreg2 : tregister;
  715. begin
  716. ovloc.loc:=LOC_VOID;
  717. case op of
  718. OP_SUB,
  719. OP_ADD :
  720. begin
  721. if (a=0) then
  722. begin
  723. a_load_reg_reg(list,size,size,src,dst);
  724. exit;
  725. end;
  726. end;
  727. end;
  728. if setflags then
  729. begin
  730. handle_reg_const_reg(list,TOpCG2AsmOpWithFlags[op],src,a,dst);
  731. case op of
  732. OP_MUL:
  733. begin
  734. tmpreg1:=GetIntRegister(list,OS_INT);
  735. list.concat(taicpu.op_reg_reg(A_MOV,NR_Y,tmpreg1));
  736. list.concat(taicpu.op_reg_reg(A_CMP,NR_G0,tmpreg1));
  737. ovloc.loc:=LOC_FLAGS;
  738. ovloc.resflags:=F_NE;
  739. end;
  740. OP_IMUL:
  741. begin
  742. tmpreg1:=GetIntRegister(list,OS_INT);
  743. tmpreg2:=GetIntRegister(list,OS_INT);
  744. list.concat(taicpu.op_reg_reg(A_MOV,NR_Y,tmpreg1));
  745. list.concat(taicpu.op_reg_const_reg(A_SRL,dst,31,tmpreg2));
  746. list.concat(taicpu.op_reg_reg(A_CMP,tmpreg1,tmpreg2));
  747. ovloc.loc:=LOC_FLAGS;
  748. ovloc.resflags:=F_NE;
  749. end;
  750. end;
  751. end
  752. else
  753. handle_reg_const_reg(list,TOpCG2AsmOp[op],src,a,dst)
  754. end;
  755. procedure tcgsparc.a_op_reg_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister;setflags : boolean;var ovloc : tlocation);
  756. var
  757. tmpreg1,tmpreg2 : tregister;
  758. begin
  759. ovloc.loc:=LOC_VOID;
  760. if setflags then
  761. begin
  762. list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOpWithFlags[op],src2,src1,dst));
  763. case op of
  764. OP_MUL:
  765. begin
  766. tmpreg1:=GetIntRegister(list,OS_INT);
  767. list.concat(taicpu.op_reg_reg(A_MOV,NR_Y,tmpreg1));
  768. list.concat(taicpu.op_reg_reg(A_CMP,NR_G0,tmpreg1));
  769. ovloc.loc:=LOC_FLAGS;
  770. ovloc.resflags:=F_NE;
  771. end;
  772. OP_IMUL:
  773. begin
  774. tmpreg1:=GetIntRegister(list,OS_INT);
  775. tmpreg2:=GetIntRegister(list,OS_INT);
  776. list.concat(taicpu.op_reg_reg(A_MOV,NR_Y,tmpreg1));
  777. list.concat(taicpu.op_reg_const_reg(A_SRL,dst,31,tmpreg2));
  778. list.concat(taicpu.op_reg_reg(A_CMP,tmpreg1,tmpreg2));
  779. ovloc.loc:=LOC_FLAGS;
  780. ovloc.resflags:=F_NE;
  781. end;
  782. end;
  783. end
  784. else
  785. list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],src2,src1,dst))
  786. end;
  787. {*************** compare instructructions ****************}
  788. procedure TCgSparc.a_cmp_const_reg_label(list:TAsmList;size:tcgsize;cmp_op:topcmp;a:aint;reg:tregister;l:tasmlabel);
  789. begin
  790. if (a=0) then
  791. list.concat(taicpu.op_reg_reg_reg(A_SUBcc,reg,NR_G0,NR_G0))
  792. else
  793. handle_reg_const_reg(list,A_SUBcc,reg,a,NR_G0);
  794. a_jmp_cond(list,cmp_op,l);
  795. end;
  796. procedure TCgSparc.a_cmp_reg_reg_label(list:TAsmList;size:tcgsize;cmp_op:topcmp;reg1,reg2:tregister;l:tasmlabel);
  797. begin
  798. list.concat(taicpu.op_reg_reg_reg(A_SUBcc,reg2,reg1,NR_G0));
  799. a_jmp_cond(list,cmp_op,l);
  800. end;
  801. procedure TCgSparc.a_jmp_always(List:TAsmList;l:TAsmLabel);
  802. begin
  803. List.Concat(TAiCpu.op_sym(A_BA,current_asmdata.RefAsmSymbol(l.name)));
  804. { Delay slot }
  805. list.Concat(TAiCpu.Op_none(A_NOP));
  806. end;
  807. procedure tcgsparc.a_jmp_name(list : TAsmList;const s : string);
  808. begin
  809. List.Concat(TAiCpu.op_sym(A_BA,current_asmdata.RefAsmSymbol(s)));
  810. { Delay slot }
  811. list.Concat(TAiCpu.Op_none(A_NOP));
  812. end;
  813. procedure TCgSparc.a_jmp_cond(list:TAsmList;cond:TOpCmp;l:TAsmLabel);
  814. var
  815. ai:TAiCpu;
  816. begin
  817. ai:=TAiCpu.Op_sym(A_Bxx,l);
  818. ai.SetCondition(TOpCmp2AsmCond[cond]);
  819. list.Concat(ai);
  820. { Delay slot }
  821. list.Concat(TAiCpu.Op_none(A_NOP));
  822. end;
  823. procedure TCgSparc.a_jmp_flags(list:TAsmList;const f:TResFlags;l:tasmlabel);
  824. var
  825. ai : taicpu;
  826. op : tasmop;
  827. begin
  828. if f in [F_FE,F_FNE,F_FG,F_FL,F_FGE,F_FLE] then
  829. op:=A_FBxx
  830. else
  831. op:=A_Bxx;
  832. ai := Taicpu.op_sym(op,l);
  833. ai.SetCondition(flags_to_cond(f));
  834. list.Concat(ai);
  835. { Delay slot }
  836. list.Concat(TAiCpu.Op_none(A_NOP));
  837. end;
  838. procedure TCgSparc.g_flags2reg(list:TAsmList;Size:TCgSize;const f:tresflags;reg:TRegister);
  839. var
  840. hl : tasmlabel;
  841. begin
  842. current_asmdata.getjumplabel(hl);
  843. a_load_const_reg(list,size,1,reg);
  844. a_jmp_flags(list,f,hl);
  845. a_load_const_reg(list,size,0,reg);
  846. a_label(list,hl);
  847. end;
  848. procedure tcgsparc.g_overflowCheck(List:TAsmList;const Loc:TLocation;def:TDef);
  849. var
  850. l : tlocation;
  851. begin
  852. l.loc:=LOC_VOID;
  853. g_overflowCheck_loc(list,loc,def,l);
  854. end;
  855. procedure TCgSparc.g_overflowCheck_loc(List:TAsmList;const Loc:TLocation;def:TDef;ovloc : tlocation);
  856. var
  857. hl : tasmlabel;
  858. ai:TAiCpu;
  859. hflags : tresflags;
  860. begin
  861. if not(cs_check_overflow in aktlocalswitches) then
  862. exit;
  863. current_asmdata.getjumplabel(hl);
  864. case ovloc.loc of
  865. LOC_VOID:
  866. begin
  867. if not((def.deftype=pointerdef) or
  868. ((def.deftype=orddef) and
  869. (torddef(def).typ in [u64bit,u16bit,u32bit,u8bit,uchar,bool8bit,bool16bit,bool32bit]))) then
  870. begin
  871. ai:=TAiCpu.Op_sym(A_Bxx,hl);
  872. ai.SetCondition(C_NO);
  873. list.Concat(ai);
  874. { Delay slot }
  875. list.Concat(TAiCpu.Op_none(A_NOP));
  876. end
  877. else
  878. a_jmp_cond(list,OC_AE,hl);
  879. end;
  880. LOC_FLAGS:
  881. begin
  882. hflags:=ovloc.resflags;
  883. inverse_flags(hflags);
  884. cg.a_jmp_flags(list,hflags,hl);
  885. end;
  886. else
  887. internalerror(200409281);
  888. end;
  889. a_call_name(list,'FPC_OVERFLOW');
  890. a_label(list,hl);
  891. end;
  892. { *********** entry/exit code and address loading ************ }
  893. procedure TCgSparc.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
  894. begin
  895. if nostackframe then
  896. exit;
  897. { Althogh the SPARC architecture require only word alignment, software
  898. convention and the operating system require every stack frame to be double word
  899. aligned }
  900. LocalSize:=align(LocalSize,8);
  901. { Execute the SAVE instruction to get a new register window and create a new
  902. stack frame. In the "SAVE %i6,size,%i6" the first %i6 is related to the state
  903. before execution of the SAVE instrucion so it is the caller %i6, when the %i6
  904. after execution of that instruction is the called function stack pointer}
  905. { constant can be 13 bit signed, since it's negative, size can be max. 4096 }
  906. if LocalSize>4096 then
  907. begin
  908. a_load_const_reg(list,OS_ADDR,-LocalSize,NR_G1);
  909. list.concat(Taicpu.Op_reg_reg_reg(A_SAVE,NR_STACK_POINTER_REG,NR_G1,NR_STACK_POINTER_REG));
  910. end
  911. else
  912. list.concat(Taicpu.Op_reg_const_reg(A_SAVE,NR_STACK_POINTER_REG,-LocalSize,NR_STACK_POINTER_REG));
  913. if (cs_create_pic in aktmoduleswitches) and
  914. (pi_needs_got in current_procinfo.flags) then
  915. begin
  916. current_procinfo.got:=NR_L7;
  917. end;
  918. end;
  919. procedure TCgSparc.g_restore_standard_registers(list:TAsmList);
  920. begin
  921. { The sparc port uses the sparc standard calling convetions so this function has no used }
  922. end;
  923. procedure TCgSparc.g_proc_exit(list : TAsmList;parasize:longint;nostackframe:boolean);
  924. var
  925. hr : treference;
  926. begin
  927. if paramanager.ret_in_param(current_procinfo.procdef.returndef,current_procinfo.procdef.proccalloption) then
  928. begin
  929. reference_reset(hr);
  930. hr.offset:=12;
  931. hr.refaddr:=addr_full;
  932. if nostackframe then
  933. begin
  934. hr.base:=NR_O7;
  935. list.concat(taicpu.op_ref_reg(A_JMPL,hr,NR_G0));
  936. list.concat(Taicpu.op_none(A_NOP))
  937. end
  938. else
  939. begin
  940. { We use trivial restore in the delay slot of the JMPL instruction, as we
  941. already set result onto %i0 }
  942. hr.base:=NR_I7;
  943. list.concat(taicpu.op_ref_reg(A_JMPL,hr,NR_G0));
  944. list.concat(Taicpu.op_none(A_RESTORE));
  945. end;
  946. end
  947. else
  948. begin
  949. if nostackframe then
  950. begin
  951. { Here we need to use RETL instead of RET so it uses %o7 }
  952. list.concat(Taicpu.op_none(A_RETL));
  953. list.concat(Taicpu.op_none(A_NOP))
  954. end
  955. else
  956. begin
  957. { We use trivial restore in the delay slot of the JMPL instruction, as we
  958. already set result onto %i0 }
  959. list.concat(Taicpu.op_none(A_RET));
  960. list.concat(Taicpu.op_none(A_RESTORE));
  961. end;
  962. end;
  963. end;
  964. procedure TCgSparc.g_save_standard_registers(list : TAsmList);
  965. begin
  966. { The sparc port uses the sparc standard calling convetions so this function has no used }
  967. end;
  968. { ************* concatcopy ************ }
  969. procedure tcgsparc.g_concatcopy_move(list : TAsmList;const source,dest : treference;len : aint);
  970. var
  971. paraloc1,paraloc2,paraloc3 : TCGPara;
  972. begin
  973. paraloc1.init;
  974. paraloc2.init;
  975. paraloc3.init;
  976. paramanager.getintparaloc(pocall_default,1,paraloc1);
  977. paramanager.getintparaloc(pocall_default,2,paraloc2);
  978. paramanager.getintparaloc(pocall_default,3,paraloc3);
  979. paramanager.allocparaloc(list,paraloc3);
  980. a_param_const(list,OS_INT,len,paraloc3);
  981. paramanager.allocparaloc(list,paraloc2);
  982. a_paramaddr_ref(list,dest,paraloc2);
  983. paramanager.allocparaloc(list,paraloc2);
  984. a_paramaddr_ref(list,source,paraloc1);
  985. paramanager.freeparaloc(list,paraloc3);
  986. paramanager.freeparaloc(list,paraloc2);
  987. paramanager.freeparaloc(list,paraloc1);
  988. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  989. alloccpuregisters(list,R_FPUREGISTER,paramanager.get_volatile_registers_fpu(pocall_default));
  990. a_call_name(list,'FPC_MOVE');
  991. dealloccpuregisters(list,R_FPUREGISTER,paramanager.get_volatile_registers_fpu(pocall_default));
  992. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  993. paraloc3.done;
  994. paraloc2.done;
  995. paraloc1.done;
  996. end;
  997. procedure TCgSparc.g_concatcopy(list:TAsmList;const source,dest:treference;len:aint);
  998. var
  999. tmpreg1,
  1000. hreg,
  1001. countreg: TRegister;
  1002. src, dst: TReference;
  1003. lab: tasmlabel;
  1004. count, count2: aint;
  1005. begin
  1006. if len>high(longint) then
  1007. internalerror(2002072704);
  1008. { anybody wants to determine a good value here :)? }
  1009. if len>100 then
  1010. g_concatcopy_move(list,source,dest,len)
  1011. else
  1012. begin
  1013. reference_reset(src);
  1014. reference_reset(dst);
  1015. { load the address of source into src.base }
  1016. src.base:=GetAddressRegister(list);
  1017. a_loadaddr_ref_reg(list,source,src.base);
  1018. { load the address of dest into dst.base }
  1019. dst.base:=GetAddressRegister(list);
  1020. a_loadaddr_ref_reg(list,dest,dst.base);
  1021. { generate a loop }
  1022. count:=len div 4;
  1023. if count>4 then
  1024. begin
  1025. { the offsets are zero after the a_loadaddress_ref_reg and just }
  1026. { have to be set to 8. I put an Inc there so debugging may be }
  1027. { easier (should offset be different from zero here, it will be }
  1028. { easy to notice in the generated assembler }
  1029. countreg:=GetIntRegister(list,OS_INT);
  1030. tmpreg1:=GetIntRegister(list,OS_INT);
  1031. a_load_const_reg(list,OS_INT,count,countreg);
  1032. { explicitely allocate R_O0 since it can be used safely here }
  1033. { (for holding date that's being copied) }
  1034. current_asmdata.getjumplabel(lab);
  1035. a_label(list, lab);
  1036. list.concat(taicpu.op_ref_reg(A_LD,src,tmpreg1));
  1037. list.concat(taicpu.op_reg_ref(A_ST,tmpreg1,dst));
  1038. list.concat(taicpu.op_reg_const_reg(A_ADD,src.base,4,src.base));
  1039. list.concat(taicpu.op_reg_const_reg(A_ADD,dst.base,4,dst.base));
  1040. list.concat(taicpu.op_reg_const_reg(A_SUBcc,countreg,1,countreg));
  1041. a_jmp_cond(list,OC_NE,lab);
  1042. list.concat(taicpu.op_none(A_NOP));
  1043. { keep the registers alive }
  1044. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  1045. list.concat(taicpu.op_reg_reg(A_MOV,src.base,src.base));
  1046. list.concat(taicpu.op_reg_reg(A_MOV,dst.base,dst.base));
  1047. len := len mod 4;
  1048. end;
  1049. { unrolled loop }
  1050. count:=len div 4;
  1051. if count>0 then
  1052. begin
  1053. tmpreg1:=GetIntRegister(list,OS_INT);
  1054. for count2 := 1 to count do
  1055. begin
  1056. list.concat(taicpu.op_ref_reg(A_LD,src,tmpreg1));
  1057. list.concat(taicpu.op_reg_ref(A_ST,tmpreg1,dst));
  1058. inc(src.offset,4);
  1059. inc(dst.offset,4);
  1060. end;
  1061. len := len mod 4;
  1062. end;
  1063. if (len and 4) <> 0 then
  1064. begin
  1065. hreg:=GetIntRegister(list,OS_INT);
  1066. a_load_ref_reg(list,OS_32,OS_32,src,hreg);
  1067. a_load_reg_ref(list,OS_32,OS_32,hreg,dst);
  1068. inc(src.offset,4);
  1069. inc(dst.offset,4);
  1070. end;
  1071. { copy the leftovers }
  1072. if (len and 2) <> 0 then
  1073. begin
  1074. hreg:=GetIntRegister(list,OS_INT);
  1075. a_load_ref_reg(list,OS_16,OS_16,src,hreg);
  1076. a_load_reg_ref(list,OS_16,OS_16,hreg,dst);
  1077. inc(src.offset,2);
  1078. inc(dst.offset,2);
  1079. end;
  1080. if (len and 1) <> 0 then
  1081. begin
  1082. hreg:=GetIntRegister(list,OS_INT);
  1083. a_load_ref_reg(list,OS_8,OS_8,src,hreg);
  1084. a_load_reg_ref(list,OS_8,OS_8,hreg,dst);
  1085. end;
  1086. end;
  1087. end;
  1088. procedure tcgsparc.g_concatcopy_unaligned(list : TAsmList;const source,dest : treference;len : aint);
  1089. var
  1090. src, dst: TReference;
  1091. tmpreg1,
  1092. countreg: TRegister;
  1093. i : aint;
  1094. lab: tasmlabel;
  1095. begin
  1096. if len>31 then
  1097. g_concatcopy_move(list,source,dest,len)
  1098. else
  1099. begin
  1100. reference_reset(src);
  1101. reference_reset(dst);
  1102. { load the address of source into src.base }
  1103. src.base:=GetAddressRegister(list);
  1104. a_loadaddr_ref_reg(list,source,src.base);
  1105. { load the address of dest into dst.base }
  1106. dst.base:=GetAddressRegister(list);
  1107. a_loadaddr_ref_reg(list,dest,dst.base);
  1108. { generate a loop }
  1109. if len>4 then
  1110. begin
  1111. { the offsets are zero after the a_loadaddress_ref_reg and just }
  1112. { have to be set to 8. I put an Inc there so debugging may be }
  1113. { easier (should offset be different from zero here, it will be }
  1114. { easy to notice in the generated assembler }
  1115. countreg:=GetIntRegister(list,OS_INT);
  1116. tmpreg1:=GetIntRegister(list,OS_INT);
  1117. a_load_const_reg(list,OS_INT,len,countreg);
  1118. { explicitely allocate R_O0 since it can be used safely here }
  1119. { (for holding date that's being copied) }
  1120. current_asmdata.getjumplabel(lab);
  1121. a_label(list, lab);
  1122. list.concat(taicpu.op_ref_reg(A_LDUB,src,tmpreg1));
  1123. list.concat(taicpu.op_reg_ref(A_STB,tmpreg1,dst));
  1124. list.concat(taicpu.op_reg_const_reg(A_ADD,src.base,1,src.base));
  1125. list.concat(taicpu.op_reg_const_reg(A_ADD,dst.base,1,dst.base));
  1126. list.concat(taicpu.op_reg_const_reg(A_SUBcc,countreg,1,countreg));
  1127. a_jmp_cond(list,OC_NE,lab);
  1128. list.concat(taicpu.op_none(A_NOP));
  1129. { keep the registers alive }
  1130. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  1131. list.concat(taicpu.op_reg_reg(A_MOV,src.base,src.base));
  1132. list.concat(taicpu.op_reg_reg(A_MOV,dst.base,dst.base));
  1133. end
  1134. else
  1135. begin
  1136. { unrolled loop }
  1137. tmpreg1:=GetIntRegister(list,OS_INT);
  1138. for i:=1 to len do
  1139. begin
  1140. list.concat(taicpu.op_ref_reg(A_LDUB,src,tmpreg1));
  1141. list.concat(taicpu.op_reg_ref(A_STB,tmpreg1,dst));
  1142. inc(src.offset);
  1143. inc(dst.offset);
  1144. end;
  1145. end;
  1146. end;
  1147. end;
  1148. procedure tcgsparc.g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);
  1149. var
  1150. make_global : boolean;
  1151. href : treference;
  1152. begin
  1153. if not(procdef.proctypeoption in [potype_function,potype_procedure]) then
  1154. Internalerror(200006137);
  1155. if not assigned(procdef._class) or
  1156. (procdef.procoptions*[po_classmethod, po_staticmethod,
  1157. po_methodpointer, po_interrupt, po_iocheck]<>[]) then
  1158. Internalerror(200006138);
  1159. if procdef.owner.symtabletype<>objectsymtable then
  1160. Internalerror(200109191);
  1161. make_global:=false;
  1162. if (not current_module.is_unit) or
  1163. (procdef.owner.defowner.owner.symtabletype=globalsymtable) then
  1164. make_global:=true;
  1165. if make_global then
  1166. List.concat(Tai_symbol.Createname_global(labelname,AT_FUNCTION,0))
  1167. else
  1168. List.concat(Tai_symbol.Createname(labelname,AT_FUNCTION,0));
  1169. { set param1 interface to self }
  1170. g_adjust_self_value(list,procdef,ioffset);
  1171. if po_virtualmethod in procdef.procoptions then
  1172. begin
  1173. if (procdef.extnumber=$ffff) then
  1174. Internalerror(200006139);
  1175. { mov 0(%rdi),%rax ; load vmt}
  1176. reference_reset_base(href,NR_O0,0);
  1177. cg.a_load_ref_reg(list,OS_ADDR,OS_ADDR,href,NR_L0);
  1178. { jmp *vmtoffs(%eax) ; method offs }
  1179. reference_reset_base(href,NR_L0,procdef._class.vmtmethodoffset(procdef.extnumber));
  1180. list.concat(taicpu.op_ref_reg(A_LD,href,NR_L1));
  1181. list.concat(taicpu.op_reg(A_JMP,NR_L1));
  1182. end
  1183. else
  1184. list.concat(taicpu.op_sym(A_BA,current_asmdata.RefAsmSymbol(procdef.mangledname)));
  1185. { Delay slot }
  1186. list.Concat(TAiCpu.Op_none(A_NOP));
  1187. List.concat(Tai_symbol_end.Createname(labelname));
  1188. end;
  1189. {****************************************************************************
  1190. TCG64Sparc
  1191. ****************************************************************************}
  1192. procedure tcg64sparc.a_load64_reg_ref(list : TAsmList;reg : tregister64;const ref : treference);
  1193. var
  1194. tmpref: treference;
  1195. begin
  1196. { Override this function to prevent loading the reference twice }
  1197. tmpref:=ref;
  1198. cg.a_load_reg_ref(list,OS_32,OS_32,reg.reghi,tmpref);
  1199. inc(tmpref.offset,4);
  1200. cg.a_load_reg_ref(list,OS_32,OS_32,reg.reglo,tmpref);
  1201. end;
  1202. procedure tcg64sparc.a_load64_ref_reg(list : TAsmList;const ref : treference;reg : tregister64);
  1203. var
  1204. tmpref: treference;
  1205. begin
  1206. { Override this function to prevent loading the reference twice }
  1207. tmpref:=ref;
  1208. cg.a_load_ref_reg(list,OS_32,OS_32,tmpref,reg.reghi);
  1209. inc(tmpref.offset,4);
  1210. cg.a_load_ref_reg(list,OS_32,OS_32,tmpref,reg.reglo);
  1211. end;
  1212. procedure tcg64sparc.a_param64_ref(list : TAsmList;const r : treference;const paraloc : tcgpara);
  1213. var
  1214. hreg64 : tregister64;
  1215. begin
  1216. { Override this function to prevent loading the reference twice.
  1217. Use here some extra registers, but those are optimized away by the RA }
  1218. hreg64.reglo:=cg.GetIntRegister(list,OS_32);
  1219. hreg64.reghi:=cg.GetIntRegister(list,OS_32);
  1220. a_load64_ref_reg(list,r,hreg64);
  1221. a_param64_reg(list,hreg64,paraloc);
  1222. end;
  1223. procedure TCg64Sparc.get_64bit_ops(op:TOpCG;var op1,op2:TAsmOp;checkoverflow : boolean);
  1224. begin
  1225. case op of
  1226. OP_ADD :
  1227. begin
  1228. op1:=A_ADDCC;
  1229. if checkoverflow then
  1230. op2:=A_ADDXCC
  1231. else
  1232. op2:=A_ADDX;
  1233. end;
  1234. OP_SUB :
  1235. begin
  1236. op1:=A_SUBCC;
  1237. if checkoverflow then
  1238. op2:=A_SUBXCC
  1239. else
  1240. op2:=A_SUBX;
  1241. end;
  1242. OP_XOR :
  1243. begin
  1244. op1:=A_XOR;
  1245. op2:=A_XOR;
  1246. end;
  1247. OP_OR :
  1248. begin
  1249. op1:=A_OR;
  1250. op2:=A_OR;
  1251. end;
  1252. OP_AND :
  1253. begin
  1254. op1:=A_AND;
  1255. op2:=A_AND;
  1256. end;
  1257. else
  1258. internalerror(200203241);
  1259. end;
  1260. end;
  1261. procedure TCg64Sparc.a_op64_reg_reg(list:TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst:TRegister64);
  1262. var
  1263. op1,op2 : TAsmOp;
  1264. begin
  1265. case op of
  1266. OP_NEG :
  1267. begin
  1268. { Use the simple code: y=0-z }
  1269. list.concat(taicpu.op_reg_reg_reg(A_SUBcc,NR_G0,regsrc.reglo,regdst.reglo));
  1270. list.concat(taicpu.op_reg_reg_reg(A_SUBX,NR_G0,regsrc.reghi,regdst.reghi));
  1271. exit;
  1272. end;
  1273. OP_NOT :
  1274. begin
  1275. list.concat(taicpu.op_reg_reg_reg(A_XNOR,regsrc.reglo,NR_G0,regdst.reglo));
  1276. list.concat(taicpu.op_reg_reg_reg(A_XNOR,regsrc.reghi,NR_G0,regdst.reghi));
  1277. exit;
  1278. end;
  1279. end;
  1280. get_64bit_ops(op,op1,op2,false);
  1281. list.concat(taicpu.op_reg_reg_reg(op1,regdst.reglo,regsrc.reglo,regdst.reglo));
  1282. list.concat(taicpu.op_reg_reg_reg(op2,regdst.reghi,regsrc.reghi,regdst.reghi));
  1283. end;
  1284. procedure TCg64Sparc.a_op64_const_reg(list:TAsmList;op:TOpCG;size : tcgsize;value:int64;regdst:TRegister64);
  1285. var
  1286. op1,op2:TAsmOp;
  1287. begin
  1288. case op of
  1289. OP_NEG,
  1290. OP_NOT :
  1291. internalerror(200306017);
  1292. end;
  1293. get_64bit_ops(op,op1,op2,false);
  1294. tcgsparc(cg).handle_reg_const_reg(list,op1,regdst.reglo,aint(lo(value)),regdst.reglo);
  1295. tcgsparc(cg).handle_reg_const_reg(list,op2,regdst.reghi,aint(hi(value)),regdst.reghi);
  1296. end;
  1297. procedure tcg64sparc.a_op64_const_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;value : int64; regsrc,regdst : tregister64);
  1298. var
  1299. l : tlocation;
  1300. begin
  1301. a_op64_const_reg_reg_checkoverflow(list,op,size,value,regsrc,regdst,false,l);
  1302. end;
  1303. procedure tcg64sparc.a_op64_reg_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64);
  1304. var
  1305. l : tlocation;
  1306. begin
  1307. a_op64_reg_reg_reg_checkoverflow(list,op,size,regsrc1,regsrc2,regdst,false,l);
  1308. end;
  1309. procedure tcg64sparc.a_op64_const_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64;setflags : boolean;var ovloc : tlocation);
  1310. var
  1311. op1,op2:TAsmOp;
  1312. begin
  1313. case op of
  1314. OP_NEG,
  1315. OP_NOT :
  1316. internalerror(200306017);
  1317. end;
  1318. get_64bit_ops(op,op1,op2,setflags);
  1319. tcgsparc(cg).handle_reg_const_reg(list,op1,regsrc.reglo,aint(lo(value)),regdst.reglo);
  1320. tcgsparc(cg).handle_reg_const_reg(list,op2,regsrc.reghi,aint(hi(value)),regdst.reghi);
  1321. end;
  1322. procedure tcg64sparc.a_op64_reg_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64;setflags : boolean;var ovloc : tlocation);
  1323. var
  1324. op1,op2:TAsmOp;
  1325. begin
  1326. case op of
  1327. OP_NEG,
  1328. OP_NOT :
  1329. internalerror(200306017);
  1330. end;
  1331. get_64bit_ops(op,op1,op2,setflags);
  1332. list.concat(taicpu.op_reg_reg_reg(op1,regsrc2.reglo,regsrc1.reglo,regdst.reglo));
  1333. list.concat(taicpu.op_reg_reg_reg(op2,regsrc2.reghi,regsrc1.reghi,regdst.reghi));
  1334. end;
  1335. begin
  1336. cg:=TCgSparc.Create;
  1337. cg64:=TCg64Sparc.Create;
  1338. end.