aasmcpu.pas 97 KB

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  1. {
  2. Copyright (c) 2003 by Florian Klaempfl
  3. Contains the assembler object for the ARM
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit aasmcpu;
  18. {$i fpcdefs.inc}
  19. interface
  20. uses
  21. globtype,globals,verbose,
  22. aasmbase,aasmtai,aasmdata,aasmsym,
  23. ogbase,
  24. symtype,
  25. cpubase,cpuinfo,cgbase,cgutils;
  26. const
  27. { "mov reg,reg" source operand number }
  28. O_MOV_SOURCE = 1;
  29. { "mov reg,reg" source operand number }
  30. O_MOV_DEST = 0;
  31. { Operand types }
  32. OT_NONE = $00000000;
  33. OT_BITS8 = $00000001; { size, and other attributes, of the operand }
  34. OT_BITS16 = $00000002;
  35. OT_BITS32 = $00000004;
  36. OT_BITS64 = $00000008; { FPU only }
  37. OT_BITS80 = $00000010;
  38. OT_FAR = $00000020; { this means 16:16 or 16:32, like in CALL/JMP }
  39. OT_NEAR = $00000040;
  40. OT_SHORT = $00000080;
  41. OT_BITSTINY = $00000100; { fpu constant }
  42. OT_BITSSHIFTER =
  43. $00000200;
  44. OT_SIZE_MASK = $000003FF; { all the size attributes }
  45. OT_NON_SIZE = longint(not OT_SIZE_MASK);
  46. OT_SIGNED = $00000100; { the operand need to be signed -128-127 }
  47. OT_TO = $00000200; { operand is followed by a colon }
  48. { reverse effect in FADD, FSUB &c }
  49. OT_COLON = $00000400;
  50. OT_SHIFTEROP = $00000800;
  51. OT_REGISTER = $00001000;
  52. OT_IMMEDIATE = $00002000;
  53. OT_REGLIST = $00008000;
  54. OT_IMM8 = $00002001;
  55. OT_IMM24 = $00002002;
  56. OT_IMM32 = $00002004;
  57. OT_IMM64 = $00002008;
  58. OT_IMM80 = $00002010;
  59. OT_IMMTINY = $00002100;
  60. OT_IMMSHIFTER= $00002200;
  61. OT_IMMEDIATE24 = OT_IMM24;
  62. OT_SHIFTIMM = OT_SHIFTEROP or OT_IMMSHIFTER;
  63. OT_SHIFTIMMEDIATE = OT_SHIFTIMM;
  64. OT_IMMEDIATESHIFTER = OT_IMMSHIFTER;
  65. OT_IMMEDIATEFPU = OT_IMMTINY;
  66. OT_REGMEM = $00200000; { for r/m, ie EA, operands }
  67. OT_REGNORM = $00201000; { 'normal' reg, qualifies as EA }
  68. OT_REG8 = $00201001;
  69. OT_REG16 = $00201002;
  70. OT_REG32 = $00201004;
  71. OT_REG64 = $00201008;
  72. OT_VREG = $00201010; { vector register }
  73. OT_REGF = $00201020; { coproc register }
  74. OT_MEMORY = $00204000; { register number in 'basereg' }
  75. OT_MEM8 = $00204001;
  76. OT_MEM16 = $00204002;
  77. OT_MEM32 = $00204004;
  78. OT_MEM64 = $00204008;
  79. OT_MEM80 = $00204010;
  80. { word/byte load/store }
  81. OT_AM2 = $00010000;
  82. { misc ld/st operations }
  83. OT_AM3 = $00020000;
  84. { multiple ld/st operations }
  85. OT_AM4 = $00040000;
  86. { co proc. ld/st operations }
  87. OT_AM5 = $00080000;
  88. OT_AMMASK = $000f0000;
  89. { IT instruction }
  90. OT_CONDITION = $00100000;
  91. OT_MEMORYAM2 = OT_MEMORY or OT_AM2;
  92. OT_MEMORYAM3 = OT_MEMORY or OT_AM3;
  93. OT_MEMORYAM4 = OT_MEMORY or OT_AM4;
  94. OT_MEMORYAM5 = OT_MEMORY or OT_AM5;
  95. OT_FPUREG = $01000000; { floating point stack registers }
  96. OT_REG_SMASK = $00070000; { special register operands: these may be treated differently }
  97. { a mask for the following }
  98. OT_MEM_OFFS = $00604000; { special type of EA }
  99. { simple [address] offset }
  100. OT_ONENESS = $00800000; { special type of immediate operand }
  101. { so UNITY == IMMEDIATE | ONENESS }
  102. OT_UNITY = $00802000; { for shift/rotate instructions }
  103. instabentries = {$i armnop.inc}
  104. maxinfolen = 5;
  105. IF_NONE = $00000000;
  106. IF_ARMMASK = $000F0000;
  107. IF_ARM7 = $00070000;
  108. IF_FPMASK = $00F00000;
  109. IF_FPA = $00100000;
  110. { if the instruction can change in a second pass }
  111. IF_PASS2 = longint($80000000);
  112. type
  113. TInsTabCache=array[TasmOp] of longint;
  114. PInsTabCache=^TInsTabCache;
  115. tinsentry = record
  116. opcode : tasmop;
  117. ops : byte;
  118. optypes : array[0..3] of longint;
  119. code : array[0..maxinfolen] of char;
  120. flags : longint;
  121. end;
  122. pinsentry=^tinsentry;
  123. const
  124. InsTab : array[0..instabentries-1] of TInsEntry={$i armtab.inc}
  125. var
  126. InsTabCache : PInsTabCache;
  127. type
  128. taicpu = class(tai_cpu_abstract_sym)
  129. oppostfix : TOpPostfix;
  130. wideformat : boolean;
  131. roundingmode : troundingmode;
  132. procedure loadshifterop(opidx:longint;const so:tshifterop);
  133. procedure loadregset(opidx:longint; regsetregtype: tregistertype; regsetsubregtype: tsubregister; const s:tcpuregisterset; ausermode: boolean=false);
  134. procedure loadconditioncode(opidx:longint;const cond:tasmcond);
  135. procedure loadmodeflags(opidx:longint;const flags:tcpumodeflags);
  136. procedure loadspecialreg(opidx:longint;const areg:tregister; const aflags:tspecialregflags);
  137. constructor op_none(op : tasmop);
  138. constructor op_reg(op : tasmop;_op1 : tregister);
  139. constructor op_ref(op : tasmop;const _op1 : treference);
  140. constructor op_const(op : tasmop;_op1 : longint);
  141. constructor op_reg_reg(op : tasmop;_op1,_op2 : tregister);
  142. constructor op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
  143. constructor op_reg_const(op:tasmop; _op1: tregister; _op2: aint);
  144. constructor op_regset(op:tasmop; regtype: tregistertype; subreg: tsubregister; _op1: tcpuregisterset);
  145. constructor op_ref_regset(op:tasmop; _op1: treference; regtype: tregistertype; subreg: tsubregister; _op2: tcpuregisterset);
  146. constructor op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
  147. constructor op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: aint);
  148. constructor op_reg_const_const(op : tasmop;_op1 : tregister; _op2,_op3: aint);
  149. constructor op_reg_reg_sym_ofs(op : tasmop;_op1,_op2 : tregister; _op3: tasmsymbol;_op3ofs: longint);
  150. constructor op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister; const _op3: treference);
  151. constructor op_reg_reg_shifterop(op : tasmop;_op1,_op2 : tregister;_op3 : tshifterop);
  152. constructor op_reg_reg_reg_shifterop(op : tasmop;_op1,_op2,_op3 : tregister;_op4 : tshifterop);
  153. { SFM/LFM }
  154. constructor op_reg_const_ref(op : tasmop;_op1 : tregister;_op2 : aint;_op3 : treference);
  155. { ITxxx }
  156. constructor op_cond(op: tasmop; cond: tasmcond);
  157. { CPSxx }
  158. constructor op_modeflags(op: tasmop; flags: tcpumodeflags);
  159. constructor op_modeflags_const(op: tasmop; flags: tcpumodeflags; a: aint);
  160. { MSR }
  161. constructor op_specialreg_reg(op: tasmop; specialreg: tregister; specialregflags: tspecialregflags; _op2: tregister);
  162. { *M*LL }
  163. constructor op_reg_reg_reg_reg(op : tasmop;_op1,_op2,_op3,_op4 : tregister);
  164. { this is for Jmp instructions }
  165. constructor op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
  166. constructor op_sym(op : tasmop;_op1 : tasmsymbol);
  167. constructor op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
  168. constructor op_reg_sym_ofs(op : tasmop;_op1 : tregister;_op2:tasmsymbol;_op2ofs : longint);
  169. constructor op_sym_ofs_ref(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  170. function is_same_reg_move(regtype: Tregistertype):boolean; override;
  171. function spilling_get_operation_type(opnr: longint): topertype;override;
  172. { assembler }
  173. public
  174. { the next will reset all instructions that can change in pass 2 }
  175. procedure ResetPass1;override;
  176. procedure ResetPass2;override;
  177. function CheckIfValid:boolean;
  178. function GetString:string;
  179. function Pass1(objdata:TObjData):longint;override;
  180. procedure Pass2(objdata:TObjData);override;
  181. protected
  182. procedure ppuloadoper(ppufile:tcompilerppufile;var o:toper);override;
  183. procedure ppuwriteoper(ppufile:tcompilerppufile;const o:toper);override;
  184. procedure ppubuildderefimploper(var o:toper);override;
  185. procedure ppuderefoper(var o:toper);override;
  186. private
  187. { next fields are filled in pass1, so pass2 is faster }
  188. inssize : shortint;
  189. insoffset : longint;
  190. LastInsOffset : longint; { need to be public to be reset }
  191. insentry : PInsEntry;
  192. function InsEnd:longint;
  193. procedure create_ot(objdata:TObjData);
  194. function Matches(p:PInsEntry):longint;
  195. function calcsize(p:PInsEntry):shortint;
  196. procedure gencode(objdata:TObjData);
  197. function NeedAddrPrefix(opidx:byte):boolean;
  198. procedure Swapoperands;
  199. function FindInsentry(objdata:TObjData):boolean;
  200. end;
  201. tai_align = class(tai_align_abstract)
  202. { nothing to add }
  203. end;
  204. tai_thumb_func = class(tai)
  205. constructor create;
  206. end;
  207. function spilling_create_load(const ref:treference;r:tregister):Taicpu;
  208. function spilling_create_store(r:tregister; const ref:treference):Taicpu;
  209. function setoppostfix(i : taicpu;pf : toppostfix) : taicpu;
  210. function setroundingmode(i : taicpu;rm : troundingmode) : taicpu;
  211. function setcondition(i : taicpu;c : tasmcond) : taicpu;
  212. { inserts pc relative symbols at places where they are reachable
  213. and transforms special instructions to valid instruction encodings }
  214. procedure finalizearmcode(list,listtoinsert : TAsmList);
  215. { inserts .pdata section and dummy function prolog needed for arm-wince exception handling }
  216. procedure InsertPData;
  217. procedure InitAsm;
  218. procedure DoneAsm;
  219. implementation
  220. uses
  221. itcpugas,aoptcpu;
  222. procedure taicpu.loadshifterop(opidx:longint;const so:tshifterop);
  223. begin
  224. allocate_oper(opidx+1);
  225. with oper[opidx]^ do
  226. begin
  227. if typ<>top_shifterop then
  228. begin
  229. clearop(opidx);
  230. new(shifterop);
  231. end;
  232. shifterop^:=so;
  233. typ:=top_shifterop;
  234. if assigned(add_reg_instruction_hook) then
  235. add_reg_instruction_hook(self,shifterop^.rs);
  236. end;
  237. end;
  238. procedure taicpu.loadregset(opidx:longint; regsetregtype: tregistertype; regsetsubregtype: tsubregister; const s:tcpuregisterset; ausermode: boolean);
  239. var
  240. i : byte;
  241. begin
  242. allocate_oper(opidx+1);
  243. with oper[opidx]^ do
  244. begin
  245. if typ<>top_regset then
  246. begin
  247. clearop(opidx);
  248. new(regset);
  249. end;
  250. regset^:=s;
  251. regtyp:=regsetregtype;
  252. subreg:=regsetsubregtype;
  253. usermode:=ausermode;
  254. typ:=top_regset;
  255. case regsetregtype of
  256. R_INTREGISTER:
  257. for i:=RS_R0 to RS_R15 do
  258. begin
  259. if assigned(add_reg_instruction_hook) and (i in regset^) then
  260. add_reg_instruction_hook(self,newreg(R_INTREGISTER,i,regsetsubregtype));
  261. end;
  262. R_MMREGISTER:
  263. { both RS_S0 and RS_D0 range from 0 to 31 }
  264. for i:=RS_D0 to RS_D31 do
  265. begin
  266. if assigned(add_reg_instruction_hook) and (i in regset^) then
  267. add_reg_instruction_hook(self,newreg(R_MMREGISTER,i,regsetsubregtype));
  268. end;
  269. end;
  270. end;
  271. end;
  272. procedure taicpu.loadconditioncode(opidx:longint;const cond:tasmcond);
  273. begin
  274. allocate_oper(opidx+1);
  275. with oper[opidx]^ do
  276. begin
  277. if typ<>top_conditioncode then
  278. clearop(opidx);
  279. cc:=cond;
  280. typ:=top_conditioncode;
  281. end;
  282. end;
  283. procedure taicpu.loadmodeflags(opidx: longint; const flags: tcpumodeflags);
  284. begin
  285. allocate_oper(opidx+1);
  286. with oper[opidx]^ do
  287. begin
  288. if typ<>top_modeflags then
  289. clearop(opidx);
  290. modeflags:=flags;
  291. typ:=top_modeflags;
  292. end;
  293. end;
  294. procedure taicpu.loadspecialreg(opidx: longint; const areg: tregister; const aflags: tspecialregflags);
  295. begin
  296. allocate_oper(opidx+1);
  297. with oper[opidx]^ do
  298. begin
  299. if typ<>top_specialreg then
  300. clearop(opidx);
  301. specialreg:=areg;
  302. specialflags:=aflags;
  303. typ:=top_specialreg;
  304. end;
  305. end;
  306. {*****************************************************************************
  307. taicpu Constructors
  308. *****************************************************************************}
  309. constructor taicpu.op_none(op : tasmop);
  310. begin
  311. inherited create(op);
  312. end;
  313. { for pld }
  314. constructor taicpu.op_ref(op : tasmop;const _op1 : treference);
  315. begin
  316. inherited create(op);
  317. ops:=1;
  318. loadref(0,_op1);
  319. end;
  320. constructor taicpu.op_reg(op : tasmop;_op1 : tregister);
  321. begin
  322. inherited create(op);
  323. ops:=1;
  324. loadreg(0,_op1);
  325. end;
  326. constructor taicpu.op_const(op : tasmop;_op1 : longint);
  327. begin
  328. inherited create(op);
  329. ops:=1;
  330. loadconst(0,aint(_op1));
  331. end;
  332. constructor taicpu.op_reg_reg(op : tasmop;_op1,_op2 : tregister);
  333. begin
  334. inherited create(op);
  335. ops:=2;
  336. loadreg(0,_op1);
  337. loadreg(1,_op2);
  338. end;
  339. constructor taicpu.op_reg_const(op:tasmop; _op1: tregister; _op2: aint);
  340. begin
  341. inherited create(op);
  342. ops:=2;
  343. loadreg(0,_op1);
  344. loadconst(1,aint(_op2));
  345. end;
  346. constructor taicpu.op_regset(op: tasmop; regtype: tregistertype; subreg: tsubregister; _op1: tcpuregisterset);
  347. begin
  348. inherited create(op);
  349. ops:=1;
  350. loadregset(0,regtype,subreg,_op1);
  351. end;
  352. constructor taicpu.op_ref_regset(op:tasmop; _op1: treference; regtype: tregistertype; subreg: tsubregister; _op2: tcpuregisterset);
  353. begin
  354. inherited create(op);
  355. ops:=2;
  356. loadref(0,_op1);
  357. loadregset(1,regtype,subreg,_op2);
  358. end;
  359. constructor taicpu.op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
  360. begin
  361. inherited create(op);
  362. ops:=2;
  363. loadreg(0,_op1);
  364. loadref(1,_op2);
  365. end;
  366. constructor taicpu.op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
  367. begin
  368. inherited create(op);
  369. ops:=3;
  370. loadreg(0,_op1);
  371. loadreg(1,_op2);
  372. loadreg(2,_op3);
  373. end;
  374. constructor taicpu.op_reg_reg_reg_reg(op : tasmop;_op1,_op2,_op3,_op4 : tregister);
  375. begin
  376. inherited create(op);
  377. ops:=4;
  378. loadreg(0,_op1);
  379. loadreg(1,_op2);
  380. loadreg(2,_op3);
  381. loadreg(3,_op4);
  382. end;
  383. constructor taicpu.op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: aint);
  384. begin
  385. inherited create(op);
  386. ops:=3;
  387. loadreg(0,_op1);
  388. loadreg(1,_op2);
  389. loadconst(2,aint(_op3));
  390. end;
  391. constructor taicpu.op_reg_const_const(op : tasmop;_op1 : tregister; _op2,_op3: aint);
  392. begin
  393. inherited create(op);
  394. ops:=3;
  395. loadreg(0,_op1);
  396. loadconst(1,aint(_op2));
  397. loadconst(2,aint(_op3));
  398. end;
  399. constructor taicpu.op_reg_const_ref(op : tasmop;_op1 : tregister;_op2 : aint;_op3 : treference);
  400. begin
  401. inherited create(op);
  402. ops:=3;
  403. loadreg(0,_op1);
  404. loadconst(1,_op2);
  405. loadref(2,_op3);
  406. end;
  407. constructor taicpu.op_cond(op: tasmop; cond: tasmcond);
  408. begin
  409. inherited create(op);
  410. ops:=1;
  411. loadconditioncode(0, cond);
  412. end;
  413. constructor taicpu.op_modeflags(op: tasmop; flags: tcpumodeflags);
  414. begin
  415. inherited create(op);
  416. ops := 1;
  417. loadmodeflags(0,flags);
  418. end;
  419. constructor taicpu.op_modeflags_const(op: tasmop; flags: tcpumodeflags; a: aint);
  420. begin
  421. inherited create(op);
  422. ops := 2;
  423. loadmodeflags(0,flags);
  424. loadconst(1,a);
  425. end;
  426. constructor taicpu.op_specialreg_reg(op: tasmop; specialreg: tregister; specialregflags: tspecialregflags; _op2: tregister);
  427. begin
  428. inherited create(op);
  429. ops:=2;
  430. loadspecialreg(0,specialreg,specialregflags);
  431. loadreg(1,_op2);
  432. end;
  433. constructor taicpu.op_reg_reg_sym_ofs(op : tasmop;_op1,_op2 : tregister; _op3: tasmsymbol;_op3ofs: longint);
  434. begin
  435. inherited create(op);
  436. ops:=3;
  437. loadreg(0,_op1);
  438. loadreg(1,_op2);
  439. loadsymbol(0,_op3,_op3ofs);
  440. end;
  441. constructor taicpu.op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister; const _op3: treference);
  442. begin
  443. inherited create(op);
  444. ops:=3;
  445. loadreg(0,_op1);
  446. loadreg(1,_op2);
  447. loadref(2,_op3);
  448. end;
  449. constructor taicpu.op_reg_reg_shifterop(op : tasmop;_op1,_op2 : tregister;_op3 : tshifterop);
  450. begin
  451. inherited create(op);
  452. ops:=3;
  453. loadreg(0,_op1);
  454. loadreg(1,_op2);
  455. loadshifterop(2,_op3);
  456. end;
  457. constructor taicpu.op_reg_reg_reg_shifterop(op : tasmop;_op1,_op2,_op3 : tregister;_op4 : tshifterop);
  458. begin
  459. inherited create(op);
  460. ops:=4;
  461. loadreg(0,_op1);
  462. loadreg(1,_op2);
  463. loadreg(2,_op3);
  464. loadshifterop(3,_op4);
  465. end;
  466. constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
  467. begin
  468. inherited create(op);
  469. condition:=cond;
  470. ops:=1;
  471. loadsymbol(0,_op1,0);
  472. end;
  473. constructor taicpu.op_sym(op : tasmop;_op1 : tasmsymbol);
  474. begin
  475. inherited create(op);
  476. ops:=1;
  477. loadsymbol(0,_op1,0);
  478. end;
  479. constructor taicpu.op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
  480. begin
  481. inherited create(op);
  482. ops:=1;
  483. loadsymbol(0,_op1,_op1ofs);
  484. end;
  485. constructor taicpu.op_reg_sym_ofs(op : tasmop;_op1 : tregister;_op2:tasmsymbol;_op2ofs : longint);
  486. begin
  487. inherited create(op);
  488. ops:=2;
  489. loadreg(0,_op1);
  490. loadsymbol(1,_op2,_op2ofs);
  491. end;
  492. constructor taicpu.op_sym_ofs_ref(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  493. begin
  494. inherited create(op);
  495. ops:=2;
  496. loadsymbol(0,_op1,_op1ofs);
  497. loadref(1,_op2);
  498. end;
  499. function taicpu.is_same_reg_move(regtype: Tregistertype):boolean;
  500. begin
  501. { allow the register allocator to remove unnecessary moves }
  502. result:=(
  503. ((opcode=A_MOV) and (regtype = R_INTREGISTER)) or
  504. ((opcode=A_MVF) and (regtype = R_FPUREGISTER)) or
  505. ((opcode in [A_FCPYS, A_FCPYD]) and (regtype = R_MMREGISTER))
  506. ) and
  507. (oppostfix in [PF_None,PF_D]) and
  508. (condition=C_None) and
  509. (ops=2) and
  510. (oper[0]^.typ=top_reg) and
  511. (oper[1]^.typ=top_reg) and
  512. (oper[0]^.reg=oper[1]^.reg);
  513. end;
  514. function spilling_create_load(const ref:treference;r:tregister):Taicpu;
  515. var
  516. op: tasmop;
  517. begin
  518. case getregtype(r) of
  519. R_INTREGISTER :
  520. result:=taicpu.op_reg_ref(A_LDR,r,ref);
  521. R_FPUREGISTER :
  522. { use lfm because we don't know the current internal format
  523. and avoid exceptions
  524. }
  525. result:=taicpu.op_reg_const_ref(A_LFM,r,1,ref);
  526. R_MMREGISTER :
  527. begin
  528. case getsubreg(r) of
  529. R_SUBFD:
  530. op:=A_FLDD;
  531. R_SUBFS:
  532. op:=A_FLDS;
  533. R_SUBNONE:
  534. op:=A_VLDR;
  535. else
  536. internalerror(2009112905);
  537. end;
  538. result:=taicpu.op_reg_ref(op,r,ref);
  539. end;
  540. else
  541. internalerror(200401041);
  542. end;
  543. end;
  544. function spilling_create_store(r:tregister; const ref:treference):Taicpu;
  545. var
  546. op: tasmop;
  547. begin
  548. case getregtype(r) of
  549. R_INTREGISTER :
  550. result:=taicpu.op_reg_ref(A_STR,r,ref);
  551. R_FPUREGISTER :
  552. { use sfm because we don't know the current internal format
  553. and avoid exceptions
  554. }
  555. result:=taicpu.op_reg_const_ref(A_SFM,r,1,ref);
  556. R_MMREGISTER :
  557. begin
  558. case getsubreg(r) of
  559. R_SUBFD:
  560. op:=A_FSTD;
  561. R_SUBFS:
  562. op:=A_FSTS;
  563. R_SUBNONE:
  564. op:=A_VSTR;
  565. else
  566. internalerror(2009112904);
  567. end;
  568. result:=taicpu.op_reg_ref(op,r,ref);
  569. end;
  570. else
  571. internalerror(200401041);
  572. end;
  573. end;
  574. function taicpu.spilling_get_operation_type(opnr: longint): topertype;
  575. begin
  576. case opcode of
  577. A_ADC,A_ADD,A_AND,A_BIC,
  578. A_EOR,A_CLZ,A_RBIT,
  579. A_LDR,A_LDRB,A_LDRBT,A_LDRH,A_LDRSB,
  580. A_LDRSH,A_LDRT,
  581. A_MOV,A_MVN,A_MLA,A_MUL,
  582. A_ORR,A_RSB,A_RSC,A_SBC,A_SUB,
  583. A_SWP,A_SWPB,
  584. A_LDF,A_FLT,A_FIX,
  585. A_ADF,A_DVF,A_FDV,A_FML,
  586. A_RFS,A_RFC,A_RDF,
  587. A_RMF,A_RPW,A_RSF,A_SUF,A_ABS,A_ACS,A_ASN,A_ATN,A_COS,
  588. A_EXP,A_LOG,A_LGN,A_MVF,A_MNF,A_FRD,A_MUF,A_POL,A_RND,A_SIN,A_SQT,A_TAN,
  589. A_LFM,
  590. A_FLDS,A_FLDD,
  591. A_FMRX,A_FMXR,A_FMSTAT,
  592. A_FMSR,A_FMRS,A_FMDRR,
  593. A_FCPYS,A_FCPYD,A_FCVTSD,A_FCVTDS,
  594. A_FABSS,A_FABSD,A_FSQRTS,A_FSQRTD,A_FMULS,A_FMULD,
  595. A_FADDS,A_FADDD,A_FSUBS,A_FSUBD,A_FDIVS,A_FDIVD,
  596. A_FMACS,A_FMACD,A_FMSCS,A_FMSCD,A_FNMACS,A_FNMACD,
  597. A_FNMSCS,A_FNMSCD,A_FNMULS,A_FNMULD,
  598. A_FMDHR,A_FMRDH,A_FMDLR,A_FMRDL,
  599. A_FNEGS,A_FNEGD,
  600. A_FSITOS,A_FSITOD,A_FTOSIS,A_FTOSID,
  601. A_FTOUIS,A_FTOUID,A_FUITOS,A_FUITOD,
  602. A_SXTB16,A_UXTB16,
  603. A_UXTB,A_UXTH,A_SXTB,A_SXTH,
  604. A_NEG,
  605. A_VABS,A_VADD,A_VCVT,A_VDIV,A_VLDR,A_VMOV,A_VMUL,A_VNEG,A_VSQRT,A_VSUB:
  606. if opnr=0 then
  607. result:=operand_write
  608. else
  609. result:=operand_read;
  610. A_BKPT,A_B,A_BL,A_BLX,A_BX,
  611. A_CMN,A_CMP,A_TEQ,A_TST,
  612. A_CMF,A_CMFE,A_WFS,A_CNF,
  613. A_FCMPS,A_FCMPD,A_FCMPES,A_FCMPED,A_FCMPEZS,A_FCMPEZD,
  614. A_FCMPZS,A_FCMPZD,
  615. A_VCMP,A_VCMPE:
  616. result:=operand_read;
  617. A_SMLAL,A_UMLAL:
  618. if opnr in [0,1] then
  619. result:=operand_readwrite
  620. else
  621. result:=operand_read;
  622. A_SMULL,A_UMULL,
  623. A_FMRRD:
  624. if opnr in [0,1] then
  625. result:=operand_write
  626. else
  627. result:=operand_read;
  628. A_STR,A_STRB,A_STRBT,
  629. A_STRH,A_STRT,A_STF,A_SFM,
  630. A_FSTS,A_FSTD,
  631. A_VSTR:
  632. { important is what happens with the involved registers }
  633. if opnr=0 then
  634. result := operand_read
  635. else
  636. { check for pre/post indexed }
  637. result := operand_read;
  638. //Thumb2
  639. A_LSL, A_LSR, A_ROR, A_ASR, A_SDIV, A_UDIV, A_MOVW, A_MOVT, A_MLS, A_BFI:
  640. if opnr in [0] then
  641. result:=operand_write
  642. else
  643. result:=operand_read;
  644. A_BFC:
  645. if opnr in [0] then
  646. result:=operand_readwrite
  647. else
  648. result:=operand_read;
  649. A_LDREX:
  650. if opnr in [0] then
  651. result:=operand_write
  652. else
  653. result:=operand_read;
  654. A_STREX:
  655. result:=operand_write;
  656. else
  657. internalerror(200403151);
  658. end;
  659. end;
  660. procedure BuildInsTabCache;
  661. var
  662. i : longint;
  663. begin
  664. new(instabcache);
  665. FillChar(instabcache^,sizeof(tinstabcache),$ff);
  666. i:=0;
  667. while (i<InsTabEntries) do
  668. begin
  669. if InsTabCache^[InsTab[i].Opcode]=-1 then
  670. InsTabCache^[InsTab[i].Opcode]:=i;
  671. inc(i);
  672. end;
  673. end;
  674. procedure InitAsm;
  675. begin
  676. if not assigned(instabcache) then
  677. BuildInsTabCache;
  678. end;
  679. procedure DoneAsm;
  680. begin
  681. if assigned(instabcache) then
  682. begin
  683. dispose(instabcache);
  684. instabcache:=nil;
  685. end;
  686. end;
  687. function setoppostfix(i : taicpu;pf : toppostfix) : taicpu;
  688. begin
  689. i.oppostfix:=pf;
  690. result:=i;
  691. end;
  692. function setroundingmode(i : taicpu;rm : troundingmode) : taicpu;
  693. begin
  694. i.roundingmode:=rm;
  695. result:=i;
  696. end;
  697. function setcondition(i : taicpu;c : tasmcond) : taicpu;
  698. begin
  699. i.condition:=c;
  700. result:=i;
  701. end;
  702. Function SimpleGetNextInstruction(Current: tai; Var Next: tai): Boolean;
  703. Begin
  704. Current:=tai(Current.Next);
  705. While Assigned(Current) And (Current.typ In SkipInstr) Do
  706. Current:=tai(Current.Next);
  707. Next:=Current;
  708. If Assigned(Next) And Not(Next.typ In SkipInstr) Then
  709. Result:=True
  710. Else
  711. Begin
  712. Next:=Nil;
  713. Result:=False;
  714. End;
  715. End;
  716. (*
  717. function armconstequal(hp1,hp2: tai): boolean;
  718. begin
  719. result:=false;
  720. if hp1.typ<>hp2.typ then
  721. exit;
  722. case hp1.typ of
  723. tai_const:
  724. result:=
  725. (tai_const(hp2).sym=tai_const(hp).sym) and
  726. (tai_const(hp2).value=tai_const(hp).value) and
  727. (tai(hp2.previous).typ=ait_label);
  728. tai_const:
  729. result:=
  730. (tai_const(hp2).sym=tai_const(hp).sym) and
  731. (tai_const(hp2).value=tai_const(hp).value) and
  732. (tai(hp2.previous).typ=ait_label);
  733. end;
  734. end;
  735. *)
  736. procedure insertpcrelativedata(list,listtoinsert : TAsmList);
  737. var
  738. limit: longint;
  739. { FLD/FST VFP instructions have a limit of +/- 1024, not 4096, this
  740. function checks the next count instructions if the limit must be
  741. decreased }
  742. procedure CheckLimit(hp : tai;count : integer);
  743. var
  744. i : Integer;
  745. begin
  746. for i:=1 to count do
  747. if SimpleGetNextInstruction(hp,hp) and
  748. (tai(hp).typ=ait_instruction) and
  749. ((taicpu(hp).opcode=A_FLDS) or
  750. (taicpu(hp).opcode=A_FLDD) or
  751. (taicpu(hp).opcode=A_VLDR)) then
  752. limit:=254;
  753. end;
  754. var
  755. curinspos,
  756. penalty,
  757. lastinspos,
  758. { increased for every data element > 4 bytes inserted }
  759. currentsize,
  760. extradataoffset,
  761. curop : longint;
  762. curtai : tai;
  763. ai_label : tai_label;
  764. curdatatai,hp,hp2 : tai;
  765. curdata : TAsmList;
  766. l : tasmlabel;
  767. doinsert,
  768. removeref : boolean;
  769. multiplier : byte;
  770. begin
  771. curdata:=TAsmList.create;
  772. lastinspos:=-1;
  773. curinspos:=0;
  774. extradataoffset:=0;
  775. if GenerateThumbCode then
  776. begin
  777. multiplier:=2;
  778. limit:=504;
  779. end
  780. else
  781. begin
  782. limit:=1016;
  783. multiplier:=1;
  784. end;
  785. curtai:=tai(list.first);
  786. doinsert:=false;
  787. while assigned(curtai) do
  788. begin
  789. { instruction? }
  790. case curtai.typ of
  791. ait_instruction:
  792. begin
  793. { walk through all operand of the instruction }
  794. for curop:=0 to taicpu(curtai).ops-1 do
  795. begin
  796. { reference? }
  797. if (taicpu(curtai).oper[curop]^.typ=top_ref) then
  798. begin
  799. { pc relative symbol? }
  800. curdatatai:=tai(taicpu(curtai).oper[curop]^.ref^.symboldata);
  801. if assigned(curdatatai) then
  802. begin
  803. { create a new copy of a data entry on arm thumb if the entry has been inserted already
  804. before because arm thumb does not allow pc relative negative offsets }
  805. if (GenerateThumbCode) and
  806. tai_label(curdatatai).inserted then
  807. begin
  808. current_asmdata.getjumplabel(l);
  809. hp:=tai_label.create(l);
  810. listtoinsert.Concat(hp);
  811. hp2:=tai(curdatatai.Next.GetCopy);
  812. hp2.Next:=nil;
  813. hp2.Previous:=nil;
  814. listtoinsert.Concat(hp2);
  815. taicpu(curtai).oper[curop]^.ref^.symboldata:=hp;
  816. taicpu(curtai).oper[curop]^.ref^.symbol:=l;
  817. curdatatai:=hp;
  818. end;
  819. { move only if we're at the first reference of a label }
  820. if not(tai_label(curdatatai).moved) then
  821. begin
  822. tai_label(curdatatai).moved:=true;
  823. { check if symbol already used. }
  824. { if yes, reuse the symbol }
  825. hp:=tai(curdatatai.next);
  826. removeref:=false;
  827. if assigned(hp) then
  828. begin
  829. case hp.typ of
  830. ait_const:
  831. begin
  832. if (tai_const(hp).consttype=aitconst_64bit) then
  833. inc(extradataoffset,multiplier);
  834. end;
  835. ait_comp_64bit,
  836. ait_real_64bit:
  837. begin
  838. inc(extradataoffset,multiplier);
  839. end;
  840. ait_real_80bit:
  841. begin
  842. inc(extradataoffset,2*multiplier);
  843. end;
  844. end;
  845. { check if the same constant has been already inserted into the currently handled list,
  846. if yes, reuse it }
  847. if (hp.typ=ait_const) then
  848. begin
  849. hp2:=tai(curdata.first);
  850. while assigned(hp2) do
  851. begin
  852. if (hp2.typ=ait_const) and (tai_const(hp2).sym=tai_const(hp).sym)
  853. and (tai_const(hp2).value=tai_const(hp).value) and (tai(hp2.previous).typ=ait_label)
  854. then
  855. begin
  856. with taicpu(curtai).oper[curop]^.ref^ do
  857. begin
  858. symboldata:=hp2.previous;
  859. symbol:=tai_label(hp2.previous).labsym;
  860. end;
  861. removeref:=true;
  862. break;
  863. end;
  864. hp2:=tai(hp2.next);
  865. end;
  866. end;
  867. end;
  868. { move or remove symbol reference }
  869. repeat
  870. hp:=tai(curdatatai.next);
  871. listtoinsert.remove(curdatatai);
  872. if removeref then
  873. curdatatai.free
  874. else
  875. curdata.concat(curdatatai);
  876. curdatatai:=hp;
  877. until (curdatatai=nil) or (curdatatai.typ=ait_label);
  878. if lastinspos=-1 then
  879. lastinspos:=curinspos;
  880. end;
  881. end;
  882. end;
  883. end;
  884. inc(curinspos,multiplier);
  885. end;
  886. ait_align:
  887. begin
  888. { code is always 4 byte aligned, so we don't have to take care of .align 2 which would
  889. requires also incrementing curinspos by 1 }
  890. inc(curinspos,(tai_align(curtai).aligntype div 4)*multiplier);
  891. end;
  892. ait_const:
  893. begin
  894. inc(curinspos,multiplier);
  895. if (tai_const(curtai).consttype=aitconst_64bit) then
  896. inc(curinspos,multiplier);
  897. end;
  898. ait_real_32bit:
  899. begin
  900. inc(curinspos,multiplier);
  901. end;
  902. ait_comp_64bit,
  903. ait_real_64bit:
  904. begin
  905. inc(curinspos,2*multiplier);
  906. end;
  907. ait_real_80bit:
  908. begin
  909. inc(curinspos,3*multiplier);
  910. end;
  911. end;
  912. { special case for case jump tables }
  913. penalty:=0;
  914. if SimpleGetNextInstruction(curtai,hp) and
  915. (tai(hp).typ=ait_instruction) then
  916. begin
  917. case taicpu(hp).opcode of
  918. A_BX,
  919. A_LDR,
  920. A_ADD:
  921. { approximation if we hit a case jump table }
  922. if ((taicpu(hp).opcode in [A_ADD,A_LDR]) and not(GenerateThumbCode or GenerateThumb2Code) and
  923. (taicpu(hp).oper[0]^.typ=top_reg) and
  924. (taicpu(hp).oper[0]^.reg=NR_PC)) or
  925. ((taicpu(hp).opcode=A_BX) and (GenerateThumbCode) and
  926. (taicpu(hp).oper[0]^.typ=top_reg))
  927. then
  928. begin
  929. penalty:=multiplier;
  930. hp:=tai(hp.next);
  931. { skip register allocations and comments inserted by the optimizer as well as a label
  932. as jump tables for thumb might have }
  933. while assigned(hp) and (hp.typ in [ait_comment,ait_regalloc,ait_label]) do
  934. hp:=tai(hp.next);
  935. while assigned(hp) and (hp.typ=ait_const) do
  936. begin
  937. inc(penalty,multiplier);
  938. hp:=tai(hp.next);
  939. end;
  940. end;
  941. A_IT:
  942. begin
  943. if GenerateThumb2Code then
  944. penalty:=multiplier;
  945. { check if the next instruction fits as well
  946. or if we splitted after the it so split before }
  947. CheckLimit(hp,1);
  948. end;
  949. A_ITE,
  950. A_ITT:
  951. begin
  952. if GenerateThumb2Code then
  953. penalty:=2*multiplier;
  954. { check if the next two instructions fit as well
  955. or if we splitted them so split before }
  956. CheckLimit(hp,2);
  957. end;
  958. A_ITEE,
  959. A_ITTE,
  960. A_ITET,
  961. A_ITTT:
  962. begin
  963. if GenerateThumb2Code then
  964. penalty:=3*multiplier;
  965. { check if the next three instructions fit as well
  966. or if we splitted them so split before }
  967. CheckLimit(hp,3);
  968. end;
  969. A_ITEEE,
  970. A_ITTEE,
  971. A_ITETE,
  972. A_ITTTE,
  973. A_ITEET,
  974. A_ITTET,
  975. A_ITETT,
  976. A_ITTTT:
  977. begin
  978. if GenerateThumb2Code then
  979. penalty:=4*multiplier;
  980. { check if the next three instructions fit as well
  981. or if we splitted them so split before }
  982. CheckLimit(hp,4);
  983. end;
  984. end;
  985. end;
  986. CheckLimit(curtai,1);
  987. { don't miss an insert }
  988. doinsert:=doinsert or
  989. (not(curdata.empty) and
  990. (curinspos-lastinspos+penalty+extradataoffset>limit));
  991. { split only at real instructions else the test below fails }
  992. if doinsert and (curtai.typ=ait_instruction) and
  993. (
  994. { don't split loads of pc to lr and the following move }
  995. not(
  996. (taicpu(curtai).opcode=A_MOV) and
  997. (taicpu(curtai).oper[0]^.typ=top_reg) and
  998. (taicpu(curtai).oper[0]^.reg=NR_R14) and
  999. (taicpu(curtai).oper[1]^.typ=top_reg) and
  1000. (taicpu(curtai).oper[1]^.reg=NR_PC)
  1001. )
  1002. ) and
  1003. (
  1004. { do not insert data after a B instruction due to their limited range }
  1005. not((GenerateThumbCode) and
  1006. (taicpu(curtai).opcode=A_B)
  1007. )
  1008. ) then
  1009. begin
  1010. lastinspos:=-1;
  1011. extradataoffset:=0;
  1012. if GenerateThumbCode then
  1013. limit:=502
  1014. else
  1015. limit:=1016;
  1016. { on arm thumb, insert the data always after all labels etc. following an instruction so it
  1017. is prevent that a bxx yyy; bl xxx; yyyy: sequence gets separated ( we never insert on arm thumb after
  1018. bxx) and the distance of bxx gets too long }
  1019. if GenerateThumbCode then
  1020. while assigned(tai(curtai.Next)) and (tai(curtai.Next).typ in SkipInstr+[ait_label]) do
  1021. curtai:=tai(curtai.next);
  1022. doinsert:=false;
  1023. current_asmdata.getjumplabel(l);
  1024. { align jump in thumb .text section to 4 bytes }
  1025. if not(curdata.empty) and (GenerateThumbCode) then
  1026. curdata.Insert(tai_align.Create(4));
  1027. curdata.insert(taicpu.op_sym(A_B,l));
  1028. curdata.concat(tai_label.create(l));
  1029. { mark all labels as inserted, arm thumb
  1030. needs this, so data referencing an already inserted label can be
  1031. duplicated because arm thumb does not allow negative pc relative offset }
  1032. hp2:=tai(curdata.first);
  1033. while assigned(hp2) do
  1034. begin
  1035. if hp2.typ=ait_label then
  1036. tai_label(hp2).inserted:=true;
  1037. hp2:=tai(hp2.next);
  1038. end;
  1039. { continue with the last inserted label because we use later
  1040. on SimpleGetNextInstruction, so if we used curtai.next (which
  1041. is then equal curdata.last.previous) we could over see one
  1042. instruction }
  1043. hp:=tai(curdata.Last);
  1044. list.insertlistafter(curtai,curdata);
  1045. curtai:=hp;
  1046. end
  1047. else
  1048. curtai:=tai(curtai.next);
  1049. end;
  1050. { align jump in thumb .text section to 4 bytes }
  1051. if not(curdata.empty) and (GenerateThumbCode or GenerateThumb2Code) then
  1052. curdata.Insert(tai_align.Create(4));
  1053. list.concatlist(curdata);
  1054. curdata.free;
  1055. end;
  1056. procedure ensurethumb2encodings(list: TAsmList);
  1057. var
  1058. curtai: tai;
  1059. op2reg: TRegister;
  1060. begin
  1061. { Do Thumb-2 16bit -> 32bit transformations }
  1062. curtai:=tai(list.first);
  1063. while assigned(curtai) do
  1064. begin
  1065. case curtai.typ of
  1066. ait_instruction:
  1067. begin
  1068. case taicpu(curtai).opcode of
  1069. A_ADD:
  1070. begin
  1071. { Set wide flag for ADD Rd,Rn,Rm where registers are over R7(high register set) }
  1072. if taicpu(curtai).ops = 3 then
  1073. begin
  1074. if taicpu(curtai).oper[2]^.typ in [top_reg,top_shifterop] then
  1075. begin
  1076. if taicpu(curtai).oper[2]^.typ = top_reg then
  1077. op2reg := taicpu(curtai).oper[2]^.reg
  1078. else if taicpu(curtai).oper[2]^.shifterop^.rs <> NR_NO then
  1079. op2reg := taicpu(curtai).oper[2]^.shifterop^.rs
  1080. else
  1081. op2reg := NR_NO;
  1082. if op2reg <> NR_NO then
  1083. begin
  1084. if (taicpu(curtai).oper[0]^.reg >= NR_R8) or
  1085. (taicpu(curtai).oper[1]^.reg >= NR_R8) or
  1086. (op2reg >= NR_R8) then
  1087. begin
  1088. taicpu(curtai).wideformat:=true;
  1089. { Handle special cases where register rules are violated by optimizer/user }
  1090. { if d == 13 || (d == 15 && S == ‘0’) || n == 15 || m IN [13,15] then UNPREDICTABLE; }
  1091. { Transform ADD.W Rx, Ry, R13 into ADD.W Rx, R13, Ry }
  1092. if (op2reg = NR_R13) and (taicpu(curtai).oper[2]^.typ = top_reg) then
  1093. begin
  1094. taicpu(curtai).oper[2]^.reg := taicpu(curtai).oper[1]^.reg;
  1095. taicpu(curtai).oper[1]^.reg := op2reg;
  1096. end;
  1097. end;
  1098. end;
  1099. end;
  1100. end;
  1101. end;
  1102. end;
  1103. end;
  1104. end;
  1105. curtai:=tai(curtai.Next);
  1106. end;
  1107. end;
  1108. function getMergedInstruction(FirstOp,LastOp:TAsmOp;InvertLast:boolean) : TAsmOp;
  1109. const
  1110. opTable: array[A_IT..A_ITTTT] of string =
  1111. ('T','TE','TT','TEE','TTE','TET','TTT',
  1112. 'TEEE','TTEE','TETE','TTTE',
  1113. 'TEET','TTET','TETT','TTTT');
  1114. invertedOpTable: array[A_IT..A_ITTTT] of string =
  1115. ('E','ET','EE','ETT','EET','ETE','EEE',
  1116. 'ETTT','EETT','ETET','EEET',
  1117. 'ETTE','EETE','ETEE','EEEE');
  1118. var
  1119. resStr : string;
  1120. i : TAsmOp;
  1121. begin
  1122. if InvertLast then
  1123. resStr := opTable[FirstOp]+invertedOpTable[LastOp]
  1124. else
  1125. resStr := opTable[FirstOp]+opTable[LastOp];
  1126. if length(resStr) > 4 then
  1127. internalerror(2012100805);
  1128. for i := low(opTable) to high(opTable) do
  1129. if opTable[i] = resStr then
  1130. exit(i);
  1131. internalerror(2012100806);
  1132. end;
  1133. procedure foldITInstructions(list: TAsmList);
  1134. var
  1135. curtai,hp1 : tai;
  1136. levels,i : LongInt;
  1137. begin
  1138. curtai:=tai(list.First);
  1139. while assigned(curtai) do
  1140. begin
  1141. case curtai.typ of
  1142. ait_instruction:
  1143. if IsIT(taicpu(curtai).opcode) then
  1144. begin
  1145. levels := GetITLevels(taicpu(curtai).opcode);
  1146. if levels < 4 then
  1147. begin
  1148. i:=levels;
  1149. hp1:=tai(curtai.Next);
  1150. while assigned(hp1) and
  1151. (i > 0) do
  1152. begin
  1153. if hp1.typ=ait_instruction then
  1154. begin
  1155. dec(i);
  1156. if (i = 0) and
  1157. mustbelast(hp1) then
  1158. begin
  1159. hp1:=nil;
  1160. break;
  1161. end;
  1162. end;
  1163. hp1:=tai(hp1.Next);
  1164. end;
  1165. if assigned(hp1) then
  1166. begin
  1167. // We are pointing at the first instruction after the IT block
  1168. while assigned(hp1) and
  1169. (hp1.typ<>ait_instruction) do
  1170. hp1:=tai(hp1.Next);
  1171. if assigned(hp1) and
  1172. (hp1.typ=ait_instruction) and
  1173. IsIT(taicpu(hp1).opcode) then
  1174. begin
  1175. if (levels+GetITLevels(taicpu(hp1).opcode) <= 4) and
  1176. ((taicpu(curtai).oper[0]^.cc=taicpu(hp1).oper[0]^.cc) or
  1177. (taicpu(curtai).oper[0]^.cc=inverse_cond(taicpu(hp1).oper[0]^.cc))) then
  1178. begin
  1179. taicpu(curtai).opcode:=getMergedInstruction(taicpu(curtai).opcode,
  1180. taicpu(hp1).opcode,
  1181. taicpu(curtai).oper[0]^.cc=inverse_cond(taicpu(hp1).oper[0]^.cc));
  1182. list.Remove(hp1);
  1183. hp1.Free;
  1184. end;
  1185. end;
  1186. end;
  1187. end;
  1188. end;
  1189. end;
  1190. curtai:=tai(curtai.Next);
  1191. end;
  1192. end;
  1193. procedure finalizearmcode(list, listtoinsert: TAsmList);
  1194. begin
  1195. { Do Thumb-2 16bit -> 32bit transformations }
  1196. if GenerateThumb2Code then
  1197. begin
  1198. ensurethumb2encodings(list);
  1199. foldITInstructions(list);
  1200. end;
  1201. insertpcrelativedata(list, listtoinsert);
  1202. end;
  1203. procedure InsertPData;
  1204. var
  1205. prolog: TAsmList;
  1206. begin
  1207. prolog:=TAsmList.create;
  1208. new_section(prolog,sec_code,'FPC_EH_PROLOG',sizeof(pint),secorder_begin);
  1209. prolog.concat(Tai_const.Createname('_ARM_ExceptionHandler', 0));
  1210. prolog.concat(Tai_const.Create_32bit(0));
  1211. prolog.concat(Tai_symbol.Createname_global('FPC_EH_CODE_START',AT_DATA,0));
  1212. { dummy function }
  1213. prolog.concat(taicpu.op_reg_reg(A_MOV,NR_R15,NR_R14));
  1214. current_asmdata.asmlists[al_start].insertList(prolog);
  1215. prolog.Free;
  1216. new_section(current_asmdata.asmlists[al_end],sec_pdata,'',sizeof(pint));
  1217. current_asmdata.asmlists[al_end].concat(Tai_const.Createname('FPC_EH_CODE_START', 0));
  1218. current_asmdata.asmlists[al_end].concat(Tai_const.Create_32bit(longint($ffffff01)));
  1219. end;
  1220. (*
  1221. Floating point instruction format information, taken from the linux kernel
  1222. ARM Floating Point Instruction Classes
  1223. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  1224. |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
  1225. |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|1|0| o f f s e t | CPDT (copro 2)
  1226. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  1227. |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
  1228. |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
  1229. |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
  1230. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  1231. CPDT data transfer instructions
  1232. LDF, STF, LFM (copro 2), SFM (copro 2)
  1233. CPDO dyadic arithmetic instructions
  1234. ADF, MUF, SUF, RSF, DVF, RDF,
  1235. POW, RPW, RMF, FML, FDV, FRD, POL
  1236. CPDO monadic arithmetic instructions
  1237. MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
  1238. SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
  1239. CPRT joint arithmetic/data transfer instructions
  1240. FIX (arithmetic followed by load/store)
  1241. FLT (load/store followed by arithmetic)
  1242. CMF, CNF CMFE, CNFE (comparisons)
  1243. WFS, RFS (write/read floating point status register)
  1244. WFC, RFC (write/read floating point control register)
  1245. cond condition codes
  1246. P pre/post index bit: 0 = postindex, 1 = preindex
  1247. U up/down bit: 0 = stack grows down, 1 = stack grows up
  1248. W write back bit: 1 = update base register (Rn)
  1249. L load/store bit: 0 = store, 1 = load
  1250. Rn base register
  1251. Rd destination/source register
  1252. Fd floating point destination register
  1253. Fn floating point source register
  1254. Fm floating point source register or floating point constant
  1255. uv transfer length (TABLE 1)
  1256. wx register count (TABLE 2)
  1257. abcd arithmetic opcode (TABLES 3 & 4)
  1258. ef destination size (rounding precision) (TABLE 5)
  1259. gh rounding mode (TABLE 6)
  1260. j dyadic/monadic bit: 0 = dyadic, 1 = monadic
  1261. i constant bit: 1 = constant (TABLE 6)
  1262. */
  1263. /*
  1264. TABLE 1
  1265. +-------------------------+---+---+---------+---------+
  1266. | Precision | u | v | FPSR.EP | length |
  1267. +-------------------------+---+---+---------+---------+
  1268. | Single | 0 | 0 | x | 1 words |
  1269. | Double | 1 | 1 | x | 2 words |
  1270. | Extended | 1 | 1 | x | 3 words |
  1271. | Packed decimal | 1 | 1 | 0 | 3 words |
  1272. | Expanded packed decimal | 1 | 1 | 1 | 4 words |
  1273. +-------------------------+---+---+---------+---------+
  1274. Note: x = don't care
  1275. */
  1276. /*
  1277. TABLE 2
  1278. +---+---+---------------------------------+
  1279. | w | x | Number of registers to transfer |
  1280. +---+---+---------------------------------+
  1281. | 0 | 1 | 1 |
  1282. | 1 | 0 | 2 |
  1283. | 1 | 1 | 3 |
  1284. | 0 | 0 | 4 |
  1285. +---+---+---------------------------------+
  1286. */
  1287. /*
  1288. TABLE 3: Dyadic Floating Point Opcodes
  1289. +---+---+---+---+----------+-----------------------+-----------------------+
  1290. | a | b | c | d | Mnemonic | Description | Operation |
  1291. +---+---+---+---+----------+-----------------------+-----------------------+
  1292. | 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm |
  1293. | 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm |
  1294. | 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm |
  1295. | 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn |
  1296. | 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm |
  1297. | 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn |
  1298. | 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm |
  1299. | 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn |
  1300. | 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) |
  1301. | 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm |
  1302. | 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm |
  1303. | 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn |
  1304. | 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) |
  1305. | 1 | 1 | 0 | 1 | | undefined instruction | trap |
  1306. | 1 | 1 | 1 | 0 | | undefined instruction | trap |
  1307. | 1 | 1 | 1 | 1 | | undefined instruction | trap |
  1308. +---+---+---+---+----------+-----------------------+-----------------------+
  1309. Note: POW, RPW, POL are deprecated, and are available for backwards
  1310. compatibility only.
  1311. */
  1312. /*
  1313. TABLE 4: Monadic Floating Point Opcodes
  1314. +---+---+---+---+----------+-----------------------+-----------------------+
  1315. | a | b | c | d | Mnemonic | Description | Operation |
  1316. +---+---+---+---+----------+-----------------------+-----------------------+
  1317. | 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm |
  1318. | 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm |
  1319. | 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) |
  1320. | 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) |
  1321. | 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) |
  1322. | 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) |
  1323. | 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) |
  1324. | 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm |
  1325. | 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) |
  1326. | 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) |
  1327. | 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) |
  1328. | 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) |
  1329. | 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) |
  1330. | 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) |
  1331. | 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) |
  1332. | 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) |
  1333. +---+---+---+---+----------+-----------------------+-----------------------+
  1334. Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are
  1335. available for backwards compatibility only.
  1336. */
  1337. /*
  1338. TABLE 5
  1339. +-------------------------+---+---+
  1340. | Rounding Precision | e | f |
  1341. +-------------------------+---+---+
  1342. | IEEE Single precision | 0 | 0 |
  1343. | IEEE Double precision | 0 | 1 |
  1344. | IEEE Extended precision | 1 | 0 |
  1345. | undefined (trap) | 1 | 1 |
  1346. +-------------------------+---+---+
  1347. */
  1348. /*
  1349. TABLE 5
  1350. +---------------------------------+---+---+
  1351. | Rounding Mode | g | h |
  1352. +---------------------------------+---+---+
  1353. | Round to nearest (default) | 0 | 0 |
  1354. | Round toward plus infinity | 0 | 1 |
  1355. | Round toward negative infinity | 1 | 0 |
  1356. | Round toward zero | 1 | 1 |
  1357. +---------------------------------+---+---+
  1358. *)
  1359. function taicpu.GetString:string;
  1360. var
  1361. i : longint;
  1362. s : string;
  1363. addsize : boolean;
  1364. begin
  1365. s:='['+gas_op2str[opcode];
  1366. for i:=0 to ops-1 do
  1367. begin
  1368. with oper[i]^ do
  1369. begin
  1370. if i=0 then
  1371. s:=s+' '
  1372. else
  1373. s:=s+',';
  1374. { type }
  1375. addsize:=false;
  1376. if (ot and OT_VREG)=OT_VREG then
  1377. s:=s+'vreg'
  1378. else
  1379. if (ot and OT_FPUREG)=OT_FPUREG then
  1380. s:=s+'fpureg'
  1381. else
  1382. if (ot and OT_REGISTER)=OT_REGISTER then
  1383. begin
  1384. s:=s+'reg';
  1385. addsize:=true;
  1386. end
  1387. else
  1388. if (ot and OT_REGLIST)=OT_REGLIST then
  1389. begin
  1390. s:=s+'reglist';
  1391. addsize:=false;
  1392. end
  1393. else
  1394. if (ot and OT_IMMEDIATE)=OT_IMMEDIATE then
  1395. begin
  1396. s:=s+'imm';
  1397. addsize:=true;
  1398. end
  1399. else
  1400. if (ot and OT_MEMORY)=OT_MEMORY then
  1401. begin
  1402. s:=s+'mem';
  1403. addsize:=true;
  1404. if (ot and OT_AM2)<>0 then
  1405. s:=s+' am2 ';
  1406. end
  1407. else
  1408. s:=s+'???';
  1409. { size }
  1410. if addsize then
  1411. begin
  1412. if (ot and OT_BITS8)<>0 then
  1413. s:=s+'8'
  1414. else
  1415. if (ot and OT_BITS16)<>0 then
  1416. s:=s+'24'
  1417. else
  1418. if (ot and OT_BITS32)<>0 then
  1419. s:=s+'32'
  1420. else
  1421. if (ot and OT_BITSSHIFTER)<>0 then
  1422. s:=s+'shifter'
  1423. else
  1424. s:=s+'??';
  1425. { signed }
  1426. if (ot and OT_SIGNED)<>0 then
  1427. s:=s+'s';
  1428. end;
  1429. end;
  1430. end;
  1431. GetString:=s+']';
  1432. end;
  1433. procedure taicpu.ResetPass1;
  1434. begin
  1435. { we need to reset everything here, because the choosen insentry
  1436. can be invalid for a new situation where the previously optimized
  1437. insentry is not correct }
  1438. InsEntry:=nil;
  1439. InsSize:=0;
  1440. LastInsOffset:=-1;
  1441. end;
  1442. procedure taicpu.ResetPass2;
  1443. begin
  1444. { we are here in a second pass, check if the instruction can be optimized }
  1445. if assigned(InsEntry) and
  1446. ((InsEntry^.flags and IF_PASS2)<>0) then
  1447. begin
  1448. InsEntry:=nil;
  1449. InsSize:=0;
  1450. end;
  1451. LastInsOffset:=-1;
  1452. end;
  1453. function taicpu.CheckIfValid:boolean;
  1454. begin
  1455. Result:=False; { unimplemented }
  1456. end;
  1457. function taicpu.Pass1(objdata:TObjData):longint;
  1458. var
  1459. ldr2op : array[PF_B..PF_T] of tasmop = (
  1460. A_LDRB,A_LDRSB,A_LDRBT,A_LDRH,A_LDRSH,A_LDRT);
  1461. str2op : array[PF_B..PF_T] of tasmop = (
  1462. A_STRB,A_None,A_STRBT,A_STRH,A_None,A_STRT);
  1463. begin
  1464. Pass1:=0;
  1465. { Save the old offset and set the new offset }
  1466. InsOffset:=ObjData.CurrObjSec.Size;
  1467. { Error? }
  1468. if (Insentry=nil) and (InsSize=-1) then
  1469. exit;
  1470. { set the file postion }
  1471. current_filepos:=fileinfo;
  1472. { tranlate LDR+postfix to complete opcode }
  1473. if (opcode=A_LDR) and (oppostfix<>PF_None) then
  1474. begin
  1475. if (oppostfix in [low(ldr2op)..high(ldr2op)]) then
  1476. opcode:=ldr2op[oppostfix]
  1477. else
  1478. internalerror(2005091001);
  1479. if opcode=A_None then
  1480. internalerror(2005091004);
  1481. { postfix has been added to opcode }
  1482. oppostfix:=PF_None;
  1483. end
  1484. else if (opcode=A_STR) and (oppostfix<>PF_None) then
  1485. begin
  1486. if (oppostfix in [low(str2op)..high(str2op)]) then
  1487. opcode:=str2op[oppostfix]
  1488. else
  1489. internalerror(2005091002);
  1490. if opcode=A_None then
  1491. internalerror(2005091003);
  1492. { postfix has been added to opcode }
  1493. oppostfix:=PF_None;
  1494. end;
  1495. { Get InsEntry }
  1496. if FindInsEntry(objdata) then
  1497. begin
  1498. InsSize:=4;
  1499. LastInsOffset:=InsOffset;
  1500. Pass1:=InsSize;
  1501. exit;
  1502. end;
  1503. LastInsOffset:=-1;
  1504. end;
  1505. procedure taicpu.Pass2(objdata:TObjData);
  1506. begin
  1507. { error in pass1 ? }
  1508. if insentry=nil then
  1509. exit;
  1510. current_filepos:=fileinfo;
  1511. { Generate the instruction }
  1512. GenCode(objdata);
  1513. end;
  1514. procedure taicpu.ppuloadoper(ppufile:tcompilerppufile;var o:toper);
  1515. begin
  1516. end;
  1517. procedure taicpu.ppuwriteoper(ppufile:tcompilerppufile;const o:toper);
  1518. begin
  1519. end;
  1520. procedure taicpu.ppubuildderefimploper(var o:toper);
  1521. begin
  1522. end;
  1523. procedure taicpu.ppuderefoper(var o:toper);
  1524. begin
  1525. end;
  1526. function taicpu.InsEnd:longint;
  1527. begin
  1528. Result:=0; { unimplemented }
  1529. end;
  1530. procedure taicpu.create_ot(objdata:TObjData);
  1531. var
  1532. i,l,relsize : longint;
  1533. dummy : byte;
  1534. currsym : TObjSymbol;
  1535. begin
  1536. if ops=0 then
  1537. exit;
  1538. { update oper[].ot field }
  1539. for i:=0 to ops-1 do
  1540. with oper[i]^ do
  1541. begin
  1542. case typ of
  1543. top_regset:
  1544. begin
  1545. ot:=OT_REGLIST;
  1546. end;
  1547. top_reg :
  1548. begin
  1549. case getregtype(reg) of
  1550. R_INTREGISTER:
  1551. ot:=OT_REG32 or OT_SHIFTEROP;
  1552. R_FPUREGISTER:
  1553. ot:=OT_FPUREG;
  1554. else
  1555. internalerror(2005090901);
  1556. end;
  1557. end;
  1558. top_ref :
  1559. begin
  1560. if ref^.refaddr=addr_no then
  1561. begin
  1562. { create ot field }
  1563. { we should get the size here dependend on the
  1564. instruction }
  1565. if (ot and OT_SIZE_MASK)=0 then
  1566. ot:=OT_MEMORY or OT_BITS32
  1567. else
  1568. ot:=OT_MEMORY or (ot and OT_SIZE_MASK);
  1569. if (ref^.base=NR_NO) and (ref^.index=NR_NO) then
  1570. ot:=ot or OT_MEM_OFFS;
  1571. { if we need to fix a reference, we do it here }
  1572. { pc relative addressing }
  1573. if (ref^.base=NR_NO) and
  1574. (ref^.index=NR_NO) and
  1575. (ref^.shiftmode=SM_None)
  1576. { at least we should check if the destination symbol
  1577. is in a text section }
  1578. { and
  1579. (ref^.symbol^.owner="text") } then
  1580. ref^.base:=NR_PC;
  1581. { determine possible address modes }
  1582. if (ref^.base<>NR_NO) and
  1583. (
  1584. (
  1585. (ref^.index=NR_NO) and
  1586. (ref^.shiftmode=SM_None) and
  1587. (ref^.offset>=-4097) and
  1588. (ref^.offset<=4097)
  1589. ) or
  1590. (
  1591. (ref^.shiftmode=SM_None) and
  1592. (ref^.offset=0)
  1593. ) or
  1594. (
  1595. (ref^.index<>NR_NO) and
  1596. (ref^.shiftmode<>SM_None) and
  1597. (ref^.shiftimm<=31) and
  1598. (ref^.offset=0)
  1599. )
  1600. ) then
  1601. ot:=ot or OT_AM2;
  1602. if (ref^.index<>NR_NO) and
  1603. (oppostfix in [PF_IA,PF_IB,PF_DA,PF_DB,PF_FD,PF_FA,PF_ED,PF_EA]) and
  1604. (
  1605. (ref^.base=NR_NO) and
  1606. (ref^.shiftmode=SM_None) and
  1607. (ref^.offset=0)
  1608. ) then
  1609. ot:=ot or OT_AM4;
  1610. end
  1611. else
  1612. begin
  1613. l:=ref^.offset;
  1614. currsym:=ObjData.symbolref(ref^.symbol);
  1615. if assigned(currsym) then
  1616. inc(l,currsym.address);
  1617. relsize:=(InsOffset+2)-l;
  1618. if (relsize<-33554428) or (relsize>33554428) then
  1619. ot:=OT_IMM32
  1620. else
  1621. ot:=OT_IMM24;
  1622. end;
  1623. end;
  1624. top_local :
  1625. begin
  1626. { we should get the size here dependend on the
  1627. instruction }
  1628. if (ot and OT_SIZE_MASK)=0 then
  1629. ot:=OT_MEMORY or OT_BITS32
  1630. else
  1631. ot:=OT_MEMORY or (ot and OT_SIZE_MASK);
  1632. end;
  1633. top_const :
  1634. begin
  1635. ot:=OT_IMMEDIATE;
  1636. if is_shifter_const(val,dummy) then
  1637. ot:=OT_IMMSHIFTER
  1638. else
  1639. ot:=OT_IMM32
  1640. end;
  1641. top_none :
  1642. begin
  1643. { generated when there was an error in the
  1644. assembler reader. It never happends when generating
  1645. assembler }
  1646. end;
  1647. top_shifterop:
  1648. begin
  1649. ot:=OT_SHIFTEROP;
  1650. end;
  1651. else
  1652. internalerror(200402261);
  1653. end;
  1654. end;
  1655. end;
  1656. function taicpu.Matches(p:PInsEntry):longint;
  1657. { * IF_SM stands for Size Match: any operand whose size is not
  1658. * explicitly specified by the template is `really' intended to be
  1659. * the same size as the first size-specified operand.
  1660. * Non-specification is tolerated in the input instruction, but
  1661. * _wrong_ specification is not.
  1662. *
  1663. * IF_SM2 invokes Size Match on only the first _two_ operands, for
  1664. * three-operand instructions such as SHLD: it implies that the
  1665. * first two operands must match in size, but that the third is
  1666. * required to be _unspecified_.
  1667. *
  1668. * IF_SB invokes Size Byte: operands with unspecified size in the
  1669. * template are really bytes, and so no non-byte specification in
  1670. * the input instruction will be tolerated. IF_SW similarly invokes
  1671. * Size Word, and IF_SD invokes Size Doubleword.
  1672. *
  1673. * (The default state if neither IF_SM nor IF_SM2 is specified is
  1674. * that any operand with unspecified size in the template is
  1675. * required to have unspecified size in the instruction too...)
  1676. }
  1677. var
  1678. i{,j,asize,oprs} : longint;
  1679. {siz : array[0..3] of longint;}
  1680. begin
  1681. Matches:=100;
  1682. writeln(getstring,'---');
  1683. { Check the opcode and operands }
  1684. if (p^.opcode<>opcode) or (p^.ops<>ops) then
  1685. begin
  1686. Matches:=0;
  1687. exit;
  1688. end;
  1689. { Check that no spurious colons or TOs are present }
  1690. for i:=0 to p^.ops-1 do
  1691. if (oper[i]^.ot and (not p^.optypes[i]) and (OT_COLON or OT_TO))<>0 then
  1692. begin
  1693. Matches:=0;
  1694. exit;
  1695. end;
  1696. { Check that the operand flags all match up }
  1697. for i:=0 to p^.ops-1 do
  1698. begin
  1699. if ((p^.optypes[i] and (not oper[i]^.ot)) or
  1700. ((p^.optypes[i] and OT_SIZE_MASK) and
  1701. ((p^.optypes[i] xor oper[i]^.ot) and OT_SIZE_MASK)))<>0 then
  1702. begin
  1703. if ((p^.optypes[i] and (not oper[i]^.ot) and OT_NON_SIZE) or
  1704. (oper[i]^.ot and OT_SIZE_MASK))<>0 then
  1705. begin
  1706. Matches:=0;
  1707. exit;
  1708. end
  1709. else
  1710. Matches:=1;
  1711. end;
  1712. end;
  1713. { check postfixes:
  1714. the existance of a certain postfix requires a
  1715. particular code }
  1716. { update condition flags
  1717. or floating point single }
  1718. if (oppostfix=PF_S) and
  1719. not(p^.code[0] in [#$04]) then
  1720. begin
  1721. Matches:=0;
  1722. exit;
  1723. end;
  1724. { floating point size }
  1725. if (oppostfix in [PF_D,PF_E,PF_P,PF_EP]) and
  1726. not(p^.code[0] in []) then
  1727. begin
  1728. Matches:=0;
  1729. exit;
  1730. end;
  1731. { multiple load/store address modes }
  1732. if (oppostfix in [PF_IA,PF_IB,PF_DA,PF_DB,PF_FD,PF_FA,PF_ED,PF_EA]) and
  1733. not(p^.code[0] in [
  1734. // ldr,str,ldrb,strb
  1735. #$17,
  1736. // stm,ldm
  1737. #$26
  1738. ]) then
  1739. begin
  1740. Matches:=0;
  1741. exit;
  1742. end;
  1743. { we shouldn't see any opsize prefixes here }
  1744. if (oppostfix in [PF_B,PF_SB,PF_BT,PF_H,PF_SH,PF_T]) then
  1745. begin
  1746. Matches:=0;
  1747. exit;
  1748. end;
  1749. if (roundingmode<>RM_None) and not(p^.code[0] in []) then
  1750. begin
  1751. Matches:=0;
  1752. exit;
  1753. end;
  1754. { Check operand sizes }
  1755. { as default an untyped size can get all the sizes, this is different
  1756. from nasm, but else we need to do a lot checking which opcodes want
  1757. size or not with the automatic size generation }
  1758. (*
  1759. asize:=longint($ffffffff);
  1760. if (p^.flags and IF_SB)<>0 then
  1761. asize:=OT_BITS8
  1762. else if (p^.flags and IF_SW)<>0 then
  1763. asize:=OT_BITS16
  1764. else if (p^.flags and IF_SD)<>0 then
  1765. asize:=OT_BITS32;
  1766. if (p^.flags and IF_ARMASK)<>0 then
  1767. begin
  1768. siz[0]:=0;
  1769. siz[1]:=0;
  1770. siz[2]:=0;
  1771. if (p^.flags and IF_AR0)<>0 then
  1772. siz[0]:=asize
  1773. else if (p^.flags and IF_AR1)<>0 then
  1774. siz[1]:=asize
  1775. else if (p^.flags and IF_AR2)<>0 then
  1776. siz[2]:=asize;
  1777. end
  1778. else
  1779. begin
  1780. { we can leave because the size for all operands is forced to be
  1781. the same
  1782. but not if IF_SB IF_SW or IF_SD is set PM }
  1783. if asize=-1 then
  1784. exit;
  1785. siz[0]:=asize;
  1786. siz[1]:=asize;
  1787. siz[2]:=asize;
  1788. end;
  1789. if (p^.flags and (IF_SM or IF_SM2))<>0 then
  1790. begin
  1791. if (p^.flags and IF_SM2)<>0 then
  1792. oprs:=2
  1793. else
  1794. oprs:=p^.ops;
  1795. for i:=0 to oprs-1 do
  1796. if ((p^.optypes[i] and OT_SIZE_MASK) <> 0) then
  1797. begin
  1798. for j:=0 to oprs-1 do
  1799. siz[j]:=p^.optypes[i] and OT_SIZE_MASK;
  1800. break;
  1801. end;
  1802. end
  1803. else
  1804. oprs:=2;
  1805. { Check operand sizes }
  1806. for i:=0 to p^.ops-1 do
  1807. begin
  1808. if ((p^.optypes[i] and OT_SIZE_MASK)=0) and
  1809. ((oper[i]^.ot and OT_SIZE_MASK and (not siz[i]))<>0) and
  1810. { Immediates can always include smaller size }
  1811. ((oper[i]^.ot and OT_IMMEDIATE)=0) and
  1812. (((p^.optypes[i] and OT_SIZE_MASK) or siz[i])<(oper[i]^.ot and OT_SIZE_MASK)) then
  1813. Matches:=2;
  1814. end;
  1815. *)
  1816. end;
  1817. function taicpu.calcsize(p:PInsEntry):shortint;
  1818. begin
  1819. result:=4;
  1820. end;
  1821. function taicpu.NeedAddrPrefix(opidx:byte):boolean;
  1822. begin
  1823. Result:=False; { unimplemented }
  1824. end;
  1825. procedure taicpu.Swapoperands;
  1826. begin
  1827. end;
  1828. function taicpu.FindInsentry(objdata:TObjData):boolean;
  1829. var
  1830. i : longint;
  1831. begin
  1832. result:=false;
  1833. { Things which may only be done once, not when a second pass is done to
  1834. optimize }
  1835. if (Insentry=nil) or ((InsEntry^.flags and IF_PASS2)<>0) then
  1836. begin
  1837. { create the .ot fields }
  1838. create_ot(objdata);
  1839. { set the file postion }
  1840. current_filepos:=fileinfo;
  1841. end
  1842. else
  1843. begin
  1844. { we've already an insentry so it's valid }
  1845. result:=true;
  1846. exit;
  1847. end;
  1848. { Lookup opcode in the table }
  1849. InsSize:=-1;
  1850. i:=instabcache^[opcode];
  1851. if i=-1 then
  1852. begin
  1853. Message1(asmw_e_opcode_not_in_table,gas_op2str[opcode]);
  1854. exit;
  1855. end;
  1856. insentry:=@instab[i];
  1857. while (insentry^.opcode=opcode) do
  1858. begin
  1859. if matches(insentry)=100 then
  1860. begin
  1861. result:=true;
  1862. exit;
  1863. end;
  1864. inc(i);
  1865. insentry:=@instab[i];
  1866. end;
  1867. Message1(asmw_e_invalid_opcode_and_operands,GetString);
  1868. { No instruction found, set insentry to nil and inssize to -1 }
  1869. insentry:=nil;
  1870. inssize:=-1;
  1871. end;
  1872. procedure taicpu.gencode(objdata:TObjData);
  1873. var
  1874. bytes : dword;
  1875. i_field : byte;
  1876. procedure setshifterop(op : byte);
  1877. begin
  1878. case oper[op]^.typ of
  1879. top_const:
  1880. begin
  1881. i_field:=1;
  1882. bytes:=bytes or dword(oper[op]^.val and $fff);
  1883. end;
  1884. top_reg:
  1885. begin
  1886. i_field:=0;
  1887. bytes:=bytes or (getsupreg(oper[op]^.reg) shl 16);
  1888. { does a real shifter op follow? }
  1889. if (op+1<=op) and (oper[op+1]^.typ=top_shifterop) then
  1890. begin
  1891. end;
  1892. end;
  1893. else
  1894. internalerror(2005091103);
  1895. end;
  1896. end;
  1897. begin
  1898. bytes:=$0;
  1899. i_field:=0;
  1900. { evaluate and set condition code }
  1901. { condition code allowed? }
  1902. { setup rest of the instruction }
  1903. case insentry^.code[0] of
  1904. #$08:
  1905. begin
  1906. { set instruction code }
  1907. bytes:=bytes or (ord(insentry^.code[1]) shl 26);
  1908. bytes:=bytes or (ord(insentry^.code[2]) shl 21);
  1909. { set destination }
  1910. bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
  1911. { create shifter op }
  1912. setshifterop(1);
  1913. { set i field }
  1914. bytes:=bytes or (i_field shl 25);
  1915. { set s if necessary }
  1916. if oppostfix=PF_S then
  1917. bytes:=bytes or (1 shl 20);
  1918. end;
  1919. #$ff:
  1920. internalerror(2005091101);
  1921. else
  1922. internalerror(2005091102);
  1923. end;
  1924. { we're finished, write code }
  1925. objdata.writebytes(bytes,sizeof(bytes));
  1926. end;
  1927. {$ifdef dummy}
  1928. (*
  1929. static void gencode (long segment, long offset, int bits,
  1930. insn *ins, char *codes, long insn_end)
  1931. {
  1932. int has_S_code; /* S - setflag */
  1933. int has_B_code; /* B - setflag */
  1934. int has_T_code; /* T - setflag */
  1935. int has_W_code; /* ! => W flag */
  1936. int has_F_code; /* ^ => S flag */
  1937. int keep;
  1938. unsigned char c;
  1939. unsigned char bytes[4];
  1940. long data, size;
  1941. static int cc_code[] = /* bit pattern of cc */
  1942. { /* order as enum in */
  1943. 0x0E, 0x03, 0x02, 0x00, /* nasm.h */
  1944. 0x0A, 0x0C, 0x08, 0x0D,
  1945. 0x09, 0x0B, 0x04, 0x01,
  1946. 0x05, 0x07, 0x06,
  1947. };
  1948. #ifdef DEBUG
  1949. static char *CC[] =
  1950. { /* condition code names */
  1951. "AL", "CC", "CS", "EQ",
  1952. "GE", "GT", "HI", "LE",
  1953. "LS", "LT", "MI", "NE",
  1954. "PL", "VC", "VS", "",
  1955. "S"
  1956. };
  1957. has_S_code = (ins->condition & C_SSETFLAG);
  1958. has_B_code = (ins->condition & C_BSETFLAG);
  1959. has_T_code = (ins->condition & C_TSETFLAG);
  1960. has_W_code = (ins->condition & C_EXSETFLAG);
  1961. has_F_code = (ins->condition & C_FSETFLAG);
  1962. ins->condition = (ins->condition & 0x0F);
  1963. if (rt_debug)
  1964. {
  1965. printf ("gencode: instruction: %s%s", insn_names[ins->opcode],
  1966. CC[ins->condition & 0x0F]);
  1967. if (has_S_code)
  1968. printf ("S");
  1969. if (has_B_code)
  1970. printf ("B");
  1971. if (has_T_code)
  1972. printf ("T");
  1973. if (has_W_code)
  1974. printf ("!");
  1975. if (has_F_code)
  1976. printf ("^");
  1977. printf ("\n");
  1978. c = *codes;
  1979. printf (" (%d) decode - '0x%02X'\n", ins->operands, c);
  1980. bytes[0] = 0xB;
  1981. bytes[1] = 0xE;
  1982. bytes[2] = 0xE;
  1983. bytes[3] = 0xF;
  1984. }
  1985. // First condition code in upper nibble
  1986. if (ins->condition < C_NONE)
  1987. {
  1988. c = cc_code[ins->condition] << 4;
  1989. }
  1990. else
  1991. {
  1992. c = cc_code[C_AL] << 4; // is often ALWAYS but not always
  1993. }
  1994. switch (keep = *codes)
  1995. {
  1996. case 1:
  1997. // B, BL
  1998. ++codes;
  1999. c |= *codes++;
  2000. bytes[0] = c;
  2001. if (ins->oprs[0].segment != segment)
  2002. {
  2003. // fais une relocation
  2004. c = 1;
  2005. data = 0; // Let the linker locate ??
  2006. }
  2007. else
  2008. {
  2009. c = 0;
  2010. data = ins->oprs[0].offset - (offset + 8);
  2011. if (data % 4)
  2012. {
  2013. errfunc (ERR_NONFATAL, "offset not aligned on 4 bytes");
  2014. }
  2015. }
  2016. if (data >= 0x1000)
  2017. {
  2018. errfunc (ERR_NONFATAL, "too long offset");
  2019. }
  2020. data = data >> 2;
  2021. bytes[1] = (data >> 16) & 0xFF;
  2022. bytes[2] = (data >> 8) & 0xFF;
  2023. bytes[3] = (data ) & 0xFF;
  2024. if (c == 1)
  2025. {
  2026. // out (offset, segment, &bytes[0], OUT_RAWDATA+1, NO_SEG, NO_SEG);
  2027. out (offset, segment, &bytes[0], OUT_REL3ADR+4, ins->oprs[0].segment, NO_SEG);
  2028. }
  2029. else
  2030. {
  2031. out (offset, segment, &bytes[0], OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2032. }
  2033. return;
  2034. case 2:
  2035. // SWI
  2036. ++codes;
  2037. c |= *codes++;
  2038. bytes[0] = c;
  2039. data = ins->oprs[0].offset;
  2040. bytes[1] = (data >> 16) & 0xFF;
  2041. bytes[2] = (data >> 8) & 0xFF;
  2042. bytes[3] = (data) & 0xFF;
  2043. out (offset, segment, &bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2044. return;
  2045. case 3:
  2046. // BX
  2047. ++codes;
  2048. c |= *codes++;
  2049. bytes[0] = c;
  2050. bytes[1] = *codes++;
  2051. bytes[2] = *codes++;
  2052. bytes[3] = *codes++;
  2053. c = regval (&ins->oprs[0],1);
  2054. if (c == 15) // PC
  2055. {
  2056. errfunc (ERR_WARNING, "'BX' with R15 has undefined behaviour");
  2057. }
  2058. else if (c > 15)
  2059. {
  2060. errfunc (ERR_NONFATAL, "Illegal register specified for 'BX'");
  2061. }
  2062. bytes[3] |= (c & 0x0F);
  2063. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2064. return;
  2065. case 4: // AND Rd,Rn,Rm
  2066. case 5: // AND Rd,Rn,Rm,<shift>Rs
  2067. case 6: // AND Rd,Rn,Rm,<shift>imm
  2068. case 7: // AND Rd,Rn,<shift>imm
  2069. ++codes;
  2070. #ifdef DEBUG
  2071. if (rt_debug)
  2072. {
  2073. printf (" decode - '0x%02X'\n", keep);
  2074. printf (" code - '0x%02X'\n", (unsigned char) ( *codes));
  2075. }
  2076. #endif
  2077. bytes[0] = c | *codes;
  2078. ++codes;
  2079. bytes[1] = *codes;
  2080. if (has_S_code)
  2081. bytes[1] |= 0x10;
  2082. c = regval (&ins->oprs[1],1);
  2083. // Rn in low nibble
  2084. bytes[1] |= c;
  2085. // Rd in high nibble
  2086. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2087. if (keep != 7)
  2088. {
  2089. // Rm in low nibble
  2090. bytes[3] = regval (&ins->oprs[2],1);
  2091. }
  2092. // Shifts if any
  2093. if (keep == 5 || keep == 6)
  2094. {
  2095. // Shift in bytes 2 and 3
  2096. if (keep == 5)
  2097. {
  2098. // Rs
  2099. c = regval (&ins->oprs[3],1);
  2100. bytes[2] |= c;
  2101. c = 0x10; // Set bit 4 in byte[3]
  2102. }
  2103. if (keep == 6)
  2104. {
  2105. c = (ins->oprs[3].offset) & 0x1F;
  2106. // #imm
  2107. bytes[2] |= c >> 1;
  2108. if (c & 0x01)
  2109. {
  2110. bytes[3] |= 0x80;
  2111. }
  2112. c = 0; // Clr bit 4 in byte[3]
  2113. }
  2114. // <shift>
  2115. c |= shiftval (&ins->oprs[3]) << 5;
  2116. bytes[3] |= c;
  2117. }
  2118. // reg,reg,imm
  2119. if (keep == 7)
  2120. {
  2121. int shimm;
  2122. shimm = imm_shift (ins->oprs[2].offset);
  2123. if (shimm == -1)
  2124. {
  2125. errfunc (ERR_NONFATAL, "cannot create that constant");
  2126. }
  2127. bytes[3] = shimm & 0xFF;
  2128. bytes[2] |= (shimm & 0xF00) >> 8;
  2129. }
  2130. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2131. return;
  2132. case 8: // MOV Rd,Rm
  2133. case 9: // MOV Rd,Rm,<shift>Rs
  2134. case 0xA: // MOV Rd,Rm,<shift>imm
  2135. case 0xB: // MOV Rd,<shift>imm
  2136. ++codes;
  2137. #ifdef DEBUG
  2138. if (rt_debug)
  2139. {
  2140. printf (" decode - '0x%02X'\n", keep);
  2141. printf (" code - '0x%02X'\n", (unsigned char) ( *codes));
  2142. }
  2143. #endif
  2144. bytes[0] = c | *codes;
  2145. ++codes;
  2146. bytes[1] = *codes;
  2147. if (has_S_code)
  2148. bytes[1] |= 0x10;
  2149. // Rd in high nibble
  2150. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2151. if (keep != 0x0B)
  2152. {
  2153. // Rm in low nibble
  2154. bytes[3] = regval (&ins->oprs[1],1);
  2155. }
  2156. // Shifts if any
  2157. if (keep == 0x09 || keep == 0x0A)
  2158. {
  2159. // Shift in bytes 2 and 3
  2160. if (keep == 0x09)
  2161. {
  2162. // Rs
  2163. c = regval (&ins->oprs[2],1);
  2164. bytes[2] |= c;
  2165. c = 0x10; // Set bit 4 in byte[3]
  2166. }
  2167. if (keep == 0x0A)
  2168. {
  2169. c = (ins->oprs[2].offset) & 0x1F;
  2170. // #imm
  2171. bytes[2] |= c >> 1;
  2172. if (c & 0x01)
  2173. {
  2174. bytes[3] |= 0x80;
  2175. }
  2176. c = 0; // Clr bit 4 in byte[3]
  2177. }
  2178. // <shift>
  2179. c |= shiftval (&ins->oprs[2]) << 5;
  2180. bytes[3] |= c;
  2181. }
  2182. // reg,imm
  2183. if (keep == 0x0B)
  2184. {
  2185. int shimm;
  2186. shimm = imm_shift (ins->oprs[1].offset);
  2187. if (shimm == -1)
  2188. {
  2189. errfunc (ERR_NONFATAL, "cannot create that constant");
  2190. }
  2191. bytes[3] = shimm & 0xFF;
  2192. bytes[2] |= (shimm & 0xF00) >> 8;
  2193. }
  2194. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2195. return;
  2196. case 0xC: // CMP Rn,Rm
  2197. case 0xD: // CMP Rn,Rm,<shift>Rs
  2198. case 0xE: // CMP Rn,Rm,<shift>imm
  2199. case 0xF: // CMP Rn,<shift>imm
  2200. ++codes;
  2201. bytes[0] = c | *codes++;
  2202. bytes[1] = *codes;
  2203. // Implicit S code
  2204. bytes[1] |= 0x10;
  2205. c = regval (&ins->oprs[0],1);
  2206. // Rn in low nibble
  2207. bytes[1] |= c;
  2208. // No destination
  2209. bytes[2] = 0;
  2210. if (keep != 0x0B)
  2211. {
  2212. // Rm in low nibble
  2213. bytes[3] = regval (&ins->oprs[1],1);
  2214. }
  2215. // Shifts if any
  2216. if (keep == 0x0D || keep == 0x0E)
  2217. {
  2218. // Shift in bytes 2 and 3
  2219. if (keep == 0x0D)
  2220. {
  2221. // Rs
  2222. c = regval (&ins->oprs[2],1);
  2223. bytes[2] |= c;
  2224. c = 0x10; // Set bit 4 in byte[3]
  2225. }
  2226. if (keep == 0x0E)
  2227. {
  2228. c = (ins->oprs[2].offset) & 0x1F;
  2229. // #imm
  2230. bytes[2] |= c >> 1;
  2231. if (c & 0x01)
  2232. {
  2233. bytes[3] |= 0x80;
  2234. }
  2235. c = 0; // Clr bit 4 in byte[3]
  2236. }
  2237. // <shift>
  2238. c |= shiftval (&ins->oprs[2]) << 5;
  2239. bytes[3] |= c;
  2240. }
  2241. // reg,imm
  2242. if (keep == 0x0F)
  2243. {
  2244. int shimm;
  2245. shimm = imm_shift (ins->oprs[1].offset);
  2246. if (shimm == -1)
  2247. {
  2248. errfunc (ERR_NONFATAL, "cannot create that constant");
  2249. }
  2250. bytes[3] = shimm & 0xFF;
  2251. bytes[2] |= (shimm & 0xF00) >> 8;
  2252. }
  2253. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2254. return;
  2255. case 0x10: // MRS Rd,<psr>
  2256. ++codes;
  2257. bytes[0] = c | *codes++;
  2258. bytes[1] = *codes++;
  2259. // Rd
  2260. c = regval (&ins->oprs[0],1);
  2261. bytes[2] = c << 4;
  2262. bytes[3] = 0;
  2263. c = ins->oprs[1].basereg;
  2264. if (c == R_CPSR || c == R_SPSR)
  2265. {
  2266. if (c == R_SPSR)
  2267. {
  2268. bytes[1] |= 0x40;
  2269. }
  2270. }
  2271. else
  2272. {
  2273. errfunc (ERR_NONFATAL, "CPSR or SPSR expected");
  2274. }
  2275. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2276. return;
  2277. case 0x11: // MSR <psr>,Rm
  2278. case 0x12: // MSR <psrf>,Rm
  2279. case 0x13: // MSR <psrf>,#expression
  2280. ++codes;
  2281. bytes[0] = c | *codes++;
  2282. bytes[1] = *codes++;
  2283. bytes[2] = *codes;
  2284. if (keep == 0x11 || keep == 0x12)
  2285. {
  2286. // Rm
  2287. c = regval (&ins->oprs[1],1);
  2288. bytes[3] = c;
  2289. }
  2290. else
  2291. {
  2292. int shimm;
  2293. shimm = imm_shift (ins->oprs[1].offset);
  2294. if (shimm == -1)
  2295. {
  2296. errfunc (ERR_NONFATAL, "cannot create that constant");
  2297. }
  2298. bytes[3] = shimm & 0xFF;
  2299. bytes[2] |= (shimm & 0xF00) >> 8;
  2300. }
  2301. c = ins->oprs[0].basereg;
  2302. if ( keep == 0x11)
  2303. {
  2304. if ( c == R_CPSR || c == R_SPSR)
  2305. {
  2306. if ( c== R_SPSR)
  2307. {
  2308. bytes[1] |= 0x40;
  2309. }
  2310. }
  2311. else
  2312. {
  2313. errfunc (ERR_NONFATAL, "CPSR or SPSR expected");
  2314. }
  2315. }
  2316. else
  2317. {
  2318. if ( c == R_CPSR_FLG || c == R_SPSR_FLG)
  2319. {
  2320. if ( c== R_SPSR_FLG)
  2321. {
  2322. bytes[1] |= 0x40;
  2323. }
  2324. }
  2325. else
  2326. {
  2327. errfunc (ERR_NONFATAL, "CPSR_flg or SPSR_flg expected");
  2328. }
  2329. }
  2330. break;
  2331. case 0x14: // MUL Rd,Rm,Rs
  2332. case 0x15: // MULA Rd,Rm,Rs,Rn
  2333. ++codes;
  2334. bytes[0] = c | *codes++;
  2335. bytes[1] = *codes++;
  2336. bytes[3] = *codes;
  2337. // Rd
  2338. bytes[1] |= regval (&ins->oprs[0],1);
  2339. if (has_S_code)
  2340. bytes[1] |= 0x10;
  2341. // Rm
  2342. bytes[3] |= regval (&ins->oprs[1],1);
  2343. // Rs
  2344. bytes[2] = regval (&ins->oprs[2],1);
  2345. if (keep == 0x15)
  2346. {
  2347. bytes[2] |= regval (&ins->oprs[3],1) << 4;
  2348. }
  2349. break;
  2350. case 0x16: // SMLAL RdHi,RdLo,Rm,Rs
  2351. ++codes;
  2352. bytes[0] = c | *codes++;
  2353. bytes[1] = *codes++;
  2354. bytes[3] = *codes;
  2355. // RdHi
  2356. bytes[1] |= regval (&ins->oprs[1],1);
  2357. if (has_S_code)
  2358. bytes[1] |= 0x10;
  2359. // RdLo
  2360. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2361. // Rm
  2362. bytes[3] |= regval (&ins->oprs[2],1);
  2363. // Rs
  2364. bytes[2] |= regval (&ins->oprs[3],1);
  2365. break;
  2366. case 0x17: // LDR Rd, expression
  2367. ++codes;
  2368. bytes[0] = c | *codes++;
  2369. bytes[1] = *codes++;
  2370. // Rd
  2371. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2372. if (has_B_code)
  2373. bytes[1] |= 0x40;
  2374. if (has_T_code)
  2375. {
  2376. errfunc (ERR_NONFATAL, "'T' not allowed in pre-index mode");
  2377. }
  2378. if (has_W_code)
  2379. {
  2380. errfunc (ERR_NONFATAL, "'!' not allowed");
  2381. }
  2382. // Rn - implicit R15
  2383. bytes[1] |= 0xF;
  2384. if (ins->oprs[1].segment != segment)
  2385. {
  2386. errfunc (ERR_NONFATAL, "label not in same segment");
  2387. }
  2388. data = ins->oprs[1].offset - (offset + 8);
  2389. if (data < 0)
  2390. {
  2391. data = -data;
  2392. }
  2393. else
  2394. {
  2395. bytes[1] |= 0x80;
  2396. }
  2397. if (data >= 0x1000)
  2398. {
  2399. errfunc (ERR_NONFATAL, "too long offset");
  2400. }
  2401. bytes[2] |= ((data & 0xF00) >> 8);
  2402. bytes[3] = data & 0xFF;
  2403. break;
  2404. case 0x18: // LDR Rd, [Rn]
  2405. ++codes;
  2406. bytes[0] = c | *codes++;
  2407. bytes[1] = *codes++;
  2408. // Rd
  2409. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2410. if (has_B_code)
  2411. bytes[1] |= 0x40;
  2412. if (has_T_code)
  2413. {
  2414. bytes[1] |= 0x20; // write-back
  2415. }
  2416. else
  2417. {
  2418. bytes[0] |= 0x01; // implicit pre-index mode
  2419. }
  2420. if (has_W_code)
  2421. {
  2422. bytes[1] |= 0x20; // write-back
  2423. }
  2424. // Rn
  2425. c = regval (&ins->oprs[1],1);
  2426. bytes[1] |= c;
  2427. if (c == 0x15) // R15
  2428. data = -8;
  2429. else
  2430. data = 0;
  2431. if (data < 0)
  2432. {
  2433. data = -data;
  2434. }
  2435. else
  2436. {
  2437. bytes[1] |= 0x80;
  2438. }
  2439. bytes[2] |= ((data & 0xF00) >> 8);
  2440. bytes[3] = data & 0xFF;
  2441. break;
  2442. case 0x19: // LDR Rd, [Rn,#expression]
  2443. case 0x20: // LDR Rd, [Rn,Rm]
  2444. case 0x21: // LDR Rd, [Rn,Rm,shift]
  2445. ++codes;
  2446. bytes[0] = c | *codes++;
  2447. bytes[1] = *codes++;
  2448. // Rd
  2449. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2450. if (has_B_code)
  2451. bytes[1] |= 0x40;
  2452. // Rn
  2453. c = regval (&ins->oprs[1],1);
  2454. bytes[1] |= c;
  2455. if (ins->oprs[ins->operands-1].bracket) // FIXME: Bracket on last operand -> pre-index <--
  2456. {
  2457. bytes[0] |= 0x01; // pre-index mode
  2458. if (has_W_code)
  2459. {
  2460. bytes[1] |= 0x20;
  2461. }
  2462. if (has_T_code)
  2463. {
  2464. errfunc (ERR_NONFATAL, "'T' not allowed in pre-index mode");
  2465. }
  2466. }
  2467. else
  2468. {
  2469. if (has_T_code) // Forced write-back in post-index mode
  2470. {
  2471. bytes[1] |= 0x20;
  2472. }
  2473. if (has_W_code)
  2474. {
  2475. errfunc (ERR_NONFATAL, "'!' not allowed in post-index mode");
  2476. }
  2477. }
  2478. if (keep == 0x19)
  2479. {
  2480. data = ins->oprs[2].offset;
  2481. if (data < 0)
  2482. {
  2483. data = -data;
  2484. }
  2485. else
  2486. {
  2487. bytes[1] |= 0x80;
  2488. }
  2489. if (data >= 0x1000)
  2490. {
  2491. errfunc (ERR_NONFATAL, "too long offset");
  2492. }
  2493. bytes[2] |= ((data & 0xF00) >> 8);
  2494. bytes[3] = data & 0xFF;
  2495. }
  2496. else
  2497. {
  2498. if (ins->oprs[2].minus == 0)
  2499. {
  2500. bytes[1] |= 0x80;
  2501. }
  2502. c = regval (&ins->oprs[2],1);
  2503. bytes[3] = c;
  2504. if (keep == 0x21)
  2505. {
  2506. c = ins->oprs[3].offset;
  2507. if (c > 0x1F)
  2508. {
  2509. errfunc (ERR_NONFATAL, "too large shiftvalue");
  2510. c = c & 0x1F;
  2511. }
  2512. bytes[2] |= c >> 1;
  2513. if (c & 0x01)
  2514. {
  2515. bytes[3] |= 0x80;
  2516. }
  2517. bytes[3] |= shiftval (&ins->oprs[3]) << 5;
  2518. }
  2519. }
  2520. break;
  2521. case 0x22: // LDRH Rd, expression
  2522. ++codes;
  2523. bytes[0] = c | 0x01; // Implicit pre-index
  2524. bytes[1] = *codes++;
  2525. // Rd
  2526. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2527. // Rn - implicit R15
  2528. bytes[1] |= 0xF;
  2529. if (ins->oprs[1].segment != segment)
  2530. {
  2531. errfunc (ERR_NONFATAL, "label not in same segment");
  2532. }
  2533. data = ins->oprs[1].offset - (offset + 8);
  2534. if (data < 0)
  2535. {
  2536. data = -data;
  2537. }
  2538. else
  2539. {
  2540. bytes[1] |= 0x80;
  2541. }
  2542. if (data >= 0x100)
  2543. {
  2544. errfunc (ERR_NONFATAL, "too long offset");
  2545. }
  2546. bytes[3] = *codes++;
  2547. bytes[2] |= ((data & 0xF0) >> 4);
  2548. bytes[3] |= data & 0xF;
  2549. break;
  2550. case 0x23: // LDRH Rd, Rn
  2551. ++codes;
  2552. bytes[0] = c | 0x01; // Implicit pre-index
  2553. bytes[1] = *codes++;
  2554. // Rd
  2555. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2556. // Rn
  2557. c = regval (&ins->oprs[1],1);
  2558. bytes[1] |= c;
  2559. if (c == 0x15) // R15
  2560. data = -8;
  2561. else
  2562. data = 0;
  2563. if (data < 0)
  2564. {
  2565. data = -data;
  2566. }
  2567. else
  2568. {
  2569. bytes[1] |= 0x80;
  2570. }
  2571. if (data >= 0x100)
  2572. {
  2573. errfunc (ERR_NONFATAL, "too long offset");
  2574. }
  2575. bytes[3] = *codes++;
  2576. bytes[2] |= ((data & 0xF0) >> 4);
  2577. bytes[3] |= data & 0xF;
  2578. break;
  2579. case 0x24: // LDRH Rd, Rn, expression
  2580. case 0x25: // LDRH Rd, Rn, Rm
  2581. ++codes;
  2582. bytes[0] = c;
  2583. bytes[1] = *codes++;
  2584. // Rd
  2585. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2586. // Rn
  2587. c = regval (&ins->oprs[1],1);
  2588. bytes[1] |= c;
  2589. if (ins->oprs[ins->operands-1].bracket) // FIXME: Bracket on last operand -> pre-index <--
  2590. {
  2591. bytes[0] |= 0x01; // pre-index mode
  2592. if (has_W_code)
  2593. {
  2594. bytes[1] |= 0x20;
  2595. }
  2596. }
  2597. else
  2598. {
  2599. if (has_W_code)
  2600. {
  2601. errfunc (ERR_NONFATAL, "'!' not allowed in post-index mode");
  2602. }
  2603. }
  2604. bytes[3] = *codes++;
  2605. if (keep == 0x24)
  2606. {
  2607. data = ins->oprs[2].offset;
  2608. if (data < 0)
  2609. {
  2610. data = -data;
  2611. }
  2612. else
  2613. {
  2614. bytes[1] |= 0x80;
  2615. }
  2616. if (data >= 0x100)
  2617. {
  2618. errfunc (ERR_NONFATAL, "too long offset");
  2619. }
  2620. bytes[2] |= ((data & 0xF0) >> 4);
  2621. bytes[3] |= data & 0xF;
  2622. }
  2623. else
  2624. {
  2625. if (ins->oprs[2].minus == 0)
  2626. {
  2627. bytes[1] |= 0x80;
  2628. }
  2629. c = regval (&ins->oprs[2],1);
  2630. bytes[3] |= c;
  2631. }
  2632. break;
  2633. case 0x26: // LDM/STM Rn, {reg-list}
  2634. ++codes;
  2635. bytes[0] = c;
  2636. bytes[0] |= ( *codes >> 4) & 0xF;
  2637. bytes[1] = ( *codes << 4) & 0xF0;
  2638. ++codes;
  2639. if (has_W_code)
  2640. {
  2641. bytes[1] |= 0x20;
  2642. }
  2643. if (has_F_code)
  2644. {
  2645. bytes[1] |= 0x40;
  2646. }
  2647. // Rn
  2648. bytes[1] |= regval (&ins->oprs[0],1);
  2649. data = ins->oprs[1].basereg;
  2650. bytes[2] = ((data >> 8) & 0xFF);
  2651. bytes[3] = (data & 0xFF);
  2652. break;
  2653. case 0x27: // SWP Rd, Rm, [Rn]
  2654. ++codes;
  2655. bytes[0] = c;
  2656. bytes[0] |= *codes++;
  2657. bytes[1] = regval (&ins->oprs[2],1);
  2658. if (has_B_code)
  2659. {
  2660. bytes[1] |= 0x40;
  2661. }
  2662. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2663. bytes[3] = *codes++;
  2664. bytes[3] |= regval (&ins->oprs[1],1);
  2665. break;
  2666. default:
  2667. errfunc (ERR_FATAL, "unknown decoding of instruction");
  2668. bytes[0] = c;
  2669. // And a fix nibble
  2670. ++codes;
  2671. bytes[0] |= *codes++;
  2672. if ( *codes == 0x01) // An I bit
  2673. {
  2674. }
  2675. if ( *codes == 0x02) // An I bit
  2676. {
  2677. }
  2678. ++codes;
  2679. }
  2680. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2681. }
  2682. *)
  2683. {$endif dummy}
  2684. constructor tai_thumb_func.create;
  2685. begin
  2686. inherited create;
  2687. typ:=ait_thumb_func;
  2688. end;
  2689. begin
  2690. cai_align:=tai_align;
  2691. end.