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aasmcpu.pas
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4664e510e6
* RiscV: handle more instructions in taicpu.spilling_get_operation_type
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5 months ago |
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agrvgas.pas
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da6c0e919b
+ RiscV: rv32gcb
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5 months ago |
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aoptcpurv.pas
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860a2d0145
- disable Slti0B2B as well
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5 months ago |
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cgrv.pas
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b2f6214b33
+ a_bit_scan_reg_reg gets a flag if src cannot be zero: this simplifies the generated code
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6 months ago |
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cpubase.pas
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5bb4049737
* remove accidently committed debug statement
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7 months ago |
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hlcgrv.pas
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637976e83f
* patch by Marģers to unify internal error numbers, resolves #37888
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4 years ago |
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itcpugas.pas
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971d97c179
+ RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0
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7 months ago |
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nrvadd.pas
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95c2a5a2d7
+ RiscV: support ZMMUL extension
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6 months ago |
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nrvcnv.pas
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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7 years ago |
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nrvcon.pas
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f417c87ec8
* RiscV: check for cpu capabilities before using fmv for loading zero
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7 months ago |
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nrvinl.pas
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7aae7a8d51
+ min/max optimization support for RiscV
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7 months ago |
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nrvmat.pas
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c3110dfaa9
+ RiscV: make use of the fneg.* instruction
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7 months ago |
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nrvset.pas
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ccae78f97a
+ RiscV64: apply OptPass1OP also to addiw
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9 months ago |
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nrvutil.pas
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fecd25bac1
* fix typo
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5 months ago |
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pararv.pas
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b7608b045b
* RiscV: push_addr_param unified
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7 months ago |
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rarv.pas
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d1fb44044f
* unified RiscV32 and RiscV64 GAS readers
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4 years ago |
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rarvgas.pas
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a05aa25aad
* Risc-V: allow also register aliases in register modification lists after asm blocks, last part to resolve #39738
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3 years ago |
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rgcpu.pas
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92b0ea7d02
Add explicit smallint typecast to first marameter of SarSmallint call to avoid range check errors
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5 years ago |
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rvreg.dat
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8d0bdf2f16
+ RiscV: vector registers
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7 months ago |
florian
860a2d0145
- disable Slti0B2B as well