cpuinfo.pas 27 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122
  1. {
  2. Copyright (c) 1998-2002 by the Free Pascal development team
  3. Basic Processor information for the ARM
  4. See the file COPYING.FPC, included in this distribution,
  5. for details about the copyright.
  6. This program is distributed in the hope that it will be useful,
  7. but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  9. **********************************************************************}
  10. Unit CPUInfo;
  11. Interface
  12. uses
  13. globtype;
  14. Type
  15. bestreal = double;
  16. ts32real = single;
  17. ts64real = double;
  18. ts80real = type extended;
  19. ts128real = type extended;
  20. ts64comp = comp;
  21. pbestreal=^bestreal;
  22. { possible supported processors for this target }
  23. tcputype =
  24. (cpu_none,
  25. cpu_armv3,
  26. cpu_armv4,
  27. cpu_armv4t,
  28. cpu_armv5,
  29. cpu_armv5t,
  30. cpu_armv5te,
  31. cpu_armv6,
  32. cpu_armv7,
  33. cpu_armv7m
  34. );
  35. Const
  36. cpu_arm = [cpu_none,cpu_armv3,cpu_armv4,cpu_armv4t,cpu_armv5];
  37. cpu_thumb = [];
  38. cpu_thumb2 = [cpu_armv7m];
  39. Type
  40. tfputype =
  41. (fpu_none,
  42. fpu_soft,
  43. fpu_libgcc,
  44. fpu_fpa,
  45. fpu_fpa10,
  46. fpu_fpa11,
  47. fpu_vfpv2,
  48. fpu_vfpv3,
  49. fpu_vfpv3_d16
  50. );
  51. tcontrollertype =
  52. (ct_none,
  53. { Phillips }
  54. ct_lpc2114,
  55. ct_lpc2124,
  56. ct_lpc2194,
  57. ct_lpc1754,
  58. ct_lpc1756,
  59. ct_lpc1758,
  60. ct_lpc1764,
  61. ct_lpc1766,
  62. ct_lpc1768,
  63. { ATMEL }
  64. ct_at91sam7s256,
  65. ct_at91sam7se256,
  66. ct_at91sam7x256,
  67. ct_at91sam7xc256,
  68. { STMicroelectronics }
  69. ct_stm32f103rb,
  70. ct_stm32f103re,
  71. ct_stm32f103c4t,
  72. { TI - Fury Class - 64 K Flash, 16 K SRAM Devices }
  73. ct_lm3s1110,
  74. ct_lm3s1133,
  75. ct_lm3s1138,
  76. ct_lm3s1150,
  77. ct_lm3s1162,
  78. ct_lm3s1165,
  79. ct_lm3s1166,
  80. ct_lm3s2110,
  81. ct_lm3s2139,
  82. ct_lm3s6100,
  83. ct_lm3s6110,
  84. { TI - Fury Class - 128K Flash, 32K SRAM devices }
  85. ct_lm3s1601,
  86. ct_lm3s1608,
  87. ct_lm3s1620,
  88. ct_lm3s1635,
  89. ct_lm3s1636,
  90. ct_lm3s1637,
  91. ct_lm3s1651,
  92. ct_lm3s2601,
  93. ct_lm3s2608,
  94. ct_lm3s2620,
  95. ct_lm3s2637,
  96. ct_lm3s2651,
  97. ct_lm3s6610,
  98. ct_lm3s6611,
  99. ct_lm3s6618,
  100. ct_lm3s6633,
  101. ct_lm3s6637,
  102. ct_lm3s8630,
  103. { TI - Fury Class - 256K Flash, 64K SRAM devices }
  104. ct_lm3s1911,
  105. ct_lm3s1918,
  106. ct_lm3s1937,
  107. ct_lm3s1958,
  108. ct_lm3s1960,
  109. ct_lm3s1968,
  110. ct_lm3s1969,
  111. ct_lm3s2911,
  112. ct_lm3s2918,
  113. ct_lm3s2919,
  114. ct_lm3s2939,
  115. ct_lm3s2948,
  116. ct_lm3s2950,
  117. ct_lm3s2965,
  118. ct_lm3s6911,
  119. ct_lm3s6918,
  120. ct_lm3s6938,
  121. ct_lm3s6950,
  122. ct_lm3s6952,
  123. ct_lm3s6965,
  124. ct_lm3s8930,
  125. ct_lm3s8933,
  126. ct_lm3s8938,
  127. ct_lm3s8962,
  128. ct_lm3s8970,
  129. ct_lm3s8971,
  130. { TI - Tempest Tempest - 256 K Flash, 64 K SRAM }
  131. ct_lm3s5951,
  132. ct_lm3s5956,
  133. ct_lm3s1b21,
  134. ct_lm3s2b93,
  135. ct_lm3s5b91,
  136. ct_lm3s9b81,
  137. ct_lm3s9b90,
  138. ct_lm3s9b92,
  139. ct_lm3s9b95,
  140. ct_lm3s9b96,
  141. { SAMSUNG }
  142. ct_sc32442b,
  143. // generic Thumb2 target
  144. ct_thumb2bare
  145. );
  146. Const
  147. {# Size of native extended floating point type }
  148. extended_size = 12;
  149. {# Size of a multimedia register }
  150. mmreg_size = 16;
  151. { target cpu string (used by compiler options) }
  152. target_cpu_string = 'arm';
  153. { calling conventions supported by the code generator }
  154. supported_calling_conventions : tproccalloptions = [
  155. pocall_internproc,
  156. pocall_safecall,
  157. pocall_stdcall,
  158. { same as stdcall only different name mangling }
  159. pocall_cdecl,
  160. { same as stdcall only different name mangling }
  161. pocall_cppdecl,
  162. { same as stdcall but floating point numbers are handled like equal sized integers }
  163. pocall_softfloat,
  164. { same as stdcall (requires that all const records are passed by
  165. reference, but that's already done for stdcall) }
  166. pocall_mwpascal,
  167. { used for interrupt handling }
  168. pocall_interrupt
  169. ];
  170. cputypestr : array[tcputype] of string[8] = ('',
  171. 'ARMV3',
  172. 'ARMV4',
  173. 'ARMV4T',
  174. 'ARMV5',
  175. 'ARMV5T',
  176. 'ARMV5TE',
  177. 'ARMV6',
  178. 'ARMV7',
  179. 'ARMV7M'
  180. );
  181. fputypestr : array[tfputype] of string[9] = ('',
  182. 'SOFT',
  183. 'LIBGCC',
  184. 'FPA',
  185. 'FPA10',
  186. 'FPA11',
  187. 'VFPV2',
  188. 'VFPV3',
  189. 'VFPV3_D16'
  190. );
  191. { We know that there are fields after sramsize
  192. but we don't care about this warning }
  193. {$WARN 3177 OFF}
  194. embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
  195. ((
  196. controllertypestr:'';
  197. controllerunitstr:'';
  198. interruptvectors:0;
  199. flashbase:0;
  200. flashsize:0;
  201. srambase:0;
  202. sramsize:0
  203. ),
  204. (
  205. controllertypestr:'LPC2114';
  206. controllerunitstr:'LPC21x4';
  207. interruptvectors:8;
  208. flashbase:$00000000;
  209. flashsize:$00040000;
  210. srambase:$40000000;
  211. sramsize:$00004000
  212. ),
  213. (
  214. controllertypestr:'LPC2124';
  215. controllerunitstr:'LPC21x4';
  216. interruptvectors:8;
  217. flashbase:$00000000;
  218. flashsize:$00040000;
  219. srambase:$40000000;
  220. sramsize:$00004000
  221. ),
  222. (
  223. controllertypestr:'LPC2194';
  224. controllerunitstr:'LPC21x4';
  225. interruptvectors:8;
  226. flashbase:$00000000;
  227. flashsize:$00040000;
  228. srambase:$40000000;
  229. sramsize:$00004000
  230. ),
  231. (
  232. controllertypestr:'LPC1754';
  233. controllerunitstr:'LPC1754';
  234. interruptvectors:12;
  235. flashbase:$00000000;
  236. flashsize:$00020000;
  237. srambase:$10000000;
  238. sramsize:$00004000
  239. ),
  240. (
  241. controllertypestr:'LPC1756';
  242. controllerunitstr:'LPC1756';
  243. interruptvectors:12;
  244. flashbase:$00000000;
  245. flashsize:$00040000;
  246. srambase:$10000000;
  247. sramsize:$00004000
  248. ),
  249. (
  250. controllertypestr:'LPC1758';
  251. controllerunitstr:'LPC1758';
  252. interruptvectors:12;
  253. flashbase:$00000000;
  254. flashsize:$00080000;
  255. srambase:$10000000;
  256. sramsize:$00008000
  257. ),
  258. (
  259. controllertypestr:'LPC1764';
  260. controllerunitstr:'LPC1764';
  261. interruptvectors:12;
  262. flashbase:$00000000;
  263. flashsize:$00020000;
  264. srambase:$10000000;
  265. sramsize:$00004000
  266. ),
  267. (
  268. controllertypestr:'LPC1766';
  269. controllerunitstr:'LPC1766';
  270. interruptvectors:12;
  271. flashbase:$00000000;
  272. flashsize:$00040000;
  273. srambase:$10000000;
  274. sramsize:$00008000
  275. ),
  276. (
  277. controllertypestr:'LPC1768';
  278. controllerunitstr:'LPC1768';
  279. interruptvectors:12;
  280. flashbase:$00000000;
  281. flashsize:$00080000;
  282. srambase:$10000000;
  283. sramsize:$00008000
  284. ),
  285. (
  286. controllertypestr:'AT91SAM7S256';
  287. controllerunitstr:'AT91SAM7x256';
  288. interruptvectors:8;
  289. flashbase:$00000000;
  290. flashsize:$00040000;
  291. srambase:$00200000;
  292. sramsize:$00010000
  293. ),
  294. (
  295. controllertypestr:'AT91SAM7SE256';
  296. controllerunitstr:'AT91SAM7x256';
  297. interruptvectors:8;
  298. flashbase:$00000000;
  299. flashsize:$00040000;
  300. srambase:$00200000;
  301. sramsize:$00010000
  302. ),
  303. (
  304. controllertypestr:'AT91SAM7X256';
  305. controllerunitstr:'AT91SAM7x256';
  306. interruptvectors:8;
  307. flashbase:$00000000;
  308. flashsize:$00040000;
  309. srambase:$00200000;
  310. sramsize:$00010000
  311. ),
  312. (
  313. controllertypestr:'AT91SAM7XC256';
  314. controllerunitstr:'AT91SAM7x256';
  315. interruptvectors:8;
  316. flashbase:$00000000;
  317. flashsize:$00040000;
  318. srambase:$00200000;
  319. sramsize:$00010000
  320. ),
  321. // ct_stm32f103rb,
  322. (
  323. controllertypestr:'STM32F103RB';
  324. controllerunitstr:'STM32F103';
  325. interruptvectors:12;
  326. flashbase:$08000000;
  327. flashsize:$00020000;
  328. srambase:$20000000;
  329. sramsize:$00005000
  330. ),
  331. // ct_stm32f103re,
  332. (
  333. controllertypestr:'STM32F103RE';
  334. controllerunitstr:'STM32F103';
  335. interruptvectors:12;
  336. flashbase:$08000000;
  337. flashsize:$00080000;
  338. srambase:$20000000;
  339. sramsize:$00010000
  340. ),
  341. // ct_stm32f103re,
  342. (
  343. controllertypestr:'STM32F103C4T';
  344. controllerunitstr:'STM32F103';
  345. interruptvectors:12;
  346. flashbase:$08000000;
  347. flashsize:$00004000;
  348. srambase:$20000000;
  349. sramsize:$00001800
  350. ),
  351. { TI - 64 K Flash, 16 K SRAM Devices }
  352. // ct_lm3s1110,
  353. (
  354. controllertypestr:'LM3S1110';
  355. controllerunitstr:'LM3FURY';
  356. interruptvectors:72;
  357. flashbase:$00000000;
  358. flashsize:$00010000;
  359. srambase:$20000000;
  360. sramsize:$00004000
  361. ),
  362. // ct_lm3s1133,
  363. (
  364. controllertypestr:'LM3S1133';
  365. controllerunitstr:'LM3FURY';
  366. interruptvectors:72;
  367. flashbase:$00000000;
  368. flashsize:$00010000;
  369. srambase:$20000000;
  370. sramsize:$00004000
  371. ),
  372. // ct_lm3s1138,
  373. (
  374. controllertypestr:'LM3S1138';
  375. controllerunitstr:'LM3FURY';
  376. interruptvectors:72;
  377. flashbase:$00000000;
  378. flashsize:$00010000;
  379. srambase:$20000000;
  380. sramsize:$00004000
  381. ),
  382. // ct_lm3s1150,
  383. (
  384. controllertypestr:'LM3S1150';
  385. controllerunitstr:'LM3FURY';
  386. interruptvectors:72;
  387. flashbase:$00000000;
  388. flashsize:$00010000;
  389. srambase:$20000000;
  390. sramsize:$00004000
  391. ),
  392. // ct_lm3s1162,
  393. (
  394. controllertypestr:'LM3S1162';
  395. controllerunitstr:'LM3FURY';
  396. interruptvectors:72;
  397. flashbase:$00000000;
  398. flashsize:$00010000;
  399. srambase:$20000000;
  400. sramsize:$00004000
  401. ),
  402. // ct_lm3s1165,
  403. (
  404. controllertypestr:'LM3S1165';
  405. controllerunitstr:'LM3FURY';
  406. interruptvectors:72;
  407. flashbase:$00000000;
  408. flashsize:$00010000;
  409. srambase:$20000000;
  410. sramsize:$00004000
  411. ),
  412. // ct_lm3s1166,
  413. (
  414. controllertypestr:'LM3S1166';
  415. controllerunitstr:'LM3FURY';
  416. interruptvectors:72;
  417. flashbase:$00000000;
  418. flashsize:$00010000;
  419. srambase:$20000000;
  420. sramsize:$00004000
  421. ),
  422. // ct_lm3s2110,
  423. (
  424. controllertypestr:'LM3S2110';
  425. controllerunitstr:'LM3FURY';
  426. interruptvectors:72;
  427. flashbase:$00000000;
  428. flashsize:$00010000;
  429. srambase:$20000000;
  430. sramsize:$00004000
  431. ),
  432. // ct_lm3s2139,
  433. (
  434. controllertypestr:'LM3S2139';
  435. controllerunitstr:'LM3FURY';
  436. interruptvectors:72;
  437. flashbase:$00000000;
  438. flashsize:$00010000;
  439. srambase:$20000000;
  440. sramsize:$00004000
  441. ),
  442. // ct_lm3s6100,
  443. (
  444. controllertypestr:'LM3S6100';
  445. controllerunitstr:'LM3FURY';
  446. interruptvectors:72;
  447. flashbase:$00000000;
  448. flashsize:$00010000;
  449. srambase:$20000000;
  450. sramsize:$00004000
  451. ),
  452. // ct_lm3s6110,
  453. (
  454. controllertypestr:'LM3S6110';
  455. controllerunitstr:'LM3FURY';
  456. interruptvectors:72;
  457. flashbase:$00000000;
  458. flashsize:$00010000;
  459. srambase:$20000000;
  460. sramsize:$00004000
  461. ),
  462. { TI - 128K Flash, 32K SRAM devices }
  463. // ct_lm3s1601,
  464. (
  465. controllertypestr:'LM3S1601';
  466. controllerunitstr:'LM3FURY';
  467. interruptvectors:72;
  468. flashbase:$00000000;
  469. flashsize:$00020000;
  470. srambase:$20000000;
  471. sramsize:$00008000
  472. ),
  473. // ct_lm3s1608,
  474. (
  475. controllertypestr:'LM3S1608';
  476. controllerunitstr:'LM3FURY';
  477. interruptvectors:72;
  478. flashbase:$00000000;
  479. flashsize:$00020000;
  480. srambase:$20000000;
  481. sramsize:$00008000
  482. ),
  483. // ct_lm3s1620,
  484. (
  485. controllertypestr:'LM3S1620';
  486. controllerunitstr:'LM3FURY';
  487. interruptvectors:72;
  488. flashbase:$00000000;
  489. flashsize:$00020000;
  490. srambase:$20000000;
  491. sramsize:$00008000
  492. ),
  493. // ct_lm3s1635,
  494. (
  495. controllertypestr:'LM3S1635';
  496. controllerunitstr:'LM3FURY';
  497. interruptvectors:72;
  498. flashbase:$00000000;
  499. flashsize:$00020000;
  500. srambase:$20000000;
  501. sramsize:$00008000
  502. ),
  503. // ct_lm3s1636,
  504. (
  505. controllertypestr:'LM3S1636';
  506. controllerunitstr:'LM3FURY';
  507. interruptvectors:72;
  508. flashbase:$00000000;
  509. flashsize:$00020000;
  510. srambase:$20000000;
  511. sramsize:$00008000
  512. ),
  513. // ct_lm3s1637,
  514. (
  515. controllertypestr:'LM3S1637';
  516. controllerunitstr:'LM3FURY';
  517. interruptvectors:72;
  518. flashbase:$00000000;
  519. flashsize:$00020000;
  520. srambase:$20000000;
  521. sramsize:$00008000
  522. ),
  523. // ct_lm3s1651,
  524. (
  525. controllertypestr:'LM3S1651';
  526. controllerunitstr:'LM3FURY';
  527. interruptvectors:72;
  528. flashbase:$00000000;
  529. flashsize:$00020000;
  530. srambase:$20000000;
  531. sramsize:$00008000
  532. ),
  533. // ct_lm3s2601,
  534. (
  535. controllertypestr:'LM3S2601';
  536. controllerunitstr:'LM3FURY';
  537. interruptvectors:72;
  538. flashbase:$00000000;
  539. flashsize:$00020000;
  540. srambase:$20000000;
  541. sramsize:$00008000
  542. ),
  543. // ct_lm3s2608,
  544. (
  545. controllertypestr:'LM3S2608';
  546. controllerunitstr:'LM3FURY';
  547. interruptvectors:72;
  548. flashbase:$00000000;
  549. flashsize:$00020000;
  550. srambase:$20000000;
  551. sramsize:$00008000
  552. ),
  553. // ct_lm3s2620,
  554. (
  555. controllertypestr:'LM3S2620';
  556. controllerunitstr:'LM3FURY';
  557. interruptvectors:72;
  558. flashbase:$00000000;
  559. flashsize:$00020000;
  560. srambase:$20000000;
  561. sramsize:$00008000
  562. ),
  563. // ct_lm3s2637,
  564. (
  565. controllertypestr:'LM3S2637';
  566. controllerunitstr:'LM3FURY';
  567. interruptvectors:72;
  568. flashbase:$00000000;
  569. flashsize:$00020000;
  570. srambase:$20000000;
  571. sramsize:$00008000
  572. ),
  573. // ct_lm3s2651,
  574. (
  575. controllertypestr:'LM3S2651';
  576. controllerunitstr:'LM3FURY';
  577. interruptvectors:72;
  578. flashbase:$00000000;
  579. flashsize:$00020000;
  580. srambase:$20000000;
  581. sramsize:$00008000
  582. ),
  583. // ct_lm3s6610,
  584. (
  585. controllertypestr:'LM3S6610';
  586. controllerunitstr:'LM3FURY';
  587. interruptvectors:72;
  588. flashbase:$00000000;
  589. flashsize:$00020000;
  590. srambase:$20000000;
  591. sramsize:$00008000
  592. ),
  593. // ct_lm3s6611,
  594. (
  595. controllertypestr:'LM3S6611';
  596. controllerunitstr:'LM3FURY';
  597. interruptvectors:72;
  598. flashbase:$00000000;
  599. flashsize:$00020000;
  600. srambase:$20000000;
  601. sramsize:$00008000
  602. ),
  603. // ct_lm3s6618,
  604. (
  605. controllertypestr:'LM3S6618';
  606. controllerunitstr:'LM3FURY';
  607. interruptvectors:72;
  608. flashbase:$00000000;
  609. flashsize:$00020000;
  610. srambase:$20000000;
  611. sramsize:$00008000
  612. ),
  613. // ct_lm3s6633,
  614. (
  615. controllertypestr:'LM3S6633';
  616. controllerunitstr:'LM3FURY';
  617. interruptvectors:72;
  618. flashbase:$00000000;
  619. flashsize:$00020000;
  620. srambase:$20000000;
  621. sramsize:$00008000
  622. ),
  623. // ct_lm3s6637,
  624. (
  625. controllertypestr:'LM3S6637';
  626. controllerunitstr:'LM3FURY';
  627. interruptvectors:72;
  628. flashbase:$00000000;
  629. flashsize:$00020000;
  630. srambase:$20000000;
  631. sramsize:$00008000
  632. ),
  633. // ct_lm3s8630,
  634. (
  635. controllertypestr:'LM3S8630';
  636. controllerunitstr:'LM3FURY';
  637. interruptvectors:72;
  638. flashbase:$00000000;
  639. flashsize:$00020000;
  640. srambase:$20000000;
  641. sramsize:$00008000
  642. ),
  643. { TI - 256K Flash, 64K SRAM devices }
  644. // ct_lm3s1911,
  645. (
  646. controllertypestr:'LM3S1911';
  647. controllerunitstr:'LM3FURY';
  648. interruptvectors:72;
  649. flashbase:$00000000;
  650. flashsize:$00040000;
  651. srambase:$20000000;
  652. sramsize:$00010000
  653. ),
  654. // ct_lm3s1918,
  655. (
  656. controllertypestr:'LM3S1918';
  657. controllerunitstr:'LM3FURY';
  658. interruptvectors:72;
  659. flashbase:$00000000;
  660. flashsize:$00040000;
  661. srambase:$20000000;
  662. sramsize:$00010000
  663. ),
  664. // ct_lm3s1937,
  665. (
  666. controllertypestr:'LM3S1937';
  667. controllerunitstr:'LM3FURY';
  668. interruptvectors:72;
  669. flashbase:$00000000;
  670. flashsize:$00040000;
  671. srambase:$20000000;
  672. sramsize:$00010000
  673. ),
  674. // ct_lm3s1958,
  675. (
  676. controllertypestr:'LM3S1958';
  677. controllerunitstr:'LM3FURY';
  678. interruptvectors:72;
  679. flashbase:$00000000;
  680. flashsize:$00040000;
  681. srambase:$20000000;
  682. sramsize:$00010000
  683. ),
  684. // ct_lm3s1960,
  685. (
  686. controllertypestr:'LM3S1960';
  687. controllerunitstr:'LM3FURY';
  688. interruptvectors:72;
  689. flashbase:$00000000;
  690. flashsize:$00040000;
  691. srambase:$20000000;
  692. sramsize:$00010000
  693. ),
  694. // ct_lm3s1968,
  695. (
  696. controllertypestr:'LM3S1968';
  697. controllerunitstr:'LM3FURY';
  698. interruptvectors:72;
  699. flashbase:$00000000;
  700. flashsize:$00040000;
  701. srambase:$20000000;
  702. sramsize:$00010000
  703. ),
  704. // ct_lm3s1969,
  705. (
  706. controllertypestr:'LM3S1969';
  707. controllerunitstr:'LM3FURY';
  708. interruptvectors:72;
  709. flashbase:$00000000;
  710. flashsize:$00040000;
  711. srambase:$20000000;
  712. sramsize:$00010000
  713. ),
  714. // ct_lm3s2911,
  715. (
  716. controllertypestr:'LM3S2911';
  717. controllerunitstr:'LM3FURY';
  718. interruptvectors:72;
  719. flashbase:$00000000;
  720. flashsize:$00040000;
  721. srambase:$20000000;
  722. sramsize:$00010000
  723. ),
  724. // ct_lm3s2918,
  725. (
  726. controllertypestr:'LM3S2918';
  727. controllerunitstr:'LM3FURY';
  728. interruptvectors:72;
  729. flashbase:$00000000;
  730. flashsize:$00040000;
  731. srambase:$20000000;
  732. sramsize:$00010000
  733. ),
  734. // ct_lm3s2919,
  735. (
  736. controllertypestr:'LM3S2919';
  737. controllerunitstr:'LM3FURY';
  738. interruptvectors:72;
  739. flashbase:$00000000;
  740. flashsize:$00040000;
  741. srambase:$20000000;
  742. sramsize:$00010000
  743. ),
  744. // ct_lm3s2939,
  745. (
  746. controllertypestr:'LM3S2939';
  747. controllerunitstr:'LM3FURY';
  748. interruptvectors:72;
  749. flashbase:$00000000;
  750. flashsize:$00040000;
  751. srambase:$20000000;
  752. sramsize:$00010000
  753. ),
  754. // ct_lm3s2948,
  755. (
  756. controllertypestr:'LM3S2948';
  757. controllerunitstr:'LM3FURY';
  758. interruptvectors:72;
  759. flashbase:$00000000;
  760. flashsize:$00040000;
  761. srambase:$20000000;
  762. sramsize:$00010000
  763. ),
  764. // ct_lm3s2950,
  765. (
  766. controllertypestr:'LM3S2950';
  767. controllerunitstr:'LM3FURY';
  768. interruptvectors:72;
  769. flashbase:$00000000;
  770. flashsize:$00040000;
  771. srambase:$20000000;
  772. sramsize:$00010000
  773. ),
  774. // ct_lm3s2965,
  775. (
  776. controllertypestr:'LM3S2965';
  777. controllerunitstr:'LM3FURY';
  778. interruptvectors:72;
  779. flashbase:$00000000;
  780. flashsize:$00040000;
  781. srambase:$20000000;
  782. sramsize:$00010000
  783. ),
  784. // ct_lm3s6911,
  785. (
  786. controllertypestr:'LM3S6911';
  787. controllerunitstr:'LM3FURY';
  788. interruptvectors:72;
  789. flashbase:$00000000;
  790. flashsize:$00040000;
  791. srambase:$20000000;
  792. sramsize:$00010000
  793. ),
  794. // ct_lm3s6918,
  795. (
  796. controllertypestr:'LM3S6918';
  797. controllerunitstr:'LM3FURY';
  798. interruptvectors:72;
  799. flashbase:$00000000;
  800. flashsize:$00040000;
  801. srambase:$20000000;
  802. sramsize:$00010000
  803. ),
  804. // ct_lm3s6938,
  805. (
  806. controllertypestr:'LM3S6938';
  807. controllerunitstr:'LM3FURY';
  808. interruptvectors:72;
  809. flashbase:$00000000;
  810. flashsize:$00040000;
  811. srambase:$20000000;
  812. sramsize:$00010000
  813. ),
  814. // ct_lm3s6950,
  815. (
  816. controllertypestr:'LM3S6950';
  817. controllerunitstr:'LM3FURY';
  818. interruptvectors:72;
  819. flashbase:$00000000;
  820. flashsize:$00040000;
  821. srambase:$20000000;
  822. sramsize:$00010000
  823. ),
  824. // ct_lm3s6952,
  825. (
  826. controllertypestr:'LM3S6952';
  827. controllerunitstr:'LM3FURY';
  828. interruptvectors:72;
  829. flashbase:$00000000;
  830. flashsize:$00040000;
  831. srambase:$20000000;
  832. sramsize:$00010000
  833. ),
  834. // ct_lm3s6965,
  835. (
  836. controllertypestr:'LM3S6965';
  837. controllerunitstr:'LM3FURY';
  838. interruptvectors:72;
  839. flashbase:$00000000;
  840. flashsize:$00040000;
  841. srambase:$20000000;
  842. sramsize:$00010000
  843. ),
  844. // ct_lm3s8930,
  845. (
  846. controllertypestr:'LM3S8930';
  847. controllerunitstr:'LM3FURY';
  848. interruptvectors:72;
  849. flashbase:$00000000;
  850. flashsize:$00040000;
  851. srambase:$20000000;
  852. sramsize:$00010000
  853. ),
  854. // ct_lm3s8933,
  855. (
  856. controllertypestr:'LM3S8933';
  857. controllerunitstr:'LM3FURY';
  858. interruptvectors:72;
  859. flashbase:$00000000;
  860. flashsize:$00040000;
  861. srambase:$20000000;
  862. sramsize:$00010000
  863. ),
  864. // ct_lm3s8938,
  865. (
  866. controllertypestr:'LM3S8938';
  867. controllerunitstr:'LM3FURY';
  868. interruptvectors:72;
  869. flashbase:$00000000;
  870. flashsize:$00040000;
  871. srambase:$20000000;
  872. sramsize:$00010000
  873. ),
  874. // ct_lm3s8962,
  875. (
  876. controllertypestr:'LM3S8962';
  877. controllerunitstr:'LM3FURY';
  878. interruptvectors:72;
  879. flashbase:$00000000;
  880. flashsize:$00040000;
  881. srambase:$20000000;
  882. sramsize:$00010000
  883. ),
  884. // ct_lm3s8970,
  885. (
  886. controllertypestr:'LM3S8970';
  887. controllerunitstr:'LM3FURY';
  888. interruptvectors:72;
  889. flashbase:$00000000;
  890. flashsize:$00040000;
  891. srambase:$20000000;
  892. sramsize:$00010000
  893. ),
  894. // ct_lm3s8971,
  895. (
  896. controllertypestr:'LM3S8971';
  897. controllerunitstr:'LM3FURY';
  898. interruptvectors:72;
  899. flashbase:$00000000;
  900. flashsize:$00040000;
  901. srambase:$20000000;
  902. sramsize:$00010000
  903. ),
  904. { TI - Tempest parts - 256 K Flash, 64 K SRAM }
  905. // ct_lm3s5951,
  906. (
  907. controllertypestr:'LM3S5951';
  908. controllerunitstr:'LM3TEMPEST';
  909. interruptvectors:72;
  910. flashbase:$00000000;
  911. flashsize:$00040000;
  912. srambase:$20000000;
  913. sramsize:$00010000
  914. ),
  915. // ct_lm3s5956,
  916. (
  917. controllertypestr:'LM3S5956';
  918. controllerunitstr:'LM3TEMPEST';
  919. interruptvectors:72;
  920. flashbase:$00000000;
  921. flashsize:$00040000;
  922. srambase:$20000000;
  923. sramsize:$00010000
  924. ),
  925. // ct_lm3s1b21,
  926. (
  927. controllertypestr:'LM3S1B21';
  928. controllerunitstr:'LM3TEMPEST';
  929. interruptvectors:72;
  930. flashbase:$00000000;
  931. flashsize:$00040000;
  932. srambase:$20000000;
  933. sramsize:$00010000
  934. ),
  935. // ct_lm3s2b93,
  936. (
  937. controllertypestr:'LM3S2B93';
  938. controllerunitstr:'LM3TEMPEST';
  939. interruptvectors:72;
  940. flashbase:$00000000;
  941. flashsize:$00040000;
  942. srambase:$20000000;
  943. sramsize:$00010000
  944. ),
  945. // ct_lm3s5b91,
  946. (
  947. controllertypestr:'LM3S5B91';
  948. controllerunitstr:'LM3TEMPEST';
  949. interruptvectors:72;
  950. flashbase:$00000000;
  951. flashsize:$00040000;
  952. srambase:$20000000;
  953. sramsize:$00010000
  954. ),
  955. // ct_lm3s9b81,
  956. (
  957. controllertypestr:'LM3S9B81';
  958. controllerunitstr:'LM3TEMPEST';
  959. interruptvectors:72;
  960. flashbase:$00000000;
  961. flashsize:$00040000;
  962. srambase:$20000000;
  963. sramsize:$00010000
  964. ),
  965. // ct_lm3s9b90,
  966. (
  967. controllertypestr:'LM3S9B90';
  968. controllerunitstr:'LM3TEMPEST';
  969. interruptvectors:72;
  970. flashbase:$00000000;
  971. flashsize:$00040000;
  972. srambase:$20000000;
  973. sramsize:$00010000
  974. ),
  975. // ct_lm3s9b92,
  976. (
  977. controllertypestr:'LM3S9B92';
  978. controllerunitstr:'LM3TEMPEST';
  979. interruptvectors:72;
  980. flashbase:$00000000;
  981. flashsize:$00040000;
  982. srambase:$20000000;
  983. sramsize:$00010000
  984. ),
  985. // ct_lm3s9b95,
  986. (
  987. controllertypestr:'LM3S9B95';
  988. controllerunitstr:'LM3TEMPEST';
  989. interruptvectors:72;
  990. flashbase:$00000000;
  991. flashsize:$00040000;
  992. srambase:$20000000;
  993. sramsize:$00010000
  994. ),
  995. // ct_lm3s9b96,
  996. (
  997. controllertypestr:'LM3S9B96';
  998. controllerunitstr:'LM3TEMPEST';
  999. interruptvectors:72;
  1000. flashbase:$00000000;
  1001. flashsize:$00040000;
  1002. srambase:$20000000;
  1003. sramsize:$00010000
  1004. ),
  1005. //ct_SC32442b,
  1006. (
  1007. controllertypestr:'SC32442B';
  1008. controllerunitstr:'sc32442b';
  1009. interruptvectors:7;
  1010. flashbase:$00000000;
  1011. flashsize:$00000000;
  1012. srambase:$00000000;
  1013. sramsize:$08000000
  1014. ),
  1015. // bare bones Thumb2
  1016. (
  1017. controllertypestr:'THUMB2_BARE';
  1018. controllerunitstr:'THUMB2_BARE';
  1019. interruptvectors:128;
  1020. flashbase:$00000000;
  1021. flashsize:$00100000;
  1022. srambase:$20000000;
  1023. sramsize:$00100000
  1024. )
  1025. );
  1026. vfp_scalar = [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16];
  1027. { Supported optimizations, only used for information }
  1028. supported_optimizerswitches = genericlevel1optimizerswitches+
  1029. genericlevel2optimizerswitches+
  1030. genericlevel3optimizerswitches-
  1031. { no need to write info about those }
  1032. [cs_opt_level1,cs_opt_level2,cs_opt_level3]+
  1033. [cs_opt_regvar,cs_opt_loopunroll,cs_opt_tailrecursion,
  1034. cs_opt_stackframe,cs_opt_nodecse,cs_opt_reorder_fields,cs_opt_fastmath];
  1035. level1optimizerswitches = genericlevel1optimizerswitches;
  1036. level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
  1037. [cs_opt_regvar,cs_opt_stackframe,cs_opt_tailrecursion,cs_opt_nodecse {,cs_opt_scheduler}];
  1038. level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{,cs_opt_loopunroll}];
  1039. level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
  1040. type
  1041. tcpuflags =
  1042. (CPUARM_HAS_BX,
  1043. CPUARM_HAS_BLX,
  1044. CPUARM_HAS_LDRDSTRD,
  1045. CPUARM_HAS_PLD,
  1046. CPUARM_HAS_REV,
  1047. CPUARM_HAS_LDREX,
  1048. CPUARM_HAS_IDIV
  1049. );
  1050. const
  1051. cpu_capabilities : array[tcputype] of set of tcpuflags =
  1052. ( { cpu_none } [],
  1053. { cpu_armv3 } [],
  1054. { cpu_armv4 } [],
  1055. { cpu_armv4t } [CPUARM_HAS_BX],
  1056. { cpu_armv5 } [CPUARM_HAS_BX,CPUARM_HAS_BLX],
  1057. { cpu_armv5t } [CPUARM_HAS_BX,CPUARM_HAS_BLX],
  1058. { cpu_armv5te } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_LDRDSTRD,CPUARM_HAS_PLD],
  1059. { cpu_armv6 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_LDRDSTRD,CPUARM_HAS_PLD,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  1060. { cpu_armv7 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_LDRDSTRD,CPUARM_HAS_PLD,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  1061. { cpu_armv7m } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_LDRDSTRD,CPUARM_HAS_PLD,CPUARM_HAS_REV,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV]
  1062. );
  1063. Implementation
  1064. end.