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aasmcpu.pas
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e23ed15634
* MIPS: reworked and fixed procedure fixup_jmps:
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9 years ago |
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aoptcpu.pas
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41751bc5b4
+ Next portion of MIPS peephole optimizations. Get more aggressive and do more than a single pass if needed, enabling optimization of instructions that logically turn into MOVE due to register renaming.
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9 years ago |
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aoptcpub.pas
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93e0dd9c2f
* Patch from Fuxin Zhang: other mips and mipsel CPUs changes
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13 years ago |
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aoptcpud.pas
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0c8546f94c
* more MIPS code of David Zhang integrated
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15 years ago |
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cgcpu.pas
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5456960d54
* MIPS: Fixed code generation for PIC calls to local functions. Uncovered by r32803, before that the buggy branch was never taken because all functions were global.
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9 years ago |
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cpubase.pas
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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cpuelf.pas
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919cc8377a
+ added class type property CObjSymbol to TExeOutput as well
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10 years ago |
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cpugas.pas
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ed2488eb03
- MIPS: removed the ugly hack of splitting LDC1/SDC1 instructions into pairs of LWC1/SWC1 at assembler writer level. It probably was there as a workaround for insufficient alignment of double-precision variables, which was present once, but fixed a long time ago.
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9 years ago |
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cpuinfo.pas
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3cb9be73bc
Moved tcontrollerdatatype out into cpuinfo.
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10 years ago |
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cpunode.pas
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b57c95043f
+ support overriding tdef/tsym methods with target-specific functionality:
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11 years ago |
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cpupara.pas
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fa3b0ca312
* support marking defs created via the getreusable*() class methods as
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9 years ago |
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cpupi.pas
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96dd464bf2
* Moved fixup_jmps to target-specific classes for powerpc,powerpc64 and MIPS, cleaned out remaining $ifdef's. A slight functionality change is that fixup_jmps is now called before adding the procedure end symbol, not after, but that should not matter.
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11 years ago |
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cputarg.pas
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b2b26f84cf
* partially merged the mips-embedded branch of Michael Ring:
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11 years ago |
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hlcgcpu.pas
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b745dcc64c
* moved g_external_wrapper() to the hlcg, and also g_intf_wrapper() because
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11 years ago |
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itcpugas.pas
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11a9ff4a43
* Removed unused vars for mipsel compiler.
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10 years ago |
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mipsreg.dat
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e367ccc0ee
* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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11 years ago |
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ncpuadd.pas
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11a9ff4a43
* Removed unused vars for mipsel compiler.
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10 years ago |
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ncpucall.pas
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87684e1cf1
* MIPS: clean up
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11 years ago |
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ncpucnv.pas
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0fc1fd6ac1
* replaced current_procinfo.currtrue/falselabel with storing the true/false
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10 years ago |
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ncpuinln.pas
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4065483a50
* completed thlcgobj.location_force_fpureg(), use it everywhere and removed
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11 years ago |
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ncpuld.pas
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4b820a1ca5
- Removed tcgloadnode.generate_picvaraccess, it is never used and is not necessary because PIC stuff is handled at lower levels.
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12 years ago |
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ncpumat.pas
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7949bebb8d
* synchronised with r28168 of trunk
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11 years ago |
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ncpuset.pas
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11a9ff4a43
* Removed unused vars for mipsel compiler.
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10 years ago |
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opcode.inc
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4e7c908b0d
+ MIPS: added movn and movz instructions.
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11 years ago |
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racpugas.pas
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55492a0f30
* Don't do useless string case conversions in a loop.
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9 years ago |
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rgcpu.pas
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67b8aceaee
* synchronized with privatetrunk till r30095
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10 years ago |
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rmipscon.inc
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e367ccc0ee
* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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11 years ago |
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rmipsdwf.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsgas.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsgri.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsgss.inc
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f58fcdf401
+ basic mips stuff
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20 years ago |
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rmipsnor.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsnum.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsrni.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipssri.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipssta.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsstd.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipssup.inc
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e367ccc0ee
* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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11 years ago |
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strinst.inc
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4e7c908b0d
+ MIPS: added movn and movz instructions.
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11 years ago |
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symcpu.pas
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7dd1d6aa77
o fixes handling of iso i/o parameters/program parameters:
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10 years ago |
sergei
41751bc5b4
+ Next portion of MIPS peephole optimizations. Get more aggressive and do more than a single pass if needed, enabling optimization of instructions that logically turn into MOVE due to register renaming.