ncpuadd.pas 41 KB

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  1. {******************************************************************************
  2. $Id$
  3. Copyright (c) 2000-2002 by Florian Klaempfl
  4. Code generation for add nodes on the i386
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; IF not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************}
  17. unit ncpuadd;
  18. {$INCLUDE fpcdefs.inc}
  19. interface
  20. uses
  21. node,nadd,cpubase,cginfo;
  22. type
  23. TSparcAddNode=class(TAddNode)
  24. procedure pass_2;override;
  25. private
  26. procedure clear_left_right(cmpop:Boolean);
  27. procedure second_addboolean;
  28. procedure second_add64bit;
  29. procedure second_addfloat;
  30. function GetResFlags(unsigned:Boolean):TResFlags;
  31. procedure left_must_be_reg(OpSize:TOpSize;NoSwap:Boolean);
  32. procedure emit_generic_code(op:TAsmOp;OpSize:TOpSize;unsigned,extra_not,mboverflow:Boolean);
  33. procedure emit_op_right_left(op:TAsmOp);
  34. procedure Load_left_right(cmpop,load_constants:Boolean);
  35. procedure pass_left_and_right;
  36. procedure set_result_location(cmpOp,unsigned:Boolean);
  37. end;
  38. implementation
  39. uses
  40. globtype,systems,
  41. cutils,verbose,globals,
  42. symconst,symdef,SymType,paramgr,
  43. aasmbase,aasmtai,aasmcpu,defutil,htypechk,
  44. cgbase,pass_2,regvars,
  45. cpupara,
  46. ncon,nset,
  47. ncgutil,tgobj,rgobj,rgcpu,cgobj,cg64f32;
  48. const
  49. opsize_2_cgSize:array[S_B..S_L]of TCgSize=(OS_8,OS_16,OS_32);
  50. procedure TSparcAddNode.clear_left_right(cmpop:Boolean);
  51. begin
  52. if(right.location.loc in [LOC_REGISTER,LOC_FPUREGISTER])and(cmpop or(location.register.enum <> right.location.register.enum))
  53. then
  54. begin
  55. rg.ungetregister(exprasmlist,right.location.register);
  56. if is_64bitint(right.resulttype.def)
  57. then
  58. rg.ungetregister(exprasmlist,right.location.registerhigh);
  59. end;
  60. if(left.location.loc in [LOC_REGISTER,LOC_FPUREGISTER])and(cmpop or(location.register.enum <> left.location.register.enum))
  61. then
  62. begin
  63. rg.ungetregister(exprasmlist,left.location.register);
  64. if is_64bitint(left.resulttype.def)
  65. then
  66. rg.ungetregister(exprasmlist,left.location.registerhigh);
  67. end;
  68. end;
  69. procedure TSparcAddNode.second_addboolean;
  70. var
  71. cgop:TOpCg;
  72. cgsize:TCgSize;
  73. cmpop,isjump:boolean;
  74. otl,ofl:tasmlabel;
  75. pushedregs:TMaybeSave;
  76. begin
  77. { calculate the operator which is more difficult }
  78. firstcomplex(self);
  79. cmpop:=false;
  80. if (torddef(left.resulttype.def).typ=bool8bit) or
  81. (torddef(right.resulttype.def).typ=bool8bit)
  82. then
  83. cgsize:=OS_8
  84. else if (torddef(left.resulttype.def).typ=bool16bit) or
  85. (torddef(right.resulttype.def).typ=bool16bit)
  86. then
  87. cgsize:=OS_16
  88. else
  89. cgsize:=OS_32;
  90. if (cs_full_boolean_eval in aktlocalswitches) or
  91. (nodetype in [unequaln,ltn,lten,gtn,gten,equaln,xorn])
  92. then
  93. begin
  94. if left.nodetype in [ordconstn,realconstn]
  95. then
  96. swapleftright;
  97. isjump:=(left.location.loc=LOC_JUMP);
  98. if isjump
  99. then
  100. begin
  101. otl:=truelabel;
  102. objectlibrary.getlabel(truelabel);
  103. ofl:=falselabel;
  104. objectlibrary.getlabel(falselabel);
  105. end;
  106. secondpass(left);
  107. if left.location.loc in [LOC_FLAGS,LOC_JUMP]
  108. then
  109. location_force_reg(exprasmlist,left.location,cgsize,false);
  110. if isjump
  111. then
  112. begin
  113. truelabel:=otl;
  114. falselabel:=ofl;
  115. end;
  116. maybe_save(exprasmlist,right.registers32,left.location,pushedregs);
  117. isjump:=(right.location.loc=LOC_JUMP);
  118. if isjump
  119. then
  120. begin
  121. otl:=truelabel;
  122. objectlibrary.getlabel(truelabel);
  123. ofl:=falselabel;
  124. objectlibrary.getlabel(falselabel);
  125. end;
  126. secondpass(right);
  127. maybe_restore(exprasmlist,left.location,pushedregs);
  128. if right.location.loc in [LOC_FLAGS,LOC_JUMP]
  129. then
  130. location_force_reg(exprasmlist,right.location,cgsize,false);
  131. if isjump
  132. then
  133. begin
  134. truelabel:=otl;
  135. falselabel:=ofl;
  136. end;
  137. cmpop := nodetype in [ltn,lten,gtn,gten,equaln,unequaln];
  138. { set result location }
  139. if not cmpop
  140. then
  141. location_reset(location,LOC_REGISTER,def_cgsize(resulttype.def))
  142. else
  143. location_reset(location,LOC_FLAGS,OS_NO);
  144. load_left_right(cmpop,false);
  145. if (left.location.loc = LOC_CONSTANT)
  146. then
  147. swapleftright;
  148. { compare the }
  149. case nodetype of
  150. ltn,lten,gtn,gten,
  151. equaln,unequaln :
  152. begin
  153. if (right.location.loc <> LOC_CONSTANT)
  154. then
  155. exprasmlist.concat(taicpu.op_reg_reg(A_JMPL,left.location.register,right.location.register))
  156. else
  157. exprasmlist.concat(taicpu.op_reg_const(A_JMPL,left.location.register,longint(right.location.value)));
  158. location.resflags := GetResFlags(true);
  159. end;
  160. else
  161. begin
  162. case nodetype of
  163. xorn :
  164. cgop:=OP_XOR;
  165. orn :
  166. cgop:=OP_OR;
  167. andn :
  168. cgop:=OP_AND;
  169. else
  170. internalerror(200203247);
  171. end;
  172. if right.location.loc <> LOC_CONSTANT
  173. then
  174. cg.a_op_reg_reg_reg(exprasmlist,cgop,OS_INT,left.location.register,right.location.register,location.register)
  175. else
  176. cg.a_op_const_reg_reg(exprasmlist,cgop,OS_INT,right.location.value,left.location.register,location.register);
  177. end;
  178. end;
  179. end
  180. else
  181. begin
  182. // just to make sure we free the right registers
  183. cmpop := true;
  184. case nodetype of
  185. andn,
  186. orn :
  187. begin
  188. location_reset(location,LOC_JUMP,OS_NO);
  189. case nodetype of
  190. andn :
  191. begin
  192. otl:=truelabel;
  193. objectlibrary.getlabel(truelabel);
  194. secondpass(left);
  195. maketojumpbool(exprasmlist,left,lr_load_regvars);
  196. cg.a_label(exprasmlist,truelabel);
  197. truelabel:=otl;
  198. end;
  199. orn :
  200. begin
  201. ofl:=falselabel;
  202. objectlibrary.getlabel(falselabel);
  203. secondpass(left);
  204. maketojumpbool(exprasmlist,left,lr_load_regvars);
  205. cg.a_label(exprasmlist,falselabel);
  206. falselabel:=ofl;
  207. end;
  208. else
  209. CGMessage(type_e_mismatch);
  210. end;
  211. secondpass(right);
  212. maketojumpbool(exprasmlist,right,lr_load_regvars);
  213. end;
  214. end;
  215. end;
  216. clear_left_right(CmpOp);
  217. end;
  218. function TSparcAddNode.GetResFlags(unsigned:Boolean):TResFlags;
  219. begin
  220. case NodeType of
  221. equaln:
  222. GetResFlags:=F_E;
  223. unequaln:
  224. GetResFlags:=F_NE;
  225. else
  226. if not(unsigned)
  227. then
  228. if nf_swaped IN flags
  229. then
  230. case NodeType of
  231. ltn:
  232. GetResFlags:=F_G;
  233. lten:
  234. GetResFlags:=F_GE;
  235. gtn:
  236. GetResFlags:=F_L;
  237. gten:
  238. GetResFlags:=F_LE;
  239. end
  240. else
  241. case NodeType of
  242. ltn:
  243. GetResFlags:=F_L;
  244. lten:
  245. GetResFlags:=F_LE;
  246. gtn:
  247. GetResFlags:=F_G;
  248. gten:
  249. GetResFlags:=F_GE;
  250. end
  251. else
  252. if nf_swaped IN Flags
  253. then
  254. case NodeType of
  255. ltn:
  256. GetResFlags:=F_A;
  257. lten:
  258. GetResFlags:=F_AE;
  259. gtn:
  260. GetResFlags:=F_B;
  261. gten:
  262. GetResFlags:=F_BE;
  263. end
  264. else
  265. case NodeType of
  266. ltn:
  267. GetResFlags:=F_B;
  268. lten:
  269. GetResFlags:=F_BE;
  270. gtn:
  271. GetResFlags:=F_A;
  272. gten:
  273. GetResFlags:=F_AE;
  274. end;
  275. end;
  276. end;
  277. procedure TSparcAddNode.left_must_be_reg(OpSize:TOpSize;NoSwap:Boolean);
  278. begin
  279. if(left.location.loc=LOC_REGISTER)
  280. then
  281. exit;
  282. {left location is not a register}
  283. if(not NoSwap)and(right.location.loc=LOC_REGISTER)
  284. then{right is register so we can swap the locations}
  285. begin
  286. location_swap(left.location,right.location);
  287. toggleflag(nf_swaped);
  288. end
  289. else
  290. begin
  291. {maybe we can reuse a constant register when the operation is a comparison that
  292. doesn't change the value of the register}
  293. location_force_reg(exprasmlist,left.location,opsize_2_cgsize[opsize],(nodetype in [ltn,lten,gtn,gten,equaln,unequaln]));
  294. end;
  295. end;
  296. procedure TSparcAddNode.emit_generic_code(op:TAsmOp;OpSize:TOpSize;unsigned,extra_not,mboverflow:Boolean);
  297. VAR
  298. power:LongInt;
  299. hl4:TAsmLabel;
  300. begin
  301. { at this point, left.location.loc should be LOC_REGISTER }
  302. if right.location.loc=LOC_REGISTER
  303. then
  304. begin
  305. { right.location is a LOC_REGISTER }
  306. { when swapped another result register }
  307. if(nodetype=subn)and(nf_swaped in flags)
  308. then
  309. begin
  310. if extra_not
  311. then
  312. exprasmList.concat(Taicpu.Op_reg(A_NOT,left.location.register));
  313. exprasmList.concat(Taicpu.Op_reg_reg_reg(Op,right.location.register,left.location.register,right.location.register));
  314. { newly swapped also set swapped flag }
  315. location_swap(left.location,right.location);
  316. toggleflag(nf_swaped);
  317. end
  318. else
  319. begin
  320. if extra_not
  321. then
  322. exprasmList.concat(Taicpu.Op_reg(A_NOT,right.location.register));
  323. // emit_reg_reg(op,opsize,right.location.register,left.location.register);
  324. exprasmList.concat(Taicpu.Op_reg_reg_reg(Op,right.location.register,left.location.register,right.location.register));
  325. end;
  326. end
  327. ELSE
  328. begin
  329. { right.location is not a LOC_REGISTER }
  330. IF(nodetype=subn)AND(nf_swaped IN flags)
  331. THEN
  332. begin
  333. IF extra_not
  334. THEN
  335. exprasmList.concat(Taicpu.Op_reg(A_NOT,left.location.register));
  336. // rg.getexplicitregisterint(exprasmlist,R_EDI);
  337. // cg.a_load_loc_reg(exprasmlist,right.location,R_EDI);
  338. // emit_reg_reg(op,opsize,left.location.register,R_EDI);
  339. // emit_reg_reg(A_MOV,opsize,R_EDI,left.location.register);
  340. // rg.ungetregisterint(exprasmlist,R_EDI);
  341. end
  342. ELSE
  343. begin
  344. { Optimizations when right.location is a constant value }
  345. IF(op=A_CMP)AND(nodetype IN [equaln,unequaln])AND(right.location.loc=LOC_CONSTANT)AND(right.location.value=0)
  346. THEN
  347. begin
  348. // emit_reg_reg(A_TEST,opsize,left.location.register,left.location.register);
  349. end
  350. ELSE IF(op=A_ADD)AND(right.location.loc=LOC_CONSTANT)AND(right.location.value=1)AND NOT(cs_check_overflow in aktlocalswitches)
  351. THEN
  352. with ExprAsmList,left.location do
  353. begin
  354. concat(TAiCpu.op_reg_const_reg(A_ADD,register,1,register));
  355. end
  356. ELSE IF(op=A_SUB)AND(right.location.loc=LOC_CONSTANT)AND(right.location.value=1)AND NOT(cs_check_overflow in aktlocalswitches)
  357. THEN
  358. begin
  359. exprasmList.concat(Taicpu.Op_reg(A_DEC,left.location.register));
  360. end
  361. ELSE IF(op=A_SMUL)AND(right.location.loc=LOC_CONSTANT)AND(ispowerof2(right.location.value,power))AND NOT(cs_check_overflow in aktlocalswitches)
  362. THEN
  363. begin
  364. exprasmList.concat(Taicpu.Op_const_reg(A_SLL,power,left.location.register));
  365. end
  366. ELSE
  367. begin
  368. IF extra_not
  369. THEN
  370. begin
  371. // rg.getexplicitregisterint(exprasmlist,R_EDI);
  372. // cg.a_load_loc_reg(exprasmlist,right.location,R_EDI);
  373. // emit_reg(A_NOT,S_L,R_EDI);
  374. // emit_reg_reg(A_AND,S_L,R_EDI,left.location.register);
  375. // rg.ungetregisterint(exprasmlist,R_EDI);
  376. end
  377. ELSE
  378. begin
  379. emit_op_right_left(op);
  380. end;
  381. end;
  382. end;
  383. end;
  384. { only in case of overflow operations }
  385. { produce overflow code }
  386. { we must put it here directly, because sign of operation }
  387. { is in unsigned VAR!! }
  388. IF mboverflow
  389. THEN
  390. begin
  391. IF cs_check_overflow IN aktlocalswitches
  392. THEN
  393. begin
  394. // getlabel(hl4);
  395. IF unsigned
  396. THEN
  397. exprasmList.concat(Taicpu.Op_sym(A_JMPL,S_NO,hl4))
  398. ELSE
  399. exprasmList.concat(Taicpu.Op_sym(A_JMPL,S_NO,hl4));
  400. cg.a_call_name(exprasmlist,'FPC_OVERFLOW');
  401. cg.a_label(exprasmlist,hl4);
  402. end;
  403. end;
  404. end;
  405. procedure TSparcAddNode.emit_op_right_left(op:TAsmOp);
  406. begin
  407. {left must be a register}
  408. with left,location,exprasmlist do
  409. case Right.Location.Loc of
  410. LOC_REGISTER,LOC_CREGISTER:
  411. concat(taicpu.op_reg_reg_reg(op,Register,Right.Location.register,register));
  412. LOC_REFERENCE,LOC_CREFERENCE :
  413. begin
  414. location_force_reg(exprasmlist,Right.Location,OS_32,(nodetype in [ltn,lten,gtn,gten,equaln,unequaln]));
  415. concat(taicpu.op_reg_reg_reg(op,register,Right.Location.register,register));
  416. end;
  417. LOC_CONSTANT:
  418. concat(taicpu.op_reg_const_reg(op,register,Right.Location.value,register));
  419. else
  420. InternalError(200203232);
  421. end;
  422. end;
  423. procedure TSparcAddNode.second_add64bit;
  424. var
  425. op : TOpCG;
  426. op1,op2 : TAsmOp;
  427. hl4 : tasmlabel;
  428. cmpop,
  429. unsigned : boolean;
  430. r : Tregister;
  431. procedure emit_cmp64_hi;
  432. var
  433. oldleft, oldright: tlocation;
  434. begin
  435. // put the high part of the location in the low part
  436. location_copy(oldleft,left.location);
  437. location_copy(oldright,right.location);
  438. if left.location.loc = LOC_CONSTANT
  439. then
  440. left.location.valueqword := left.location.valueqword shr 32
  441. else
  442. left.location.registerlow := left.location.registerhigh;
  443. if right.location.loc = LOC_CONSTANT
  444. then
  445. right.location.valueqword := right.location.valueqword shr 32
  446. else
  447. right.location.registerlow := right.location.registerhigh;
  448. // and call the normal emit_compare
  449. //emit_compare(unsigned);
  450. location_copy(left.location,oldleft);
  451. location_copy(right.location,oldright);
  452. end;
  453. procedure emit_cmp64_lo;
  454. begin
  455. // emit_compare(true);
  456. end;
  457. procedure firstjmp64bitcmp;
  458. var
  459. oldnodetype: tnodetype;
  460. begin
  461. load_all_regvars(exprasmlist);
  462. { the jump the sequence is a little bit hairy }
  463. case nodetype of
  464. ltn,gtn:
  465. begin
  466. cg.a_jmp_flags(exprasmlist,getresflags(false),truelabel);
  467. { cheat a little bit for the negative test }
  468. toggleflag(nf_swaped);
  469. cg.a_jmp_flags(exprasmlist,getresflags(false),falselabel);
  470. toggleflag(nf_swaped);
  471. end;
  472. lten,gten:
  473. begin
  474. oldnodetype:=nodetype;
  475. if nodetype=lten then
  476. nodetype:=ltn
  477. else
  478. nodetype:=gtn;
  479. cg.a_jmp_flags(exprasmlist,getresflags(false),truelabel);
  480. { cheat for the negative test }
  481. if nodetype=ltn then
  482. nodetype:=gtn
  483. else
  484. nodetype:=ltn;
  485. cg.a_jmp_flags(exprasmlist,getresflags(false),falselabel);
  486. nodetype:=oldnodetype;
  487. end;
  488. equaln:
  489. begin
  490. nodetype := unequaln;
  491. cg.a_jmp_flags(exprasmlist,getresflags(true),falselabel);
  492. nodetype := equaln;
  493. end;
  494. unequaln:
  495. begin
  496. cg.a_jmp_flags(exprasmlist,getresflags(true),truelabel);
  497. end;
  498. end;
  499. end;
  500. procedure secondjmp64bitcmp;
  501. begin
  502. { the jump the sequence is a little bit hairy }
  503. case nodetype of
  504. ltn,gtn,lten,gten:
  505. begin
  506. { the comparison of the low dword always has }
  507. { to be always unsigned! }
  508. cg.a_jmp_flags(exprasmlist,getresflags(false),truelabel);
  509. cg.a_jmp_always(exprasmlist,falselabel);
  510. end;
  511. equaln:
  512. begin
  513. nodetype := unequaln;
  514. cg.a_jmp_flags(exprasmlist,getresflags(true),falselabel);
  515. cg.a_jmp_always(exprasmlist,truelabel);
  516. nodetype := equaln;
  517. end;
  518. unequaln:
  519. begin
  520. cg.a_jmp_flags(exprasmlist,getresflags(true),truelabel);
  521. cg.a_jmp_always(exprasmlist,falselabel);
  522. end;
  523. end;
  524. end;
  525. var
  526. tempreg64: tregister64;
  527. begin
  528. firstcomplex(self);
  529. pass_left_and_right;
  530. cmpop:=false;
  531. unsigned:=((left.resulttype.def.deftype=orddef) and
  532. (torddef(left.resulttype.def).typ=u64bit)) or
  533. ((right.resulttype.def.deftype=orddef) and
  534. (torddef(right.resulttype.def).typ=u64bit));
  535. case nodetype of
  536. addn :
  537. begin
  538. op:=OP_ADD;
  539. end;
  540. subn :
  541. begin
  542. op:=OP_SUB;
  543. end;
  544. ltn,lten,
  545. gtn,gten,
  546. equaln,unequaln:
  547. begin
  548. op:=OP_NONE;
  549. cmpop:=true;
  550. end;
  551. xorn:
  552. op:=OP_XOR;
  553. orn:
  554. op:=OP_OR;
  555. andn:
  556. op:=OP_AND;
  557. muln:
  558. begin
  559. { should be handled in pass_1 (JM) }
  560. internalerror(200109051);
  561. end;
  562. else
  563. internalerror(2002072705);
  564. end;
  565. if not cmpop then
  566. location_reset(location,LOC_REGISTER,def_cgsize(resulttype.def));
  567. load_left_right(cmpop,(cs_check_overflow in aktlocalswitches) and (nodetype in [addn,subn]));
  568. if not(cs_check_overflow in aktlocalswitches) or
  569. not(nodetype in [addn,subn]) then
  570. begin
  571. case nodetype of
  572. ltn,lten,
  573. gtn,gten:
  574. begin
  575. emit_cmp64_hi;
  576. firstjmp64bitcmp;
  577. emit_cmp64_lo;
  578. secondjmp64bitcmp;
  579. end;
  580. equaln,unequaln:
  581. begin
  582. // instead of doing a complicated compare, do
  583. // (left.hi xor right.hi) or (left.lo xor right.lo)
  584. // (somewhate optimized so that no superfluous 'mr's are
  585. // generated)
  586. if (left.location.loc = LOC_CONSTANT) then
  587. swapleftright;
  588. if (right.location.loc = LOC_CONSTANT) then
  589. begin
  590. if left.location.loc = LOC_REGISTER then
  591. begin
  592. tempreg64.reglo := left.location.registerlow;
  593. tempreg64.reghi := left.location.registerhigh;
  594. end
  595. else
  596. begin
  597. if (right.location.valueqword <> 0)
  598. then
  599. tempreg64.reglo := cg.get_scratch_reg_int(exprasmlist)
  600. else
  601. tempreg64.reglo := left.location.registerlow;
  602. if ((right.location.valueqword shr 32) <> 0) then
  603. tempreg64.reghi := cg.get_scratch_reg_int(exprasmlist)
  604. else
  605. tempreg64.reghi := left.location.registerhigh;
  606. end;
  607. if (right.location.valueqword <> 0) then
  608. { negative values can be handled using SUB, }
  609. { positive values < 65535 using XOR. }
  610. if (longint(right.location.valueqword) >= -32767) and
  611. (longint(right.location.valueqword) < 0) then
  612. cg.a_op_const_reg_reg(exprasmlist,OP_SUB,OS_INT,
  613. right.location.valueqword,
  614. left.location.registerlow,tempreg64.reglo)
  615. else
  616. cg.a_op_const_reg_reg(exprasmlist,OP_XOR,OS_INT,
  617. right.location.valueqword,
  618. left.location.registerlow,tempreg64.reglo);
  619. if ((right.location.valueqword shr 32) <> 0) then
  620. if (longint(right.location.valueqword shr 32) >= -32767) and
  621. (longint(right.location.valueqword shr 32) < 0) then
  622. cg.a_op_const_reg_reg(exprasmlist,OP_SUB,OS_INT,
  623. right.location.valueqword shr 32,
  624. left.location.registerhigh,tempreg64.reghi)
  625. else
  626. cg.a_op_const_reg_reg(exprasmlist,OP_XOR,OS_INT,
  627. right.location.valueqword shr 32,
  628. left.location.registerhigh,tempreg64.reghi);
  629. end
  630. else
  631. begin
  632. tempreg64.reglo := cg.get_scratch_reg_int(exprasmlist);
  633. tempreg64.reghi := cg.get_scratch_reg_int(exprasmlist);
  634. cg64.a_op64_reg_reg_reg(exprasmlist,OP_XOR,
  635. left.location.register64,right.location.register64,
  636. tempreg64);
  637. end;
  638. r.enum:=R_G0;
  639. cg.a_reg_alloc(exprasmlist,r);
  640. exprasmlist.concat(taicpu.op_reg_reg_reg(A_OR,r,
  641. tempreg64.reglo,tempreg64.reghi));
  642. cg.a_reg_dealloc(exprasmlist,r);
  643. if (tempreg64.reglo.enum <> left.location.registerlow.enum) then
  644. cg.free_scratch_reg(exprasmlist,tempreg64.reglo);
  645. if (tempreg64.reghi.enum <> left.location.registerhigh.enum) then
  646. cg.free_scratch_reg(exprasmlist,tempreg64.reghi);
  647. location_reset(location,LOC_FLAGS,OS_NO);
  648. location.resflags := getresflags(true);
  649. end;
  650. xorn,orn,andn,addn:
  651. begin
  652. if (location.registerlow.enum = R_NO) then
  653. begin
  654. location.registerlow := rg.getregisterint(exprasmlist);
  655. location.registerhigh := rg.getregisterint(exprasmlist);
  656. end;
  657. if (left.location.loc = LOC_CONSTANT) then
  658. swapleftright;
  659. if (right.location.loc = LOC_CONSTANT) then
  660. cg64.a_op64_const_reg_reg(exprasmlist,op,right.location.valueqword,
  661. left.location.register64,location.register64)
  662. else
  663. cg64.a_op64_reg_reg_reg(exprasmlist,op,right.location.register64,
  664. left.location.register64,location.register64);
  665. end;
  666. subn:
  667. begin
  668. if (nf_swaped in flags) then
  669. swapleftright;
  670. if left.location.loc <> LOC_CONSTANT then
  671. begin
  672. if (location.registerlow.enum = R_NO) then
  673. begin
  674. location.registerlow := rg.getregisterint(exprasmlist);
  675. location.registerhigh := rg.getregisterint(exprasmlist);
  676. end;
  677. if right.location.loc <> LOC_CONSTANT then
  678. // reg64 - reg64
  679. cg64.a_op64_reg_reg_reg(exprasmlist,OP_SUB,
  680. right.location.register64,left.location.register64,
  681. location.register64)
  682. else
  683. // reg64 - const64
  684. cg64.a_op64_const_reg_reg(exprasmlist,OP_SUB,
  685. right.location.valueqword,left.location.register64,
  686. location.register64)
  687. end
  688. else if ((left.location.valueqword shr 32) = 0) then
  689. begin
  690. if (location.registerlow.enum = R_NO) then
  691. begin
  692. location.registerlow := rg.getregisterint(exprasmlist);
  693. location.registerhigh := rg.getregisterint(exprasmlist);
  694. end;
  695. if (int64(left.location.valueqword) >= low(smallint)) and
  696. (int64(left.location.valueqword) <= high(smallint))
  697. then
  698. begin
  699. // consts16 - reg64
  700. exprasmlist.concat(taicpu.op_reg_const_Reg(A_SUBcc,location.registerlow,left.location.value,right.location.registerlow));
  701. end
  702. else
  703. begin
  704. // const32 - reg64
  705. cg.a_load_const_reg(exprasmlist,OS_32,
  706. left.location.valueqword,location.registerlow);
  707. exprasmlist.concat(taicpu.op_reg_reg_reg(A_SUBcc,
  708. location.registerlow,location.registerlow,
  709. right.location.registerlow));
  710. end;
  711. exprasmlist.concat(taicpu.op_reg_reg(A_SUBcc,
  712. location.registerhigh,right.location.registerhigh));
  713. end
  714. else if (left.location.valueqword = 0) then
  715. begin
  716. // (const32 shl 32) - reg64
  717. if (location.registerlow.enum = R_NO) then
  718. begin
  719. location.registerlow := rg.getregisterint(exprasmlist);
  720. location.registerhigh := rg.getregisterint(exprasmlist);
  721. end;
  722. exprasmlist.concat(taicpu.op_reg_Const_reg(A_SUBcc,location.registerlow,0,right.location.registerlow));
  723. cg.a_load_const_reg(exprasmlist,OS_INT,
  724. left.location.valueqword shr 32,location.registerhigh);
  725. exprasmlist.concat(taicpu.op_reg_reg_reg(A_SUBcc,
  726. location.registerhigh,right.location.registerhigh,
  727. location.registerhigh));
  728. end
  729. else
  730. begin
  731. // const64 - reg64
  732. location_force_reg(exprasmlist,left.location,
  733. def_cgsize(left.resulttype.def),true);
  734. if (left.location.loc = LOC_REGISTER) then
  735. location.register64 := left.location.register64
  736. else if (location.registerlow.enum = R_NO) then
  737. begin
  738. location.registerlow := rg.getregisterint(exprasmlist);
  739. location.registerhigh := rg.getregisterint(exprasmlist);
  740. end;
  741. cg64.a_op64_reg_reg_reg(exprasmlist,OP_SUB,
  742. right.location.register64,left.location.register64,
  743. location.register64);
  744. end;
  745. end;
  746. else
  747. internalerror(2002072803);
  748. end;
  749. end
  750. else
  751. begin
  752. case nodetype of
  753. addn:
  754. begin
  755. op1 := A_ADDcc;
  756. op2 := A_ADDcc;
  757. end;
  758. subn:
  759. begin
  760. op1 := A_SUBcc;
  761. op2 := A_SUBcc;
  762. end;
  763. else
  764. internalerror(2002072806);
  765. end;
  766. exprasmlist.concat(taicpu.op_reg_reg_reg(op1,location.registerlow,
  767. left.location.registerlow,right.location.registerlow));
  768. exprasmlist.concat(taicpu.op_reg_reg_reg(op2,location.registerhigh,
  769. right.location.registerhigh,left.location.registerhigh));
  770. cg.g_overflowcheck(exprasmlist,self);
  771. end;
  772. { set result location }
  773. { (emit_compare sets it to LOC_FLAGS for compares, so set the }
  774. { real location only now) (JM) }
  775. if cmpop and
  776. not(nodetype in [equaln,unequaln]) then
  777. location_reset(location,LOC_JUMP,OS_NO);
  778. clear_left_right(cmpop);
  779. end;
  780. procedure TSparcAddNode.load_left_right(cmpop,load_constants:Boolean);
  781. procedure load_node(var n:tnode);
  782. begin
  783. case n.location.loc of
  784. LOC_REGISTER:
  785. if not cmpop
  786. then
  787. begin
  788. location.register := n.location.register;
  789. if is_64bitint(n.resulttype.def)
  790. then
  791. location.registerhigh := n.location.registerhigh;
  792. end;
  793. LOC_REFERENCE,LOC_CREFERENCE:
  794. begin
  795. location_force_reg(exprasmlist,n.location,def_cgsize(n.resulttype.def),false);
  796. if not cmpop
  797. then
  798. begin
  799. location.register := n.location.register;
  800. if is_64bitint(n.resulttype.def)
  801. then
  802. location.registerhigh := n.location.registerhigh;
  803. end;
  804. end;
  805. LOC_CONSTANT:
  806. begin
  807. if load_constants
  808. then
  809. begin
  810. location_force_reg(exprasmlist,n.location,def_cgsize(n.resulttype.def),false);
  811. if not cmpop
  812. then
  813. location.register := n.location.register;
  814. if is_64bitint(n.resulttype.def)
  815. then
  816. location.registerhigh := n.location.registerhigh;
  817. end;
  818. end;
  819. end;
  820. end;
  821. begin
  822. load_node(left);
  823. load_node(right);
  824. end;
  825. procedure TSparcAddNode.second_addfloat;
  826. var
  827. reg : tregister;
  828. op : TAsmOp;
  829. cmpop : boolean;
  830. r : Tregister;
  831. procedure location_force_fpureg(var l: tlocation);
  832. begin
  833. if not(l.loc in [LOC_FPUREGISTER,LOC_CFPUREGISTER]) then
  834. begin
  835. reg := rg.getregisterfpu(exprasmlist);
  836. cg.a_loadfpu_loc_reg(exprasmlist,l,reg);
  837. location_freetemp(exprasmlist,l);
  838. location_release(exprasmlist,l);
  839. location_reset(l,LOC_FPUREGISTER,l.size);
  840. l.register := reg;
  841. end;
  842. end;
  843. begin
  844. pass_left_and_right;
  845. cmpop:=false;
  846. case nodetype of
  847. addn :
  848. op:=A_FADDs;
  849. muln :
  850. op:=A_FMULs;
  851. subn :
  852. op:=A_FSUBs;
  853. slashn :
  854. op:=A_FDIVs;
  855. ltn,lten,gtn,gten,
  856. equaln,unequaln :
  857. begin
  858. op:=A_FCMPs;
  859. cmpop:=true;
  860. end;
  861. else
  862. CGMessage(type_e_mismatch);
  863. end;
  864. // get the operands in the correct order, there are no special cases
  865. // here, everything is register-based
  866. if nf_swaped in flags then
  867. swapleftright;
  868. // put both operands in a register
  869. location_force_fpureg(right.location);
  870. location_force_fpureg(left.location);
  871. // initialize de result
  872. if not cmpop then
  873. begin
  874. location_reset(location,LOC_FPUREGISTER,def_cgsize(resulttype.def));
  875. if left.location.loc = LOC_FPUREGISTER then
  876. location.register := left.location.register
  877. else if right.location.loc = LOC_FPUREGISTER then
  878. location.register := right.location.register
  879. else
  880. location.register := rg.getregisterfpu(exprasmlist);
  881. end
  882. else
  883. begin
  884. location_reset(location,LOC_FLAGS,OS_NO);
  885. location.resflags := getresflags(true);
  886. end;
  887. // emit the actual operation
  888. if not cmpop then
  889. begin
  890. exprasmlist.concat(taicpu.op_reg_reg_reg(op,
  891. location.register,left.location.register,
  892. right.location.register))
  893. end
  894. else
  895. begin
  896. r.enum:=R_PSR;
  897. exprasmlist.concat(taicpu.op_reg_reg_reg(op,
  898. r,left.location.register,right.location.register))
  899. end;
  900. clear_left_right(cmpop);
  901. end;
  902. procedure TSparcAddNode.set_result_location(cmpOp,unsigned:Boolean);
  903. begin
  904. IF cmpOp
  905. THEN
  906. begin
  907. location_reset(location,LOC_FLAGS,OS_NO);
  908. location.resflags:=GetResFlags(unsigned);
  909. end
  910. ELSE
  911. location_copy(location,left.location);
  912. end;
  913. function def_opsize(p1:tdef):topsize;
  914. begin
  915. case p1.size of
  916. 1:def_opsize:=S_B;
  917. 2:def_opsize:=S_W;
  918. 4:def_opsize:=S_L;
  919. 8:def_opsize:=S_L;
  920. else
  921. InternalError(130820001);
  922. end;
  923. end;
  924. procedure TSparcAddNode.pass_2;
  925. {is also being used for "xor", and "mul", "sub", or and comparative operators}
  926. var
  927. popeax,popedx,pushedfpu,mboverflow,cmpop:Boolean;
  928. op:TAsmOp;
  929. power:LongInt;
  930. OpSize:TOpSize;
  931. unsigned:Boolean;{true, if unsigned types are compared}
  932. extra_not:Boolean;
  933. cgop:TOpCg;
  934. begin
  935. {to make it more readable, string and set (not smallset!) have their own
  936. procedures }
  937. case left.resulttype.def.deftype of
  938. orddef:
  939. if is_boolean(left.resulttype.def)and is_boolean(right.resulttype.def)
  940. then{handling boolean expressions}
  941. begin
  942. second_addboolean;
  943. exit;
  944. end
  945. else if is_64bitint(left.resulttype.def)
  946. then{64bit operations}
  947. begin
  948. second_add64bit;
  949. exit;
  950. end;
  951. stringdef:
  952. InternalError(20020726);//second_addstring;
  953. setdef:
  954. {normalsets are already handled in pass1}
  955. if(tsetdef(left.resulttype.def).settype<>smallset)
  956. then
  957. internalerror(200109041)
  958. else
  959. InternalError(20020726);//second_addsmallset;
  960. arraydef :
  961. InternalError(2002110600);
  962. floatdef :
  963. begin
  964. second_addfloat;
  965. exit;
  966. end;
  967. end;
  968. {defaults}
  969. extra_not:=false;
  970. mboverflow:=false;
  971. cmpop:=nodetype in [ltn,lten,gtn,gten,equaln,unequaln];
  972. unsigned:=not(is_signed(left.resulttype.def))or
  973. not(is_signed(right.resulttype.def));
  974. opsize:=def_opsize(left.resulttype.def);
  975. pass_left_and_right;
  976. { set result location }
  977. if not cmpop
  978. then
  979. location_reset(location,LOC_REGISTER,def_cgsize(resulttype.def))
  980. else
  981. location_reset(location,LOC_FLAGS,OS_NO);
  982. load_left_right(cmpop,(cs_check_overflow in aktlocalswitches)and(nodetype in [addn,subn,muln]));
  983. if(location.register.enum = R_NO)and not(cmpop)
  984. then
  985. location.register := rg.getregisterint(exprasmlist);
  986. if not(cs_check_overflow in aktlocalswitches)or cmpop or (nodetype in [orn,andn,xorn])
  987. then
  988. begin
  989. case NodeType of
  990. addn:
  991. begin
  992. op:=A_ADD;
  993. mboverflow:=true;
  994. end;
  995. muln:
  996. begin
  997. IF unsigned
  998. THEN
  999. op:=A_UMUL
  1000. ELSE
  1001. op:=A_SMUL;
  1002. mboverflow:=true;
  1003. end;
  1004. subn:
  1005. begin
  1006. op:=A_SUB;
  1007. mboverflow:=true;
  1008. end;
  1009. ltn,lten,
  1010. gtn,gten,
  1011. equaln,unequaln:
  1012. begin
  1013. op:=A_CMP;
  1014. cmpop:=true;
  1015. end;
  1016. xorn:
  1017. op:=A_XOR;
  1018. orn:
  1019. op:=A_OR;
  1020. andn:
  1021. op:=A_AND;
  1022. else
  1023. CGMessage(type_e_mismatch);
  1024. end;
  1025. { Convert flags to register first }
  1026. if(left.location.loc=LOC_FLAGS)
  1027. then
  1028. location_force_reg(exprasmlist,left.location,opsize_2_cgsize[opsize],false);
  1029. if (right.location.loc=LOC_FLAGS)
  1030. then
  1031. location_force_reg(exprasmlist,right.location,opsize_2_cgsize[opsize],false);
  1032. left_must_be_reg(OpSize,false);
  1033. emit_generic_code(op,opsize,unsigned,extra_not,mboverflow);
  1034. location_freetemp(exprasmlist,right.location);
  1035. location_release(exprasmlist,right.location);
  1036. if cmpop and(left.location.loc<>LOC_CREGISTER)
  1037. then
  1038. begin
  1039. location_freetemp(exprasmlist,left.location);
  1040. location_release(exprasmlist,left.location);
  1041. end;
  1042. end;
  1043. clear_left_right(cmpop);
  1044. end;
  1045. procedure TSparcAddNode.pass_left_and_right;
  1046. var
  1047. pushedregs:tmaybesave;
  1048. tmpreg:tregister;
  1049. pushedfpu:boolean;
  1050. begin
  1051. { calculate the operator which is more difficult }
  1052. firstcomplex(self);
  1053. { in case of constant put it to the left }
  1054. if (left.nodetype=ordconstn)
  1055. then
  1056. swapleftright;
  1057. secondpass(left);
  1058. { are too few registers free? }
  1059. maybe_save(exprasmlist,right.registers32,left.location,pushedregs);
  1060. if location.loc=LOC_FPUREGISTER
  1061. then
  1062. pushedfpu:=maybe_pushfpu(exprasmlist,right.registersfpu,left.location)
  1063. else
  1064. pushedfpu:=false;
  1065. secondpass(right);
  1066. maybe_restore(exprasmlist,left.location,pushedregs);
  1067. if pushedfpu
  1068. then
  1069. begin
  1070. tmpreg := rg.getregisterfpu(exprasmlist);
  1071. cg.a_loadfpu_loc_reg(exprasmlist,left.location,tmpreg);
  1072. location_reset(left.location,LOC_FPUREGISTER,left.location.size);
  1073. left.location.register := tmpreg;
  1074. end;
  1075. end;
  1076. begin
  1077. cAddNode:=TSparcAddNode;
  1078. end.
  1079. {
  1080. $Log$
  1081. Revision 1.9 2003-02-13 21:15:18 mazen
  1082. + Load_left_right and clear_left_right implemented fixing test0001 register
  1083. allocation bug.
  1084. Revision 1.8 2003/01/22 20:45:15 mazen
  1085. * making math code in RTL compiling.
  1086. *NB : This does NOT mean necessary that it will generate correct code!
  1087. Revision 1.7 2003/01/20 22:21:36 mazen
  1088. * many stuff related to RTL fixed
  1089. Revision 1.6 2003/01/08 18:43:58 daniel
  1090. * Tregister changed into a record
  1091. Revision 1.5 2003/01/07 22:03:40 mazen
  1092. * adding unequaln node support to sparc compiler
  1093. Revision 1.4 2002/12/30 21:17:22 mazen
  1094. - unit cga no more used in sparc compiler.
  1095. Revision 1.3 2002/12/25 20:59:49 mazen
  1096. - many emitXXX removed from cga.pas in order to remove that file.
  1097. Revision 1.2 2002/12/22 19:26:32 mazen
  1098. * many internal errors related to unimplemented nodes are fixed
  1099. Revision 1.1 2002/12/21 23:21:47 mazen
  1100. + added support for the shift nodes
  1101. + added debug output on screen with -an command line option
  1102. Revision 1.10 2002/11/25 17:43:28 peter
  1103. * splitted defbase in defutil,symutil,defcmp
  1104. * merged isconvertable and is_equal into compare_defs(_ext)
  1105. * made operator search faster by walking the list only once
  1106. Revision 1.9 2002/11/10 19:07:46 mazen
  1107. * SPARC calling mechanism almost OK (as in GCC./mppcsparc )
  1108. Revision 1.8 2002/11/06 15:34:00 mazen
  1109. *** empty log message ***
  1110. Revision 1.7 2002/11/06 11:31:24 mazen
  1111. * op_reg_reg_reg don't need any more a TOpSize parameter
  1112. Revision 1.6 2002/11/05 16:15:00 mazen
  1113. *** empty log message ***
  1114. Revision 1.5 2002/10/22 13:43:01 mazen
  1115. - cga.pas redueced to an empty unit
  1116. Revision 1.4 2002/10/10 20:23:57 mazen
  1117. * tabs replaces by spaces
  1118. }