popt386.pas 115 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl and Jonas Maebe
  3. This unit contains the peephole optimizer.
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit popt386;
  18. {$i fpcdefs.inc}
  19. interface
  20. uses Aasmbase,aasmtai,aasmdata,aasmcpu,verbose;
  21. procedure PrePeepHoleOpts(asml: TAsmList; BlockStart, BlockEnd: tai);
  22. procedure PeepHoleOptPass1(asml: TAsmList; BlockStart, BlockEnd: tai);
  23. procedure PeepHoleOptPass2(asml: TAsmList; BlockStart, BlockEnd: tai);
  24. procedure PostPeepHoleOpts(asml: TAsmList; BlockStart, BlockEnd: tai);
  25. implementation
  26. uses
  27. globtype,systems,
  28. globals,cgbase,procinfo,
  29. symsym,
  30. {$ifdef finaldestdebug}
  31. cobjects,
  32. {$endif finaldestdebug}
  33. cpuinfo,cpubase,cgutils,daopt386;
  34. function isFoldableArithOp(hp1: taicpu; reg: tregister): boolean;
  35. begin
  36. isFoldableArithOp := False;
  37. case hp1.opcode of
  38. A_ADD,A_SUB,A_OR,A_XOR,A_AND,A_SHL,A_SHR,A_SAR:
  39. isFoldableArithOp :=
  40. ((taicpu(hp1).oper[0]^.typ = top_const) or
  41. ((taicpu(hp1).oper[0]^.typ = top_reg) and
  42. (taicpu(hp1).oper[0]^.reg <> reg))) and
  43. (taicpu(hp1).oper[1]^.typ = top_reg) and
  44. (taicpu(hp1).oper[1]^.reg = reg);
  45. A_INC,A_DEC:
  46. isFoldableArithOp :=
  47. (taicpu(hp1).oper[0]^.typ = top_reg) and
  48. (taicpu(hp1).oper[0]^.reg = reg);
  49. end;
  50. end;
  51. function RegUsedAfterInstruction(reg: Tregister; p: tai; var UsedRegs: TRegSet): Boolean;
  52. var
  53. supreg: tsuperregister;
  54. begin
  55. supreg := getsupreg(reg);
  56. UpdateUsedRegs(UsedRegs, tai(p.Next));
  57. RegUsedAfterInstruction :=
  58. (supreg in UsedRegs) and
  59. (not(getNextInstruction(p,p)) or
  60. not(regLoadedWithNewValue(supreg,false,p)));
  61. end;
  62. function doFpuLoadStoreOpt(asmL: TAsmList; var p: tai): boolean;
  63. { returns true if a "continue" should be done after this optimization }
  64. var hp1, hp2: tai;
  65. begin
  66. doFpuLoadStoreOpt := false;
  67. if (taicpu(p).oper[0]^.typ = top_ref) and
  68. getNextInstruction(p, hp1) and
  69. (hp1.typ = ait_instruction) and
  70. (((taicpu(hp1).opcode = A_FLD) and
  71. (taicpu(p).opcode = A_FSTP)) or
  72. ((taicpu(p).opcode = A_FISTP) and
  73. (taicpu(hp1).opcode = A_FILD))) and
  74. (taicpu(hp1).oper[0]^.typ = top_ref) and
  75. (taicpu(hp1).opsize = taicpu(p).opsize) and
  76. refsEqual(taicpu(p).oper[0]^.ref^, taicpu(hp1).oper[0]^.ref^) then
  77. begin
  78. { replacing fstp f;fld f by fst f is only valid for extended because of rounding }
  79. if (taicpu(p).opsize=S_FX) and
  80. getNextInstruction(hp1, hp2) and
  81. (hp2.typ = ait_instruction) and
  82. ((taicpu(hp2).opcode = A_LEAVE) or
  83. (taicpu(hp2).opcode = A_RET)) and
  84. (taicpu(p).oper[0]^.ref^.base = current_procinfo.FramePointer) and
  85. not(assigned(current_procinfo.procdef.funcretsym) and
  86. (taicpu(p).oper[0]^.ref^.offset < tabstractnormalvarsym(current_procinfo.procdef.funcretsym).localloc.reference.offset)) and
  87. (taicpu(p).oper[0]^.ref^.index = NR_NO) then
  88. begin
  89. asml.remove(p);
  90. asml.remove(hp1);
  91. p.free;
  92. hp1.free;
  93. p := hp2;
  94. removeLastDeallocForFuncRes(asmL, p);
  95. doFPULoadStoreOpt := true;
  96. end
  97. (* can't be done because the store operation rounds
  98. else
  99. { fst can't store an extended value! }
  100. if (taicpu(p).opsize <> S_FX) and
  101. (taicpu(p).opsize <> S_IQ) then
  102. begin
  103. if (taicpu(p).opcode = A_FSTP) then
  104. taicpu(p).opcode := A_FST
  105. else taicpu(p).opcode := A_FIST;
  106. asml.remove(hp1);
  107. hp1.free;
  108. end
  109. *)
  110. end;
  111. end;
  112. { returns true if p contains a memory operand with a segment set }
  113. function InsContainsSegRef(p: taicpu): boolean;
  114. var
  115. i: longint;
  116. begin
  117. result:=true;
  118. for i:=0 to p.opercnt-1 do
  119. if (p.oper[i]^.typ=top_ref) and
  120. (p.oper[i]^.ref^.segment<>NR_NO) then
  121. exit;
  122. result:=false;
  123. end;
  124. procedure PrePeepHoleOpts(asml: TAsmList; BlockStart, BlockEnd: tai);
  125. var
  126. p,hp1: tai;
  127. l: aint;
  128. tmpRef: treference;
  129. begin
  130. p := BlockStart;
  131. while (p <> BlockEnd) Do
  132. begin
  133. case p.Typ Of
  134. Ait_Instruction:
  135. begin
  136. if InsContainsSegRef(taicpu(p)) then
  137. begin
  138. p := tai(p.next);
  139. continue;
  140. end;
  141. case taicpu(p).opcode Of
  142. A_IMUL:
  143. {changes certain "imul const, %reg"'s to lea sequences}
  144. begin
  145. if (taicpu(p).oper[0]^.typ = Top_Const) and
  146. (taicpu(p).oper[1]^.typ = Top_Reg) and
  147. (taicpu(p).opsize = S_L) then
  148. if (taicpu(p).oper[0]^.val = 1) then
  149. if (taicpu(p).ops = 2) then
  150. {remove "imul $1, reg"}
  151. begin
  152. hp1 := tai(p.Next);
  153. asml.remove(p);
  154. p.free;
  155. p := hp1;
  156. continue;
  157. end
  158. else
  159. {change "imul $1, reg1, reg2" to "mov reg1, reg2"}
  160. begin
  161. hp1 := taicpu.Op_Reg_Reg(A_MOV, S_L, taicpu(p).oper[1]^.reg,taicpu(p).oper[2]^.reg);
  162. InsertLLItem(asml, p.previous, p.next, hp1);
  163. p.free;
  164. p := hp1;
  165. end
  166. else if
  167. ((taicpu(p).ops <= 2) or
  168. (taicpu(p).oper[2]^.typ = Top_Reg)) and
  169. (taicpu(p).oper[0]^.val <= 12) and
  170. not(cs_opt_size in current_settings.optimizerswitches) and
  171. (not(GetNextInstruction(p, hp1)) or
  172. {GetNextInstruction(p, hp1) and}
  173. not((tai(hp1).typ = ait_instruction) and
  174. ((taicpu(hp1).opcode=A_Jcc) and
  175. (taicpu(hp1).condition in [C_O,C_NO])))) then
  176. begin
  177. reference_reset(tmpref,1);
  178. case taicpu(p).oper[0]^.val Of
  179. 3: begin
  180. {imul 3, reg1, reg2 to
  181. lea (reg1,reg1,2), reg2
  182. imul 3, reg1 to
  183. lea (reg1,reg1,2), reg1}
  184. TmpRef.base := taicpu(p).oper[1]^.reg;
  185. TmpRef.index := taicpu(p).oper[1]^.reg;
  186. TmpRef.ScaleFactor := 2;
  187. if (taicpu(p).ops = 2) then
  188. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg)
  189. else
  190. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
  191. InsertLLItem(asml,p.previous, p.next, hp1);
  192. p.free;
  193. p := hp1;
  194. end;
  195. 5: begin
  196. {imul 5, reg1, reg2 to
  197. lea (reg1,reg1,4), reg2
  198. imul 5, reg1 to
  199. lea (reg1,reg1,4), reg1}
  200. TmpRef.base := taicpu(p).oper[1]^.reg;
  201. TmpRef.index := taicpu(p).oper[1]^.reg;
  202. TmpRef.ScaleFactor := 4;
  203. if (taicpu(p).ops = 2) then
  204. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg)
  205. else
  206. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
  207. InsertLLItem(asml,p.previous, p.next, hp1);
  208. p.free;
  209. p := hp1;
  210. end;
  211. 6: begin
  212. {imul 6, reg1, reg2 to
  213. lea (,reg1,2), reg2
  214. lea (reg2,reg1,4), reg2
  215. imul 6, reg1 to
  216. lea (reg1,reg1,2), reg1
  217. add reg1, reg1}
  218. if (current_settings.optimizecputype <= cpu_386) then
  219. begin
  220. TmpRef.index := taicpu(p).oper[1]^.reg;
  221. if (taicpu(p).ops = 3) then
  222. begin
  223. TmpRef.base := taicpu(p).oper[2]^.reg;
  224. TmpRef.ScaleFactor := 4;
  225. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
  226. end
  227. else
  228. begin
  229. hp1 := taicpu.op_reg_reg(A_ADD, S_L,
  230. taicpu(p).oper[1]^.reg,taicpu(p).oper[1]^.reg);
  231. end;
  232. InsertLLItem(asml,p, p.next, hp1);
  233. reference_reset(tmpref,2);
  234. TmpRef.index := taicpu(p).oper[1]^.reg;
  235. TmpRef.ScaleFactor := 2;
  236. if (taicpu(p).ops = 3) then
  237. begin
  238. TmpRef.base := NR_NO;
  239. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef,
  240. taicpu(p).oper[2]^.reg);
  241. end
  242. else
  243. begin
  244. TmpRef.base := taicpu(p).oper[1]^.reg;
  245. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
  246. end;
  247. InsertLLItem(asml,p.previous, p.next, hp1);
  248. p.free;
  249. p := tai(hp1.next);
  250. end
  251. end;
  252. 9: begin
  253. {imul 9, reg1, reg2 to
  254. lea (reg1,reg1,8), reg2
  255. imul 9, reg1 to
  256. lea (reg1,reg1,8), reg1}
  257. TmpRef.base := taicpu(p).oper[1]^.reg;
  258. TmpRef.index := taicpu(p).oper[1]^.reg;
  259. TmpRef.ScaleFactor := 8;
  260. if (taicpu(p).ops = 2) then
  261. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg)
  262. else
  263. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
  264. InsertLLItem(asml,p.previous, p.next, hp1);
  265. p.free;
  266. p := hp1;
  267. end;
  268. 10: begin
  269. {imul 10, reg1, reg2 to
  270. lea (reg1,reg1,4), reg2
  271. add reg2, reg2
  272. imul 10, reg1 to
  273. lea (reg1,reg1,4), reg1
  274. add reg1, reg1}
  275. if (current_settings.optimizecputype <= cpu_386) then
  276. begin
  277. if (taicpu(p).ops = 3) then
  278. hp1 := taicpu.op_reg_reg(A_ADD, S_L,
  279. taicpu(p).oper[2]^.reg,taicpu(p).oper[2]^.reg)
  280. else
  281. hp1 := taicpu.op_reg_reg(A_ADD, S_L,
  282. taicpu(p).oper[1]^.reg,taicpu(p).oper[1]^.reg);
  283. InsertLLItem(asml,p, p.next, hp1);
  284. TmpRef.base := taicpu(p).oper[1]^.reg;
  285. TmpRef.index := taicpu(p).oper[1]^.reg;
  286. TmpRef.ScaleFactor := 4;
  287. if (taicpu(p).ops = 3) then
  288. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg)
  289. else
  290. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
  291. InsertLLItem(asml,p.previous, p.next, hp1);
  292. p.free;
  293. p := tai(hp1.next);
  294. end
  295. end;
  296. 12: begin
  297. {imul 12, reg1, reg2 to
  298. lea (,reg1,4), reg2
  299. lea (,reg1,8) reg2
  300. imul 12, reg1 to
  301. lea (reg1,reg1,2), reg1
  302. lea (,reg1,4), reg1}
  303. if (current_settings.optimizecputype <= cpu_386)
  304. then
  305. begin
  306. TmpRef.index := taicpu(p).oper[1]^.reg;
  307. if (taicpu(p).ops = 3) then
  308. begin
  309. TmpRef.base := taicpu(p).oper[2]^.reg;
  310. TmpRef.ScaleFactor := 8;
  311. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
  312. end
  313. else
  314. begin
  315. TmpRef.base := NR_NO;
  316. TmpRef.ScaleFactor := 4;
  317. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
  318. end;
  319. InsertLLItem(asml,p, p.next, hp1);
  320. reference_reset(tmpref,2);
  321. TmpRef.index := taicpu(p).oper[1]^.reg;
  322. if (taicpu(p).ops = 3) then
  323. begin
  324. TmpRef.base := NR_NO;
  325. TmpRef.ScaleFactor := 4;
  326. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
  327. end
  328. else
  329. begin
  330. TmpRef.base := taicpu(p).oper[1]^.reg;
  331. TmpRef.ScaleFactor := 2;
  332. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
  333. end;
  334. InsertLLItem(asml,p.previous, p.next, hp1);
  335. p.free;
  336. p := tai(hp1.next);
  337. end
  338. end
  339. end;
  340. end;
  341. end;
  342. A_SAR, A_SHR:
  343. {changes the code sequence
  344. shr/sar const1, x
  345. shl const2, x
  346. to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
  347. begin
  348. if GetNextInstruction(p, hp1) and
  349. (tai(hp1).typ = ait_instruction) and
  350. (taicpu(hp1).opcode = A_SHL) and
  351. (taicpu(p).oper[0]^.typ = top_const) and
  352. (taicpu(hp1).oper[0]^.typ = top_const) and
  353. (taicpu(hp1).opsize = taicpu(p).opsize) and
  354. (taicpu(hp1).oper[1]^.typ = taicpu(p).oper[1]^.typ) and
  355. OpsEqual(taicpu(hp1).oper[1]^, taicpu(p).oper[1]^) then
  356. if (taicpu(p).oper[0]^.val > taicpu(hp1).oper[0]^.val) and
  357. not(cs_opt_size in current_settings.optimizerswitches) then
  358. { shr/sar const1, %reg
  359. shl const2, %reg
  360. with const1 > const2 }
  361. begin
  362. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val-taicpu(hp1).oper[0]^.val);
  363. taicpu(hp1).opcode := A_AND;
  364. l := (1 shl (taicpu(hp1).oper[0]^.val)) - 1;
  365. case taicpu(p).opsize Of
  366. S_L: taicpu(hp1).loadConst(0,l Xor aint($ffffffff));
  367. S_B: taicpu(hp1).loadConst(0,l Xor $ff);
  368. S_W: taicpu(hp1).loadConst(0,l Xor $ffff);
  369. end;
  370. end
  371. else if (taicpu(p).oper[0]^.val<taicpu(hp1).oper[0]^.val) and
  372. not(cs_opt_size in current_settings.optimizerswitches) then
  373. { shr/sar const1, %reg
  374. shl const2, %reg
  375. with const1 < const2 }
  376. begin
  377. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val-taicpu(p).oper[0]^.val);
  378. taicpu(p).opcode := A_AND;
  379. l := (1 shl (taicpu(p).oper[0]^.val))-1;
  380. case taicpu(p).opsize Of
  381. S_L: taicpu(p).loadConst(0,l Xor aint($ffffffff));
  382. S_B: taicpu(p).loadConst(0,l Xor $ff);
  383. S_W: taicpu(p).loadConst(0,l Xor $ffff);
  384. end;
  385. end
  386. else
  387. { shr/sar const1, %reg
  388. shl const2, %reg
  389. with const1 = const2 }
  390. if (taicpu(p).oper[0]^.val = taicpu(hp1).oper[0]^.val) then
  391. begin
  392. taicpu(p).opcode := A_AND;
  393. l := (1 shl (taicpu(p).oper[0]^.val))-1;
  394. case taicpu(p).opsize Of
  395. S_B: taicpu(p).loadConst(0,l Xor $ff);
  396. S_W: taicpu(p).loadConst(0,l Xor $ffff);
  397. S_L: taicpu(p).loadConst(0,l Xor aint($ffffffff));
  398. end;
  399. asml.remove(hp1);
  400. hp1.free;
  401. end;
  402. end;
  403. A_XOR:
  404. if (taicpu(p).oper[0]^.typ = top_reg) and
  405. (taicpu(p).oper[1]^.typ = top_reg) and
  406. (taicpu(p).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  407. { temporarily change this to 'mov reg,0' to make it easier }
  408. { for the CSE. Will be changed back in pass 2 }
  409. begin
  410. taicpu(p).opcode := A_MOV;
  411. taicpu(p).loadConst(0,0);
  412. end;
  413. end;
  414. end;
  415. end;
  416. p := tai(p.next)
  417. end;
  418. end;
  419. procedure PeepHoleOptPass1(Asml: TAsmList; BlockStart, BlockEnd: tai);
  420. {First pass of peepholeoptimizations}
  421. var
  422. l : longint;
  423. p,hp1,hp2 : tai;
  424. hp3,hp4: tai;
  425. v:aint;
  426. TmpRef: TReference;
  427. UsedRegs, TmpUsedRegs: TRegSet;
  428. TmpBool1, TmpBool2: Boolean;
  429. function SkipLabels(hp: tai; var hp2: tai): boolean;
  430. {skips all labels and returns the next "real" instruction}
  431. begin
  432. while assigned(hp.next) and
  433. (tai(hp.next).typ in SkipInstr + [ait_label,ait_align]) Do
  434. hp := tai(hp.next);
  435. if assigned(hp.next) then
  436. begin
  437. SkipLabels := True;
  438. hp2 := tai(hp.next)
  439. end
  440. else
  441. begin
  442. hp2 := hp;
  443. SkipLabels := False
  444. end;
  445. end;
  446. function GetFinalDestination(asml: TAsmList; hp: taicpu; level: longint): boolean;
  447. {traces sucessive jumps to their final destination and sets it, e.g.
  448. je l1 je l3
  449. <code> <code>
  450. l1: becomes l1:
  451. je l2 je l3
  452. <code> <code>
  453. l2: l2:
  454. jmp l3 jmp l3
  455. the level parameter denotes how deeep we have already followed the jump,
  456. to avoid endless loops with constructs such as "l5: ; jmp l5" }
  457. var p1, p2: tai;
  458. l: tasmlabel;
  459. function FindAnyLabel(hp: tai; var l: tasmlabel): Boolean;
  460. begin
  461. FindAnyLabel := false;
  462. while assigned(hp.next) and
  463. (tai(hp.next).typ in (SkipInstr+[ait_align])) Do
  464. hp := tai(hp.next);
  465. if assigned(hp.next) and
  466. (tai(hp.next).typ = ait_label) then
  467. begin
  468. FindAnyLabel := true;
  469. l := tai_label(hp.next).labsym;
  470. end
  471. end;
  472. begin
  473. GetfinalDestination := false;
  474. if level > 20 then
  475. exit;
  476. p1 := dfa.getlabelwithsym(tasmlabel(hp.oper[0]^.ref^.symbol));
  477. if assigned(p1) then
  478. begin
  479. SkipLabels(p1,p1);
  480. if (tai(p1).typ = ait_instruction) and
  481. (taicpu(p1).is_jmp) then
  482. if { the next instruction after the label where the jump hp arrives}
  483. { is unconditional or of the same type as hp, so continue }
  484. (taicpu(p1).condition in [C_None,hp.condition]) or
  485. { the next instruction after the label where the jump hp arrives}
  486. { is the opposite of hp (so this one is never taken), but after }
  487. { that one there is a branch that will be taken, so perform a }
  488. { little hack: set p1 equal to this instruction (that's what the}
  489. { last SkipLabels is for, only works with short bool evaluation)}
  490. ((taicpu(p1).condition = inverse_cond(hp.condition)) and
  491. SkipLabels(p1,p2) and
  492. (p2.typ = ait_instruction) and
  493. (taicpu(p2).is_jmp) and
  494. (taicpu(p2).condition in [C_None,hp.condition]) and
  495. SkipLabels(p1,p1)) then
  496. begin
  497. { quick check for loops of the form "l5: ; jmp l5 }
  498. if (tasmlabel(taicpu(p1).oper[0]^.ref^.symbol).labelnr =
  499. tasmlabel(hp.oper[0]^.ref^.symbol).labelnr) then
  500. exit;
  501. if not GetFinalDestination(asml, taicpu(p1),succ(level)) then
  502. exit;
  503. tasmlabel(hp.oper[0]^.ref^.symbol).decrefs;
  504. hp.oper[0]^.ref^.symbol:=taicpu(p1).oper[0]^.ref^.symbol;
  505. tasmlabel(hp.oper[0]^.ref^.symbol).increfs;
  506. end
  507. else
  508. if (taicpu(p1).condition = inverse_cond(hp.condition)) then
  509. if not FindAnyLabel(p1,l) then
  510. begin
  511. {$ifdef finaldestdebug}
  512. insertllitem(asml,p1,p1.next,tai_comment.Create(
  513. strpnew('previous label inserted'))));
  514. {$endif finaldestdebug}
  515. current_asmdata.getjumplabel(l);
  516. insertllitem(asml,p1,p1.next,tai_label.Create(l));
  517. tasmlabel(taicpu(hp).oper[0]^.ref^.symbol).decrefs;
  518. hp.oper[0]^.ref^.symbol := l;
  519. l.increfs;
  520. { this won't work, since the new label isn't in the labeltable }
  521. { so it will fail the rangecheck. Labeltable should become a }
  522. { hashtable to support this: }
  523. { GetFinalDestination(asml, hp); }
  524. end
  525. else
  526. begin
  527. {$ifdef finaldestdebug}
  528. insertllitem(asml,p1,p1.next,tai_comment.Create(
  529. strpnew('next label reused'))));
  530. {$endif finaldestdebug}
  531. l.increfs;
  532. hp.oper[0]^.ref^.symbol := l;
  533. if not GetFinalDestination(asml, hp,succ(level)) then
  534. exit;
  535. end;
  536. end;
  537. GetFinalDestination := true;
  538. end;
  539. function DoSubAddOpt(var p: tai): Boolean;
  540. begin
  541. DoSubAddOpt := False;
  542. if GetLastInstruction(p, hp1) and
  543. (hp1.typ = ait_instruction) and
  544. (taicpu(hp1).opsize = taicpu(p).opsize) then
  545. case taicpu(hp1).opcode Of
  546. A_DEC:
  547. if (taicpu(hp1).oper[0]^.typ = top_reg) and
  548. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  549. begin
  550. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val+1);
  551. asml.remove(hp1);
  552. hp1.free;
  553. end;
  554. A_SUB:
  555. if (taicpu(hp1).oper[0]^.typ = top_const) and
  556. (taicpu(hp1).oper[1]^.typ = top_reg) and
  557. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  558. begin
  559. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val+taicpu(hp1).oper[0]^.val);
  560. asml.remove(hp1);
  561. hp1.free;
  562. end;
  563. A_ADD:
  564. if (taicpu(hp1).oper[0]^.typ = top_const) and
  565. (taicpu(hp1).oper[1]^.typ = top_reg) and
  566. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  567. begin
  568. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val-taicpu(hp1).oper[0]^.val);
  569. asml.remove(hp1);
  570. hp1.free;
  571. if (taicpu(p).oper[0]^.val = 0) then
  572. begin
  573. hp1 := tai(p.next);
  574. asml.remove(p);
  575. p.free;
  576. if not GetLastInstruction(hp1, p) then
  577. p := hp1;
  578. DoSubAddOpt := True;
  579. end
  580. end;
  581. end;
  582. end;
  583. begin
  584. p := BlockStart;
  585. UsedRegs := [];
  586. while (p <> BlockEnd) Do
  587. begin
  588. UpDateUsedRegs(UsedRegs, tai(p.next));
  589. case p.Typ Of
  590. ait_instruction:
  591. begin
  592. if InsContainsSegRef(taicpu(p)) then
  593. begin
  594. p := tai(p.next);
  595. continue;
  596. end;
  597. { Handle Jmp Optimizations }
  598. if taicpu(p).is_jmp then
  599. begin
  600. {the following if-block removes all code between a jmp and the next label,
  601. because it can never be executed}
  602. if (taicpu(p).opcode = A_JMP) then
  603. begin
  604. hp2:=p;
  605. while GetNextInstruction(hp2, hp1) and
  606. (hp1.typ <> ait_label) do
  607. if not(hp1.typ in ([ait_label,ait_align]+skipinstr)) then
  608. begin
  609. { don't kill start/end of assembler block,
  610. no-line-info-start/end etc }
  611. if hp1.typ<>ait_marker then
  612. begin
  613. asml.remove(hp1);
  614. hp1.free;
  615. end
  616. else
  617. hp2:=hp1;
  618. end
  619. else break;
  620. end;
  621. { remove jumps to a label coming right after them }
  622. if GetNextInstruction(p, hp1) then
  623. begin
  624. if FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol), hp1) and
  625. { TODO: FIXME removing the first instruction fails}
  626. (p<>blockstart) then
  627. begin
  628. hp2:=tai(hp1.next);
  629. asml.remove(p);
  630. p.free;
  631. p:=hp2;
  632. continue;
  633. end
  634. else
  635. begin
  636. if hp1.typ = ait_label then
  637. SkipLabels(hp1,hp1);
  638. if (tai(hp1).typ=ait_instruction) and
  639. (taicpu(hp1).opcode=A_JMP) and
  640. GetNextInstruction(hp1, hp2) and
  641. FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol), hp2) then
  642. begin
  643. if taicpu(p).opcode=A_Jcc then
  644. begin
  645. taicpu(p).condition:=inverse_cond(taicpu(p).condition);
  646. tai_label(hp2).labsym.decrefs;
  647. taicpu(p).oper[0]^.ref^.symbol:=taicpu(hp1).oper[0]^.ref^.symbol;
  648. { when free'ing hp1, the ref. isn't decresed, so we don't
  649. increase it (FK)
  650. taicpu(p).oper[0]^.ref^.symbol.increfs;
  651. }
  652. asml.remove(hp1);
  653. hp1.free;
  654. GetFinalDestination(asml, taicpu(p),0);
  655. end
  656. else
  657. begin
  658. GetFinalDestination(asml, taicpu(p),0);
  659. p:=tai(p.next);
  660. continue;
  661. end;
  662. end
  663. else
  664. GetFinalDestination(asml, taicpu(p),0);
  665. end;
  666. end;
  667. end
  668. else
  669. { All other optimizes }
  670. begin
  671. for l := 0 to taicpu(p).ops-1 Do
  672. if (taicpu(p).oper[l]^.typ = top_ref) then
  673. With taicpu(p).oper[l]^.ref^ Do
  674. begin
  675. if (base = NR_NO) and
  676. (index <> NR_NO) and
  677. (scalefactor in [0,1]) then
  678. begin
  679. base := index;
  680. index := NR_NO
  681. end
  682. end;
  683. case taicpu(p).opcode Of
  684. A_AND:
  685. begin
  686. if (taicpu(p).oper[0]^.typ = top_const) and
  687. (taicpu(p).oper[1]^.typ = top_reg) and
  688. GetNextInstruction(p, hp1) and
  689. (tai(hp1).typ = ait_instruction) and
  690. (taicpu(hp1).opcode = A_AND) and
  691. (taicpu(hp1).oper[0]^.typ = top_const) and
  692. (taicpu(hp1).oper[1]^.typ = top_reg) and
  693. (getsupreg(taicpu(p).oper[1]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) and
  694. (getsubreg(taicpu(p).oper[1]^.reg)<=getsubreg(taicpu(hp1).oper[1]^.reg)) then
  695. {change "and const1, reg; and const2, reg" to "and (const1 and const2), reg"}
  696. begin
  697. taicpu(hp1).loadConst(0,taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val);
  698. asml.remove(p);
  699. p.free;
  700. p:=hp1;
  701. end
  702. else
  703. {change "and x, reg; jxx" to "test x, reg", if reg is deallocated before the
  704. jump, but only if it's a conditional jump (PFV) }
  705. if (taicpu(p).oper[1]^.typ = top_reg) and
  706. GetNextInstruction(p, hp1) and
  707. (hp1.typ = ait_instruction) and
  708. (taicpu(hp1).is_jmp) and
  709. (taicpu(hp1).opcode<>A_JMP) and
  710. not(getsupreg(taicpu(p).oper[1]^.reg) in UsedRegs) then
  711. taicpu(p).opcode := A_TEST;
  712. end;
  713. A_CMP:
  714. begin
  715. { cmp register,$8000 neg register
  716. je target --> jo target
  717. .... only if register is deallocated before jump.}
  718. case Taicpu(p).opsize of
  719. S_B: v:=$80;
  720. S_W: v:=$8000;
  721. S_L: v:=aint($80000000);
  722. end;
  723. if (taicpu(p).oper[0]^.typ=Top_const) and
  724. (taicpu(p).oper[0]^.val=v) and
  725. (Taicpu(p).oper[1]^.typ=top_reg) and
  726. GetNextInstruction(p, hp1) and
  727. (hp1.typ=ait_instruction) and
  728. (taicpu(hp1).opcode=A_Jcc) and
  729. (Taicpu(hp1).condition in [C_E,C_NE]) and
  730. not(getsupreg(Taicpu(p).oper[1]^.reg) in usedregs) then
  731. begin
  732. Taicpu(p).opcode:=A_NEG;
  733. Taicpu(p).loadoper(0,Taicpu(p).oper[1]^);
  734. Taicpu(p).clearop(1);
  735. Taicpu(p).ops:=1;
  736. if Taicpu(hp1).condition=C_E then
  737. Taicpu(hp1).condition:=C_O
  738. else
  739. Taicpu(hp1).condition:=C_NO;
  740. continue;
  741. end;
  742. {
  743. @@2: @@2:
  744. .... ....
  745. cmp operand1,0
  746. jle/jbe @@1
  747. dec operand1 --> sub operand1,1
  748. jmp @@2 jge/jae @@2
  749. @@1: @@1:
  750. ... ....}
  751. if (taicpu(p).oper[0]^.typ = top_const) and
  752. (taicpu(p).oper[1]^.typ in [top_reg,top_ref]) and
  753. (taicpu(p).oper[0]^.val = 0) and
  754. GetNextInstruction(p, hp1) and
  755. (hp1.typ = ait_instruction) and
  756. (taicpu(hp1).is_jmp) and
  757. (taicpu(hp1).opcode=A_Jcc) and
  758. (taicpu(hp1).condition in [C_LE,C_BE]) and
  759. GetNextInstruction(hp1,hp2) and
  760. (hp2.typ = ait_instruction) and
  761. (taicpu(hp2).opcode = A_DEC) and
  762. OpsEqual(taicpu(hp2).oper[0]^,taicpu(p).oper[1]^) and
  763. GetNextInstruction(hp2, hp3) and
  764. (hp3.typ = ait_instruction) and
  765. (taicpu(hp3).is_jmp) and
  766. (taicpu(hp3).opcode = A_JMP) and
  767. GetNextInstruction(hp3, hp4) and
  768. FindLabel(tasmlabel(taicpu(hp1).oper[0]^.ref^.symbol),hp4) then
  769. begin
  770. taicpu(hp2).Opcode := A_SUB;
  771. taicpu(hp2).loadoper(1,taicpu(hp2).oper[0]^);
  772. taicpu(hp2).loadConst(0,1);
  773. taicpu(hp2).ops:=2;
  774. taicpu(hp3).Opcode := A_Jcc;
  775. case taicpu(hp1).condition of
  776. C_LE: taicpu(hp3).condition := C_GE;
  777. C_BE: taicpu(hp3).condition := C_AE;
  778. end;
  779. asml.remove(p);
  780. asml.remove(hp1);
  781. p.free;
  782. hp1.free;
  783. p := hp2;
  784. continue;
  785. end
  786. end;
  787. A_FLD:
  788. begin
  789. if (taicpu(p).oper[0]^.typ = top_reg) and
  790. GetNextInstruction(p, hp1) and
  791. (hp1.typ = Ait_Instruction) and
  792. (taicpu(hp1).oper[0]^.typ = top_reg) and
  793. (taicpu(hp1).oper[1]^.typ = top_reg) and
  794. (taicpu(hp1).oper[0]^.reg = NR_ST) and
  795. (taicpu(hp1).oper[1]^.reg = NR_ST1) then
  796. { change to
  797. fld reg fxxx reg,st
  798. fxxxp st, st1 (hp1)
  799. Remark: non commutative operations must be reversed!
  800. }
  801. begin
  802. case taicpu(hp1).opcode Of
  803. A_FMULP,A_FADDP,
  804. A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  805. begin
  806. case taicpu(hp1).opcode Of
  807. A_FADDP: taicpu(hp1).opcode := A_FADD;
  808. A_FMULP: taicpu(hp1).opcode := A_FMUL;
  809. A_FSUBP: taicpu(hp1).opcode := A_FSUBR;
  810. A_FSUBRP: taicpu(hp1).opcode := A_FSUB;
  811. A_FDIVP: taicpu(hp1).opcode := A_FDIVR;
  812. A_FDIVRP: taicpu(hp1).opcode := A_FDIV;
  813. end;
  814. taicpu(hp1).oper[0]^.reg := taicpu(p).oper[0]^.reg;
  815. taicpu(hp1).oper[1]^.reg := NR_ST;
  816. asml.remove(p);
  817. p.free;
  818. p := hp1;
  819. continue;
  820. end;
  821. end;
  822. end
  823. else
  824. if (taicpu(p).oper[0]^.typ = top_ref) and
  825. GetNextInstruction(p, hp2) and
  826. (hp2.typ = Ait_Instruction) and
  827. (taicpu(hp2).ops = 2) and
  828. (taicpu(hp2).oper[0]^.typ = top_reg) and
  829. (taicpu(hp2).oper[1]^.typ = top_reg) and
  830. (taicpu(p).opsize in [S_FS, S_FL]) and
  831. (taicpu(hp2).oper[0]^.reg = NR_ST) and
  832. (taicpu(hp2).oper[1]^.reg = NR_ST1) then
  833. if GetLastInstruction(p, hp1) and
  834. (hp1.typ = Ait_Instruction) and
  835. ((taicpu(hp1).opcode = A_FLD) or
  836. (taicpu(hp1).opcode = A_FST)) and
  837. (taicpu(hp1).opsize = taicpu(p).opsize) and
  838. (taicpu(hp1).oper[0]^.typ = top_ref) and
  839. RefsEqual(taicpu(p).oper[0]^.ref^, taicpu(hp1).oper[0]^.ref^) then
  840. if ((taicpu(hp2).opcode = A_FMULP) or
  841. (taicpu(hp2).opcode = A_FADDP)) then
  842. { change to
  843. fld/fst mem1 (hp1) fld/fst mem1
  844. fld mem1 (p) fadd/
  845. faddp/ fmul st, st
  846. fmulp st, st1 (hp2) }
  847. begin
  848. asml.remove(p);
  849. p.free;
  850. p := hp1;
  851. if (taicpu(hp2).opcode = A_FADDP) then
  852. taicpu(hp2).opcode := A_FADD
  853. else
  854. taicpu(hp2).opcode := A_FMUL;
  855. taicpu(hp2).oper[1]^.reg := NR_ST;
  856. end
  857. else
  858. { change to
  859. fld/fst mem1 (hp1) fld/fst mem1
  860. fld mem1 (p) fld st}
  861. begin
  862. taicpu(p).changeopsize(S_FL);
  863. taicpu(p).loadreg(0,NR_ST);
  864. end
  865. else
  866. begin
  867. case taicpu(hp2).opcode Of
  868. A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  869. { change to
  870. fld/fst mem1 (hp1) fld/fst mem1
  871. fld mem2 (p) fxxx mem2
  872. fxxxp st, st1 (hp2) }
  873. begin
  874. case taicpu(hp2).opcode Of
  875. A_FADDP: taicpu(p).opcode := A_FADD;
  876. A_FMULP: taicpu(p).opcode := A_FMUL;
  877. A_FSUBP: taicpu(p).opcode := A_FSUBR;
  878. A_FSUBRP: taicpu(p).opcode := A_FSUB;
  879. A_FDIVP: taicpu(p).opcode := A_FDIVR;
  880. A_FDIVRP: taicpu(p).opcode := A_FDIV;
  881. end;
  882. asml.remove(hp2);
  883. hp2.free;
  884. end
  885. end
  886. end
  887. end;
  888. A_FSTP,A_FISTP:
  889. if doFpuLoadStoreOpt(asmL,p) then
  890. continue;
  891. A_LEA:
  892. begin
  893. {removes seg register prefixes from LEA operations, as they
  894. don't do anything}
  895. taicpu(p).oper[0]^.ref^.Segment := NR_NO;
  896. {changes "lea (%reg1), %reg2" into "mov %reg1, %reg2"}
  897. if (taicpu(p).oper[0]^.ref^.base <> NR_NO) and
  898. (getsupreg(taicpu(p).oper[0]^.ref^.base) in [RS_EAX..RS_ESP]) and
  899. (taicpu(p).oper[0]^.ref^.index = NR_NO) and
  900. (not(Assigned(taicpu(p).oper[0]^.ref^.Symbol))) then
  901. if (taicpu(p).oper[0]^.ref^.base <> taicpu(p).oper[1]^.reg) and
  902. (taicpu(p).oper[0]^.ref^.offset = 0) then
  903. begin
  904. hp1 := taicpu.op_reg_reg(A_MOV, S_L,taicpu(p).oper[0]^.ref^.base,
  905. taicpu(p).oper[1]^.reg);
  906. InsertLLItem(asml,p.previous,p.next, hp1);
  907. p.free;
  908. p := hp1;
  909. continue;
  910. end
  911. else if (taicpu(p).oper[0]^.ref^.offset = 0) then
  912. begin
  913. hp1 := tai(p.Next);
  914. asml.remove(p);
  915. p.free;
  916. p := hp1;
  917. continue;
  918. end
  919. else
  920. with taicpu(p).oper[0]^.ref^ do
  921. if (base = taicpu(p).oper[1]^.reg) then
  922. begin
  923. l := offset;
  924. if (l=1) then
  925. begin
  926. taicpu(p).opcode := A_INC;
  927. taicpu(p).loadreg(0,taicpu(p).oper[1]^.reg);
  928. taicpu(p).ops := 1
  929. end
  930. else if (l=-1) then
  931. begin
  932. taicpu(p).opcode := A_DEC;
  933. taicpu(p).loadreg(0,taicpu(p).oper[1]^.reg);
  934. taicpu(p).ops := 1;
  935. end
  936. else
  937. begin
  938. taicpu(p).opcode := A_ADD;
  939. taicpu(p).loadConst(0,l);
  940. end;
  941. end;
  942. end;
  943. A_MOV:
  944. begin
  945. TmpUsedRegs := UsedRegs;
  946. if (taicpu(p).oper[1]^.typ = top_reg) and
  947. (getsupreg(taicpu(p).oper[1]^.reg) in [RS_EAX, RS_EBX, RS_ECX, RS_EDX, RS_ESI, RS_EDI]) and
  948. GetNextInstruction(p, hp1) and
  949. (tai(hp1).typ = ait_instruction) and
  950. (taicpu(hp1).opcode = A_MOV) and
  951. (taicpu(hp1).oper[0]^.typ = top_reg) and
  952. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  953. begin
  954. {we have "mov x, %treg; mov %treg, y}
  955. if not(RegInOp(getsupreg(taicpu(p).oper[1]^.reg),taicpu(hp1).oper[1]^)) and
  956. not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp1, TmpUsedRegs)) then
  957. {we've got "mov x, %treg; mov %treg, y; with %treg is not used after }
  958. case taicpu(p).oper[0]^.typ Of
  959. top_reg:
  960. begin
  961. { change "mov %reg, %treg; mov %treg, y"
  962. to "mov %reg, y" }
  963. taicpu(p).loadOper(1,taicpu(hp1).oper[1]^);
  964. asml.remove(hp1);
  965. hp1.free;
  966. continue;
  967. end;
  968. top_ref:
  969. if (taicpu(hp1).oper[1]^.typ = top_reg) then
  970. begin
  971. { change "mov mem, %treg; mov %treg, %reg"
  972. to "mov mem, %reg" }
  973. taicpu(p).loadoper(1,taicpu(hp1).oper[1]^);
  974. asml.remove(hp1);
  975. hp1.free;
  976. continue;
  977. end;
  978. end
  979. end
  980. else
  981. {Change "mov %reg1, %reg2; xxx %reg2, ???" to
  982. "mov %reg1, %reg2; xxx %reg1, ???" to avoid a write/read
  983. penalty}
  984. if (taicpu(p).oper[0]^.typ = top_reg) and
  985. (taicpu(p).oper[1]^.typ = top_reg) and
  986. GetNextInstruction(p,hp1) and
  987. (tai(hp1).typ = ait_instruction) and
  988. (taicpu(hp1).ops >= 1) and
  989. (taicpu(hp1).oper[0]^.typ = top_reg) and
  990. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  991. {we have "mov %reg1, %reg2; XXX %reg2, ???"}
  992. begin
  993. if ((taicpu(hp1).opcode = A_OR) or
  994. (taicpu(hp1).opcode = A_TEST)) and
  995. (taicpu(hp1).oper[1]^.typ = top_reg) and
  996. (taicpu(hp1).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) then
  997. {we have "mov %reg1, %reg2; test/or %reg2, %reg2"}
  998. begin
  999. TmpUsedRegs := UsedRegs;
  1000. { reg1 will be used after the first instruction, }
  1001. { so update the allocation info }
  1002. allocRegBetween(asmL,taicpu(p).oper[0]^.reg,p,hp1,usedregs);
  1003. if GetNextInstruction(hp1, hp2) and
  1004. (hp2.typ = ait_instruction) and
  1005. taicpu(hp2).is_jmp and
  1006. not(RegUsedAfterInstruction(taicpu(hp1).oper[0]^.reg, hp1, TmpUsedRegs)) then
  1007. { change "mov %reg1, %reg2; test/or %reg2, %reg2; jxx" to
  1008. "test %reg1, %reg1; jxx" }
  1009. begin
  1010. taicpu(hp1).loadoper(0,taicpu(p).oper[0]^);
  1011. taicpu(hp1).loadoper(1,taicpu(p).oper[0]^);
  1012. asml.remove(p);
  1013. p.free;
  1014. p := hp1;
  1015. continue
  1016. end
  1017. else
  1018. {change "mov %reg1, %reg2; test/or %reg2, %reg2" to
  1019. "mov %reg1, %reg2; test/or %reg1, %reg1"}
  1020. begin
  1021. taicpu(hp1).loadoper(0,taicpu(p).oper[0]^);
  1022. taicpu(hp1).loadoper(1,taicpu(p).oper[0]^);
  1023. end;
  1024. end
  1025. { else
  1026. if (taicpu(p.next)^.opcode
  1027. in [A_PUSH, A_OR, A_XOR, A_AND, A_TEST])}
  1028. {change "mov %reg1, %reg2; push/or/xor/... %reg2, ???" to
  1029. "mov %reg1, %reg2; push/or/xor/... %reg1, ???"}
  1030. end
  1031. else
  1032. {leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
  1033. x >= RetOffset) as it doesn't do anything (it writes either to a
  1034. parameter or to the temporary storage room for the function
  1035. result)}
  1036. if GetNextInstruction(p, hp1) and
  1037. (tai(hp1).typ = ait_instruction) then
  1038. if ((taicpu(hp1).opcode = A_LEAVE) or
  1039. (taicpu(hp1).opcode = A_RET)) and
  1040. (taicpu(p).oper[1]^.typ = top_ref) and
  1041. (taicpu(p).oper[1]^.ref^.base = current_procinfo.FramePointer) and
  1042. not(assigned(current_procinfo.procdef.funcretsym) and
  1043. (taicpu(p).oper[1]^.ref^.offset < tabstractnormalvarsym(current_procinfo.procdef.funcretsym).localloc.reference.offset)) and
  1044. (taicpu(p).oper[1]^.ref^.index = NR_NO) and
  1045. (taicpu(p).oper[0]^.typ = top_reg) then
  1046. begin
  1047. asml.remove(p);
  1048. p.free;
  1049. p := hp1;
  1050. RemoveLastDeallocForFuncRes(asmL,p);
  1051. end
  1052. else
  1053. if (taicpu(p).oper[0]^.typ = top_reg) and
  1054. (taicpu(p).oper[1]^.typ = top_ref) and
  1055. (taicpu(p).opsize = taicpu(hp1).opsize) and
  1056. (taicpu(hp1).opcode = A_CMP) and
  1057. (taicpu(hp1).oper[1]^.typ = top_ref) and
  1058. RefsEqual(taicpu(p).oper[1]^.ref^, taicpu(hp1).oper[1]^.ref^) then
  1059. {change "mov reg1, mem1; cmp x, mem1" to "mov reg, mem1; cmp x, reg1"}
  1060. begin
  1061. taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
  1062. allocRegBetween(asmL,taicpu(p).oper[0]^.reg,p,hp1,usedregs);
  1063. end;
  1064. { Next instruction is also a MOV ? }
  1065. if GetNextInstruction(p, hp1) and
  1066. (tai(hp1).typ = ait_instruction) and
  1067. (taicpu(hp1).opcode = A_MOV) and
  1068. (taicpu(hp1).opsize = taicpu(p).opsize) then
  1069. begin
  1070. if (taicpu(hp1).oper[0]^.typ = taicpu(p).oper[1]^.typ) and
  1071. (taicpu(hp1).oper[1]^.typ = taicpu(p).oper[0]^.typ) then
  1072. {mov reg1, mem1 or mov mem1, reg1
  1073. mov mem2, reg2 mov reg2, mem2}
  1074. begin
  1075. if OpsEqual(taicpu(hp1).oper[1]^,taicpu(p).oper[0]^) then
  1076. {mov reg1, mem1 or mov mem1, reg1
  1077. mov mem2, reg1 mov reg2, mem1}
  1078. begin
  1079. if OpsEqual(taicpu(hp1).oper[0]^,taicpu(p).oper[1]^) then
  1080. { Removes the second statement from
  1081. mov reg1, mem1/reg2
  1082. mov mem1/reg2, reg1 }
  1083. begin
  1084. if (taicpu(p).oper[0]^.typ = top_reg) then
  1085. AllocRegBetween(asmL,taicpu(p).oper[0]^.reg,p,hp1,usedregs);
  1086. asml.remove(hp1);
  1087. hp1.free;
  1088. end
  1089. else
  1090. begin
  1091. TmpUsedRegs := UsedRegs;
  1092. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  1093. if (taicpu(p).oper[1]^.typ = top_ref) and
  1094. { mov reg1, mem1
  1095. mov mem2, reg1 }
  1096. (taicpu(hp1).oper[0]^.ref^.refaddr = addr_no) and
  1097. GetNextInstruction(hp1, hp2) and
  1098. (hp2.typ = ait_instruction) and
  1099. (taicpu(hp2).opcode = A_CMP) and
  1100. (taicpu(hp2).opsize = taicpu(p).opsize) and
  1101. (taicpu(hp2).oper[0]^.typ = TOp_Ref) and
  1102. (taicpu(hp2).oper[1]^.typ = TOp_Reg) and
  1103. RefsEqual(taicpu(hp2).oper[0]^.ref^, taicpu(p).oper[1]^.ref^) and
  1104. (taicpu(hp2).oper[1]^.reg= taicpu(p).oper[0]^.reg) and
  1105. not(RegUsedAfterInstruction(taicpu(p).oper[0]^.reg, hp2, TmpUsedRegs)) then
  1106. { change to
  1107. mov reg1, mem1 mov reg1, mem1
  1108. mov mem2, reg1 cmp reg1, mem2
  1109. cmp mem1, reg1 }
  1110. begin
  1111. asml.remove(hp2);
  1112. hp2.free;
  1113. taicpu(hp1).opcode := A_CMP;
  1114. taicpu(hp1).loadref(1,taicpu(hp1).oper[0]^.ref^);
  1115. taicpu(hp1).loadreg(0,taicpu(p).oper[0]^.reg);
  1116. end;
  1117. end;
  1118. end
  1119. else
  1120. begin
  1121. tmpUsedRegs := UsedRegs;
  1122. if GetNextInstruction(hp1, hp2) and
  1123. (taicpu(p).oper[0]^.typ = top_ref) and
  1124. (taicpu(p).oper[1]^.typ = top_reg) and
  1125. (taicpu(hp1).oper[0]^.typ = top_reg) and
  1126. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg) and
  1127. (taicpu(hp1).oper[1]^.typ = top_ref) and
  1128. (tai(hp2).typ = ait_instruction) and
  1129. (taicpu(hp2).opcode = A_MOV) and
  1130. (taicpu(hp2).opsize = taicpu(p).opsize) and
  1131. (taicpu(hp2).oper[1]^.typ = top_reg) and
  1132. (taicpu(hp2).oper[0]^.typ = top_ref) and
  1133. RefsEqual(taicpu(hp2).oper[0]^.ref^, taicpu(hp1).oper[1]^.ref^) then
  1134. if not regInRef(getsupreg(taicpu(hp2).oper[1]^.reg),taicpu(hp2).oper[0]^.ref^) and
  1135. not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,tmpUsedRegs)) then
  1136. { mov mem1, %reg1
  1137. mov %reg1, mem2
  1138. mov mem2, reg2
  1139. to:
  1140. mov mem1, reg2
  1141. mov reg2, mem2}
  1142. begin
  1143. AllocRegBetween(asmL,taicpu(hp2).oper[1]^.reg,p,hp2,usedregs);
  1144. taicpu(p).loadoper(1,taicpu(hp2).oper[1]^);
  1145. taicpu(hp1).loadoper(0,taicpu(hp2).oper[1]^);
  1146. asml.remove(hp2);
  1147. hp2.free;
  1148. end
  1149. else
  1150. if (taicpu(p).oper[1]^.reg <> taicpu(hp2).oper[1]^.reg) and
  1151. not(RegInRef(getsupreg(taicpu(p).oper[1]^.reg),taicpu(p).oper[0]^.ref^)) and
  1152. not(RegInRef(getsupreg(taicpu(hp2).oper[1]^.reg),taicpu(hp2).oper[0]^.ref^)) then
  1153. { mov mem1, reg1 mov mem1, reg1
  1154. mov reg1, mem2 mov reg1, mem2
  1155. mov mem2, reg2 mov mem2, reg1
  1156. to: to:
  1157. mov mem1, reg1 mov mem1, reg1
  1158. mov mem1, reg2 mov reg1, mem2
  1159. mov reg1, mem2
  1160. or (if mem1 depends on reg1
  1161. and/or if mem2 depends on reg2)
  1162. to:
  1163. mov mem1, reg1
  1164. mov reg1, mem2
  1165. mov reg1, reg2
  1166. }
  1167. begin
  1168. taicpu(hp1).loadRef(0,taicpu(p).oper[0]^.ref^);
  1169. taicpu(hp1).loadReg(1,taicpu(hp2).oper[1]^.reg);
  1170. taicpu(hp2).loadRef(1,taicpu(hp2).oper[0]^.ref^);
  1171. taicpu(hp2).loadReg(0,taicpu(p).oper[1]^.reg);
  1172. allocRegBetween(asmL,taicpu(p).oper[1]^.reg,p,hp2,usedregs);
  1173. if (taicpu(p).oper[0]^.ref^.base <> NR_NO) and
  1174. (getsupreg(taicpu(p).oper[0]^.ref^.base) in [RS_EAX,RS_EBX,RS_ECX,RS_EDX,RS_ESI,RS_EDI]) then
  1175. allocRegBetween(asmL,taicpu(p).oper[0]^.ref^.base,p,hp2,usedregs);
  1176. if (taicpu(p).oper[0]^.ref^.index <> NR_NO) and
  1177. (getsupreg(taicpu(p).oper[0]^.ref^.index) in [RS_EAX,RS_EBX,RS_ECX,RS_EDX,RS_ESI,RS_EDI]) then
  1178. allocRegBetween(asmL,taicpu(p).oper[0]^.ref^.index,p,hp2,usedregs);
  1179. end
  1180. else
  1181. if (taicpu(hp1).Oper[0]^.reg <> taicpu(hp2).Oper[1]^.reg) then
  1182. begin
  1183. taicpu(hp2).loadReg(0,taicpu(hp1).Oper[0]^.reg);
  1184. allocRegBetween(asmL,taicpu(p).oper[1]^.reg,p,hp2,usedregs);
  1185. end
  1186. else
  1187. begin
  1188. asml.remove(hp2);
  1189. hp2.free;
  1190. end
  1191. end
  1192. end
  1193. else
  1194. (* {movl [mem1],reg1
  1195. movl [mem1],reg2
  1196. to:
  1197. movl [mem1],reg1
  1198. movl reg1,reg2 }
  1199. if (taicpu(p).oper[0]^.typ = top_ref) and
  1200. (taicpu(p).oper[1]^.typ = top_reg) and
  1201. (taicpu(hp1).oper[0]^.typ = top_ref) and
  1202. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1203. (taicpu(p).opsize = taicpu(hp1).opsize) and
  1204. RefsEqual(TReference(taicpu(p).oper[0]^^),taicpu(hp1).oper[0]^^.ref^) and
  1205. (taicpu(p).oper[1]^.reg<>taicpu(hp1).oper[0]^^.ref^.base) and
  1206. (taicpu(p).oper[1]^.reg<>taicpu(hp1).oper[0]^^.ref^.index) then
  1207. taicpu(hp1).loadReg(0,taicpu(p).oper[1]^.reg)
  1208. else*)
  1209. { movl const1,[mem1]
  1210. movl [mem1],reg1
  1211. to:
  1212. movl const1,reg1
  1213. movl reg1,[mem1] }
  1214. if (taicpu(p).oper[0]^.typ = top_const) and
  1215. (taicpu(p).oper[1]^.typ = top_ref) and
  1216. (taicpu(hp1).oper[0]^.typ = top_ref) and
  1217. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1218. (taicpu(p).opsize = taicpu(hp1).opsize) and
  1219. RefsEqual(taicpu(hp1).oper[0]^.ref^,taicpu(p).oper[1]^.ref^) and
  1220. not(reginref(getsupreg(taicpu(hp1).oper[1]^.reg),taicpu(hp1).oper[0]^.ref^)) then
  1221. begin
  1222. allocregbetween(asml,taicpu(hp1).oper[1]^.reg,p,hp1,usedregs);
  1223. taicpu(hp1).loadReg(0,taicpu(hp1).oper[1]^.reg);
  1224. taicpu(hp1).loadRef(1,taicpu(p).oper[1]^.ref^);
  1225. taicpu(p).loadReg(1,taicpu(hp1).oper[0]^.reg);
  1226. end
  1227. end;
  1228. if GetNextInstruction(p, hp1) and
  1229. (Tai(hp1).typ = ait_instruction) and
  1230. ((Taicpu(hp1).opcode = A_BTS) or (Taicpu(hp1).opcode = A_BTR)) and
  1231. (Taicpu(hp1).opsize = Taicpu(p).opsize) and
  1232. GetNextInstruction(hp1, hp2) and
  1233. (Tai(hp2).typ = ait_instruction) and
  1234. (Taicpu(hp2).opcode = A_OR) and
  1235. (Taicpu(hp1).opsize = Taicpu(p).opsize) and
  1236. (Taicpu(hp2).opsize = Taicpu(p).opsize) and
  1237. (Taicpu(p).oper[0]^.typ = top_const) and (Taicpu(p).oper[0]^.val=0) and
  1238. (Taicpu(p).oper[1]^.typ = top_reg) and
  1239. (Taicpu(hp1).oper[1]^.typ = top_reg) and
  1240. (Taicpu(p).oper[1]^.reg=Taicpu(hp1).oper[1]^.reg) and
  1241. (Taicpu(hp2).oper[1]^.typ = top_reg) and
  1242. (Taicpu(p).oper[1]^.reg=Taicpu(hp2).oper[1]^.reg) then
  1243. {mov reg1,0
  1244. bts reg1,operand1 --> mov reg1,operand2
  1245. or reg1,operand2 bts reg1,operand1}
  1246. begin
  1247. Taicpu(hp2).opcode:=A_MOV;
  1248. asml.remove(hp1);
  1249. insertllitem(asml,hp2,hp2.next,hp1);
  1250. asml.remove(p);
  1251. p.free;
  1252. end;
  1253. end;
  1254. A_MOVSX,
  1255. A_MOVZX :
  1256. begin
  1257. if (taicpu(p).oper[1]^.typ = top_reg) and
  1258. GetNextInstruction(p,hp1) and
  1259. (hp1.typ = ait_instruction) and
  1260. IsFoldableArithOp(taicpu(hp1),taicpu(p).oper[1]^.reg) and
  1261. (getsupreg(taicpu(hp1).oper[0]^.reg) in [RS_EAX, RS_EBX, RS_ECX, RS_EDX]) and
  1262. GetNextInstruction(hp1,hp2) and
  1263. (hp2.typ = ait_instruction) and
  1264. (taicpu(hp2).opcode = A_MOV) and
  1265. (taicpu(hp2).oper[0]^.typ = top_reg) and
  1266. OpsEqual(taicpu(hp2).oper[1]^,taicpu(p).oper[0]^) then
  1267. { change movsX/movzX reg/ref, reg2 }
  1268. { add/sub/or/... reg3/$const, reg2 }
  1269. { mov reg2 reg/ref }
  1270. { to add/sub/or/... reg3/$const, reg/ref }
  1271. begin
  1272. { by example:
  1273. movswl %si,%eax movswl %si,%eax p
  1274. decl %eax addl %edx,%eax hp1
  1275. movw %ax,%si movw %ax,%si hp2
  1276. ->
  1277. movswl %si,%eax movswl %si,%eax p
  1278. decw %eax addw %edx,%eax hp1
  1279. movw %ax,%si movw %ax,%si hp2
  1280. }
  1281. taicpu(hp1).changeopsize(taicpu(hp2).opsize);
  1282. {
  1283. ->
  1284. movswl %si,%eax movswl %si,%eax p
  1285. decw %si addw %dx,%si hp1
  1286. movw %ax,%si movw %ax,%si hp2
  1287. }
  1288. case taicpu(hp1).ops of
  1289. 1:
  1290. taicpu(hp1).loadoper(0,taicpu(hp2).oper[1]^);
  1291. 2:
  1292. begin
  1293. taicpu(hp1).loadoper(1,taicpu(hp2).oper[1]^);
  1294. if (taicpu(hp1).oper[0]^.typ = top_reg) then
  1295. setsubreg(taicpu(hp1).oper[0]^.reg,getsubreg(taicpu(hp2).oper[0]^.reg));
  1296. end;
  1297. else
  1298. internalerror(2008042701);
  1299. end;
  1300. {
  1301. ->
  1302. decw %si addw %dx,%si p
  1303. }
  1304. asml.remove(p);
  1305. asml.remove(hp2);
  1306. p.free;
  1307. hp2.free;
  1308. p := hp1
  1309. end
  1310. { removes superfluous And's after movzx's }
  1311. else if taicpu(p).opcode=A_MOVZX then
  1312. begin
  1313. if (taicpu(p).oper[1]^.typ = top_reg) and
  1314. GetNextInstruction(p, hp1) and
  1315. (tai(hp1).typ = ait_instruction) and
  1316. (taicpu(hp1).opcode = A_AND) and
  1317. (taicpu(hp1).oper[0]^.typ = top_const) and
  1318. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1319. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1320. case taicpu(p).opsize Of
  1321. S_BL, S_BW:
  1322. if (taicpu(hp1).oper[0]^.val = $ff) then
  1323. begin
  1324. asml.remove(hp1);
  1325. hp1.free;
  1326. end;
  1327. S_WL:
  1328. if (taicpu(hp1).oper[0]^.val = $ffff) then
  1329. begin
  1330. asml.remove(hp1);
  1331. hp1.free;
  1332. end;
  1333. end;
  1334. {changes some movzx constructs to faster synonims (all examples
  1335. are given with eax/ax, but are also valid for other registers)}
  1336. if (taicpu(p).oper[1]^.typ = top_reg) then
  1337. if (taicpu(p).oper[0]^.typ = top_reg) then
  1338. case taicpu(p).opsize of
  1339. S_BW:
  1340. begin
  1341. if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) and
  1342. not(cs_opt_size in current_settings.optimizerswitches) then
  1343. {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
  1344. begin
  1345. taicpu(p).opcode := A_AND;
  1346. taicpu(p).changeopsize(S_W);
  1347. taicpu(p).loadConst(0,$ff);
  1348. end
  1349. else if GetNextInstruction(p, hp1) and
  1350. (tai(hp1).typ = ait_instruction) and
  1351. (taicpu(hp1).opcode = A_AND) and
  1352. (taicpu(hp1).oper[0]^.typ = top_const) and
  1353. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1354. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1355. {Change "movzbw %reg1, %reg2; andw $const, %reg2"
  1356. to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
  1357. begin
  1358. taicpu(p).opcode := A_MOV;
  1359. taicpu(p).changeopsize(S_W);
  1360. setsubreg(taicpu(p).oper[0]^.reg,R_SUBW);
  1361. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  1362. end;
  1363. end;
  1364. S_BL:
  1365. begin
  1366. if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) and
  1367. not(cs_opt_size in current_settings.optimizerswitches) then
  1368. {Change "movzbl %al, %eax" to "andl $0x0ffh, %eax"}
  1369. begin
  1370. taicpu(p).opcode := A_AND;
  1371. taicpu(p).changeopsize(S_L);
  1372. taicpu(p).loadConst(0,$ff)
  1373. end
  1374. else if GetNextInstruction(p, hp1) and
  1375. (tai(hp1).typ = ait_instruction) and
  1376. (taicpu(hp1).opcode = A_AND) and
  1377. (taicpu(hp1).oper[0]^.typ = top_const) and
  1378. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1379. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1380. {Change "movzbl %reg1, %reg2; andl $const, %reg2"
  1381. to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
  1382. begin
  1383. taicpu(p).opcode := A_MOV;
  1384. taicpu(p).changeopsize(S_L);
  1385. setsubreg(taicpu(p).oper[0]^.reg,R_SUBWHOLE);
  1386. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  1387. end
  1388. end;
  1389. S_WL:
  1390. begin
  1391. if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) and
  1392. not(cs_opt_size in current_settings.optimizerswitches) then
  1393. {Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax"}
  1394. begin
  1395. taicpu(p).opcode := A_AND;
  1396. taicpu(p).changeopsize(S_L);
  1397. taicpu(p).loadConst(0,$ffff);
  1398. end
  1399. else if GetNextInstruction(p, hp1) and
  1400. (tai(hp1).typ = ait_instruction) and
  1401. (taicpu(hp1).opcode = A_AND) and
  1402. (taicpu(hp1).oper[0]^.typ = top_const) and
  1403. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1404. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1405. {Change "movzwl %reg1, %reg2; andl $const, %reg2"
  1406. to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
  1407. begin
  1408. taicpu(p).opcode := A_MOV;
  1409. taicpu(p).changeopsize(S_L);
  1410. setsubreg(taicpu(p).oper[0]^.reg,R_SUBWHOLE);
  1411. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ffff);
  1412. end;
  1413. end;
  1414. end
  1415. else if (taicpu(p).oper[0]^.typ = top_ref) then
  1416. begin
  1417. if GetNextInstruction(p, hp1) and
  1418. (tai(hp1).typ = ait_instruction) and
  1419. (taicpu(hp1).opcode = A_AND) and
  1420. (taicpu(hp1).oper[0]^.typ = Top_Const) and
  1421. (taicpu(hp1).oper[1]^.typ = Top_Reg) and
  1422. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1423. begin
  1424. taicpu(p).opcode := A_MOV;
  1425. case taicpu(p).opsize Of
  1426. S_BL:
  1427. begin
  1428. taicpu(p).changeopsize(S_L);
  1429. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  1430. end;
  1431. S_WL:
  1432. begin
  1433. taicpu(p).changeopsize(S_L);
  1434. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ffff);
  1435. end;
  1436. S_BW:
  1437. begin
  1438. taicpu(p).changeopsize(S_W);
  1439. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  1440. end;
  1441. end;
  1442. end;
  1443. end;
  1444. end;
  1445. end;
  1446. (* should not be generated anymore by the current code generator
  1447. A_POP:
  1448. begin
  1449. if target_info.system=system_i386_go32v2 then
  1450. begin
  1451. { Transform a series of pop/pop/pop/push/push/push to }
  1452. { 'movl x(%esp),%reg' for go32v2 (not for the rest, }
  1453. { because I'm not sure whether they can cope with }
  1454. { 'movl x(%esp),%reg' with x > 0, I believe we had }
  1455. { such a problem when using esp as frame pointer (JM) }
  1456. if (taicpu(p).oper[0]^.typ = top_reg) then
  1457. begin
  1458. hp1 := p;
  1459. hp2 := p;
  1460. l := 0;
  1461. while getNextInstruction(hp1,hp1) and
  1462. (hp1.typ = ait_instruction) and
  1463. (taicpu(hp1).opcode = A_POP) and
  1464. (taicpu(hp1).oper[0]^.typ = top_reg) do
  1465. begin
  1466. hp2 := hp1;
  1467. inc(l,4);
  1468. end;
  1469. getLastInstruction(p,hp3);
  1470. l1 := 0;
  1471. while (hp2 <> hp3) and
  1472. assigned(hp1) and
  1473. (hp1.typ = ait_instruction) and
  1474. (taicpu(hp1).opcode = A_PUSH) and
  1475. (taicpu(hp1).oper[0]^.typ = top_reg) and
  1476. (taicpu(hp1).oper[0]^.reg.enum = taicpu(hp2).oper[0]^.reg.enum) do
  1477. begin
  1478. { change it to a two op operation }
  1479. taicpu(hp2).oper[1]^.typ:=top_none;
  1480. taicpu(hp2).ops:=2;
  1481. taicpu(hp2).opcode := A_MOV;
  1482. taicpu(hp2).loadoper(1,taicpu(hp1).oper[0]^);
  1483. reference_reset(tmpref);
  1484. tmpRef.base.enum:=R_INTREGISTER;
  1485. tmpRef.base.number:=NR_STACK_POINTER_REG;
  1486. convert_register_to_enum(tmpref.base);
  1487. tmpRef.offset := l;
  1488. taicpu(hp2).loadRef(0,tmpRef);
  1489. hp4 := hp1;
  1490. getNextInstruction(hp1,hp1);
  1491. asml.remove(hp4);
  1492. hp4.free;
  1493. getLastInstruction(hp2,hp2);
  1494. dec(l,4);
  1495. inc(l1);
  1496. end;
  1497. if l <> -4 then
  1498. begin
  1499. inc(l,4);
  1500. for l1 := l1 downto 1 do
  1501. begin
  1502. getNextInstruction(hp2,hp2);
  1503. dec(taicpu(hp2).oper[0]^.ref^.offset,l);
  1504. end
  1505. end
  1506. end
  1507. end
  1508. else
  1509. begin
  1510. if (taicpu(p).oper[0]^.typ = top_reg) and
  1511. GetNextInstruction(p, hp1) and
  1512. (tai(hp1).typ=ait_instruction) and
  1513. (taicpu(hp1).opcode=A_PUSH) and
  1514. (taicpu(hp1).oper[0]^.typ = top_reg) and
  1515. (taicpu(hp1).oper[0]^.reg.enum=taicpu(p).oper[0]^.reg.enum) then
  1516. begin
  1517. { change it to a two op operation }
  1518. taicpu(p).oper[1]^.typ:=top_none;
  1519. taicpu(p).ops:=2;
  1520. taicpu(p).opcode := A_MOV;
  1521. taicpu(p).loadoper(1,taicpu(p).oper[0]^);
  1522. reference_reset(tmpref);
  1523. TmpRef.base.enum := R_ESP;
  1524. taicpu(p).loadRef(0,TmpRef);
  1525. asml.remove(hp1);
  1526. hp1.free;
  1527. end;
  1528. end;
  1529. end;
  1530. *)
  1531. A_PUSH:
  1532. begin
  1533. if (taicpu(p).opsize = S_W) and
  1534. (taicpu(p).oper[0]^.typ = Top_Const) and
  1535. GetNextInstruction(p, hp1) and
  1536. (tai(hp1).typ = ait_instruction) and
  1537. (taicpu(hp1).opcode = A_PUSH) and
  1538. (taicpu(hp1).oper[0]^.typ = Top_Const) and
  1539. (taicpu(hp1).opsize = S_W) then
  1540. begin
  1541. taicpu(p).changeopsize(S_L);
  1542. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val shl 16 + word(taicpu(hp1).oper[0]^.val));
  1543. asml.remove(hp1);
  1544. hp1.free;
  1545. end;
  1546. end;
  1547. A_SHL, A_SAL:
  1548. begin
  1549. if (taicpu(p).oper[0]^.typ = Top_Const) and
  1550. (taicpu(p).oper[1]^.typ = Top_Reg) and
  1551. (taicpu(p).opsize = S_L) and
  1552. (taicpu(p).oper[0]^.val <= 3) then
  1553. {Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement}
  1554. begin
  1555. TmpBool1 := True; {should we check the next instruction?}
  1556. TmpBool2 := False; {have we found an add/sub which could be
  1557. integrated in the lea?}
  1558. reference_reset(tmpref,2);
  1559. TmpRef.index := taicpu(p).oper[1]^.reg;
  1560. TmpRef.scalefactor := 1 shl taicpu(p).oper[0]^.val;
  1561. while TmpBool1 and
  1562. GetNextInstruction(p, hp1) and
  1563. (tai(hp1).typ = ait_instruction) and
  1564. ((((taicpu(hp1).opcode = A_ADD) or
  1565. (taicpu(hp1).opcode = A_SUB)) and
  1566. (taicpu(hp1).oper[1]^.typ = Top_Reg) and
  1567. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg)) or
  1568. (((taicpu(hp1).opcode = A_INC) or
  1569. (taicpu(hp1).opcode = A_DEC)) and
  1570. (taicpu(hp1).oper[0]^.typ = Top_Reg) and
  1571. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg))) and
  1572. (not GetNextInstruction(hp1,hp2) or
  1573. not instrReadsFlags(hp2)) Do
  1574. begin
  1575. TmpBool1 := False;
  1576. if (taicpu(hp1).oper[0]^.typ = Top_Const) then
  1577. begin
  1578. TmpBool1 := True;
  1579. TmpBool2 := True;
  1580. case taicpu(hp1).opcode of
  1581. A_ADD:
  1582. inc(TmpRef.offset, longint(taicpu(hp1).oper[0]^.val));
  1583. A_SUB:
  1584. dec(TmpRef.offset, longint(taicpu(hp1).oper[0]^.val));
  1585. end;
  1586. asml.remove(hp1);
  1587. hp1.free;
  1588. end
  1589. else
  1590. if (taicpu(hp1).oper[0]^.typ = Top_Reg) and
  1591. (((taicpu(hp1).opcode = A_ADD) and
  1592. (TmpRef.base = NR_NO)) or
  1593. (taicpu(hp1).opcode = A_INC) or
  1594. (taicpu(hp1).opcode = A_DEC)) then
  1595. begin
  1596. TmpBool1 := True;
  1597. TmpBool2 := True;
  1598. case taicpu(hp1).opcode of
  1599. A_ADD:
  1600. TmpRef.base := taicpu(hp1).oper[0]^.reg;
  1601. A_INC:
  1602. inc(TmpRef.offset);
  1603. A_DEC:
  1604. dec(TmpRef.offset);
  1605. end;
  1606. asml.remove(hp1);
  1607. hp1.free;
  1608. end;
  1609. end;
  1610. if TmpBool2 or
  1611. ((current_settings.optimizecputype < cpu_Pentium2) and
  1612. (taicpu(p).oper[0]^.val <= 3) and
  1613. not(cs_opt_size in current_settings.optimizerswitches)) then
  1614. begin
  1615. if not(TmpBool2) and
  1616. (taicpu(p).oper[0]^.val = 1) then
  1617. begin
  1618. hp1 := taicpu.Op_reg_reg(A_ADD,taicpu(p).opsize,
  1619. taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg)
  1620. end
  1621. else
  1622. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef,
  1623. taicpu(p).oper[1]^.reg);
  1624. InsertLLItem(asml,p.previous, p.next, hp1);
  1625. p.free;
  1626. p := hp1;
  1627. end;
  1628. end
  1629. else
  1630. if (current_settings.optimizecputype < cpu_Pentium2) and
  1631. (taicpu(p).oper[0]^.typ = top_const) and
  1632. (taicpu(p).oper[1]^.typ = top_reg) then
  1633. if (taicpu(p).oper[0]^.val = 1) then
  1634. {changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
  1635. but faster on a 486, and Tairable in both U and V pipes on the Pentium
  1636. (unlike shl, which is only Tairable in the U pipe)}
  1637. begin
  1638. hp1 := taicpu.Op_reg_reg(A_ADD,taicpu(p).opsize,
  1639. taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg);
  1640. InsertLLItem(asml,p.previous, p.next, hp1);
  1641. p.free;
  1642. p := hp1;
  1643. end
  1644. else if (taicpu(p).opsize = S_L) and
  1645. (taicpu(p).oper[0]^.val<= 3) then
  1646. {changes "shl $2, %reg" to "lea (,%reg,4), %reg"
  1647. "shl $3, %reg" to "lea (,%reg,8), %reg}
  1648. begin
  1649. reference_reset(tmpref,2);
  1650. TmpRef.index := taicpu(p).oper[1]^.reg;
  1651. TmpRef.scalefactor := 1 shl taicpu(p).oper[0]^.val;
  1652. hp1 := taicpu.Op_ref_reg(A_LEA,S_L,TmpRef, taicpu(p).oper[1]^.reg);
  1653. InsertLLItem(asml,p.previous, p.next, hp1);
  1654. p.free;
  1655. p := hp1;
  1656. end
  1657. end;
  1658. A_SETcc :
  1659. { changes
  1660. setcc (funcres) setcc reg
  1661. movb (funcres), reg to leave/ret
  1662. leave/ret }
  1663. begin
  1664. if (taicpu(p).oper[0]^.typ = top_ref) and
  1665. GetNextInstruction(p, hp1) and
  1666. GetNextInstruction(hp1, hp2) and
  1667. (hp2.typ = ait_instruction) and
  1668. ((taicpu(hp2).opcode = A_LEAVE) or
  1669. (taicpu(hp2).opcode = A_RET)) and
  1670. (taicpu(p).oper[0]^.ref^.base = current_procinfo.FramePointer) and
  1671. (taicpu(p).oper[0]^.ref^.index = NR_NO) and
  1672. not(assigned(current_procinfo.procdef.funcretsym) and
  1673. (taicpu(p).oper[0]^.ref^.offset < tabstractnormalvarsym(current_procinfo.procdef.funcretsym).localloc.reference.offset)) and
  1674. (hp1.typ = ait_instruction) and
  1675. (taicpu(hp1).opcode = A_MOV) and
  1676. (taicpu(hp1).opsize = S_B) and
  1677. (taicpu(hp1).oper[0]^.typ = top_ref) and
  1678. RefsEqual(taicpu(hp1).oper[0]^.ref^, taicpu(p).oper[0]^.ref^) then
  1679. begin
  1680. taicpu(p).loadReg(0,taicpu(hp1).oper[1]^.reg);
  1681. asml.remove(hp1);
  1682. hp1.free;
  1683. end
  1684. end;
  1685. A_SUB:
  1686. { * change "subl $2, %esp; pushw x" to "pushl x"}
  1687. { * change "sub/add const1, reg" or "dec reg" followed by
  1688. "sub const2, reg" to one "sub ..., reg" }
  1689. begin
  1690. if (taicpu(p).oper[0]^.typ = top_const) and
  1691. (taicpu(p).oper[1]^.typ = top_reg) then
  1692. if (taicpu(p).oper[0]^.val = 2) and
  1693. (taicpu(p).oper[1]^.reg = NR_ESP) and
  1694. { Don't do the sub/push optimization if the sub }
  1695. { comes from setting up the stack frame (JM) }
  1696. (not getLastInstruction(p,hp1) or
  1697. (hp1.typ <> ait_instruction) or
  1698. (taicpu(hp1).opcode <> A_MOV) or
  1699. (taicpu(hp1).oper[0]^.typ <> top_reg) or
  1700. (taicpu(hp1).oper[0]^.reg <> NR_ESP) or
  1701. (taicpu(hp1).oper[1]^.typ <> top_reg) or
  1702. (taicpu(hp1).oper[1]^.reg <> NR_EBP)) then
  1703. begin
  1704. hp1 := tai(p.next);
  1705. while Assigned(hp1) and
  1706. (tai(hp1).typ in [ait_instruction]+SkipInstr) and
  1707. not regReadByInstruction(RS_ESP,hp1) and
  1708. not regModifiedByInstruction(RS_ESP,hp1) do
  1709. hp1 := tai(hp1.next);
  1710. if Assigned(hp1) and
  1711. (tai(hp1).typ = ait_instruction) and
  1712. (taicpu(hp1).opcode = A_PUSH) and
  1713. (taicpu(hp1).opsize = S_W) then
  1714. begin
  1715. taicpu(hp1).changeopsize(S_L);
  1716. if taicpu(hp1).oper[0]^.typ=top_reg then
  1717. setsubreg(taicpu(hp1).oper[0]^.reg,R_SUBWHOLE);
  1718. hp1 := tai(p.next);
  1719. asml.remove(p);
  1720. p.free;
  1721. p := hp1;
  1722. continue
  1723. end;
  1724. if DoSubAddOpt(p) then
  1725. continue;
  1726. end
  1727. else if DoSubAddOpt(p) then
  1728. continue
  1729. end;
  1730. end;
  1731. end; { if is_jmp }
  1732. end;
  1733. end;
  1734. updateUsedRegs(UsedRegs,p);
  1735. p:=tai(p.next);
  1736. end;
  1737. end;
  1738. procedure PeepHoleOptPass2(asml: TAsmList; BlockStart, BlockEnd: tai);
  1739. function CanBeCMOV(p : tai) : boolean;
  1740. begin
  1741. CanBeCMOV:=assigned(p) and (p.typ=ait_instruction) and
  1742. (taicpu(p).opcode=A_MOV) and
  1743. (taicpu(p).opsize in [S_L,S_W]) and
  1744. ((taicpu(p).oper[0]^.typ = top_reg)
  1745. { we can't use cmov ref,reg because
  1746. ref could be nil and cmov still throws an exception
  1747. if ref=nil but the mov isn't done (FK)
  1748. or ((taicpu(p).oper[0]^.typ = top_ref) and
  1749. (taicpu(p).oper[0]^.ref^.refaddr = addr_no))
  1750. }
  1751. ) and
  1752. (taicpu(p).oper[1]^.typ in [top_reg]);
  1753. end;
  1754. var
  1755. p,hp1,hp2: tai;
  1756. l : longint;
  1757. condition : tasmcond;
  1758. hp3: tai;
  1759. UsedRegs, TmpUsedRegs: TRegSet;
  1760. carryadd_opcode: Tasmop;
  1761. begin
  1762. p := BlockStart;
  1763. UsedRegs := [];
  1764. while (p <> BlockEnd) Do
  1765. begin
  1766. UpdateUsedRegs(UsedRegs, tai(p.next));
  1767. case p.Typ Of
  1768. Ait_Instruction:
  1769. begin
  1770. if InsContainsSegRef(taicpu(p)) then
  1771. begin
  1772. p := tai(p.next);
  1773. continue;
  1774. end;
  1775. case taicpu(p).opcode Of
  1776. A_Jcc:
  1777. begin
  1778. { jb @@1 cmc
  1779. inc/dec operand --> adc/sbb operand,0
  1780. @@1:
  1781. ... and ...
  1782. jnb @@1
  1783. inc/dec operand --> adc/sbb operand,0
  1784. @@1: }
  1785. if GetNextInstruction(p,hp1) and (hp1.typ=ait_instruction) and
  1786. GetNextInstruction(hp1,hp2) and (hp2.typ=ait_label) and
  1787. (Tasmlabel(Taicpu(p).oper[0]^.ref^.symbol)=Tai_label(hp2).labsym) then
  1788. begin
  1789. carryadd_opcode:=A_NONE;
  1790. if Taicpu(p).condition in [C_NAE,C_B] then
  1791. begin
  1792. if Taicpu(hp1).opcode=A_INC then
  1793. carryadd_opcode:=A_ADC;
  1794. if Taicpu(hp1).opcode=A_DEC then
  1795. carryadd_opcode:=A_SBB;
  1796. if carryadd_opcode<>A_NONE then
  1797. begin
  1798. Taicpu(p).clearop(0);
  1799. Taicpu(p).ops:=0;
  1800. Taicpu(p).is_jmp:=false;
  1801. Taicpu(p).opcode:=A_CMC;
  1802. Taicpu(p).condition:=C_NONE;
  1803. Taicpu(hp1).ops:=2;
  1804. Taicpu(hp1).loadoper(1,Taicpu(hp1).oper[0]^);
  1805. Taicpu(hp1).loadconst(0,0);
  1806. Taicpu(hp1).opcode:=carryadd_opcode;
  1807. continue;
  1808. end;
  1809. end;
  1810. if Taicpu(p).condition in [C_AE,C_NB] then
  1811. begin
  1812. if Taicpu(hp1).opcode=A_INC then
  1813. carryadd_opcode:=A_ADC;
  1814. if Taicpu(hp1).opcode=A_DEC then
  1815. carryadd_opcode:=A_SBB;
  1816. if carryadd_opcode<>A_NONE then
  1817. begin
  1818. asml.remove(p);
  1819. p.free;
  1820. Taicpu(hp1).ops:=2;
  1821. Taicpu(hp1).loadoper(1,Taicpu(hp1).oper[0]^);
  1822. Taicpu(hp1).loadconst(0,0);
  1823. Taicpu(hp1).opcode:=carryadd_opcode;
  1824. p:=hp1;
  1825. continue;
  1826. end;
  1827. end;
  1828. end;
  1829. if (current_settings.cputype>=cpu_Pentium2) then
  1830. begin
  1831. { check for
  1832. jCC xxx
  1833. <several movs>
  1834. xxx:
  1835. }
  1836. l:=0;
  1837. GetNextInstruction(p, hp1);
  1838. while assigned(hp1) and
  1839. CanBeCMOV(hp1) and
  1840. { stop on labels }
  1841. not(hp1.typ=ait_label) do
  1842. begin
  1843. inc(l);
  1844. GetNextInstruction(hp1,hp1);
  1845. end;
  1846. if assigned(hp1) then
  1847. begin
  1848. if FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol),hp1) then
  1849. begin
  1850. if (l<=4) and (l>0) then
  1851. begin
  1852. condition:=inverse_cond(taicpu(p).condition);
  1853. hp2:=p;
  1854. GetNextInstruction(p,hp1);
  1855. p:=hp1;
  1856. repeat
  1857. taicpu(hp1).opcode:=A_CMOVcc;
  1858. taicpu(hp1).condition:=condition;
  1859. GetNextInstruction(hp1,hp1);
  1860. until not(assigned(hp1)) or
  1861. not(CanBeCMOV(hp1));
  1862. { wait with removing else GetNextInstruction could
  1863. ignore the label if it was the only usage in the
  1864. jump moved away }
  1865. tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol).decrefs;
  1866. asml.remove(hp2);
  1867. hp2.free;
  1868. continue;
  1869. end;
  1870. end
  1871. else
  1872. begin
  1873. { check further for
  1874. jCC xxx
  1875. <several movs 1>
  1876. jmp yyy
  1877. xxx:
  1878. <several movs 2>
  1879. yyy:
  1880. }
  1881. { hp2 points to jmp yyy }
  1882. hp2:=hp1;
  1883. { skip hp1 to xxx }
  1884. GetNextInstruction(hp1, hp1);
  1885. if assigned(hp2) and
  1886. assigned(hp1) and
  1887. (l<=3) and
  1888. (hp2.typ=ait_instruction) and
  1889. (taicpu(hp2).is_jmp) and
  1890. (taicpu(hp2).condition=C_None) and
  1891. { real label and jump, no further references to the
  1892. label are allowed }
  1893. (tasmlabel(taicpu(p).oper[0]^.ref^.symbol).getrefs=2) and
  1894. FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol),hp1) then
  1895. begin
  1896. l:=0;
  1897. { skip hp1 to <several moves 2> }
  1898. GetNextInstruction(hp1, hp1);
  1899. while assigned(hp1) and
  1900. CanBeCMOV(hp1) do
  1901. begin
  1902. inc(l);
  1903. GetNextInstruction(hp1, hp1);
  1904. end;
  1905. { hp1 points to yyy: }
  1906. if assigned(hp1) and
  1907. FindLabel(tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol),hp1) then
  1908. begin
  1909. condition:=inverse_cond(taicpu(p).condition);
  1910. GetNextInstruction(p,hp1);
  1911. hp3:=p;
  1912. p:=hp1;
  1913. repeat
  1914. taicpu(hp1).opcode:=A_CMOVcc;
  1915. taicpu(hp1).condition:=condition;
  1916. GetNextInstruction(hp1,hp1);
  1917. until not(assigned(hp1)) or
  1918. not(CanBeCMOV(hp1));
  1919. { hp2 is still at jmp yyy }
  1920. GetNextInstruction(hp2,hp1);
  1921. { hp2 is now at xxx: }
  1922. condition:=inverse_cond(condition);
  1923. GetNextInstruction(hp1,hp1);
  1924. { hp1 is now at <several movs 2> }
  1925. repeat
  1926. taicpu(hp1).opcode:=A_CMOVcc;
  1927. taicpu(hp1).condition:=condition;
  1928. GetNextInstruction(hp1,hp1);
  1929. until not(assigned(hp1)) or
  1930. not(CanBeCMOV(hp1));
  1931. {
  1932. asml.remove(hp1.next)
  1933. hp1.next.free;
  1934. asml.remove(hp1);
  1935. hp1.free;
  1936. }
  1937. { remove jCC }
  1938. tasmlabel(taicpu(hp3).oper[0]^.ref^.symbol).decrefs;
  1939. asml.remove(hp3);
  1940. hp3.free;
  1941. { remove jmp }
  1942. tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol).decrefs;
  1943. asml.remove(hp2);
  1944. hp2.free;
  1945. continue;
  1946. end;
  1947. end;
  1948. end;
  1949. end;
  1950. end;
  1951. end;
  1952. A_FSTP,A_FISTP:
  1953. if doFpuLoadStoreOpt(asmL,p) then
  1954. continue;
  1955. A_IMUL:
  1956. begin
  1957. if (taicpu(p).ops >= 2) and
  1958. ((taicpu(p).oper[0]^.typ = top_const) or
  1959. ((taicpu(p).oper[0]^.typ = top_ref) and (taicpu(p).oper[0]^.ref^.refaddr=addr_full))) and
  1960. (taicpu(p).oper[1]^.typ = top_reg) and
  1961. ((taicpu(p).ops = 2) or
  1962. ((taicpu(p).oper[2]^.typ = top_reg) and
  1963. (taicpu(p).oper[2]^.reg = taicpu(p).oper[1]^.reg))) and
  1964. getLastInstruction(p,hp1) and
  1965. (hp1.typ = ait_instruction) and
  1966. (taicpu(hp1).opcode = A_MOV) and
  1967. (taicpu(hp1).oper[0]^.typ = top_reg) and
  1968. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1969. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1970. { change "mov reg1,reg2; imul y,reg2" to "imul y,reg1,reg2" }
  1971. begin
  1972. taicpu(p).ops := 3;
  1973. taicpu(p).loadreg(1,taicpu(hp1).oper[0]^.reg);
  1974. taicpu(p).loadreg(2,taicpu(hp1).oper[1]^.reg);
  1975. asml.remove(hp1);
  1976. hp1.free;
  1977. end;
  1978. end;
  1979. A_MOV:
  1980. begin
  1981. if (taicpu(p).oper[0]^.typ = top_reg) and
  1982. (taicpu(p).oper[1]^.typ = top_reg) and
  1983. GetNextInstruction(p, hp1) and
  1984. (hp1.typ = ait_Instruction) and
  1985. ((taicpu(hp1).opcode = A_MOV) or
  1986. (taicpu(hp1).opcode = A_MOVZX) or
  1987. (taicpu(hp1).opcode = A_MOVSX)) and
  1988. (taicpu(hp1).oper[0]^.typ = top_ref) and
  1989. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1990. ((taicpu(hp1).oper[0]^.ref^.base = taicpu(p).oper[1]^.reg) or
  1991. (taicpu(hp1).oper[0]^.ref^.index = taicpu(p).oper[1]^.reg)) and
  1992. (getsupreg(taicpu(hp1).oper[1]^.reg) = getsupreg(taicpu(p).oper[1]^.reg)) then
  1993. {mov reg1, reg2
  1994. mov/zx/sx (reg2, ..), reg2 to mov/zx/sx (reg1, ..), reg2}
  1995. begin
  1996. if (taicpu(hp1).oper[0]^.ref^.base = taicpu(p).oper[1]^.reg) then
  1997. taicpu(hp1).oper[0]^.ref^.base := taicpu(p).oper[0]^.reg;
  1998. if (taicpu(hp1).oper[0]^.ref^.index = taicpu(p).oper[1]^.reg) then
  1999. taicpu(hp1).oper[0]^.ref^.index := taicpu(p).oper[0]^.reg;
  2000. asml.remove(p);
  2001. p.free;
  2002. p := hp1;
  2003. continue;
  2004. end
  2005. else if (taicpu(p).oper[0]^.typ = top_ref) and
  2006. GetNextInstruction(p,hp1) and
  2007. (hp1.typ = ait_instruction) and
  2008. IsFoldableArithOp(taicpu(hp1),taicpu(p).oper[1]^.reg) and
  2009. GetNextInstruction(hp1,hp2) and
  2010. (hp2.typ = ait_instruction) and
  2011. (taicpu(hp2).opcode = A_MOV) and
  2012. (taicpu(hp2).oper[0]^.typ = top_reg) and
  2013. (taicpu(hp2).oper[0]^.reg = taicpu(p).oper[1]^.reg) and
  2014. (taicpu(hp2).oper[1]^.typ = top_ref) then
  2015. begin
  2016. TmpUsedRegs := UsedRegs;
  2017. UpdateUsedRegs(TmpUsedRegs,tai(hp1.next));
  2018. if (RefsEqual(taicpu(hp2).oper[1]^.ref^, taicpu(p).oper[0]^.ref^) and
  2019. not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,
  2020. hp2, TmpUsedRegs))) then
  2021. { change mov (ref), reg }
  2022. { add/sub/or/... reg2/$const, reg }
  2023. { mov reg, (ref) }
  2024. { # release reg }
  2025. { to add/sub/or/... reg2/$const, (ref) }
  2026. begin
  2027. case taicpu(hp1).opcode of
  2028. A_INC,A_DEC:
  2029. taicpu(hp1).loadRef(0,taicpu(p).oper[0]^.ref^)
  2030. else
  2031. taicpu(hp1).loadRef(1,taicpu(p).oper[0]^.ref^);
  2032. end;
  2033. asml.remove(p);
  2034. asml.remove(hp2);
  2035. p.free;
  2036. hp2.free;
  2037. p := hp1
  2038. end;
  2039. end
  2040. end;
  2041. end;
  2042. end;
  2043. end;
  2044. p := tai(p.next)
  2045. end;
  2046. end;
  2047. procedure PostPeepHoleOpts(asml: TAsmList; BlockStart, BlockEnd: tai);
  2048. var
  2049. p,hp1,hp2: tai;
  2050. begin
  2051. p := BlockStart;
  2052. while (p <> BlockEnd) Do
  2053. begin
  2054. case p.Typ Of
  2055. Ait_Instruction:
  2056. begin
  2057. if InsContainsSegRef(taicpu(p)) then
  2058. begin
  2059. p := tai(p.next);
  2060. continue;
  2061. end;
  2062. case taicpu(p).opcode Of
  2063. A_CALL:
  2064. if (current_settings.optimizecputype < cpu_Pentium2) and
  2065. not(cs_create_pic in current_settings.moduleswitches) and
  2066. GetNextInstruction(p, hp1) and
  2067. (hp1.typ = ait_instruction) and
  2068. (taicpu(hp1).opcode = A_JMP) and
  2069. ((taicpu(hp1).oper[0]^.typ=top_ref) and (taicpu(hp1).oper[0]^.ref^.refaddr=addr_full)) then
  2070. begin
  2071. hp2 := taicpu.Op_sym(A_PUSH,S_L,taicpu(hp1).oper[0]^.ref^.symbol);
  2072. InsertLLItem(asml, p.previous, p, hp2);
  2073. taicpu(p).opcode := A_JMP;
  2074. taicpu(p).is_jmp := true;
  2075. asml.remove(hp1);
  2076. hp1.free;
  2077. end;
  2078. A_CMP:
  2079. begin
  2080. if (taicpu(p).oper[0]^.typ = top_const) and
  2081. (taicpu(p).oper[0]^.val = 0) and
  2082. (taicpu(p).oper[1]^.typ = top_reg) then
  2083. {change "cmp $0, %reg" to "test %reg, %reg"}
  2084. begin
  2085. taicpu(p).opcode := A_TEST;
  2086. taicpu(p).loadreg(0,taicpu(p).oper[1]^.reg);
  2087. continue;
  2088. end;
  2089. end;
  2090. (*
  2091. Optimization is not safe; xor clears the carry flag.
  2092. See test/tgadint64 in the test suite.
  2093. A_MOV:
  2094. if (taicpu(p).oper[0]^.typ = Top_Const) and
  2095. (taicpu(p).oper[0]^.val = 0) and
  2096. (taicpu(p).oper[1]^.typ = Top_Reg) then
  2097. { change "mov $0, %reg" into "xor %reg, %reg" }
  2098. begin
  2099. taicpu(p).opcode := A_XOR;
  2100. taicpu(p).loadReg(0,taicpu(p).oper[1]^.reg);
  2101. end;
  2102. *)
  2103. A_MOVZX:
  2104. { if register vars are on, it's possible there is code like }
  2105. { "cmpl $3,%eax; movzbl 8(%ebp),%ebx; je .Lxxx" }
  2106. { so we can't safely replace the movzx then with xor/mov, }
  2107. { since that would change the flags (JM) }
  2108. if not(cs_opt_regvar in current_settings.optimizerswitches) then
  2109. begin
  2110. if (taicpu(p).oper[1]^.typ = top_reg) then
  2111. if (taicpu(p).oper[0]^.typ = top_reg)
  2112. then
  2113. case taicpu(p).opsize of
  2114. S_BL:
  2115. begin
  2116. if IsGP32Reg(getsupreg(taicpu(p).oper[1]^.reg)) and
  2117. not(cs_opt_size in current_settings.optimizerswitches) and
  2118. (current_settings.optimizecputype = cpu_Pentium) then
  2119. {Change "movzbl %reg1, %reg2" to
  2120. "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
  2121. PentiumMMX}
  2122. begin
  2123. hp1 := taicpu.op_reg_reg(A_XOR, S_L,
  2124. taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg);
  2125. InsertLLItem(asml,p.previous, p, hp1);
  2126. taicpu(p).opcode := A_MOV;
  2127. taicpu(p).changeopsize(S_B);
  2128. setsubreg(taicpu(p).oper[1]^.reg,R_SUBL);
  2129. end;
  2130. end;
  2131. end
  2132. else if (taicpu(p).oper[0]^.typ = top_ref) and
  2133. (taicpu(p).oper[0]^.ref^.base <> taicpu(p).oper[1]^.reg) and
  2134. (taicpu(p).oper[0]^.ref^.index <> taicpu(p).oper[1]^.reg) and
  2135. not(cs_opt_size in current_settings.optimizerswitches) and
  2136. IsGP32Reg(getsupreg(taicpu(p).oper[1]^.reg)) and
  2137. (current_settings.optimizecputype = cpu_Pentium) and
  2138. (taicpu(p).opsize = S_BL) then
  2139. {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
  2140. Pentium and PentiumMMX}
  2141. begin
  2142. hp1 := taicpu.Op_reg_reg(A_XOR, S_L, taicpu(p).oper[1]^.reg,
  2143. taicpu(p).oper[1]^.reg);
  2144. taicpu(p).opcode := A_MOV;
  2145. taicpu(p).changeopsize(S_B);
  2146. setsubreg(taicpu(p).oper[1]^.reg,R_SUBL);
  2147. InsertLLItem(asml,p.previous, p, hp1);
  2148. end;
  2149. end;
  2150. A_TEST, A_OR:
  2151. {removes the line marked with (x) from the sequence
  2152. and/or/xor/add/sub/... $x, %y
  2153. test/or %y, %y (x)
  2154. j(n)z _Label
  2155. as the first instruction already adjusts the ZF}
  2156. begin
  2157. if OpsEqual(taicpu(p).oper[0]^,taicpu(p).oper[1]^) then
  2158. if GetLastInstruction(p, hp1) and
  2159. (tai(hp1).typ = ait_instruction) and
  2160. GetNextInstruction(p,hp2) and
  2161. (hp2.typ = ait_instruction) and
  2162. ((taicpu(hp2).opcode = A_SETcc) or
  2163. (taicpu(hp2).opcode = A_Jcc) or
  2164. (taicpu(hp2).opcode = A_CMOVcc)) then
  2165. case taicpu(hp1).opcode Of
  2166. A_ADD, A_SUB, A_OR, A_XOR, A_AND{, A_SHL, A_SHR}:
  2167. begin
  2168. if OpsEqual(taicpu(hp1).oper[1]^,taicpu(p).oper[0]^) and
  2169. { does not work in case of overflow for G(E)/L(E)/C_O/C_NO }
  2170. { and in case of carry for A(E)/B(E)/C/NC }
  2171. ((taicpu(hp2).condition in [C_Z,C_NZ,C_E,C_NE]) or
  2172. ((taicpu(hp1).opcode <> A_ADD) and
  2173. (taicpu(hp1).opcode <> A_SUB))) then
  2174. begin
  2175. hp1 := tai(p.next);
  2176. asml.remove(p);
  2177. p.free;
  2178. p := tai(hp1);
  2179. continue
  2180. end;
  2181. end;
  2182. A_DEC, A_INC, A_NEG:
  2183. begin
  2184. if OpsEqual(taicpu(hp1).oper[0]^,taicpu(p).oper[0]^) and
  2185. { does not work in case of overflow for G(E)/L(E)/C_O/C_NO }
  2186. { and in case of carry for A(E)/B(E)/C/NC }
  2187. (taicpu(hp2).condition in [C_Z,C_NZ,C_E,C_NE]) then
  2188. begin
  2189. case taicpu(hp1).opcode Of
  2190. A_DEC, A_INC:
  2191. {replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag}
  2192. begin
  2193. case taicpu(hp1).opcode Of
  2194. A_DEC: taicpu(hp1).opcode := A_SUB;
  2195. A_INC: taicpu(hp1).opcode := A_ADD;
  2196. end;
  2197. taicpu(hp1).loadoper(1,taicpu(hp1).oper[0]^);
  2198. taicpu(hp1).loadConst(0,1);
  2199. taicpu(hp1).ops:=2;
  2200. end
  2201. end;
  2202. hp1 := tai(p.next);
  2203. asml.remove(p);
  2204. p.free;
  2205. p := tai(hp1);
  2206. continue
  2207. end;
  2208. end
  2209. end
  2210. end;
  2211. end;
  2212. end;
  2213. end;
  2214. p := tai(p.next)
  2215. end;
  2216. end;
  2217. end.