cgcpu.pas 68 KB

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  1. {
  2. Copyright (c) 2008 by Florian Klaempfl
  3. Member of the Free Pascal development team
  4. This unit implements the code generator for the AVR
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. unit cgcpu;
  19. {$i fpcdefs.inc}
  20. interface
  21. uses
  22. globtype,symtype,symdef,
  23. cgbase,cgutils,cgobj,
  24. aasmbase,aasmcpu,aasmtai,aasmdata,
  25. parabase,
  26. cpubase,cpuinfo,node,cg64f32,rgcpu;
  27. type
  28. { tcgavr }
  29. tcgavr = class(tcg)
  30. { true, if the next arithmetic operation should modify the flags }
  31. cgsetflags : boolean;
  32. procedure init_register_allocators;override;
  33. procedure done_register_allocators;override;
  34. function getintregister(list:TAsmList;size:Tcgsize):Tregister;override;
  35. function getaddressregister(list:TAsmList):TRegister;override;
  36. procedure a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);override;
  37. procedure a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);override;
  38. procedure a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);override;
  39. procedure a_load_reg_cgpara(list : TAsmList; size : tcgsize;r : tregister; const cgpara : tcgpara);override;
  40. procedure a_call_name(list : TAsmList;const s : string; weak: boolean);override;
  41. procedure a_call_reg(list : TAsmList;reg: tregister);override;
  42. procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister); override;
  43. procedure a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src, dst : TRegister); override;
  44. { move instructions }
  45. procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);override;
  46. procedure a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
  47. procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
  48. procedure a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
  49. { fpu move instructions }
  50. procedure a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
  51. procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
  52. procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
  53. { comparison operations }
  54. procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
  55. l : tasmlabel);override;
  56. procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
  57. procedure a_jmp_name(list : TAsmList;const s : string); override;
  58. procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
  59. procedure a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel); override;
  60. procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  61. procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
  62. procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
  63. procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
  64. procedure g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);override;
  65. procedure g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  66. procedure g_overflowcheck(list: TAsmList; const l: tlocation; def: tdef); override;
  67. procedure g_save_registers(list : TAsmList);override;
  68. procedure g_restore_registers(list : TAsmList);override;
  69. procedure a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  70. procedure fixref(list : TAsmList;var ref : treference);
  71. function normalize_ref(list : TAsmList;ref : treference;
  72. tmpreg : tregister) : treference;
  73. procedure emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  74. procedure a_adjust_sp(list: TAsmList; value: longint);
  75. function GetLoad(const ref : treference) : tasmop;
  76. function GetStore(const ref: treference): tasmop;
  77. protected
  78. procedure a_op_reg_reg_internal(list: TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
  79. procedure a_op_const_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg, reghi: TRegister);
  80. end;
  81. tcg64favr = class(tcg64f32)
  82. procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  83. procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
  84. end;
  85. procedure create_codegen;
  86. const
  87. TOpCG2AsmOp: Array[topcg] of TAsmOp = (A_NONE,A_MOV,A_ADD,A_AND,A_NONE,
  88. A_NONE,A_MULS,A_MUL,A_NEG,A_COM,A_OR,
  89. A_ASR,A_LSL,A_LSR,A_SUB,A_EOR,A_ROL,A_ROR);
  90. implementation
  91. uses
  92. globals,verbose,systems,cutils,
  93. fmodule,
  94. symconst,symsym,symtable,
  95. tgobj,rgobj,
  96. procinfo,cpupi,
  97. paramgr;
  98. procedure tcgavr.init_register_allocators;
  99. begin
  100. inherited init_register_allocators;
  101. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  102. [RS_R18,RS_R19,RS_R20,RS_R21,RS_R22,RS_R23,RS_R24,RS_R25,
  103. RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,RS_R9,
  104. RS_R10,RS_R11,RS_R12,RS_R13,RS_R14,RS_R15,RS_R16,RS_R17],first_int_imreg,[]);
  105. end;
  106. procedure tcgavr.done_register_allocators;
  107. begin
  108. rg[R_INTREGISTER].free;
  109. // rg[R_ADDRESSREGISTER].free;
  110. inherited done_register_allocators;
  111. end;
  112. function tcgavr.getintregister(list: TAsmList; size: Tcgsize): Tregister;
  113. var
  114. tmp1,tmp2,tmp3 : TRegister;
  115. begin
  116. case size of
  117. OS_8,OS_S8:
  118. Result:=inherited getintregister(list, size);
  119. OS_16,OS_S16:
  120. begin
  121. Result:=inherited getintregister(list, OS_8);
  122. { ensure that the high register can be retrieved by
  123. GetNextReg
  124. }
  125. if inherited getintregister(list, OS_8)<>GetNextReg(Result) then
  126. internalerror(2011021331);
  127. end;
  128. OS_32,OS_S32:
  129. begin
  130. Result:=inherited getintregister(list, OS_8);
  131. tmp1:=inherited getintregister(list, OS_8);
  132. { ensure that the high register can be retrieved by
  133. GetNextReg
  134. }
  135. if tmp1<>GetNextReg(Result) then
  136. internalerror(2011021332);
  137. tmp2:=inherited getintregister(list, OS_8);
  138. { ensure that the upper register can be retrieved by
  139. GetNextReg
  140. }
  141. if tmp2<>GetNextReg(tmp1) then
  142. internalerror(2011021333);
  143. tmp3:=inherited getintregister(list, OS_8);
  144. { ensure that the upper register can be retrieved by
  145. GetNextReg
  146. }
  147. if tmp3<>GetNextReg(tmp2) then
  148. internalerror(2011021334);
  149. end;
  150. else
  151. internalerror(2011021330);
  152. end;
  153. end;
  154. function tcgavr.getaddressregister(list: TAsmList): TRegister;
  155. begin
  156. Result:=getintregister(list,OS_ADDR);
  157. end;
  158. procedure tcgavr.a_load_reg_cgpara(list : TAsmList;size : tcgsize;r : tregister;const cgpara : tcgpara);
  159. procedure load_para_loc(r : TRegister;paraloc : PCGParaLocation);
  160. var
  161. ref : treference;
  162. begin
  163. paramanager.allocparaloc(list,paraloc);
  164. case paraloc^.loc of
  165. LOC_REGISTER,LOC_CREGISTER:
  166. a_load_reg_reg(list,paraloc^.size,paraloc^.size,r,paraloc^.register);
  167. LOC_REFERENCE,LOC_CREFERENCE:
  168. begin
  169. reference_reset_base(ref,paraloc^.reference.index,paraloc^.reference.offset,2);
  170. a_load_reg_ref(list,paraloc^.size,paraloc^.size,r,ref);
  171. end;
  172. else
  173. internalerror(2002071004);
  174. end;
  175. end;
  176. var
  177. i, i2 : longint;
  178. hp : PCGParaLocation;
  179. begin
  180. { if use_push(cgpara) then
  181. begin
  182. if tcgsize2size[cgpara.Size] > 2 then
  183. begin
  184. if tcgsize2size[cgpara.Size] <> 4 then
  185. internalerror(2013031101);
  186. if cgpara.location^.Next = nil then
  187. begin
  188. if tcgsize2size[cgpara.location^.size] <> 4 then
  189. internalerror(2013031101);
  190. end
  191. else
  192. begin
  193. if tcgsize2size[cgpara.location^.size] <> 2 then
  194. internalerror(2013031101);
  195. if tcgsize2size[cgpara.location^.Next^.size] <> 2 then
  196. internalerror(2013031101);
  197. if cgpara.location^.Next^.Next <> nil then
  198. internalerror(2013031101);
  199. end;
  200. if tcgsize2size[cgpara.size]>cgpara.alignment then
  201. pushsize:=cgpara.size
  202. else
  203. pushsize:=int_cgsize(cgpara.alignment);
  204. pushsize2 := int_cgsize(tcgsize2size[pushsize] - 2);
  205. list.concat(taicpu.op_reg(A_PUSH,TCgsize2opsize[pushsize2],makeregsize(list,GetNextReg(r),pushsize2)));
  206. list.concat(taicpu.op_reg(A_PUSH,S_W,makeregsize(list,r,OS_16)));
  207. end
  208. else
  209. begin
  210. cgpara.check_simple_location;
  211. if tcgsize2size[cgpara.location^.size]>cgpara.alignment then
  212. pushsize:=cgpara.location^.size
  213. else
  214. pushsize:=int_cgsize(cgpara.alignment);
  215. list.concat(taicpu.op_reg(A_PUSH,TCgsize2opsize[pushsize],makeregsize(list,r,pushsize)));
  216. end;
  217. end
  218. else }
  219. begin
  220. if not(tcgsize2size[cgpara.Size] in [1..4]) then
  221. internalerror(2014011101);
  222. hp:=cgpara.location;
  223. i:=0;
  224. while i<tcgsize2size[cgpara.Size] do
  225. begin
  226. if not(assigned(hp)) then
  227. internalerror(2014011102);
  228. inc(i, tcgsize2size[hp^.Size]);
  229. if hp^.Loc=LOC_REGISTER then
  230. begin
  231. load_para_loc(r,hp);
  232. hp:=hp^.Next;
  233. r:=GetNextReg(r);
  234. end
  235. else
  236. begin
  237. load_para_loc(r,hp);
  238. for i2:=1 to tcgsize2size[hp^.Size] do
  239. r:=GetNextReg(r);
  240. hp:=hp^.Next;
  241. end;
  242. end;
  243. if assigned(hp) then
  244. internalerror(2014011103);
  245. end;
  246. end;
  247. procedure tcgavr.a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);
  248. var
  249. i : longint;
  250. hp : PCGParaLocation;
  251. begin
  252. if not(tcgsize2size[paraloc.Size] in [1..4]) then
  253. internalerror(2014011101);
  254. hp:=paraloc.location;
  255. for i:=1 to tcgsize2size[paraloc.Size] do
  256. begin
  257. if not(assigned(hp)) then
  258. internalerror(2014011105);
  259. case hp^.loc of
  260. LOC_REGISTER,LOC_CREGISTER:
  261. begin
  262. if (tcgsize2size[hp^.size]<>1) or
  263. (hp^.shiftval<>0) then
  264. internalerror(2015041101);
  265. a_load_const_reg(list,hp^.size,(a shr (8*(i-1))) and $ff,hp^.register);
  266. hp:=hp^.Next;
  267. end;
  268. LOC_REFERENCE,LOC_CREFERENCE:
  269. list.concat(taicpu.op_const(A_PUSH,(a shr (8*(i-1))) and $ff));
  270. else
  271. internalerror(2002071004);
  272. end;
  273. end;
  274. end;
  275. procedure tcgavr.a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);
  276. var
  277. tmpref, ref: treference;
  278. location: pcgparalocation;
  279. sizeleft: tcgint;
  280. begin
  281. location := paraloc.location;
  282. tmpref := r;
  283. sizeleft := paraloc.intsize;
  284. while assigned(location) do
  285. begin
  286. paramanager.allocparaloc(list,location);
  287. case location^.loc of
  288. LOC_REGISTER,LOC_CREGISTER:
  289. a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
  290. LOC_REFERENCE:
  291. begin
  292. reference_reset_base(ref,location^.reference.index,location^.reference.offset,paraloc.alignment);
  293. { doubles in softemu mode have a strange order of registers and references }
  294. if location^.size=OS_32 then
  295. g_concatcopy(list,tmpref,ref,4)
  296. else
  297. begin
  298. g_concatcopy(list,tmpref,ref,sizeleft);
  299. if assigned(location^.next) then
  300. internalerror(2005010710);
  301. end;
  302. end;
  303. LOC_VOID:
  304. begin
  305. // nothing to do
  306. end;
  307. else
  308. internalerror(2002081103);
  309. end;
  310. inc(tmpref.offset,tcgsize2size[location^.size]);
  311. dec(sizeleft,tcgsize2size[location^.size]);
  312. location := location^.next;
  313. end;
  314. end;
  315. procedure tcgavr.a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);
  316. var
  317. tmpreg: tregister;
  318. begin
  319. tmpreg:=getaddressregister(list);
  320. a_loadaddr_ref_reg(list,r,tmpreg);
  321. a_load_reg_cgpara(list,OS_ADDR,tmpreg,paraloc);
  322. end;
  323. procedure tcgavr.a_call_name(list : TAsmList;const s : string; weak: boolean);
  324. begin
  325. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  326. list.concat(taicpu.op_sym(A_CALL,current_asmdata.RefAsmSymbol(s)))
  327. else
  328. list.concat(taicpu.op_sym(A_RCALL,current_asmdata.RefAsmSymbol(s)));
  329. include(current_procinfo.flags,pi_do_call);
  330. end;
  331. procedure tcgavr.a_call_reg(list : TAsmList;reg: tregister);
  332. begin
  333. a_reg_alloc(list,NR_ZLO);
  334. a_reg_alloc(list,NR_ZHI);
  335. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZLO,reg));
  336. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZHI,GetHigh(reg)));
  337. list.concat(taicpu.op_none(A_ICALL));
  338. a_reg_dealloc(list,NR_ZLO);
  339. a_reg_dealloc(list,NR_ZHI);
  340. include(current_procinfo.flags,pi_do_call);
  341. end;
  342. procedure tcgavr.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister);
  343. begin
  344. if not(size in [OS_S8,OS_8,OS_S16,OS_16,OS_S32,OS_32]) then
  345. internalerror(2012102403);
  346. a_op_const_reg_internal(list,Op,size,a,reg,NR_NO);
  347. end;
  348. procedure tcgavr.a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src, dst : TRegister);
  349. begin
  350. if not(size in [OS_S8,OS_8,OS_S16,OS_16,OS_S32,OS_32]) then
  351. internalerror(2012102401);
  352. a_op_reg_reg_internal(list,Op,size,src,NR_NO,dst,NR_NO);
  353. end;
  354. procedure tcgavr.a_op_reg_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
  355. var
  356. countreg,
  357. tmpreg: tregister;
  358. i : integer;
  359. instr : taicpu;
  360. paraloc1,paraloc2,paraloc3 : TCGPara;
  361. l1,l2 : tasmlabel;
  362. pd : tprocdef;
  363. procedure NextSrcDst;
  364. begin
  365. if i=5 then
  366. begin
  367. dst:=dsthi;
  368. src:=srchi;
  369. end
  370. else
  371. begin
  372. dst:=GetNextReg(dst);
  373. src:=GetNextReg(src);
  374. end;
  375. end;
  376. { iterates TmpReg through all registers of dst }
  377. procedure NextTmp;
  378. begin
  379. if i=5 then
  380. tmpreg:=dsthi
  381. else
  382. tmpreg:=GetNextReg(tmpreg);
  383. end;
  384. begin
  385. case op of
  386. OP_ADD:
  387. begin
  388. list.concat(taicpu.op_reg_reg(A_ADD,dst,src));
  389. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  390. begin
  391. for i:=2 to tcgsize2size[size] do
  392. begin
  393. NextSrcDst;
  394. list.concat(taicpu.op_reg_reg(A_ADC,dst,src));
  395. end;
  396. end;
  397. end;
  398. OP_SUB:
  399. begin
  400. list.concat(taicpu.op_reg_reg(A_SUB,dst,src));
  401. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  402. begin
  403. for i:=2 to tcgsize2size[size] do
  404. begin
  405. NextSrcDst;
  406. list.concat(taicpu.op_reg_reg(A_SBC,dst,src));
  407. end;
  408. end;
  409. end;
  410. OP_NEG:
  411. begin
  412. if src<>dst then
  413. begin
  414. if size in [OS_S64,OS_64] then
  415. begin
  416. a_load_reg_reg(list,OS_32,OS_32,src,dst);
  417. a_load_reg_reg(list,OS_32,OS_32,srchi,dsthi);
  418. end
  419. else
  420. a_load_reg_reg(list,size,size,src,dst);
  421. end;
  422. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  423. begin
  424. tmpreg:=GetNextReg(dst);
  425. for i:=2 to tcgsize2size[size] do
  426. begin
  427. list.concat(taicpu.op_reg(A_COM,tmpreg));
  428. NextTmp;
  429. end;
  430. list.concat(taicpu.op_reg(A_NEG,dst));
  431. tmpreg:=GetNextReg(dst);
  432. for i:=2 to tcgsize2size[size] do
  433. begin
  434. list.concat(taicpu.op_reg_const(A_SBCI,tmpreg,-1));
  435. NextTmp;
  436. end;
  437. end;
  438. end;
  439. OP_NOT:
  440. begin
  441. for i:=1 to tcgsize2size[size] do
  442. begin
  443. if src<>dst then
  444. a_load_reg_reg(list,OS_8,OS_8,src,dst);
  445. list.concat(taicpu.op_reg(A_COM,dst));
  446. NextSrcDst;
  447. end;
  448. end;
  449. OP_MUL,OP_IMUL:
  450. begin
  451. if size in [OS_8,OS_S8] then
  452. begin
  453. cg.a_reg_alloc(list,NR_R0);
  454. cg.a_reg_alloc(list,NR_R1);
  455. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src));
  456. cg.a_reg_dealloc(list,NR_R1);
  457. list.concat(taicpu.op_reg_reg(A_MOV,dst,NR_R0));
  458. cg.a_reg_dealloc(list,NR_R0);
  459. end
  460. else if size=OS_16 then
  461. begin
  462. pd:=search_system_proc('fpc_mul_word');
  463. paraloc1.init;
  464. paraloc2.init;
  465. paraloc3.init;
  466. paramanager.getintparaloc(list,pd,1,paraloc1);
  467. paramanager.getintparaloc(list,pd,2,paraloc2);
  468. paramanager.getintparaloc(list,pd,3,paraloc3);
  469. a_load_const_cgpara(list,OS_8,0,paraloc3);
  470. a_load_reg_cgpara(list,OS_16,src,paraloc2);
  471. a_load_reg_cgpara(list,OS_16,dst,paraloc1);
  472. paramanager.freecgpara(list,paraloc3);
  473. paramanager.freecgpara(list,paraloc2);
  474. paramanager.freecgpara(list,paraloc1);
  475. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  476. a_call_name(list,'FPC_MUL_WORD',false);
  477. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  478. cg.a_reg_alloc(list,NR_R24);
  479. cg.a_reg_alloc(list,NR_R25);
  480. cg.a_load_reg_reg(list,OS_8,OS_8,NR_R24,dst);
  481. cg.a_reg_dealloc(list,NR_R24);
  482. cg.a_load_reg_reg(list,OS_8,OS_8,NR_R25,GetNextReg(dst));
  483. cg.a_reg_dealloc(list,NR_R25);
  484. paraloc3.done;
  485. paraloc2.done;
  486. paraloc1.done;
  487. end
  488. else
  489. internalerror(2011022002);
  490. end;
  491. OP_DIV,OP_IDIV:
  492. { special stuff, needs separate handling inside code }
  493. { generator }
  494. internalerror(2011022001);
  495. OP_SHR,OP_SHL,OP_SAR,OP_ROL,OP_ROR:
  496. begin
  497. current_asmdata.getjumplabel(l1);
  498. current_asmdata.getjumplabel(l2);
  499. countreg:=getintregister(list,OS_8);
  500. a_load_reg_reg(list,size,OS_8,src,countreg);
  501. list.concat(taicpu.op_reg(A_TST,countreg));
  502. a_jmp_flags(list,F_EQ,l2);
  503. cg.a_label(list,l1);
  504. case op of
  505. OP_SHR:
  506. list.concat(taicpu.op_reg(A_LSR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  507. OP_SHL:
  508. list.concat(taicpu.op_reg(A_LSL,dst));
  509. OP_SAR:
  510. list.concat(taicpu.op_reg(A_ASR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  511. OP_ROR:
  512. begin
  513. { load carry? }
  514. if not(size in [OS_8,OS_S8]) then
  515. begin
  516. list.concat(taicpu.op_none(A_CLC));
  517. list.concat(taicpu.op_reg_const(A_SBRC,src,0));
  518. list.concat(taicpu.op_none(A_SEC));
  519. end;
  520. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  521. end;
  522. OP_ROL:
  523. begin
  524. { load carry? }
  525. if not(size in [OS_8,OS_S8]) then
  526. begin
  527. list.concat(taicpu.op_none(A_CLC));
  528. list.concat(taicpu.op_reg_const(A_SBRC,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1),7));
  529. list.concat(taicpu.op_none(A_SEC));
  530. end;
  531. list.concat(taicpu.op_reg(A_ROL,dst))
  532. end;
  533. else
  534. internalerror(2011030901);
  535. end;
  536. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  537. begin
  538. for i:=2 to tcgsize2size[size] do
  539. begin
  540. case op of
  541. OP_ROR,
  542. OP_SHR:
  543. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  544. OP_ROL,
  545. OP_SHL:
  546. list.concat(taicpu.op_reg(A_ROL,GetOffsetReg64(dst,dsthi,i-1)));
  547. OP_SAR:
  548. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  549. else
  550. internalerror(2011030902);
  551. end;
  552. end;
  553. end;
  554. list.concat(taicpu.op_reg(A_DEC,countreg));
  555. a_jmp_flags(list,F_NE,l1);
  556. // keep registers alive
  557. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  558. cg.a_label(list,l2);
  559. end;
  560. OP_AND,OP_OR,OP_XOR:
  561. begin
  562. for i:=1 to tcgsize2size[size] do
  563. begin
  564. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src));
  565. NextSrcDst;
  566. end;
  567. end;
  568. else
  569. internalerror(2011022004);
  570. end;
  571. end;
  572. procedure tcgavr.a_op_const_reg_internal(list: TAsmList; Op: TOpCG;
  573. size: TCGSize; a: tcgint; reg, reghi: TRegister);
  574. var
  575. mask : qword;
  576. shift : byte;
  577. i : byte;
  578. tmpreg : tregister;
  579. tmpreg64 : tregister64;
  580. procedure NextReg;
  581. begin
  582. if i=5 then
  583. reg:=reghi
  584. else
  585. reg:=GetNextReg(reg);
  586. end;
  587. var
  588. curvalue : byte;
  589. begin
  590. mask:=$ff;
  591. shift:=0;
  592. case op of
  593. OP_OR:
  594. begin
  595. for i:=1 to tcgsize2size[size] do
  596. begin
  597. list.concat(taicpu.op_reg_const(A_ORI,reg,(qword(a) and mask) shr shift));
  598. NextReg;
  599. mask:=mask shl 8;
  600. inc(shift,8);
  601. end;
  602. end;
  603. OP_AND:
  604. begin
  605. for i:=1 to tcgsize2size[size] do
  606. begin
  607. list.concat(taicpu.op_reg_const(A_ANDI,reg,(qword(a) and mask) shr shift));
  608. NextReg;
  609. mask:=mask shl 8;
  610. inc(shift,8);
  611. end;
  612. end;
  613. OP_SUB:
  614. begin
  615. list.concat(taicpu.op_reg_const(A_SUBI,reg,a and mask));
  616. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  617. begin
  618. for i:=2 to tcgsize2size[size] do
  619. begin
  620. NextReg;
  621. mask:=mask shl 8;
  622. inc(shift,8);
  623. curvalue:=(qword(a) and mask) shr shift;
  624. { decrease pressure on upper half of registers by using SBC ...,R1 instead
  625. of SBCI ...,0 }
  626. if curvalue=0 then
  627. list.concat(taicpu.op_reg_reg(A_SBC,reg,NR_R1))
  628. else
  629. list.concat(taicpu.op_reg_const(A_SBCI,reg,curvalue));
  630. end;
  631. end;
  632. end;
  633. OP_ADD:
  634. begin
  635. curvalue:=a and mask;
  636. if curvalue=0 then
  637. list.concat(taicpu.op_reg_reg(A_ADD,reg,NR_R1))
  638. else
  639. begin
  640. tmpreg:=getintregister(list,OS_8);
  641. a_load_const_reg(list,OS_8,curvalue,tmpreg);
  642. list.concat(taicpu.op_reg_reg(A_ADD,reg,tmpreg));
  643. end;
  644. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  645. begin
  646. for i:=2 to tcgsize2size[size] do
  647. begin
  648. NextReg;
  649. mask:=mask shl 8;
  650. inc(shift,8);
  651. curvalue:=(qword(a) and mask) shr shift;
  652. { decrease pressure on upper half of registers by using ADC ...,R1 instead
  653. of ADD ...,0 }
  654. if curvalue=0 then
  655. list.concat(taicpu.op_reg_reg(A_ADC,reg,NR_R1))
  656. else
  657. begin
  658. tmpreg:=getintregister(list,OS_8);
  659. a_load_const_reg(list,OS_8,curvalue,tmpreg);
  660. list.concat(taicpu.op_reg_reg(A_ADC,reg,tmpreg));
  661. end;
  662. end;
  663. end;
  664. end;
  665. else
  666. begin
  667. if size in [OS_64,OS_S64] then
  668. begin
  669. tmpreg64.reglo:=getintregister(list,OS_32);
  670. tmpreg64.reghi:=getintregister(list,OS_32);
  671. cg64.a_load64_const_reg(list,a,tmpreg64);
  672. cg64.a_op64_reg_reg(list,op,size,tmpreg64,joinreg64(reg,reghi));
  673. end
  674. else
  675. begin
  676. { if (op=OP_SAR) and (a=31) and (size in [OS_32,OS_S32]) then
  677. begin
  678. { code not working yet }
  679. tmpreg:=reg;
  680. for i:=1 to 4 do
  681. begin
  682. list.concat(taicpu.op_reg_reg(A_MOV,tmpreg,NR_R1));
  683. tmpreg:=GetNextReg(tmpreg);
  684. end;
  685. end
  686. else
  687. }
  688. begin
  689. tmpreg:=getintregister(list,size);
  690. a_load_const_reg(list,size,a,tmpreg);
  691. a_op_reg_reg(list,op,size,tmpreg,reg);
  692. end;
  693. end;
  694. end;
  695. end;
  696. end;
  697. procedure tcgavr.a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);
  698. var
  699. mask : qword;
  700. shift : byte;
  701. i : byte;
  702. begin
  703. mask:=$ff;
  704. shift:=0;
  705. for i:=1 to tcgsize2size[size] do
  706. begin
  707. if ((qword(a) and mask) shr shift)=0 then
  708. emit_mov(list,reg,NR_R1)
  709. else
  710. list.concat(taicpu.op_reg_const(A_LDI,reg,(qword(a) and mask) shr shift));
  711. mask:=mask shl 8;
  712. inc(shift,8);
  713. reg:=GetNextReg(reg);
  714. end;
  715. end;
  716. function tcgavr.normalize_ref(list:TAsmList;ref: treference;tmpreg : tregister) : treference;
  717. procedure maybegetcpuregister(list:tasmlist;reg : tregister);
  718. begin
  719. { allocate the register only, if a cpu register is passed }
  720. if getsupreg(reg)<first_int_imreg then
  721. getcpuregister(list,reg);
  722. end;
  723. var
  724. tmpref : treference;
  725. l : tasmlabel;
  726. begin
  727. Result:=ref;
  728. if ref.addressmode<>AM_UNCHANGED then
  729. internalerror(2011021701);
  730. { Be sure to have a base register }
  731. if (ref.base=NR_NO) then
  732. begin
  733. { only symbol+offset? }
  734. if ref.index=NR_NO then
  735. exit;
  736. ref.base:=ref.index;
  737. ref.index:=NR_NO;
  738. end;
  739. if assigned(ref.symbol) or (ref.offset<>0) then
  740. begin
  741. reference_reset(tmpref,0);
  742. tmpref.symbol:=ref.symbol;
  743. tmpref.offset:=ref.offset;
  744. tmpref.refaddr:=addr_lo8;
  745. maybegetcpuregister(list,tmpreg);
  746. list.concat(taicpu.op_reg_ref(A_LDI,tmpreg,tmpref));
  747. tmpref.refaddr:=addr_hi8;
  748. maybegetcpuregister(list,GetNextReg(tmpreg));
  749. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(tmpreg),tmpref));
  750. if (ref.base<>NR_NO) then
  751. begin
  752. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
  753. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
  754. end;
  755. if (ref.index<>NR_NO) then
  756. begin
  757. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  758. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  759. end;
  760. ref.symbol:=nil;
  761. ref.offset:=0;
  762. ref.base:=tmpreg;
  763. ref.index:=NR_NO;
  764. end
  765. else if (ref.base<>NR_NO) and (ref.index<>NR_NO) then
  766. begin
  767. maybegetcpuregister(list,tmpreg);
  768. emit_mov(list,tmpreg,ref.base);
  769. maybegetcpuregister(list,GetNextReg(tmpreg));
  770. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  771. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  772. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  773. ref.base:=tmpreg;
  774. ref.index:=NR_NO;
  775. end
  776. else if (ref.base<>NR_NO) then
  777. begin
  778. maybegetcpuregister(list,tmpreg);
  779. emit_mov(list,tmpreg,ref.base);
  780. maybegetcpuregister(list,GetNextReg(tmpreg));
  781. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  782. ref.base:=tmpreg;
  783. ref.index:=NR_NO;
  784. end
  785. else if (ref.index<>NR_NO) then
  786. begin
  787. maybegetcpuregister(list,tmpreg);
  788. emit_mov(list,tmpreg,ref.index);
  789. maybegetcpuregister(list,GetNextReg(tmpreg));
  790. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
  791. ref.base:=tmpreg;
  792. ref.index:=NR_NO;
  793. end;
  794. Result:=ref;
  795. end;
  796. procedure tcgavr.a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);
  797. var
  798. href : treference;
  799. conv_done: boolean;
  800. tmpreg : tregister;
  801. i : integer;
  802. QuickRef : Boolean;
  803. begin
  804. QuickRef:=false;
  805. if not((Ref.addressmode=AM_UNCHANGED) and
  806. (Ref.symbol=nil) and
  807. ((Ref.base=NR_R28) or
  808. (Ref.base=NR_R29)) and
  809. (Ref.Index=NR_No) and
  810. (Ref.Offset in [0..64-tcgsize2size[tosize]])) and
  811. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  812. href:=normalize_ref(list,Ref,NR_R30)
  813. else
  814. begin
  815. QuickRef:=true;
  816. href:=Ref;
  817. end;
  818. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  819. internalerror(2011021307);
  820. conv_done:=false;
  821. if tosize<>fromsize then
  822. begin
  823. conv_done:=true;
  824. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  825. fromsize:=tosize;
  826. case fromsize of
  827. OS_8:
  828. begin
  829. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  830. href.addressmode:=AM_POSTINCREMENT;
  831. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  832. for i:=2 to tcgsize2size[tosize] do
  833. begin
  834. if QuickRef then
  835. inc(href.offset);
  836. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  837. href.addressmode:=AM_POSTINCREMENT
  838. else
  839. href.addressmode:=AM_UNCHANGED;
  840. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  841. end;
  842. end;
  843. OS_S8:
  844. begin
  845. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  846. href.addressmode:=AM_POSTINCREMENT;
  847. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  848. if tcgsize2size[tosize]>1 then
  849. begin
  850. tmpreg:=getintregister(list,OS_8);
  851. emit_mov(list,tmpreg,NR_R1);
  852. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  853. list.concat(taicpu.op_reg(A_COM,tmpreg));
  854. for i:=2 to tcgsize2size[tosize] do
  855. begin
  856. if QuickRef then
  857. inc(href.offset);
  858. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  859. href.addressmode:=AM_POSTINCREMENT
  860. else
  861. href.addressmode:=AM_UNCHANGED;
  862. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  863. end;
  864. end;
  865. end;
  866. OS_16:
  867. begin
  868. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  869. href.addressmode:=AM_POSTINCREMENT;
  870. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  871. if QuickRef then
  872. inc(href.offset)
  873. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  874. href.addressmode:=AM_POSTINCREMENT
  875. else
  876. href.addressmode:=AM_UNCHANGED;
  877. reg:=GetNextReg(reg);
  878. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  879. for i:=3 to tcgsize2size[tosize] do
  880. begin
  881. if QuickRef then
  882. inc(href.offset);
  883. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  884. href.addressmode:=AM_POSTINCREMENT
  885. else
  886. href.addressmode:=AM_UNCHANGED;
  887. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  888. end;
  889. end;
  890. OS_S16:
  891. begin
  892. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  893. href.addressmode:=AM_POSTINCREMENT;
  894. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  895. if QuickRef then
  896. inc(href.offset)
  897. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  898. href.addressmode:=AM_POSTINCREMENT
  899. else
  900. href.addressmode:=AM_UNCHANGED;
  901. reg:=GetNextReg(reg);
  902. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  903. if tcgsize2size[tosize]>2 then
  904. begin
  905. tmpreg:=getintregister(list,OS_8);
  906. emit_mov(list,tmpreg,NR_R1);
  907. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  908. list.concat(taicpu.op_reg(A_COM,tmpreg));
  909. for i:=3 to tcgsize2size[tosize] do
  910. begin
  911. if QuickRef then
  912. inc(href.offset);
  913. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  914. href.addressmode:=AM_POSTINCREMENT
  915. else
  916. href.addressmode:=AM_UNCHANGED;
  917. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  918. end;
  919. end;
  920. end;
  921. else
  922. conv_done:=false;
  923. end;
  924. end;
  925. if not conv_done then
  926. begin
  927. for i:=1 to tcgsize2size[fromsize] do
  928. begin
  929. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  930. href.addressmode:=AM_POSTINCREMENT
  931. else
  932. href.addressmode:=AM_UNCHANGED;
  933. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  934. if QuickRef then
  935. inc(href.offset);
  936. reg:=GetNextReg(reg);
  937. end;
  938. end;
  939. if not(QuickRef) then
  940. begin
  941. ungetcpuregister(list,href.base);
  942. ungetcpuregister(list,GetNextReg(href.base));
  943. end;
  944. end;
  945. procedure tcgavr.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;
  946. const Ref : treference;reg : tregister);
  947. var
  948. href : treference;
  949. conv_done: boolean;
  950. tmpreg : tregister;
  951. i : integer;
  952. QuickRef : boolean;
  953. begin
  954. QuickRef:=false;
  955. if not((Ref.addressmode=AM_UNCHANGED) and
  956. (Ref.symbol=nil) and
  957. ((Ref.base=NR_R28) or
  958. (Ref.base=NR_R29)) and
  959. (Ref.Index=NR_No) and
  960. (Ref.Offset in [0..64-tcgsize2size[fromsize]])) and
  961. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  962. href:=normalize_ref(list,Ref,NR_R30)
  963. else
  964. begin
  965. QuickRef:=true;
  966. href:=Ref;
  967. end;
  968. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  969. internalerror(2011021307);
  970. conv_done:=false;
  971. if tosize<>fromsize then
  972. begin
  973. conv_done:=true;
  974. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  975. fromsize:=tosize;
  976. case fromsize of
  977. OS_8:
  978. begin
  979. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  980. for i:=2 to tcgsize2size[tosize] do
  981. begin
  982. reg:=GetNextReg(reg);
  983. emit_mov(list,reg,NR_R1);
  984. end;
  985. end;
  986. OS_S8:
  987. begin
  988. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  989. tmpreg:=reg;
  990. if tcgsize2size[tosize]>1 then
  991. begin
  992. reg:=GetNextReg(reg);
  993. emit_mov(list,reg,NR_R1);
  994. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  995. list.concat(taicpu.op_reg(A_COM,reg));
  996. tmpreg:=reg;
  997. for i:=3 to tcgsize2size[tosize] do
  998. begin
  999. reg:=GetNextReg(reg);
  1000. emit_mov(list,reg,tmpreg);
  1001. end;
  1002. end;
  1003. end;
  1004. OS_16:
  1005. begin
  1006. if not(QuickRef) then
  1007. href.addressmode:=AM_POSTINCREMENT;
  1008. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1009. if QuickRef then
  1010. inc(href.offset);
  1011. href.addressmode:=AM_UNCHANGED;
  1012. reg:=GetNextReg(reg);
  1013. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1014. for i:=3 to tcgsize2size[tosize] do
  1015. begin
  1016. reg:=GetNextReg(reg);
  1017. emit_mov(list,reg,NR_R1);
  1018. end;
  1019. end;
  1020. OS_S16:
  1021. begin
  1022. if not(QuickRef) then
  1023. href.addressmode:=AM_POSTINCREMENT;
  1024. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1025. if QuickRef then
  1026. inc(href.offset);
  1027. href.addressmode:=AM_UNCHANGED;
  1028. reg:=GetNextReg(reg);
  1029. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1030. tmpreg:=reg;
  1031. reg:=GetNextReg(reg);
  1032. emit_mov(list,reg,NR_R1);
  1033. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  1034. list.concat(taicpu.op_reg(A_COM,reg));
  1035. tmpreg:=reg;
  1036. for i:=4 to tcgsize2size[tosize] do
  1037. begin
  1038. reg:=GetNextReg(reg);
  1039. emit_mov(list,reg,tmpreg);
  1040. end;
  1041. end;
  1042. else
  1043. conv_done:=false;
  1044. end;
  1045. end;
  1046. if not conv_done then
  1047. begin
  1048. for i:=1 to tcgsize2size[fromsize] do
  1049. begin
  1050. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  1051. href.addressmode:=AM_POSTINCREMENT
  1052. else
  1053. href.addressmode:=AM_UNCHANGED;
  1054. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1055. if QuickRef then
  1056. inc(href.offset);
  1057. reg:=GetNextReg(reg);
  1058. end;
  1059. end;
  1060. if not(QuickRef) then
  1061. begin
  1062. ungetcpuregister(list,href.base);
  1063. ungetcpuregister(list,GetNextReg(href.base));
  1064. end;
  1065. end;
  1066. procedure tcgavr.a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);
  1067. var
  1068. conv_done: boolean;
  1069. tmpreg : tregister;
  1070. i : integer;
  1071. begin
  1072. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  1073. internalerror(2011021310);
  1074. conv_done:=false;
  1075. if tosize<>fromsize then
  1076. begin
  1077. conv_done:=true;
  1078. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  1079. fromsize:=tosize;
  1080. case fromsize of
  1081. OS_8:
  1082. begin
  1083. emit_mov(list,reg2,reg1);
  1084. for i:=2 to tcgsize2size[tosize] do
  1085. begin
  1086. reg2:=GetNextReg(reg2);
  1087. emit_mov(list,reg2,NR_R1);
  1088. end;
  1089. end;
  1090. OS_S8:
  1091. begin
  1092. emit_mov(list,reg2,reg1);
  1093. if tcgsize2size[tosize]>1 then
  1094. begin
  1095. reg2:=GetNextReg(reg2);
  1096. emit_mov(list,reg2,NR_R1);
  1097. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  1098. list.concat(taicpu.op_reg(A_COM,reg2));
  1099. tmpreg:=reg2;
  1100. for i:=3 to tcgsize2size[tosize] do
  1101. begin
  1102. reg2:=GetNextReg(reg2);
  1103. emit_mov(list,reg2,tmpreg);
  1104. end;
  1105. end;
  1106. end;
  1107. OS_16:
  1108. begin
  1109. emit_mov(list,reg2,reg1);
  1110. reg1:=GetNextReg(reg1);
  1111. reg2:=GetNextReg(reg2);
  1112. emit_mov(list,reg2,reg1);
  1113. for i:=3 to tcgsize2size[tosize] do
  1114. begin
  1115. reg2:=GetNextReg(reg2);
  1116. emit_mov(list,reg2,NR_R1);
  1117. end;
  1118. end;
  1119. OS_S16:
  1120. begin
  1121. emit_mov(list,reg2,reg1);
  1122. reg1:=GetNextReg(reg1);
  1123. reg2:=GetNextReg(reg2);
  1124. emit_mov(list,reg2,reg1);
  1125. if tcgsize2size[tosize]>2 then
  1126. begin
  1127. reg2:=GetNextReg(reg2);
  1128. emit_mov(list,reg2,NR_R1);
  1129. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  1130. list.concat(taicpu.op_reg(A_COM,reg2));
  1131. tmpreg:=reg2;
  1132. for i:=4 to tcgsize2size[tosize] do
  1133. begin
  1134. reg2:=GetNextReg(reg2);
  1135. emit_mov(list,reg2,tmpreg);
  1136. end;
  1137. end;
  1138. end;
  1139. else
  1140. conv_done:=false;
  1141. end;
  1142. end;
  1143. if not conv_done and (reg1<>reg2) then
  1144. begin
  1145. for i:=1 to tcgsize2size[fromsize] do
  1146. begin
  1147. emit_mov(list,reg2,reg1);
  1148. reg1:=GetNextReg(reg1);
  1149. reg2:=GetNextReg(reg2);
  1150. end;
  1151. end;
  1152. end;
  1153. procedure tcgavr.a_loadfpu_reg_reg(list: TAsmList; fromsize,tosize: tcgsize; reg1, reg2: tregister);
  1154. begin
  1155. internalerror(2012010702);
  1156. end;
  1157. procedure tcgavr.a_loadfpu_ref_reg(list: TAsmList; fromsize,tosize: tcgsize; const ref: treference; reg: tregister);
  1158. begin
  1159. internalerror(2012010703);
  1160. end;
  1161. procedure tcgavr.a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference);
  1162. begin
  1163. internalerror(2012010704);
  1164. end;
  1165. { comparison operations }
  1166. procedure tcgavr.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;
  1167. cmp_op : topcmp;a : tcgint;reg : tregister;l : tasmlabel);
  1168. var
  1169. swapped : boolean;
  1170. tmpreg : tregister;
  1171. i : byte;
  1172. begin
  1173. if a=0 then
  1174. begin
  1175. swapped:=false;
  1176. { swap parameters? }
  1177. case cmp_op of
  1178. OC_GT:
  1179. begin
  1180. swapped:=true;
  1181. cmp_op:=OC_LT;
  1182. end;
  1183. OC_LTE:
  1184. begin
  1185. swapped:=true;
  1186. cmp_op:=OC_GTE;
  1187. end;
  1188. OC_BE:
  1189. begin
  1190. swapped:=true;
  1191. cmp_op:=OC_AE;
  1192. end;
  1193. OC_A:
  1194. begin
  1195. swapped:=true;
  1196. cmp_op:=OC_B;
  1197. end;
  1198. end;
  1199. if swapped then
  1200. list.concat(taicpu.op_reg_reg(A_CP,reg,NR_R1))
  1201. else
  1202. list.concat(taicpu.op_reg_reg(A_CP,NR_R1,reg));
  1203. for i:=2 to tcgsize2size[size] do
  1204. begin
  1205. reg:=GetNextReg(reg);
  1206. if swapped then
  1207. list.concat(taicpu.op_reg_reg(A_CPC,reg,NR_R1))
  1208. else
  1209. list.concat(taicpu.op_reg_reg(A_CPC,NR_R1,reg));
  1210. end;
  1211. a_jmp_cond(list,cmp_op,l);
  1212. end
  1213. else
  1214. inherited a_cmp_const_reg_label(list,size,cmp_op,a,reg,l);
  1215. end;
  1216. procedure tcgavr.a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;
  1217. cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
  1218. var
  1219. swapped : boolean;
  1220. tmpreg : tregister;
  1221. i : byte;
  1222. begin
  1223. swapped:=false;
  1224. { swap parameters? }
  1225. case cmp_op of
  1226. OC_GT:
  1227. begin
  1228. swapped:=true;
  1229. cmp_op:=OC_LT;
  1230. end;
  1231. OC_LTE:
  1232. begin
  1233. swapped:=true;
  1234. cmp_op:=OC_GTE;
  1235. end;
  1236. OC_BE:
  1237. begin
  1238. swapped:=true;
  1239. cmp_op:=OC_AE;
  1240. end;
  1241. OC_A:
  1242. begin
  1243. swapped:=true;
  1244. cmp_op:=OC_B;
  1245. end;
  1246. end;
  1247. if swapped then
  1248. begin
  1249. tmpreg:=reg1;
  1250. reg1:=reg2;
  1251. reg2:=tmpreg;
  1252. end;
  1253. list.concat(taicpu.op_reg_reg(A_CP,reg2,reg1));
  1254. for i:=2 to tcgsize2size[size] do
  1255. begin
  1256. reg1:=GetNextReg(reg1);
  1257. reg2:=GetNextReg(reg2);
  1258. list.concat(taicpu.op_reg_reg(A_CPC,reg2,reg1));
  1259. end;
  1260. a_jmp_cond(list,cmp_op,l);
  1261. end;
  1262. procedure tcgavr.a_jmp_name(list : TAsmList;const s : string);
  1263. var
  1264. ai : taicpu;
  1265. begin
  1266. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  1267. ai:=taicpu.op_sym(A_JMP,current_asmdata.RefAsmSymbol(s))
  1268. else
  1269. ai:=taicpu.op_sym(A_RJMP,current_asmdata.RefAsmSymbol(s));
  1270. ai.is_jmp:=true;
  1271. list.concat(ai);
  1272. end;
  1273. procedure tcgavr.a_jmp_always(list : TAsmList;l: tasmlabel);
  1274. var
  1275. ai : taicpu;
  1276. begin
  1277. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  1278. ai:=taicpu.op_sym(A_JMP,l)
  1279. else
  1280. ai:=taicpu.op_sym(A_RJMP,l);
  1281. ai.is_jmp:=true;
  1282. list.concat(ai);
  1283. end;
  1284. procedure tcgavr.a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel);
  1285. var
  1286. ai : taicpu;
  1287. begin
  1288. ai:=setcondition(taicpu.op_sym(A_BRxx,l),flags_to_cond(f));
  1289. ai.is_jmp:=true;
  1290. list.concat(ai);
  1291. end;
  1292. procedure tcgavr.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
  1293. var
  1294. l : TAsmLabel;
  1295. tmpflags : TResFlags;
  1296. begin
  1297. current_asmdata.getjumplabel(l);
  1298. {
  1299. if flags_to_cond(f) then
  1300. begin
  1301. tmpflags:=f;
  1302. inverse_flags(tmpflags);
  1303. emit_mov(reg,NR_R1);
  1304. a_jmp_flags(list,tmpflags,l);
  1305. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1306. end
  1307. else
  1308. }
  1309. begin
  1310. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1311. a_jmp_flags(list,f,l);
  1312. emit_mov(list,reg,NR_R1);
  1313. end;
  1314. cg.a_label(list,l);
  1315. end;
  1316. procedure tcgavr.a_adjust_sp(list : TAsmList; value : longint);
  1317. var
  1318. i : integer;
  1319. begin
  1320. case value of
  1321. 0:
  1322. ;
  1323. {-14..-1:
  1324. begin
  1325. if ((-value) mod 2)<>0 then
  1326. list.concat(taicpu.op_reg(A_PUSH,NR_R0));
  1327. for i:=1 to (-value) div 2 do
  1328. list.concat(taicpu.op_const(A_RCALL,0));
  1329. end;
  1330. 1..7:
  1331. begin
  1332. for i:=1 to value do
  1333. list.concat(taicpu.op_reg(A_POP,NR_R0));
  1334. end;}
  1335. else
  1336. begin
  1337. list.concat(taicpu.op_reg_const(A_SUBI,NR_R28,lo(word(-value))));
  1338. list.concat(taicpu.op_reg_const(A_SBCI,NR_R29,hi(word(-value))));
  1339. // get SREG
  1340. list.concat(taicpu.op_reg_const(A_IN,NR_R0,NIO_SREG));
  1341. // block interrupts
  1342. list.concat(taicpu.op_none(A_CLI));
  1343. // write high SP
  1344. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_HI,NR_R29));
  1345. // release interrupts
  1346. list.concat(taicpu.op_const_reg(A_OUT,NIO_SREG,NR_R0));
  1347. // write low SP
  1348. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_LO,NR_R28));
  1349. end;
  1350. end;
  1351. end;
  1352. function tcgavr.GetLoad(const ref: treference) : tasmop;
  1353. begin
  1354. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1355. result:=A_LDS
  1356. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1357. result:=A_LDD
  1358. else
  1359. result:=A_LD;
  1360. end;
  1361. function tcgavr.GetStore(const ref: treference) : tasmop;
  1362. begin
  1363. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1364. result:=A_STS
  1365. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1366. result:=A_STD
  1367. else
  1368. result:=A_ST;
  1369. end;
  1370. procedure tcgavr.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
  1371. var
  1372. regs : tcpuregisterset;
  1373. reg : tsuperregister;
  1374. begin
  1375. if not(nostackframe) then
  1376. begin
  1377. { save int registers }
  1378. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1379. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1380. regs:=regs+[RS_R28,RS_R29];
  1381. for reg:=RS_R31 downto RS_R0 do
  1382. if reg in regs then
  1383. list.concat(taicpu.op_reg(A_PUSH,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1384. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1385. begin
  1386. list.concat(taicpu.op_reg_const(A_IN,NR_R28,NIO_SP_LO));
  1387. list.concat(taicpu.op_reg_const(A_IN,NR_R29,NIO_SP_HI));
  1388. end
  1389. else
  1390. { the framepointer cannot be omitted on avr because sp
  1391. is not a register but part of the i/o map
  1392. }
  1393. internalerror(2011021901);
  1394. a_adjust_sp(list,-localsize);
  1395. end;
  1396. end;
  1397. procedure tcgavr.g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean);
  1398. var
  1399. regs : tcpuregisterset;
  1400. reg : TSuperRegister;
  1401. LocalSize : longint;
  1402. begin
  1403. if not(nostackframe) then
  1404. begin
  1405. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1406. begin
  1407. LocalSize:=current_procinfo.calc_stackframe_size;
  1408. a_adjust_sp(list,LocalSize);
  1409. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1410. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1411. regs:=regs+[RS_R28,RS_R29];
  1412. for reg:=RS_R0 to RS_R31 do
  1413. if reg in regs then
  1414. list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1415. end
  1416. else
  1417. { the framepointer cannot be omitted on avr because sp
  1418. is not a register but part of the i/o map
  1419. }
  1420. internalerror(2011021902);
  1421. end;
  1422. list.concat(taicpu.op_none(A_RET));
  1423. end;
  1424. procedure tcgavr.a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);
  1425. var
  1426. tmpref : treference;
  1427. begin
  1428. if ref.addressmode<>AM_UNCHANGED then
  1429. internalerror(2011021701);
  1430. if assigned(ref.symbol) or (ref.offset<>0) then
  1431. begin
  1432. reference_reset(tmpref,0);
  1433. tmpref.symbol:=ref.symbol;
  1434. tmpref.offset:=ref.offset;
  1435. tmpref.refaddr:=addr_lo8;
  1436. list.concat(taicpu.op_reg_ref(A_LDI,r,tmpref));
  1437. tmpref.refaddr:=addr_hi8;
  1438. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(r),tmpref));
  1439. if (ref.base<>NR_NO) then
  1440. begin
  1441. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.base));
  1442. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.base)));
  1443. end;
  1444. if (ref.index<>NR_NO) then
  1445. begin
  1446. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1447. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1448. end;
  1449. end
  1450. else if (ref.base<>NR_NO)then
  1451. begin
  1452. emit_mov(list,r,ref.base);
  1453. emit_mov(list,GetNextReg(r),GetNextReg(ref.base));
  1454. if (ref.index<>NR_NO) then
  1455. begin
  1456. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1457. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1458. end;
  1459. end
  1460. else if (ref.index<>NR_NO) then
  1461. begin
  1462. emit_mov(list,r,ref.index);
  1463. emit_mov(list,GetNextReg(r),GetNextReg(ref.index));
  1464. end;
  1465. end;
  1466. procedure tcgavr.fixref(list : TAsmList;var ref : treference);
  1467. begin
  1468. internalerror(2011021320);
  1469. end;
  1470. procedure tcgavr.g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  1471. var
  1472. paraloc1,paraloc2,paraloc3 : TCGPara;
  1473. pd : tprocdef;
  1474. begin
  1475. pd:=search_system_proc('MOVE');
  1476. paraloc1.init;
  1477. paraloc2.init;
  1478. paraloc3.init;
  1479. paramanager.getintparaloc(list,pd,1,paraloc1);
  1480. paramanager.getintparaloc(list,pd,2,paraloc2);
  1481. paramanager.getintparaloc(list,pd,3,paraloc3);
  1482. a_load_const_cgpara(list,OS_SINT,len,paraloc3);
  1483. a_loadaddr_ref_cgpara(list,dest,paraloc2);
  1484. a_loadaddr_ref_cgpara(list,source,paraloc1);
  1485. paramanager.freecgpara(list,paraloc3);
  1486. paramanager.freecgpara(list,paraloc2);
  1487. paramanager.freecgpara(list,paraloc1);
  1488. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1489. a_call_name_static(list,'FPC_MOVE');
  1490. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1491. paraloc3.done;
  1492. paraloc2.done;
  1493. paraloc1.done;
  1494. end;
  1495. procedure tcgavr.g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);
  1496. var
  1497. countreg,tmpreg : tregister;
  1498. srcref,dstref : treference;
  1499. copysize,countregsize : tcgsize;
  1500. l : TAsmLabel;
  1501. i : longint;
  1502. SrcQuickRef, DestQuickRef : Boolean;
  1503. begin
  1504. if len>16 then
  1505. begin
  1506. current_asmdata.getjumplabel(l);
  1507. reference_reset(srcref,0);
  1508. reference_reset(dstref,0);
  1509. srcref.base:=NR_R30;
  1510. srcref.addressmode:=AM_POSTINCREMENT;
  1511. dstref.base:=NR_R26;
  1512. dstref.addressmode:=AM_POSTINCREMENT;
  1513. copysize:=OS_8;
  1514. if len<256 then
  1515. countregsize:=OS_8
  1516. else if len<65536 then
  1517. countregsize:=OS_16
  1518. else
  1519. internalerror(2011022007);
  1520. countreg:=getintregister(list,countregsize);
  1521. a_load_const_reg(list,countregsize,len,countreg);
  1522. a_loadaddr_ref_reg(list,source,NR_R30);
  1523. tmpreg:=getaddressregister(list);
  1524. a_loadaddr_ref_reg(list,dest,tmpreg);
  1525. { X is used for spilling code so we can load it
  1526. only by a push/pop sequence, this can be
  1527. optimized later on by the peephole optimizer
  1528. }
  1529. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1530. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1531. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1532. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1533. cg.a_label(list,l);
  1534. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1535. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1536. a_op_const_reg(list,OP_SUB,countregsize,1,countreg);
  1537. a_jmp_flags(list,F_NE,l);
  1538. // keep registers alive
  1539. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  1540. end
  1541. else
  1542. begin
  1543. SrcQuickRef:=false;
  1544. DestQuickRef:=false;
  1545. if not((source.addressmode=AM_UNCHANGED) and
  1546. (source.symbol=nil) and
  1547. ((source.base=NR_R28) or
  1548. (source.base=NR_R29)) and
  1549. (source.Index=NR_NO) and
  1550. (source.Offset in [0..64-len])) and
  1551. not((source.Base=NR_NO) and (source.Index=NR_NO)) then
  1552. srcref:=normalize_ref(list,source,NR_R30)
  1553. else
  1554. begin
  1555. SrcQuickRef:=true;
  1556. srcref:=source;
  1557. end;
  1558. if not((dest.addressmode=AM_UNCHANGED) and
  1559. (dest.symbol=nil) and
  1560. ((dest.base=NR_R28) or
  1561. (dest.base=NR_R29)) and
  1562. (dest.Index=NR_No) and
  1563. (dest.Offset in [0..64-len])) and
  1564. not((dest.Base=NR_NO) and (dest.Index=NR_NO)) then
  1565. begin
  1566. if not(SrcQuickRef) then
  1567. begin
  1568. tmpreg:=getaddressregister(list);
  1569. dstref:=normalize_ref(list,dest,tmpreg);
  1570. { X is used for spilling code so we can load it
  1571. only by a push/pop sequence, this can be
  1572. optimized later on by the peephole optimizer
  1573. }
  1574. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1575. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1576. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1577. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1578. dstref.base:=NR_R26;
  1579. end
  1580. else
  1581. dstref:=normalize_ref(list,dest,NR_R30);
  1582. end
  1583. else
  1584. begin
  1585. DestQuickRef:=true;
  1586. dstref:=dest;
  1587. end;
  1588. for i:=1 to len do
  1589. begin
  1590. if not(SrcQuickRef) and (i<len) then
  1591. srcref.addressmode:=AM_POSTINCREMENT
  1592. else
  1593. srcref.addressmode:=AM_UNCHANGED;
  1594. if not(DestQuickRef) and (i<len) then
  1595. dstref.addressmode:=AM_POSTINCREMENT
  1596. else
  1597. dstref.addressmode:=AM_UNCHANGED;
  1598. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1599. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1600. if SrcQuickRef then
  1601. inc(srcref.offset);
  1602. if DestQuickRef then
  1603. inc(dstref.offset);
  1604. end;
  1605. if not(SrcQuickRef) then
  1606. begin
  1607. ungetcpuregister(list,srcref.base);
  1608. ungetcpuregister(list,GetNextReg(srcref.base));
  1609. end;
  1610. end;
  1611. end;
  1612. procedure tcgavr.g_overflowCheck(list : TAsmList;const l : tlocation;def : tdef);
  1613. var
  1614. hl : tasmlabel;
  1615. ai : taicpu;
  1616. cond : TAsmCond;
  1617. begin
  1618. if not(cs_check_overflow in current_settings.localswitches) then
  1619. exit;
  1620. current_asmdata.getjumplabel(hl);
  1621. if not ((def.typ=pointerdef) or
  1622. ((def.typ=orddef) and
  1623. (torddef(def).ordtype in [u64bit,u16bit,u32bit,u8bit,uchar,
  1624. pasbool8,pasbool16,pasbool32,pasbool64]))) then
  1625. cond:=C_VC
  1626. else
  1627. cond:=C_CC;
  1628. ai:=Taicpu.Op_Sym(A_BRxx,hl);
  1629. ai.SetCondition(cond);
  1630. ai.is_jmp:=true;
  1631. list.concat(ai);
  1632. a_call_name(list,'FPC_OVERFLOW',false);
  1633. a_label(list,hl);
  1634. end;
  1635. procedure tcgavr.g_save_registers(list: TAsmList);
  1636. begin
  1637. { this is done by the entry code }
  1638. end;
  1639. procedure tcgavr.g_restore_registers(list: TAsmList);
  1640. begin
  1641. { this is done by the exit code }
  1642. end;
  1643. procedure tcgavr.a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  1644. var
  1645. ai1,ai2 : taicpu;
  1646. hl : TAsmLabel;
  1647. begin
  1648. ai1:=Taicpu.Op_sym(A_BRxx,l);
  1649. ai1.is_jmp:=true;
  1650. hl:=nil;
  1651. case cond of
  1652. OC_EQ:
  1653. ai1.SetCondition(C_EQ);
  1654. OC_GT:
  1655. begin
  1656. { emulate GT }
  1657. current_asmdata.getjumplabel(hl);
  1658. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1659. ai2.SetCondition(C_EQ);
  1660. ai2.is_jmp:=true;
  1661. list.concat(ai2);
  1662. ai1.SetCondition(C_GE);
  1663. end;
  1664. OC_LT:
  1665. ai1.SetCondition(C_LT);
  1666. OC_GTE:
  1667. ai1.SetCondition(C_GE);
  1668. OC_LTE:
  1669. begin
  1670. { emulate LTE }
  1671. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1672. ai2.SetCondition(C_EQ);
  1673. ai2.is_jmp:=true;
  1674. list.concat(ai2);
  1675. ai1.SetCondition(C_LT);
  1676. end;
  1677. OC_NE:
  1678. ai1.SetCondition(C_NE);
  1679. OC_BE:
  1680. begin
  1681. { emulate BE }
  1682. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1683. ai2.SetCondition(C_EQ);
  1684. ai2.is_jmp:=true;
  1685. list.concat(ai2);
  1686. ai1.SetCondition(C_LO);
  1687. end;
  1688. OC_B:
  1689. ai1.SetCondition(C_LO);
  1690. OC_AE:
  1691. ai1.SetCondition(C_SH);
  1692. OC_A:
  1693. begin
  1694. { emulate A (unsigned GT) }
  1695. current_asmdata.getjumplabel(hl);
  1696. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1697. ai2.SetCondition(C_EQ);
  1698. ai2.is_jmp:=true;
  1699. list.concat(ai2);
  1700. ai1.SetCondition(C_SH);
  1701. end;
  1702. else
  1703. internalerror(2011082501);
  1704. end;
  1705. list.concat(ai1);
  1706. if assigned(hl) then
  1707. a_label(list,hl);
  1708. end;
  1709. procedure tcgavr.emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  1710. var
  1711. instr: taicpu;
  1712. begin
  1713. instr:=taicpu.op_reg_reg(A_MOV,reg2,reg1);
  1714. list.Concat(instr);
  1715. { Notify the register allocator that we have written a move instruction so
  1716. it can try to eliminate it. }
  1717. add_move_instruction(instr);
  1718. end;
  1719. procedure tcg64favr.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
  1720. begin
  1721. if not(size in [OS_S64,OS_64]) then
  1722. internalerror(2012102402);
  1723. tcgavr(cg).a_op_reg_reg_internal(list,Op,size,regsrc.reglo,regsrc.reghi,regdst.reglo,regdst.reghi);
  1724. end;
  1725. procedure tcg64favr.a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);
  1726. begin
  1727. tcgavr(cg).a_op_const_reg_internal(list,Op,size,value,reg.reglo,reg.reghi);
  1728. end;
  1729. procedure create_codegen;
  1730. begin
  1731. cg:=tcgavr.create;
  1732. cg64:=tcg64favr.create;
  1733. end;
  1734. end.