cgcpu.pas 54 KB

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  1. {
  2. Copyright (c) 2008 by Florian Klaempfl
  3. Member of the Free Pascal development team
  4. This unit implements the code generator for the AVR
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. unit cgcpu;
  19. {$i fpcdefs.inc}
  20. interface
  21. uses
  22. globtype,symtype,symdef,
  23. cgbase,cgutils,cgobj,
  24. aasmbase,aasmcpu,aasmtai,aasmdata,
  25. parabase,
  26. cpubase,cpuinfo,node,cg64f32,rgcpu;
  27. type
  28. { tcgavr }
  29. tcgavr = class(tcg)
  30. { true, if the next arithmetic operation should modify the flags }
  31. cgsetflags : boolean;
  32. procedure init_register_allocators;override;
  33. procedure done_register_allocators;override;
  34. function getintregister(list:TAsmList;size:Tcgsize):Tregister;override;
  35. function getaddressregister(list:TAsmList):TRegister;override;
  36. procedure a_load_const_cgpara(list : TAsmList;size : tcgsize;a : aint;const paraloc : TCGPara);override;
  37. procedure a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);override;
  38. procedure a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);override;
  39. procedure a_call_name(list : TAsmList;const s : string; weak: boolean);override;
  40. procedure a_call_reg(list : TAsmList;reg: tregister);override;
  41. procedure a_call_ref(list : TAsmList;ref: treference);override;
  42. procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: aint; reg: TRegister); override;
  43. procedure a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister); override;
  44. { move instructions }
  45. procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : aint;reg : tregister);override;
  46. procedure a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
  47. procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
  48. procedure a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
  49. { comparison operations }
  50. procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : aint;reg : tregister;
  51. l : tasmlabel);override;
  52. procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
  53. procedure a_jmp_name(list : TAsmList;const s : string); override;
  54. procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
  55. procedure a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel); override;
  56. procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  57. procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
  58. procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
  59. procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
  60. procedure g_concatcopy(list : TAsmList;const source,dest : treference;len : aint);override;
  61. procedure g_concatcopy_move(list : TAsmList;const source,dest : treference;len : aint);
  62. procedure g_overflowcheck(list: TAsmList; const l: tlocation; def: tdef); override;
  63. procedure g_save_registers(list : TAsmList);override;
  64. procedure g_restore_registers(list : TAsmList);override;
  65. procedure a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  66. procedure fixref(list : TAsmList;var ref : treference);
  67. function normalize_ref(list:TAsmList;ref: treference):treference;
  68. procedure g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);override;
  69. procedure emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  70. procedure a_adjust_sp(list: TAsmList; value: longint);
  71. function GetLoad(const ref : treference) : tasmop;
  72. function GetStore(const ref: treference): tasmop;
  73. end;
  74. tcg64favr = class(tcg64f32)
  75. procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  76. procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
  77. end;
  78. procedure create_codegen;
  79. const
  80. TOpCG2AsmOp: Array[topcg] of TAsmOp = (A_NONE,A_MOV,A_ADD,A_AND,A_NONE,
  81. A_NONE,A_MUL,A_MULS,A_NEG,A_COM,A_OR,
  82. A_ASR,A_LSL,A_LSR,A_SUB,A_EOR,A_ROL,A_ROR);
  83. implementation
  84. uses
  85. globals,verbose,systems,cutils,
  86. fmodule,
  87. symconst,symsym,
  88. tgobj,
  89. procinfo,cpupi,
  90. paramgr;
  91. procedure tcgavr.init_register_allocators;
  92. begin
  93. inherited init_register_allocators;
  94. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  95. [RS_R8,RS_R9,
  96. RS_R10,RS_R11,RS_R12,RS_R13,RS_R14,RS_R15,RS_R16,RS_R17,RS_R18,RS_R19,
  97. RS_R20,RS_R21,RS_R22,RS_R23,RS_R24,RS_R25,RS_R0,
  98. RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7],first_int_imreg,[]);
  99. { rg[R_ADDRESSREGISTER]:=trgintcpu.create(R_ADDRESSREGISTER,R_SUBWHOLE,
  100. [RS_R26,RS_R30],first_int_imreg,[]); }
  101. end;
  102. procedure tcgavr.done_register_allocators;
  103. begin
  104. rg[R_INTREGISTER].free;
  105. // rg[R_ADDRESSREGISTER].free;
  106. inherited done_register_allocators;
  107. end;
  108. function tcgavr.getintregister(list: TAsmList; size: Tcgsize): Tregister;
  109. var
  110. tmp1,tmp2,tmp3 : TRegister;
  111. begin
  112. case size of
  113. OS_8,OS_S8:
  114. Result:=inherited getintregister(list, size);
  115. OS_16,OS_S16:
  116. begin
  117. Result:=inherited getintregister(list, OS_8);
  118. { ensure that the high register can be retrieved by
  119. GetNextReg
  120. }
  121. if inherited getintregister(list, OS_8)<>GetNextReg(Result) then
  122. internalerror(2011021331);
  123. end;
  124. OS_32,OS_S32:
  125. begin
  126. Result:=inherited getintregister(list, OS_8);
  127. tmp1:=inherited getintregister(list, OS_8);
  128. { ensure that the high register can be retrieved by
  129. GetNextReg
  130. }
  131. if tmp1<>GetNextReg(Result) then
  132. internalerror(2011021332);
  133. tmp2:=inherited getintregister(list, OS_8);
  134. { ensure that the upper register can be retrieved by
  135. GetNextReg
  136. }
  137. if tmp2<>GetNextReg(tmp1) then
  138. internalerror(2011021333);
  139. tmp3:=inherited getintregister(list, OS_8);
  140. { ensure that the upper register can be retrieved by
  141. GetNextReg
  142. }
  143. if tmp3<>GetNextReg(tmp2) then
  144. internalerror(2011021334);
  145. end;
  146. else
  147. internalerror(2011021330);
  148. end;
  149. end;
  150. function tcgavr.getaddressregister(list: TAsmList): TRegister;
  151. begin
  152. Result:=getintregister(list,OS_ADDR);
  153. end;
  154. procedure tcgavr.a_load_const_cgpara(list : TAsmList;size : tcgsize;a : aint;const paraloc : TCGPara);
  155. var
  156. ref: treference;
  157. begin
  158. paraloc.check_simple_location;
  159. paramanager.allocparaloc(list,paraloc.location);
  160. case paraloc.location^.loc of
  161. LOC_REGISTER,LOC_CREGISTER:
  162. a_load_const_reg(list,size,a,paraloc.location^.register);
  163. LOC_REFERENCE:
  164. begin
  165. reference_reset(ref,paraloc.alignment);
  166. ref.base:=paraloc.location^.reference.index;
  167. ref.offset:=paraloc.location^.reference.offset;
  168. a_load_const_ref(list,size,a,ref);
  169. end;
  170. else
  171. internalerror(2002081101);
  172. end;
  173. end;
  174. procedure tcgavr.a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);
  175. var
  176. tmpref, ref: treference;
  177. location: pcgparalocation;
  178. sizeleft: aint;
  179. begin
  180. location := paraloc.location;
  181. tmpref := r;
  182. sizeleft := paraloc.intsize;
  183. while assigned(location) do
  184. begin
  185. paramanager.allocparaloc(list,location);
  186. case location^.loc of
  187. LOC_REGISTER,LOC_CREGISTER:
  188. a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
  189. LOC_REFERENCE:
  190. begin
  191. reference_reset_base(ref,location^.reference.index,location^.reference.offset,paraloc.alignment);
  192. { doubles in softemu mode have a strange order of registers and references }
  193. if location^.size=OS_32 then
  194. g_concatcopy(list,tmpref,ref,4)
  195. else
  196. begin
  197. g_concatcopy(list,tmpref,ref,sizeleft);
  198. if assigned(location^.next) then
  199. internalerror(2005010710);
  200. end;
  201. end;
  202. LOC_VOID:
  203. begin
  204. // nothing to do
  205. end;
  206. else
  207. internalerror(2002081103);
  208. end;
  209. inc(tmpref.offset,tcgsize2size[location^.size]);
  210. dec(sizeleft,tcgsize2size[location^.size]);
  211. location := location^.next;
  212. end;
  213. end;
  214. procedure tcgavr.a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);
  215. var
  216. ref: treference;
  217. tmpreg: tregister;
  218. begin
  219. paraloc.check_simple_location;
  220. paramanager.allocparaloc(list,paraloc.location);
  221. case paraloc.location^.loc of
  222. LOC_REGISTER,LOC_CREGISTER:
  223. a_loadaddr_ref_reg(list,r,paraloc.location^.register);
  224. LOC_REFERENCE:
  225. begin
  226. reference_reset(ref,paraloc.alignment);
  227. ref.base := paraloc.location^.reference.index;
  228. ref.offset := paraloc.location^.reference.offset;
  229. tmpreg := getintregister(list,OS_ADDR);
  230. a_loadaddr_ref_reg(list,r,tmpreg);
  231. a_load_reg_ref(list,OS_ADDR,OS_ADDR,tmpreg,ref);
  232. end;
  233. else
  234. internalerror(2002080701);
  235. end;
  236. end;
  237. procedure tcgavr.a_call_name(list : TAsmList;const s : string; weak: boolean);
  238. begin
  239. list.concat(taicpu.op_sym(A_RCALL,current_asmdata.RefAsmSymbol(s)));
  240. {
  241. the compiler does not properly set this flag anymore in pass 1, and
  242. for now we only need it after pass 2 (I hope) (JM)
  243. if not(pi_do_call in current_procinfo.flags) then
  244. internalerror(2003060703);
  245. }
  246. include(current_procinfo.flags,pi_do_call);
  247. end;
  248. procedure tcgavr.a_call_reg(list : TAsmList;reg: tregister);
  249. begin
  250. a_reg_alloc(list,NR_ZLO);
  251. a_reg_alloc(list,NR_ZHI);
  252. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZLO,reg));
  253. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZHI,GetHigh(reg)));
  254. list.concat(taicpu.op_none(A_ICALL));
  255. a_reg_dealloc(list,NR_ZLO);
  256. a_reg_dealloc(list,NR_ZHI);
  257. include(current_procinfo.flags,pi_do_call);
  258. end;
  259. procedure tcgavr.a_call_ref(list : TAsmList;ref: treference);
  260. begin
  261. a_reg_alloc(list,NR_ZLO);
  262. a_reg_alloc(list,NR_ZHI);
  263. a_load_ref_reg(list,OS_ADDR,OS_ADDR,ref,NR_ZLO);
  264. list.concat(taicpu.op_none(A_ICALL));
  265. a_reg_dealloc(list,NR_ZLO);
  266. a_reg_dealloc(list,NR_ZHI);
  267. include(current_procinfo.flags,pi_do_call);
  268. end;
  269. procedure tcgavr.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: aint; reg: TRegister);
  270. var
  271. mask : qword;
  272. shift : byte;
  273. i : byte;
  274. tmpreg : tregister;
  275. begin
  276. mask:=$ff;
  277. shift:=0;
  278. case op of
  279. OP_OR:
  280. begin
  281. for i:=1 to tcgsize2size[size] do
  282. begin
  283. list.concat(taicpu.op_reg_const(A_ORI,reg,(a and mask) shr shift));
  284. reg:=GetNextReg(reg);
  285. mask:=mask shl 8;
  286. inc(shift,8);
  287. end;
  288. end;
  289. OP_AND:
  290. begin
  291. for i:=1 to tcgsize2size[size] do
  292. begin
  293. list.concat(taicpu.op_reg_const(A_ANDI,reg,(a and mask) shr shift));
  294. reg:=GetNextReg(reg);
  295. mask:=mask shl 8;
  296. inc(shift,8);
  297. end;
  298. end;
  299. OP_SUB:
  300. begin
  301. list.concat(taicpu.op_reg_const(A_SUBI,reg,a));
  302. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  303. begin
  304. for i:=2 to tcgsize2size[size] do
  305. begin
  306. reg:=GetNextReg(reg);
  307. mask:=mask shl 8;
  308. inc(shift,8);
  309. list.concat(taicpu.op_reg_const(A_SBCI,reg,(a and mask) shr shift));
  310. end;
  311. end;
  312. end;
  313. else
  314. begin
  315. tmpreg:=getintregister(list,size);
  316. a_load_const_reg(list,size,a,tmpreg);
  317. a_op_reg_reg(list,op,size,tmpreg,reg);
  318. end;
  319. end;
  320. end;
  321. procedure tcgavr.a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister);
  322. var
  323. countreg,
  324. tmpreg: tregister;
  325. i : integer;
  326. instr : taicpu;
  327. paraloc1,paraloc2,paraloc3 : TCGPara;
  328. l1,l2 : tasmlabel;
  329. begin
  330. case op of
  331. OP_ADD:
  332. begin
  333. list.concat(taicpu.op_reg_reg(A_ADD,dst,src));
  334. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  335. begin
  336. for i:=2 to tcgsize2size[size] do
  337. begin
  338. dst:=GetNextReg(dst);
  339. src:=GetNextReg(src);
  340. list.concat(taicpu.op_reg_reg(A_ADC,dst,src));
  341. end;
  342. end
  343. else
  344. end;
  345. OP_SUB:
  346. begin
  347. list.concat(taicpu.op_reg_reg(A_SUB,dst,src));
  348. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  349. begin
  350. for i:=2 to tcgsize2size[size] do
  351. begin
  352. dst:=GetNextReg(dst);
  353. src:=GetNextReg(src);
  354. list.concat(taicpu.op_reg_reg(A_SBC,dst,src));
  355. end;
  356. end;
  357. end;
  358. OP_NEG:
  359. begin
  360. if src<>dst then
  361. a_load_reg_reg(list,size,size,src,dst);
  362. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  363. begin
  364. tmpreg:=GetNextReg(dst);
  365. for i:=2 to tcgsize2size[size] do
  366. begin
  367. list.concat(taicpu.op_reg(A_COM,tmpreg));
  368. tmpreg:=GetNextReg(tmpreg);
  369. end;
  370. list.concat(taicpu.op_reg(A_NEG,dst));
  371. tmpreg:=GetNextReg(dst);
  372. for i:=2 to tcgsize2size[size] do
  373. begin
  374. list.concat(taicpu.op_reg_const(A_SBCI,dst,-1));
  375. tmpreg:=GetNextReg(tmpreg);
  376. end;
  377. end
  378. else
  379. list.concat(taicpu.op_reg(A_NEG,dst));
  380. end;
  381. OP_NOT:
  382. begin
  383. for i:=1 to tcgsize2size[size] do
  384. begin
  385. if src<>dst then
  386. a_load_reg_reg(list,OS_8,OS_8,src,dst);
  387. list.concat(taicpu.op_reg(A_COM,dst));
  388. src:=GetNextReg(src);
  389. dst:=GetNextReg(dst);
  390. end;
  391. end;
  392. OP_MUL,OP_IMUL:
  393. begin
  394. if size in [OS_8,OS_S8] then
  395. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src))
  396. else if size=OS_16 then
  397. begin
  398. paraloc1.init;
  399. paraloc2.init;
  400. paraloc3.init;
  401. paramanager.getintparaloc(pocall_default,1,paraloc1);
  402. paramanager.getintparaloc(pocall_default,2,paraloc2);
  403. paramanager.getintparaloc(pocall_default,3,paraloc3);
  404. a_load_const_cgpara(list,OS_8,0,paraloc3);
  405. a_load_reg_cgpara(list,OS_16,src,paraloc2);
  406. a_load_reg_cgpara(list,OS_16,dst,paraloc1);
  407. paramanager.freecgpara(list,paraloc3);
  408. paramanager.freecgpara(list,paraloc2);
  409. paramanager.freecgpara(list,paraloc1);
  410. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  411. a_call_name(list,'FPC_MUL_WORD',false);
  412. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  413. cg.a_reg_alloc(list,NR_FUNCTION_RESULT_REG);
  414. cg.a_load_reg_reg(list,OS_16,OS_16,NR_FUNCTION_RESULT_REG,dst);
  415. paraloc3.done;
  416. paraloc2.done;
  417. paraloc1.done;
  418. end
  419. else
  420. internalerror(2011022002);
  421. end;
  422. OP_DIV,OP_IDIV:
  423. { special stuff, needs separate handling inside code }
  424. { generator }
  425. internalerror(2011022001);
  426. OP_SHR,OP_SHL,OP_SAR,OP_ROL,OP_ROR:
  427. begin
  428. current_asmdata.getjumplabel(l1);
  429. current_asmdata.getjumplabel(l2);
  430. countreg:=getintregister(list,OS_8);
  431. a_load_reg_reg(list,size,OS_8,src,countreg);
  432. list.concat(taicpu.op_reg_const(A_CP,countreg,0));
  433. a_jmp_flags(list,F_EQ,l2);
  434. cg.a_label(list,l1);
  435. case op of
  436. OP_SHR:
  437. list.concat(taicpu.op_reg(A_LSR,GetOffsetReg(dst,tcgsize2size[size]-1)));
  438. OP_SHL:
  439. list.concat(taicpu.op_reg(A_LSL,dst));
  440. OP_SAR:
  441. list.concat(taicpu.op_reg(A_ASR,GetOffsetReg(dst,tcgsize2size[size]-1)));
  442. OP_ROR:
  443. begin
  444. { load carry? }
  445. if not(size in [OS_8,OS_S8]) then
  446. begin
  447. list.concat(taicpu.op_none(A_CLC));
  448. list.concat(taicpu.op_reg_const(A_SBRC,src,0));
  449. list.concat(taicpu.op_none(A_SEC));
  450. end;
  451. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg(dst,tcgsize2size[size]-1)));
  452. end;
  453. OP_ROL:
  454. begin
  455. { load carry? }
  456. if not(size in [OS_8,OS_S8]) then
  457. begin
  458. list.concat(taicpu.op_none(A_CLC));
  459. list.concat(taicpu.op_reg_const(A_SBRC,GetOffsetReg(dst,tcgsize2size[size]-1),7));
  460. list.concat(taicpu.op_none(A_SEC));
  461. end;
  462. list.concat(taicpu.op_reg(A_ROL,dst))
  463. end;
  464. else
  465. internalerror(2011030901);
  466. end;
  467. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  468. begin
  469. for i:=2 to tcgsize2size[size] do
  470. begin
  471. case op of
  472. OP_ROR,
  473. OP_SHR:
  474. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg(dst,tcgsize2size[size]-i)));
  475. OP_ROL,
  476. OP_SHL:
  477. list.concat(taicpu.op_reg(A_ROL,GetOffsetReg(dst,i-1)));
  478. OP_SAR:
  479. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg(dst,tcgsize2size[size]-i)));
  480. else
  481. internalerror(2011030902);
  482. end;
  483. end;
  484. end;
  485. a_op_const_reg(list,OP_SUB,OS_8,1,countreg);
  486. a_jmp_flags(list,F_NE,l1);
  487. // keep registers alive
  488. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  489. cg.a_label(list,l2);
  490. end;
  491. OP_AND,OP_OR,OP_XOR:
  492. begin
  493. for i:=1 to tcgsize2size[size] do
  494. begin
  495. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src));
  496. dst:=GetNextReg(dst);
  497. src:=GetNextReg(src);
  498. end;
  499. end;
  500. else
  501. internalerror(2011022004);
  502. end;
  503. end;
  504. procedure tcgavr.a_load_const_reg(list : TAsmList; size: tcgsize; a : aint;reg : tregister);
  505. var
  506. mask : qword;
  507. shift : byte;
  508. i : byte;
  509. begin
  510. mask:=$ff;
  511. shift:=0;
  512. for i:=1 to tcgsize2size[size] do
  513. begin
  514. if ((qword(a) and mask) shr shift)=0 then
  515. emit_mov(list,reg,NR_R1)
  516. else
  517. list.concat(taicpu.op_reg_const(A_LDI,reg,(qword(a) and mask) shr shift));
  518. mask:=mask shl 8;
  519. inc(shift,8);
  520. reg:=GetNextReg(reg);
  521. end;
  522. end;
  523. { TODO : support usage of ref.base register parameter }
  524. function tcgavr.normalize_ref(list:TAsmList;ref: treference):treference;
  525. var
  526. tmpreg : tregister;
  527. tmpref : treference;
  528. l : tasmlabel;
  529. begin
  530. tmpreg:=NR_NO;
  531. Result:=ref;
  532. if ref.addressmode<>AM_UNCHANGED then
  533. internalerror(2011021701);
  534. { Be sure to have a base register }
  535. if (ref.base=NR_NO) then
  536. begin
  537. { only symbol+offset? }
  538. if ref.index=NR_NO then
  539. exit;
  540. ref.base:=ref.index;
  541. ref.index:=NR_NO;
  542. end;
  543. if assigned(ref.symbol) or (ref.offset<>0) then
  544. begin
  545. tmpreg:=NR_R30;
  546. reference_reset(tmpref,0);
  547. tmpref.symbol:=ref.symbol;
  548. tmpref.offset:=ref.offset;
  549. tmpref.refaddr:=addr_lo8;
  550. getcpuregister(list,tmpreg);
  551. list.concat(taicpu.op_reg_ref(A_LDI,tmpreg,tmpref));
  552. tmpref.refaddr:=addr_hi8;
  553. getcpuregister(list,GetNextReg(tmpreg));
  554. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(tmpreg),tmpref));
  555. if (ref.base<>NR_NO) then
  556. begin
  557. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
  558. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
  559. end;
  560. if (ref.index<>NR_NO) then
  561. begin
  562. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  563. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  564. end;
  565. ref.symbol:=nil;
  566. ref.offset:=0;
  567. ref.base:=tmpreg;
  568. ref.index:=NR_NO;
  569. end
  570. else if (ref.base<>NR_NO) and (ref.index<>NR_NO) then
  571. begin
  572. tmpreg:=NR_R30;
  573. getcpuregister(list,tmpreg);
  574. emit_mov(list,tmpreg,ref.index);
  575. getcpuregister(list,GetNextReg(tmpreg));
  576. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
  577. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
  578. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
  579. ref.base:=tmpreg;
  580. ref.index:=NR_NO;
  581. end
  582. else if (ref.base<>NR_NO) then
  583. begin
  584. tmpreg:=NR_R30;
  585. getcpuregister(list,tmpreg);
  586. emit_mov(list,tmpreg,ref.base);
  587. getcpuregister(list,GetNextReg(tmpreg));
  588. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  589. ref.base:=tmpreg;
  590. ref.index:=NR_NO;
  591. end
  592. else if (ref.index<>NR_NO) then
  593. begin
  594. tmpreg:=NR_R30;
  595. getcpuregister(list,tmpreg);
  596. emit_mov(list,tmpreg,ref.index);
  597. getcpuregister(list,GetNextReg(tmpreg));
  598. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
  599. ref.base:=tmpreg;
  600. ref.index:=NR_NO;
  601. end;
  602. Result:=ref;
  603. end;
  604. procedure tcgavr.a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);
  605. var
  606. href : treference;
  607. conv_done: boolean;
  608. tmpreg : tregister;
  609. i : integer;
  610. QuickRef : Boolean;
  611. begin
  612. QuickRef:=false;
  613. if not((Ref.addressmode=AM_UNCHANGED) and
  614. (Ref.symbol=nil) and
  615. ((Ref.base=NR_R28) or
  616. (Ref.base=NR_R29)) and
  617. (Ref.Index=NR_No) and
  618. (Ref.Offset in [0..64-tcgsize2size[tosize]])) and
  619. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  620. href:=normalize_ref(list,Ref)
  621. else
  622. begin
  623. QuickRef:=true;
  624. href:=Ref;
  625. end;
  626. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  627. internalerror(2011021307);
  628. conv_done:=false;
  629. if tosize<>fromsize then
  630. begin
  631. conv_done:=true;
  632. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  633. fromsize:=tosize;
  634. case fromsize of
  635. OS_8:
  636. begin
  637. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  638. href.addressmode:=AM_POSTINCREMENT;
  639. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  640. for i:=2 to tcgsize2size[tosize] do
  641. begin
  642. if QuickRef then
  643. inc(href.offset);
  644. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  645. href.addressmode:=AM_POSTINCREMENT
  646. else
  647. href.addressmode:=AM_UNCHANGED;
  648. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  649. end;
  650. end;
  651. OS_S8:
  652. begin
  653. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  654. href.addressmode:=AM_POSTINCREMENT;
  655. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  656. if tcgsize2size[tosize]>1 then
  657. begin
  658. tmpreg:=getintregister(list,OS_8);
  659. list.concat(taicpu.op_reg(A_CLR,tmpreg));
  660. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  661. list.concat(taicpu.op_reg(A_COM,tmpreg));
  662. for i:=2 to tcgsize2size[tosize] do
  663. begin
  664. if QuickRef then
  665. inc(href.offset);
  666. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  667. href.addressmode:=AM_POSTINCREMENT
  668. else
  669. href.addressmode:=AM_UNCHANGED;
  670. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  671. end;
  672. end;
  673. end;
  674. OS_16:
  675. begin
  676. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  677. href.addressmode:=AM_POSTINCREMENT;
  678. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  679. if QuickRef then
  680. inc(href.offset)
  681. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  682. href.addressmode:=AM_POSTINCREMENT
  683. else
  684. href.addressmode:=AM_UNCHANGED;
  685. reg:=GetNextReg(reg);
  686. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  687. for i:=3 to tcgsize2size[tosize] do
  688. begin
  689. if QuickRef then
  690. inc(href.offset);
  691. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  692. href.addressmode:=AM_POSTINCREMENT
  693. else
  694. href.addressmode:=AM_UNCHANGED;
  695. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  696. end;
  697. end;
  698. OS_S16:
  699. begin
  700. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  701. href.addressmode:=AM_POSTINCREMENT;
  702. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  703. if QuickRef then
  704. inc(href.offset)
  705. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  706. href.addressmode:=AM_POSTINCREMENT
  707. else
  708. href.addressmode:=AM_UNCHANGED;
  709. reg:=GetNextReg(reg);
  710. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  711. if tcgsize2size[tosize]>2 then
  712. begin
  713. tmpreg:=getintregister(list,OS_8);
  714. list.concat(taicpu.op_reg(A_CLR,tmpreg));
  715. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  716. list.concat(taicpu.op_reg(A_COM,tmpreg));
  717. for i:=3 to tcgsize2size[tosize] do
  718. begin
  719. if QuickRef then
  720. inc(href.offset);
  721. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  722. href.addressmode:=AM_POSTINCREMENT
  723. else
  724. href.addressmode:=AM_UNCHANGED;
  725. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  726. end;
  727. end;
  728. end;
  729. else
  730. conv_done:=false;
  731. end;
  732. end;
  733. if not conv_done then
  734. begin
  735. for i:=1 to tcgsize2size[fromsize] do
  736. begin
  737. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  738. href.addressmode:=AM_POSTINCREMENT
  739. else
  740. href.addressmode:=AM_UNCHANGED;
  741. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  742. if QuickRef then
  743. inc(href.offset);
  744. reg:=GetNextReg(reg);
  745. end;
  746. end;
  747. if not(QuickRef) then
  748. begin
  749. ungetcpuregister(list,href.base);
  750. ungetcpuregister(list,GetNextReg(href.base));
  751. end;
  752. end;
  753. procedure tcgavr.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;
  754. const Ref : treference;reg : tregister);
  755. var
  756. href : treference;
  757. conv_done: boolean;
  758. tmpreg : tregister;
  759. i : integer;
  760. QuickRef : boolean;
  761. begin
  762. QuickRef:=false;
  763. if not((Ref.addressmode=AM_UNCHANGED) and
  764. (Ref.symbol=nil) and
  765. ((Ref.base=NR_R28) or
  766. (Ref.base=NR_R29)) and
  767. (Ref.Index=NR_No) and
  768. (Ref.Offset in [0..64-tcgsize2size[fromsize]])) and
  769. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  770. href:=normalize_ref(list,Ref)
  771. else
  772. begin
  773. QuickRef:=true;
  774. href:=Ref;
  775. end;
  776. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  777. internalerror(2011021307);
  778. conv_done:=false;
  779. if tosize<>fromsize then
  780. begin
  781. conv_done:=true;
  782. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  783. fromsize:=tosize;
  784. case fromsize of
  785. OS_8:
  786. begin
  787. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  788. for i:=2 to tcgsize2size[tosize] do
  789. begin
  790. reg:=GetNextReg(reg);
  791. list.concat(taicpu.op_reg(A_CLR,reg));
  792. end;
  793. end;
  794. OS_S8:
  795. begin
  796. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  797. tmpreg:=reg;
  798. if tcgsize2size[tosize]>1 then
  799. begin
  800. reg:=GetNextReg(reg);
  801. list.concat(taicpu.op_reg(A_CLR,reg));
  802. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  803. list.concat(taicpu.op_reg(A_COM,reg));
  804. tmpreg:=reg;
  805. for i:=3 to tcgsize2size[tosize] do
  806. begin
  807. reg:=GetNextReg(reg);
  808. emit_mov(list,reg,tmpreg);
  809. end;
  810. end;
  811. end;
  812. OS_16:
  813. begin
  814. if not(QuickRef) then
  815. href.addressmode:=AM_POSTINCREMENT;
  816. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  817. if QuickRef then
  818. inc(href.offset);
  819. href.addressmode:=AM_UNCHANGED;
  820. reg:=GetNextReg(reg);
  821. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  822. for i:=3 to tcgsize2size[tosize] do
  823. begin
  824. reg:=GetNextReg(reg);
  825. list.concat(taicpu.op_reg(A_CLR,reg));
  826. end;
  827. end;
  828. OS_S16:
  829. begin
  830. if not(QuickRef) then
  831. href.addressmode:=AM_POSTINCREMENT;
  832. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  833. if QuickRef then
  834. inc(href.offset);
  835. href.addressmode:=AM_UNCHANGED;
  836. reg:=GetNextReg(reg);
  837. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  838. tmpreg:=reg;
  839. reg:=GetNextReg(reg);
  840. list.concat(taicpu.op_reg(A_CLR,reg));
  841. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  842. list.concat(taicpu.op_reg(A_COM,reg));
  843. tmpreg:=reg;
  844. for i:=4 to tcgsize2size[tosize] do
  845. begin
  846. reg:=GetNextReg(reg);
  847. emit_mov(list,reg,tmpreg);
  848. end;
  849. end;
  850. else
  851. conv_done:=false;
  852. end;
  853. end;
  854. if not conv_done then
  855. begin
  856. for i:=1 to tcgsize2size[fromsize] do
  857. begin
  858. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  859. href.addressmode:=AM_POSTINCREMENT
  860. else
  861. href.addressmode:=AM_UNCHANGED;
  862. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  863. if QuickRef then
  864. inc(href.offset);
  865. reg:=GetNextReg(reg);
  866. end;
  867. end;
  868. if not(QuickRef) then
  869. begin
  870. ungetcpuregister(list,href.base);
  871. ungetcpuregister(list,GetNextReg(href.base));
  872. end;
  873. end;
  874. procedure tcgavr.a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);
  875. var
  876. conv_done: boolean;
  877. tmpreg : tregister;
  878. i : integer;
  879. begin
  880. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  881. internalerror(2011021310);
  882. conv_done:=false;
  883. if tosize<>fromsize then
  884. begin
  885. conv_done:=true;
  886. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  887. fromsize:=tosize;
  888. case fromsize of
  889. OS_8:
  890. begin
  891. emit_mov(list,reg2,reg1);
  892. for i:=2 to tcgsize2size[tosize] do
  893. begin
  894. reg2:=GetNextReg(reg2);
  895. list.concat(taicpu.op_reg(A_CLR,reg2));
  896. end;
  897. end;
  898. OS_S8:
  899. begin
  900. { dest is always at least 16 bit at this point }
  901. emit_mov(list,reg2,reg1);
  902. reg2:=GetNextReg(reg2);
  903. list.concat(taicpu.op_reg(A_CLR,reg2));
  904. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  905. list.concat(taicpu.op_reg(A_COM,reg2));
  906. tmpreg:=reg2;
  907. for i:=3 to tcgsize2size[tosize] do
  908. begin
  909. reg2:=GetNextReg(reg2);
  910. emit_mov(list,reg2,tmpreg);
  911. end;
  912. end;
  913. OS_16:
  914. begin
  915. emit_mov(list,reg2,reg1);
  916. reg1:=GetNextReg(reg1);
  917. reg2:=GetNextReg(reg2);
  918. emit_mov(list,reg2,reg1);
  919. for i:=3 to tcgsize2size[tosize] do
  920. begin
  921. reg2:=GetNextReg(reg2);
  922. list.concat(taicpu.op_reg(A_CLR,reg2));
  923. end;
  924. end;
  925. OS_S16:
  926. begin
  927. { dest is always at least 32 bit at this point }
  928. emit_mov(list,reg2,reg1);
  929. reg1:=GetNextReg(reg1);
  930. reg2:=GetNextReg(reg2);
  931. emit_mov(list,reg2,reg1);
  932. reg2:=GetNextReg(reg2);
  933. list.concat(taicpu.op_reg(A_CLR,reg2));
  934. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  935. list.concat(taicpu.op_reg(A_COM,reg2));
  936. tmpreg:=reg2;
  937. for i:=4 to tcgsize2size[tosize] do
  938. begin
  939. reg2:=GetNextReg(reg2);
  940. emit_mov(list,reg2,tmpreg);
  941. end;
  942. end;
  943. else
  944. conv_done:=false;
  945. end;
  946. end;
  947. if not conv_done and (reg1<>reg2) then
  948. begin
  949. for i:=1 to tcgsize2size[fromsize] do
  950. begin
  951. emit_mov(list,reg2,reg1);
  952. reg1:=GetNextReg(reg1);
  953. reg2:=GetNextReg(reg2);
  954. end;
  955. end;
  956. end;
  957. { comparison operations }
  958. procedure tcgavr.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;
  959. cmp_op : topcmp;a : aint;reg : tregister;l : tasmlabel);
  960. begin
  961. { TODO : a_cmp_const_reg_label }
  962. end;
  963. procedure tcgavr.a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;
  964. cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
  965. begin
  966. { TODO : a_cmp_reg_reg_label }
  967. end;
  968. procedure tcgavr.a_jmp_name(list : TAsmList;const s : string);
  969. var
  970. ai : taicpu;
  971. begin
  972. ai:=taicpu.op_sym(A_JMP,current_asmdata.RefAsmSymbol(s));
  973. ai.is_jmp:=true;
  974. list.concat(ai);
  975. end;
  976. procedure tcgavr.a_jmp_always(list : TAsmList;l: tasmlabel);
  977. var
  978. ai : taicpu;
  979. begin
  980. ai:=taicpu.op_sym(A_JMP,l);
  981. ai.is_jmp:=true;
  982. list.concat(ai);
  983. end;
  984. procedure tcgavr.a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel);
  985. var
  986. ai : taicpu;
  987. begin
  988. ai:=setcondition(taicpu.op_sym(A_BRxx,l),flags_to_cond(f));
  989. ai.is_jmp:=true;
  990. list.concat(ai);
  991. end;
  992. procedure tcgavr.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
  993. begin
  994. { TODO : implement g_flags2reg }
  995. end;
  996. procedure tcgavr.a_adjust_sp(list : TAsmList; value : longint);
  997. var
  998. i : integer;
  999. begin
  1000. case value of
  1001. 0:
  1002. ;
  1003. -14..-1:
  1004. begin
  1005. if ((-value) mod 2)<>0 then
  1006. list.concat(taicpu.op_reg(A_PUSH,NR_R0));
  1007. for i:=1 to (-value) div 2 do
  1008. list.concat(taicpu.op_const(A_RCALL,0));
  1009. end;
  1010. 1..7:
  1011. begin
  1012. for i:=1 to value do
  1013. list.concat(taicpu.op_reg(A_POP,NR_R0));
  1014. end;
  1015. else
  1016. begin
  1017. list.concat(taicpu.op_reg_const(A_SUBI,NR_R28,lo(word(-value))));
  1018. list.concat(taicpu.op_reg_const(A_SBCI,NR_R29,hi(word(-value))));
  1019. // get SREG
  1020. list.concat(taicpu.op_reg_const(A_IN,NR_R0,NIO_SREG));
  1021. // block interrupts
  1022. list.concat(taicpu.op_none(A_CLI));
  1023. // write high SP
  1024. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_HI,NR_R29));
  1025. // release interrupts
  1026. list.concat(taicpu.op_const_reg(A_OUT,NIO_SREG,NR_R0));
  1027. // write low SP
  1028. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_LO,NR_R28));
  1029. end;
  1030. end;
  1031. end;
  1032. function tcgavr.GetLoad(const ref: treference) : tasmop;
  1033. begin
  1034. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1035. result:=A_LDS
  1036. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1037. result:=A_LDD
  1038. else
  1039. result:=A_LD;
  1040. end;
  1041. function tcgavr.GetStore(const ref: treference) : tasmop;
  1042. begin
  1043. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1044. result:=A_STS
  1045. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1046. result:=A_STD
  1047. else
  1048. result:=A_ST;
  1049. end;
  1050. procedure tcgavr.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
  1051. var
  1052. regs : tcpuregisterset;
  1053. reg : tsuperregister;
  1054. begin
  1055. if not(nostackframe) then
  1056. begin
  1057. { save int registers }
  1058. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1059. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1060. regs:=regs+[RS_R28,RS_R29];
  1061. for reg:=RS_R31 downto RS_R0 do
  1062. if reg in regs then
  1063. list.concat(taicpu.op_reg(A_PUSH,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1064. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1065. begin
  1066. list.concat(taicpu.op_reg_const(A_IN,NR_R28,NIO_SP_LO));
  1067. list.concat(taicpu.op_reg_const(A_IN,NR_R29,NIO_SP_HI));
  1068. end
  1069. else
  1070. { the framepointer cannot be omitted on avr because sp
  1071. is not a register but part of the i/o map
  1072. }
  1073. internalerror(2011021901);
  1074. a_adjust_sp(list,-localsize);
  1075. end;
  1076. end;
  1077. procedure tcgavr.g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean);
  1078. var
  1079. regs : tcpuregisterset;
  1080. reg : TSuperRegister;
  1081. LocalSize : longint;
  1082. begin
  1083. if not(nostackframe) then
  1084. begin
  1085. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1086. begin
  1087. LocalSize:=current_procinfo.calc_stackframe_size;
  1088. a_adjust_sp(list,LocalSize);
  1089. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1090. for reg:=RS_R0 to RS_R31 do
  1091. if reg in regs then
  1092. list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1093. end
  1094. else
  1095. { the framepointer cannot be omitted on avr because sp
  1096. is not a register but part of the i/o map
  1097. }
  1098. internalerror(2011021902);
  1099. end;
  1100. list.concat(taicpu.op_none(A_RET));
  1101. end;
  1102. procedure tcgavr.a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);
  1103. var
  1104. tmpref : treference;
  1105. begin
  1106. if ref.addressmode<>AM_UNCHANGED then
  1107. internalerror(2011021701);
  1108. if assigned(ref.symbol) or (ref.offset<>0) then
  1109. begin
  1110. reference_reset(tmpref,0);
  1111. tmpref.symbol:=ref.symbol;
  1112. tmpref.offset:=ref.offset;
  1113. tmpref.refaddr:=addr_lo8;
  1114. list.concat(taicpu.op_reg_ref(A_LDI,r,tmpref));
  1115. tmpref.refaddr:=addr_hi8;
  1116. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(r),tmpref));
  1117. if (ref.base<>NR_NO) then
  1118. begin
  1119. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.base));
  1120. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.base)));
  1121. end;
  1122. if (ref.index<>NR_NO) then
  1123. begin
  1124. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1125. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1126. end;
  1127. end
  1128. else if (ref.base<>NR_NO)then
  1129. begin
  1130. emit_mov(list,r,ref.base);
  1131. emit_mov(list,GetNextReg(r),GetNextReg(ref.base));
  1132. if (ref.index<>NR_NO) then
  1133. begin
  1134. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1135. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1136. end;
  1137. end
  1138. else if (ref.index<>NR_NO) then
  1139. begin
  1140. emit_mov(list,r,ref.index);
  1141. emit_mov(list,GetNextReg(r),GetNextReg(ref.index));
  1142. end;
  1143. end;
  1144. procedure tcgavr.fixref(list : TAsmList;var ref : treference);
  1145. begin
  1146. internalerror(2011021320);
  1147. end;
  1148. procedure tcgavr.g_concatcopy_move(list : TAsmList;const source,dest : treference;len : aint);
  1149. var
  1150. paraloc1,paraloc2,paraloc3 : TCGPara;
  1151. begin
  1152. paraloc1.init;
  1153. paraloc2.init;
  1154. paraloc3.init;
  1155. paramanager.getintparaloc(pocall_default,1,paraloc1);
  1156. paramanager.getintparaloc(pocall_default,2,paraloc2);
  1157. paramanager.getintparaloc(pocall_default,3,paraloc3);
  1158. a_load_const_cgpara(list,OS_INT,len,paraloc3);
  1159. a_loadaddr_ref_cgpara(list,dest,paraloc2);
  1160. a_loadaddr_ref_cgpara(list,source,paraloc1);
  1161. paramanager.freecgpara(list,paraloc3);
  1162. paramanager.freecgpara(list,paraloc2);
  1163. paramanager.freecgpara(list,paraloc1);
  1164. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1165. a_call_name_static(list,'FPC_MOVE');
  1166. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1167. paraloc3.done;
  1168. paraloc2.done;
  1169. paraloc1.done;
  1170. end;
  1171. procedure tcgavr.g_concatcopy(list : TAsmList;const source,dest : treference;len : aint);
  1172. var
  1173. countreg,tmpreg : tregister;
  1174. srcref,dstref : treference;
  1175. copysize,countregsize : tcgsize;
  1176. l : TAsmLabel;
  1177. i : longint;
  1178. SrcQuickRef, DestQuickRef : Boolean;
  1179. begin
  1180. if len>16 then
  1181. begin
  1182. current_asmdata.getjumplabel(l);
  1183. reference_reset(srcref,0);
  1184. reference_reset(dstref,0);
  1185. srcref.base:=NR_R30;
  1186. srcref.addressmode:=AM_POSTINCREMENT;
  1187. dstref.base:=NR_R26;
  1188. dstref.addressmode:=AM_POSTINCREMENT;
  1189. copysize:=OS_8;
  1190. if len<256 then
  1191. countregsize:=OS_8
  1192. else if len<65536 then
  1193. countregsize:=OS_16
  1194. else
  1195. internalerror(2011022007);
  1196. countreg:=getintregister(list,countregsize);
  1197. a_load_const_reg(list,countregsize,len,countreg);
  1198. a_loadaddr_ref_reg(list,source,NR_R30);
  1199. tmpreg:=getaddressregister(list);
  1200. a_loadaddr_ref_reg(list,dest,tmpreg);
  1201. { X is used for spilling code so we can load it
  1202. only by a push/pop sequence, this can be
  1203. optimized later on by the peephole optimizer
  1204. }
  1205. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1206. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1207. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1208. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1209. cg.a_label(list,l);
  1210. tmpreg:=getintregister(list,copysize);
  1211. list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg,srcref));
  1212. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,tmpreg));
  1213. a_op_const_reg(list,OP_SUB,countregsize,1,countreg);
  1214. a_jmp_flags(list,F_NE,l);
  1215. // keep registers alive
  1216. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  1217. end
  1218. else
  1219. begin
  1220. SrcQuickRef:=false;
  1221. DestQuickRef:=false;
  1222. if not((source.addressmode=AM_UNCHANGED) and
  1223. (source.symbol=nil) and
  1224. ((source.base=NR_R28) or
  1225. (source.base=NR_R29)) and
  1226. (source.Index=NR_No) and
  1227. (source.Offset in [0..64-len])) and
  1228. not((source.Base=NR_NO) and (source.Index=NR_NO)) then
  1229. srcref:=normalize_ref(list,source)
  1230. else
  1231. begin
  1232. SrcQuickRef:=true;
  1233. srcref:=source;
  1234. end;
  1235. if not((dest.addressmode=AM_UNCHANGED) and
  1236. (dest.symbol=nil) and
  1237. ((dest.base=NR_R28) or
  1238. (dest.base=NR_R29)) and
  1239. (dest.Index=NR_No) and
  1240. (dest.Offset in [0..64-len])) and
  1241. not((dest.Base=NR_NO) and (dest.Index=NR_NO)) then
  1242. dstref:=normalize_ref(list,dest)
  1243. else
  1244. begin
  1245. DestQuickRef:=true;
  1246. dstref:=dest;
  1247. end;
  1248. for i:=1 to len do
  1249. begin
  1250. copysize:=OS_8;
  1251. tmpreg:=getintregister(list,copysize);
  1252. if not(SrcQuickRef) and (i<len) then
  1253. srcref.addressmode:=AM_POSTINCREMENT
  1254. else
  1255. srcref.addressmode:=AM_UNCHANGED;
  1256. if not(DestQuickRef) and (i<len) then
  1257. dstref.addressmode:=AM_POSTINCREMENT
  1258. else
  1259. dstref.addressmode:=AM_UNCHANGED;
  1260. list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg,srcref));
  1261. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,tmpreg));
  1262. if SrcQuickRef then
  1263. inc(srcref.offset);
  1264. if DestQuickRef then
  1265. inc(dstref.offset);
  1266. end;
  1267. if not(SrcQuickRef) then
  1268. begin
  1269. ungetcpuregister(list,srcref.base);
  1270. ungetcpuregister(list,GetNextReg(srcref.base));
  1271. end;
  1272. end;
  1273. end;
  1274. procedure tcgavr.g_overflowCheck(list : TAsmList;const l : tlocation;def : tdef);
  1275. var
  1276. hl : tasmlabel;
  1277. ai : taicpu;
  1278. cond : TAsmCond;
  1279. begin
  1280. if not(cs_check_overflow in current_settings.localswitches) then
  1281. exit;
  1282. current_asmdata.getjumplabel(hl);
  1283. if not ((def.typ=pointerdef) or
  1284. ((def.typ=orddef) and
  1285. (torddef(def).ordtype in [u64bit,u16bit,u32bit,u8bit,uchar,pasbool]))) then
  1286. cond:=C_VC
  1287. else
  1288. cond:=C_CC;
  1289. ai:=Taicpu.Op_Sym(A_BRxx,hl);
  1290. ai.SetCondition(cond);
  1291. ai.is_jmp:=true;
  1292. list.concat(ai);
  1293. a_call_name(list,'FPC_OVERFLOW',false);
  1294. a_label(list,hl);
  1295. end;
  1296. procedure tcgavr.g_save_registers(list: TAsmList);
  1297. begin
  1298. { this is done by the entry code }
  1299. end;
  1300. procedure tcgavr.g_restore_registers(list: TAsmList);
  1301. begin
  1302. { this is done by the exit code }
  1303. end;
  1304. procedure tcgavr.a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  1305. var
  1306. ai : taicpu;
  1307. begin
  1308. { TODO : fix a_jmp_cond }
  1309. {
  1310. ai:=Taicpu.Op_sym(A_BRxx,l);
  1311. case cond of
  1312. OC_EQ:
  1313. ai.SetCondition(C_EQ);
  1314. OC_GT
  1315. OC_LT
  1316. OC_GTE
  1317. OC_LTE
  1318. OC_NE
  1319. OC_BE
  1320. OC_B
  1321. OC_AE
  1322. OC_A:
  1323. ai.is_jmp:=true;
  1324. list.concat(ai);
  1325. }
  1326. end;
  1327. procedure tcgavr.g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);
  1328. begin
  1329. internalerror(2011021324);
  1330. end;
  1331. procedure tcgavr.emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  1332. var
  1333. instr: taicpu;
  1334. begin
  1335. instr:=taicpu.op_reg_reg(A_MOV,reg2,reg1);
  1336. list.Concat(instr);
  1337. { Notify the register allocator that we have written a move instruction so
  1338. it can try to eliminate it. }
  1339. add_move_instruction(instr);
  1340. end;
  1341. procedure tcg64favr.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
  1342. begin
  1343. { TODO : a_op64_reg_reg }
  1344. end;
  1345. procedure tcg64favr.a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);
  1346. begin
  1347. { TODO : a_op64_const_reg }
  1348. end;
  1349. procedure create_codegen;
  1350. begin
  1351. cg:=tcgavr.create;
  1352. cg64:=tcg64favr.create;
  1353. end;
  1354. end.