nx86mat.pas 23 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl
  3. Generate x86 code for math nodes
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit nx86mat;
  18. {$i fpcdefs.inc}
  19. interface
  20. uses
  21. node,nmat,ncgmat;
  22. type
  23. tx86unaryminusnode = class(tcgunaryminusnode)
  24. {$ifdef SUPPORT_MMX}
  25. procedure second_mmx;override;
  26. {$endif SUPPORT_MMX}
  27. procedure second_float;override;
  28. function pass_1:tnode;override;
  29. end;
  30. tx86notnode = class(tcgnotnode)
  31. procedure second_boolean;override;
  32. {$ifdef SUPPORT_MMX}
  33. procedure second_mmx;override;
  34. {$endif SUPPORT_MMX}
  35. end;
  36. tx86moddivnode = class(tcgmoddivnode)
  37. procedure pass_generate_code;override;
  38. end;
  39. implementation
  40. uses
  41. globtype,
  42. systems,constexp,
  43. cutils,verbose,globals,
  44. symconst,symdef,
  45. aasmbase,aasmtai,aasmdata,defutil,
  46. cgbase,pass_1,pass_2,
  47. ncon,
  48. cpubase,procinfo,
  49. cga,ncgutil,cgobj,hlcgobj,cgx86,cgutils;
  50. {*****************************************************************************
  51. TI386UNARYMINUSNODE
  52. *****************************************************************************}
  53. function tx86unaryminusnode.pass_1 : tnode;
  54. begin
  55. result:=nil;
  56. firstpass(left);
  57. if codegenerror then
  58. exit;
  59. if (left.resultdef.typ=floatdef) then
  60. begin
  61. if use_vectorfpu(left.resultdef) then
  62. expectloc:=LOC_MMREGISTER
  63. else
  64. expectloc:=LOC_FPUREGISTER;
  65. end
  66. {$ifdef SUPPORT_MMX}
  67. else
  68. if (cs_mmx in current_settings.localswitches) and
  69. is_mmx_able_array(left.resultdef) then
  70. begin
  71. expectloc:=LOC_MMXREGISTER;
  72. end
  73. {$endif SUPPORT_MMX}
  74. else
  75. inherited pass_1;
  76. end;
  77. {$ifdef SUPPORT_MMX}
  78. procedure tx86unaryminusnode.second_mmx;
  79. var
  80. op : tasmop;
  81. hreg : tregister;
  82. begin
  83. op:=A_NONE;
  84. secondpass(left);
  85. location_reset(location,LOC_MMXREGISTER,OS_NO);
  86. hreg:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
  87. emit_reg_reg(A_PXOR,S_NO,hreg,hreg);
  88. case left.location.loc of
  89. LOC_MMXREGISTER:
  90. begin
  91. location.register:=left.location.register;
  92. end;
  93. LOC_CMMXREGISTER:
  94. begin
  95. location.register:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
  96. emit_reg_reg(A_MOVQ,S_NO,left.location.register,location.register);
  97. end;
  98. LOC_REFERENCE,
  99. LOC_CREFERENCE:
  100. begin
  101. location.register:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
  102. emit_ref_reg(A_MOVQ,S_NO,left.location.reference,location.register);
  103. end;
  104. else
  105. internalerror(200203225);
  106. end;
  107. if cs_mmx_saturation in current_settings.localswitches then
  108. case mmx_type(resultdef) of
  109. mmxs8bit:
  110. op:=A_PSUBSB;
  111. mmxu8bit:
  112. op:=A_PSUBUSB;
  113. mmxs16bit,mmxfixed16:
  114. op:=A_PSUBSW;
  115. mmxu16bit:
  116. op:=A_PSUBUSW;
  117. end
  118. else
  119. case mmx_type(resultdef) of
  120. mmxs8bit,mmxu8bit:
  121. op:=A_PSUBB;
  122. mmxs16bit,mmxu16bit,mmxfixed16:
  123. op:=A_PSUBW;
  124. mmxs32bit,mmxu32bit:
  125. op:=A_PSUBD;
  126. end;
  127. if op = A_NONE then
  128. internalerror(201408202);
  129. emit_reg_reg(op,S_NO,location.register,hreg);
  130. emit_reg_reg(A_MOVQ,S_NO,hreg,location.register);
  131. end;
  132. {$endif SUPPORT_MMX}
  133. procedure tx86unaryminusnode.second_float;
  134. var
  135. reg : tregister;
  136. href : treference;
  137. l1 : tasmlabel;
  138. begin
  139. secondpass(left);
  140. if expectloc=LOC_MMREGISTER then
  141. begin
  142. hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
  143. location_reset(location,LOC_MMREGISTER,def_cgsize(resultdef));
  144. { make life of register allocator easier }
  145. location.register:=cg.getmmregister(current_asmdata.CurrAsmList,def_cgsize(resultdef));
  146. current_asmdata.getglobaldatalabel(l1);
  147. new_section(current_asmdata.asmlists[al_typedconsts],sec_rodata_norel,l1.name,const_align(sizeof(pint)));
  148. current_asmdata.asmlists[al_typedconsts].concat(Tai_label.Create(l1));
  149. case def_cgsize(resultdef) of
  150. OS_F32:
  151. current_asmdata.asmlists[al_typedconsts].concat(tai_const.create_32bit(longint(1 shl 31)));
  152. OS_F64:
  153. begin
  154. current_asmdata.asmlists[al_typedconsts].concat(tai_const.create_32bit(0));
  155. current_asmdata.asmlists[al_typedconsts].concat(tai_const.create_32bit(-(1 shl 31)));
  156. end
  157. else
  158. internalerror(2004110215);
  159. end;
  160. reference_reset_symbol(href,l1,0,resultdef.alignment);
  161. if UseAVX then
  162. cg.a_opmm_ref_reg_reg(current_asmdata.CurrAsmList,OP_XOR,left.location.size,href,left.location.register,location.register,nil)
  163. else
  164. begin
  165. reg:=cg.getmmregister(current_asmdata.CurrAsmList,def_cgsize(resultdef));
  166. cg.a_loadmm_ref_reg(current_asmdata.CurrAsmList,def_cgsize(resultdef),def_cgsize(resultdef),href,reg,mms_movescalar);
  167. cg.a_loadmm_reg_reg(current_asmdata.CurrAsmList,def_cgsize(resultdef),def_cgsize(resultdef),left.location.register,location.register,mms_movescalar);
  168. cg.a_opmm_reg_reg(current_asmdata.CurrAsmList,OP_XOR,left.location.size,reg,location.register,nil);
  169. end;
  170. end
  171. else
  172. begin
  173. location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
  174. case left.location.loc of
  175. LOC_REFERENCE,
  176. LOC_CREFERENCE:
  177. begin
  178. location.register:=NR_ST;
  179. cg.a_loadfpu_ref_reg(current_asmdata.CurrAsmList,
  180. left.location.size,location.size,
  181. left.location.reference,location.register);
  182. emit_none(A_FCHS,S_NO);
  183. end;
  184. LOC_FPUREGISTER,
  185. LOC_CFPUREGISTER:
  186. begin
  187. { "load st,st" is ignored by the code generator }
  188. cg.a_loadfpu_reg_reg(current_asmdata.CurrAsmList,left.location.size,location.size,left.location.register,NR_ST);
  189. location.register:=NR_ST;
  190. emit_none(A_FCHS,S_NO);
  191. end;
  192. else
  193. internalerror(200312241);
  194. end;
  195. end;
  196. end;
  197. {*****************************************************************************
  198. TX86NOTNODE
  199. *****************************************************************************}
  200. procedure tx86notnode.second_boolean;
  201. var
  202. opsize : tcgsize;
  203. hreg: tregister;
  204. begin
  205. opsize:=def_cgsize(resultdef);
  206. if not handle_locjump then
  207. begin
  208. { the second pass could change the location of left }
  209. { if it is a register variable, so we've to do }
  210. { this before the case statement }
  211. secondpass(left);
  212. case left.expectloc of
  213. LOC_FLAGS :
  214. begin
  215. location_reset(location,LOC_FLAGS,OS_NO);
  216. location.resflags:=left.location.resflags;
  217. inverse_flags(location.resflags);
  218. end;
  219. LOC_CREFERENCE,
  220. LOC_REFERENCE:
  221. begin
  222. {$if defined(cpu32bitalu)}
  223. if is_64bit(resultdef) then
  224. begin
  225. hreg:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_32);
  226. tcgx86(cg).make_simple_ref(current_asmdata.CurrAsmList,left.location.reference);
  227. cg.a_load_ref_reg(current_asmdata.CurrAsmList,OS_32,OS_32,left.location.reference,hreg);
  228. inc(left.location.reference.offset,4);
  229. cg.a_op_ref_reg(current_asmdata.CurrAsmList,OP_OR,OS_32,left.location.reference,hreg);
  230. end
  231. else
  232. {$elseif defined(cpu16bitalu)}
  233. if is_64bit(resultdef) then
  234. begin
  235. hreg:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_16);
  236. tcgx86(cg).make_simple_ref(current_asmdata.CurrAsmList,left.location.reference);
  237. cg.a_load_ref_reg(current_asmdata.CurrAsmList,OS_16,OS_16,left.location.reference,hreg);
  238. inc(left.location.reference.offset,2);
  239. cg.a_op_ref_reg(current_asmdata.CurrAsmList,OP_OR,OS_16,left.location.reference,hreg);
  240. inc(left.location.reference.offset,2);
  241. cg.a_op_ref_reg(current_asmdata.CurrAsmList,OP_OR,OS_16,left.location.reference,hreg);
  242. inc(left.location.reference.offset,2);
  243. cg.a_op_ref_reg(current_asmdata.CurrAsmList,OP_OR,OS_16,left.location.reference,hreg);
  244. end
  245. else if is_32bit(resultdef) then
  246. begin
  247. hreg:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_16);
  248. tcgx86(cg).make_simple_ref(current_asmdata.CurrAsmList,left.location.reference);
  249. cg.a_load_ref_reg(current_asmdata.CurrAsmList,OS_16,OS_16,left.location.reference,hreg);
  250. inc(left.location.reference.offset,2);
  251. cg.a_op_ref_reg(current_asmdata.CurrAsmList,OP_OR,OS_16,left.location.reference,hreg);
  252. end
  253. else
  254. {$endif}
  255. emit_const_ref(A_CMP, TCGSize2Opsize[opsize], 0, left.location.reference);
  256. location_reset(location,LOC_FLAGS,OS_NO);
  257. location.resflags:=F_E;
  258. end;
  259. LOC_CONSTANT,
  260. LOC_REGISTER,
  261. LOC_CREGISTER,
  262. LOC_SUBSETREG,
  263. LOC_CSUBSETREG,
  264. LOC_SUBSETREF,
  265. LOC_CSUBSETREF :
  266. begin
  267. {$if defined(cpu32bitalu)}
  268. if is_64bit(resultdef) then
  269. begin
  270. hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
  271. emit_reg_reg(A_OR,S_L,left.location.register64.reghi,left.location.register64.reglo);
  272. end
  273. else
  274. {$elseif defined(cpu16bitalu)}
  275. if is_64bit(resultdef) then
  276. begin
  277. hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
  278. emit_reg_reg(A_OR,S_W,GetNextReg(left.location.register64.reghi),left.location.register64.reghi);
  279. emit_reg_reg(A_OR,S_W,GetNextReg(left.location.register64.reglo),left.location.register64.reglo);
  280. emit_reg_reg(A_OR,S_W,left.location.register64.reghi,left.location.register64.reglo);
  281. end
  282. else if is_32bit(resultdef) then
  283. begin
  284. hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
  285. emit_reg_reg(A_OR,S_L,GetNextReg(left.location.register),left.location.register);
  286. end
  287. else
  288. {$endif}
  289. begin
  290. hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,true);
  291. emit_reg_reg(A_TEST,TCGSize2Opsize[opsize],left.location.register,left.location.register);
  292. end;
  293. location_reset(location,LOC_FLAGS,OS_NO);
  294. location.resflags:=F_E;
  295. end;
  296. else
  297. internalerror(200203224);
  298. end;
  299. end;
  300. end;
  301. {$ifdef SUPPORT_MMX}
  302. procedure tx86notnode.second_mmx;
  303. var hreg,r:Tregister;
  304. begin
  305. secondpass(left);
  306. location_reset(location,LOC_MMXREGISTER,OS_NO);
  307. r:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
  308. emit_const_reg(A_MOV,S_L,longint($ffffffff),r);
  309. { load operand }
  310. case left.location.loc of
  311. LOC_MMXREGISTER:
  312. location_copy(location,left.location);
  313. LOC_CMMXREGISTER:
  314. begin
  315. location.register:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
  316. emit_reg_reg(A_MOVQ,S_NO,left.location.register,location.register);
  317. end;
  318. LOC_REFERENCE,
  319. LOC_CREFERENCE:
  320. begin
  321. location.register:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
  322. emit_ref_reg(A_MOVQ,S_NO,left.location.reference,location.register);
  323. end;
  324. end;
  325. { load mask }
  326. hreg:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
  327. emit_reg_reg(A_MOVD,S_NO,r,hreg);
  328. { lower 32 bit }
  329. emit_reg_reg(A_PXOR,S_NO,hreg,location.register);
  330. { shift mask }
  331. emit_const_reg(A_PSLLQ,S_B,32,hreg);
  332. { higher 32 bit }
  333. emit_reg_reg(A_PXOR,S_NO,hreg,location.register);
  334. end;
  335. {$endif SUPPORT_MMX}
  336. {*****************************************************************************
  337. TX86MODDIVNODE
  338. *****************************************************************************}
  339. procedure tx86moddivnode.pass_generate_code;
  340. var
  341. hreg1,hreg2,rega,regd:Tregister;
  342. power:longint;
  343. op:Tasmop;
  344. cgsize:TCgSize;
  345. opsize:topsize;
  346. e, sm: aint;
  347. d,m: aword;
  348. m_add: boolean;
  349. s: byte;
  350. begin
  351. secondpass(left);
  352. if codegenerror then
  353. exit;
  354. secondpass(right);
  355. if codegenerror then
  356. exit;
  357. { put numerator in register }
  358. cgsize:=def_cgsize(resultdef);
  359. opsize:=TCGSize2OpSize[cgsize];
  360. if not (cgsize in [OS_32,OS_S32,OS_64,OS_S64]) then
  361. InternalError(2013102702);
  362. rega:=newreg(R_INTREGISTER,RS_EAX,cgsize2subreg(R_INTREGISTER,cgsize));
  363. regd:=newreg(R_INTREGISTER,RS_EDX,cgsize2subreg(R_INTREGISTER,cgsize));
  364. location_reset(location,LOC_REGISTER,cgsize);
  365. hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
  366. hreg1:=left.location.register;
  367. if (nodetype=divn) and (right.nodetype=ordconstn) then
  368. begin
  369. if ispowerof2(int64(tordconstnode(right).value),power) then
  370. begin
  371. { for signed numbers, the numerator must be adjusted before the
  372. shift instruction, but not wih unsigned numbers! Otherwise,
  373. "Cardinal($ffffffff) div 16" overflows! (JM) }
  374. if is_signed(left.resultdef) Then
  375. begin
  376. { use a sequence without jumps, saw this in
  377. comp.compilers (JM) }
  378. { no jumps, but more operations }
  379. hreg2:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
  380. emit_reg_reg(A_MOV,opsize,hreg1,hreg2);
  381. {If the left value is signed, hreg2=$ffffffff, otherwise 0.}
  382. emit_const_reg(A_SAR,opsize,resultdef.size*8-1,hreg2);
  383. {If signed, hreg2=right value-1, otherwise 0.}
  384. { (don't use emit_const_reg, because if value>high(longint)
  385. then it must first be loaded into a register) }
  386. cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_AND,cgsize,tordconstnode(right).value-1,hreg2);
  387. { add to the left value }
  388. emit_reg_reg(A_ADD,opsize,hreg2,hreg1);
  389. { do the shift }
  390. emit_const_reg(A_SAR,opsize,power,hreg1);
  391. end
  392. else
  393. emit_const_reg(A_SHR,opsize,power,hreg1);
  394. location.register:=hreg1;
  395. end
  396. else
  397. begin
  398. if is_signed(left.resultdef) then
  399. begin
  400. e:=tordconstnode(right).value.svalue;
  401. calc_divconst_magic_signed(resultdef.size*8,e,sm,s);
  402. cg.getcpuregister(current_asmdata.CurrAsmList,rega);
  403. emit_const_reg(A_MOV,opsize,sm,rega);
  404. cg.getcpuregister(current_asmdata.CurrAsmList,regd);
  405. emit_reg(A_IMUL,opsize,hreg1);
  406. { only the high half of result is used }
  407. cg.ungetcpuregister(current_asmdata.CurrAsmList,rega);
  408. { add or subtract dividend }
  409. if (e>0) and (sm<0) then
  410. emit_reg_reg(A_ADD,opsize,hreg1,regd)
  411. else if (e<0) and (sm>0) then
  412. emit_reg_reg(A_SUB,opsize,hreg1,regd);
  413. { shift if necessary }
  414. if (s<>0) then
  415. emit_const_reg(A_SAR,opsize,s,regd);
  416. { extract and add the sign bit }
  417. if (e<0) then
  418. emit_reg_reg(A_MOV,opsize,regd,hreg1);
  419. { if e>=0, hreg1 still contains dividend }
  420. emit_const_reg(A_SHR,opsize,left.resultdef.size*8-1,hreg1);
  421. emit_reg_reg(A_ADD,opsize,hreg1,regd);
  422. cg.ungetcpuregister(current_asmdata.CurrAsmList,regd);
  423. location.register:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
  424. cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,regd,location.register)
  425. end
  426. else
  427. begin
  428. d:=tordconstnode(right).value.svalue;
  429. if d>=aword(1) shl (left.resultdef.size*8-1) then
  430. begin
  431. if (cgsize in [OS_64,OS_S64]) then
  432. begin
  433. hreg2:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
  434. emit_const_reg(A_MOV,opsize,aint(d),hreg2);
  435. emit_reg_reg(A_CMP,opsize,hreg2,hreg1);
  436. end
  437. else
  438. emit_const_reg(A_CMP,opsize,aint(d),hreg1);
  439. location.register:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
  440. emit_const_reg(A_MOV,opsize,0,location.register);
  441. emit_const_reg(A_SBB,opsize,-1,location.register);
  442. end
  443. else
  444. begin
  445. calc_divconst_magic_unsigned(resultdef.size*8,d,m,m_add,s);
  446. cg.getcpuregister(current_asmdata.CurrAsmList,rega);
  447. emit_const_reg(A_MOV,opsize,aint(m),rega);
  448. cg.getcpuregister(current_asmdata.CurrAsmList,regd);
  449. emit_reg(A_MUL,opsize,hreg1);
  450. cg.ungetcpuregister(current_asmdata.CurrAsmList,rega);
  451. if m_add then
  452. begin
  453. { addition can overflow, shift first bit considering carry,
  454. then shift remaining bits in regular way. }
  455. emit_reg_reg(A_ADD,opsize,hreg1,regd);
  456. emit_const_reg(A_RCR,opsize,1,regd);
  457. dec(s);
  458. end;
  459. if s<>0 then
  460. emit_const_reg(A_SHR,opsize,aint(s),regd);
  461. cg.ungetcpuregister(current_asmdata.CurrAsmList,regd);
  462. location.register:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
  463. cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,regd,location.register)
  464. end;
  465. end;
  466. end;
  467. end
  468. else
  469. begin
  470. {Bring denominator to a register.}
  471. cg.getcpuregister(current_asmdata.CurrAsmList,rega);
  472. emit_reg_reg(A_MOV,opsize,hreg1,rega);
  473. cg.getcpuregister(current_asmdata.CurrAsmList,regd);
  474. {Sign extension depends on the left type.}
  475. if is_signed(left.resultdef) then
  476. case left.resultdef.size of
  477. {$ifdef x86_64}
  478. 8:
  479. emit_none(A_CQO,S_NO);
  480. {$endif x86_64}
  481. 4:
  482. emit_none(A_CDQ,S_NO);
  483. else
  484. internalerror(2013102701);
  485. end
  486. else
  487. emit_reg_reg(A_XOR,opsize,regd,regd);
  488. { Division depends on the result type }
  489. if is_signed(resultdef) then
  490. op:=A_IDIV
  491. else
  492. op:=A_DIV;
  493. if right.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
  494. emit_ref(op,opsize,right.location.reference)
  495. else if right.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
  496. emit_reg(op,opsize,right.location.register)
  497. else
  498. begin
  499. hreg1:=cg.getintregister(current_asmdata.CurrAsmList,right.location.size);
  500. hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,right.resultdef,right.location,hreg1);
  501. emit_reg(op,opsize,hreg1);
  502. end;
  503. { Copy the result into a new register. Release R/EAX & R/EDX.}
  504. cg.ungetcpuregister(current_asmdata.CurrAsmList,regd);
  505. cg.ungetcpuregister(current_asmdata.CurrAsmList,rega);
  506. location.register:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
  507. if nodetype=divn then
  508. cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,rega,location.register)
  509. else
  510. cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,regd,location.register);
  511. end;
  512. end;
  513. end.