fpc/rtl/embedded/arm/mk20d7.pp

{ Unit created by Michael Ring }
unit MK20D7;
interface
{$goto on}
{$inline on}
{$modeswitch advancedrecords}
  {$PACKRECORDS 2}
type
  TBits_1 = 0..1;
  TBits_2 = 0..3;
  TBits_3 = 0..7;
  TBits_4 = 0..15;
  TBits_5 = 0..31;
  TBits_6 = 0..63;
  TBits_7 = 0..127;
  TBits_8 = 0..255;
  TBits_9 = 0..511;
  TBits_10 = 0..1023;
  TBits_11 = 0..2047;
  TBits_12 = 0..4095;
  TBits_13 = 0..8191;
  TBits_14 = 0..16383;
  TBits_15 = 0..32767;
  TBits_16 = 0..65535;
  TBits_17 = 0..131071;
  TBits_18 = 0..262143;
  TBits_19 = 0..524287;
  TBits_20 = 0..1048575;
  TBits_21 = 0..2097151;
  TBits_22 = 0..4194303;
  TBits_23 = 0..8388607;
  TBits_24 = 0..16777215;
  TBits_25 = 0..33554431;
  TBits_26 = 0..67108863;
  TBits_27 = 0..134217727;
  TBits_28 = 0..268435455;
  TBits_29 = 0..536870911;
  TBits_30 = 0..1073741823;
  TBits_31 = 0..2147483647;
  TBits_32 = 0..4294967295;

  TIRQn_Enum = (
    NonMaskableInt_IRQn  = -14,                        // Non Maskable Interrupt
    HardFault_IRQn       = -13,                        // Cortex Hard Fault Interrupt
    MemoryManagement_IRQn = -12,                       // Memory Management Interrupt
    BusFault_IRQn        = -11,                        // Bus Fault Interrupt
    UsageFault_IRQn      = -10,                        // Usage Fault Interrupt
    SVC_IRQn             = -5,                         // Cortex SV Call Interrupt
    DebugMonitor_IRQn    = -4,                         // Debug Monitor Interrupt
    PendSV_IRQn          = -2,                         // Cortex Pend SV Interrupt
    SysTick_IRQn         = -1,                         // Cortex System Tick Interrupt
    INT_DMA0_IRQn        = 16,
    INT_DMA1_IRQn        = 17,
    INT_DMA2_IRQn        = 18,
    INT_DMA3_IRQn        = 19,
    INT_DMA4_IRQn        = 20,
    INT_DMA5_IRQn        = 21,
    INT_DMA6_IRQn        = 22,
    INT_DMA7_IRQn        = 23,
    INT_DMA8_IRQn        = 24,
    INT_DMA9_IRQn        = 25,
    INT_DMA10_IRQn       = 26,
    INT_DMA11_IRQn       = 27,
    INT_DMA12_IRQn       = 28,
    INT_DMA13_IRQn       = 29,
    INT_DMA14_IRQn       = 30,
    INT_DMA15_IRQn       = 31,
    INT_DMA_Error_IRQn   = 32,
    INT_FTFL_IRQn        = 34,
    INT_LVD_LVW_IRQn     = 36,
    INT_LLW_IRQn         = 37,
    INT_Watchdog_IRQn    = 38,
    INT_I2C0_IRQn        = 40,
    INT_I2C1_IRQn        = 41,
    INT_SPI0_IRQn        = 42,
    INT_SPI1_IRQn        = 43,
    INT_CAN0_ORed_Message_buffer_IRQn = 45,
    INT_CAN0_Bus_Off_IRQn = 46,
    INT_CAN0_Error_IRQn  = 47,
    INT_CAN0_Tx_Warning_IRQn = 48,
    INT_CAN0_Rx_Warning_IRQn = 49,
    INT_CAN0_Wake_Up_IRQn = 50,
    INT_I2S0_Tx_IRQn     = 51,
    INT_I2S0_Rx_IRQn     = 52,
    INT_UART0_LON_IRQn   = 60,
    INT_UART0_RX_TX_IRQn = 61,
    INT_UART0_ERR_IRQn   = 62,
    INT_UART1_RX_TX_IRQn = 63,
    INT_UART1_ERR_IRQn   = 64,
    INT_UART2_RX_TX_IRQn = 65,
    INT_UART2_ERR_IRQn   = 66,
    INT_UART3_RX_TX_IRQn = 67,
    INT_UART3_ERR_IRQn   = 68,
    INT_UART4_RX_TX_IRQn = 69,
    INT_UART4_ERR_IRQn   = 70,
    INT_ADC0_IRQn        = 73,
    INT_ADC1_IRQn        = 74,
    INT_CMP0_IRQn        = 75,
    INT_CMP1_IRQn        = 76,
    INT_CMP2_IRQn        = 77,
    INT_FTM0_IRQn        = 78,
    INT_FTM1_IRQn        = 79,
    INT_FTM2_IRQn        = 80,
    INT_CMT_IRQn         = 81,
    INT_RTC_IRQn         = 82,
    INT_RTC_Seconds_IRQn = 83,
    INT_PIT0_IRQn        = 84,
    INT_PIT1_IRQn        = 85,
    INT_PIT2_IRQn        = 86,
    INT_PIT3_IRQn        = 87,
    INT_PDB0_IRQn        = 88,
    INT_USB0_IRQn        = 89,
    INT_USBDCD_IRQn      = 90,
    INT_Reserved95_IRQn  = 95,
    INT_DAC0_IRQn        = 97,
    INT_TSI0_IRQn        = 99,
    INT_LPTimer_IRQn     = 101,
    INT_PORTA_IRQn       = 103,
    INT_PORTB_IRQn       = 104,
    INT_PORTC_IRQn       = 105,
    INT_PORTD_IRQn       = 106,
    INT_PORTE_IRQn = 107
  );

  // Analog-to-Digital Converter
  TADC0_SC1_bits = bitpacked record
    ADCH                 : TBits_5;                    // [0:4] Input channel select
    DIFF                 : TBits_1;                    // [5:5] Differential mode enable
    AIEN                 : TBits_1;                    // [6:6] Interrupt enable
    COCO                 : TBits_1;                    // [7:7] Conversion complete flag
    RESERVED0            : TBits_24;                   // [8:31] no description available
  end;

  TADC0_SC1_bitbanded = record
    ADCH                 : array[0..4] of longWord;    // [0:4] Input channel select
    DIFF                 : longWord;                   // [5:5] Differential mode enable
    AIEN                 : longWord;                   // [6:6] Interrupt enable
    COCO                 : longWord;                   // [7:7] Conversion complete flag
    RESERVED0            : array[0..23] of longWord;   // [8:31] no description available
  end;

  TADC0_CFG1_bits = bitpacked record
    ADICLK               : TBits_2;                    // [0:1] Input clock select
    MODE                 : TBits_2;                    // [2:3] Conversion mode selection
    ADLSMP               : TBits_1;                    // [4:4] Sample time configuration
    ADIV                 : TBits_2;                    // [5:6] Clock divide select
    ADLPC                : TBits_1;                    // [7:7] Low-power configuration
    RESERVED0            : TBits_24;                   // [8:31] no description available
  end;

  TADC0_CFG1_bitbanded = record
    ADICLK               : array[0..1] of longWord;    // [0:1] Input clock select
    MODE                 : array[0..1] of longWord;    // [2:3] Conversion mode selection
    ADLSMP               : longWord;                   // [4:4] Sample time configuration
    ADIV                 : array[0..1] of longWord;    // [5:6] Clock divide select
    ADLPC                : longWord;                   // [7:7] Low-power configuration
    RESERVED0            : array[0..23] of longWord;   // [8:31] no description available
  end;

  TADC0_CFG2_bits = bitpacked record
    ADLSTS               : TBits_2;                    // [0:1] Long sample time select
    ADHSC                : TBits_1;                    // [2:2] High speed configuration
    ADACKEN              : TBits_1;                    // [3:3] Asynchronous clock output enable
    MUXSEL               : TBits_1;                    // [4:4] ADC Mux select
    RESERVED0            : TBits_3;                    // [5:7] no description available
    RESERVED1            : TBits_24;                   // [8:31] no description available
  end;

  TADC0_CFG2_bitbanded = record
    ADLSTS               : array[0..1] of longWord;    // [0:1] Long sample time select
    ADHSC                : longWord;                   // [2:2] High speed configuration
    ADACKEN              : longWord;                   // [3:3] Asynchronous clock output enable
    MUXSEL               : longWord;                   // [4:4] ADC Mux select
    RESERVED0            : array[0..2] of longWord;    // [5:7] no description available
    RESERVED1            : array[0..23] of longWord;   // [8:31] no description available
  end;

  TADC0_R_bits = bitpacked record
    D                    : TBits_16;                   // [0:15] Data result
    RESERVED0            : TBits_16;                   // [16:31] no description available
  end;

  TADC0_R_bitbanded = record
    D                    : array[0..15] of longWord;   // [0:15] Data result
    RESERVED0            : array[0..15] of longWord;   // [16:31] no description available
  end;

  TADC0_CV_bits = bitpacked record
    CV                   : TBits_16;                   // [0:15] Compare value
    RESERVED0            : TBits_16;                   // [16:31] no description available
  end;

  TADC0_CV_bitbanded = record
    CV                   : array[0..15] of longWord;   // [0:15] Compare value
    RESERVED0            : array[0..15] of longWord;   // [16:31] no description available
  end;

  TADC0_SC2_bits = bitpacked record
    REFSEL               : TBits_2;                    // [0:1] Voltage reference selection
    DMAEN                : TBits_1;                    // [2:2] DMA enable
    ACREN                : TBits_1;                    // [3:3] Compare function range enable
    ACFGT                : TBits_1;                    // [4:4] Compare function greater than enable
    ACFE                 : TBits_1;                    // [5:5] Compare function enable
    ADTRG                : TBits_1;                    // [6:6] Conversion trigger select
    ADACT                : TBits_1;                    // [7:7] Conversion active
    RESERVED0            : TBits_24;                   // [8:31] no description available
  end;

  TADC0_SC2_bitbanded = record
    REFSEL               : array[0..1] of longWord;    // [0:1] Voltage reference selection
    DMAEN                : longWord;                   // [2:2] DMA enable
    ACREN                : longWord;                   // [3:3] Compare function range enable
    ACFGT                : longWord;                   // [4:4] Compare function greater than enable
    ACFE                 : longWord;                   // [5:5] Compare function enable
    ADTRG                : longWord;                   // [6:6] Conversion trigger select
    ADACT                : longWord;                   // [7:7] Conversion active
    RESERVED0            : array[0..23] of longWord;   // [8:31] no description available
  end;

  TADC0_SC3_bits = bitpacked record
    AVGS                 : TBits_2;                    // [0:1] Hardware average select
    AVGE                 : TBits_1;                    // [2:2] Hardware average enable
    ADCO                 : TBits_1;                    // [3:3] Continuous conversion enable
    RESERVED0            : TBits_2;                    // [4:5] no description available
    CALF                 : TBits_1;                    // [6:6] Calibration failed flag
    CAL                  : TBits_1;                    // [7:7] Calibration
    RESERVED1            : TBits_24;                   // [8:31] no description available
  end;

  TADC0_SC3_bitbanded = record
    AVGS                 : array[0..1] of longWord;    // [0:1] Hardware average select
    AVGE                 : longWord;                   // [2:2] Hardware average enable
    ADCO                 : longWord;                   // [3:3] Continuous conversion enable
    RESERVED0            : array[0..1] of longWord;    // [4:5] no description available
    CALF                 : longWord;                   // [6:6] Calibration failed flag
    CAL                  : longWord;                   // [7:7] Calibration
    RESERVED1            : array[0..23] of longWord;   // [8:31] no description available
  end;

  TADC0_OFS_bits = bitpacked record
    OFS                  : TBits_16;                   // [0:15] Offset error correction value
    RESERVED0            : TBits_16;                   // [16:31] no description available
  end;

  TADC0_OFS_bitbanded = record
    OFS                  : array[0..15] of longWord;   // [0:15] Offset error correction value
    RESERVED0            : array[0..15] of longWord;   // [16:31] no description available
  end;

  TADC0_PG_bits = bitpacked record
    PG                   : TBits_16;                   // [0:15] Plus-side gain
    RESERVED0            : TBits_16;                   // [16:31] no description available
  end;

  TADC0_PG_bitbanded = record
    PG                   : array[0..15] of longWord;   // [0:15] Plus-side gain
    RESERVED0            : array[0..15] of longWord;   // [16:31] no description available
  end;

  TADC0_MG_bits = bitpacked record
    MG                   : TBits_16;                   // [0:15] Minus-side gain
    RESERVED0            : TBits_16;                   // [16:31] no description available
  end;

  TADC0_MG_bitbanded = record
    MG                   : array[0..15] of longWord;   // [0:15] Minus-side gain
    RESERVED0            : array[0..15] of longWord;   // [16:31] no description available
  end;

  TADC0_CLPD_bits = bitpacked record
    CLPD                 : TBits_6;                    // [0:5] no description available
    RESERVED0            : TBits_26;                   // [6:31] no description available
  end;

  TADC0_CLPD_bitbanded = record
    CLPD                 : array[0..5] of longWord;    // [0:5] no description available
    RESERVED0            : array[0..25] of longWord;   // [6:31] no description available
  end;

  TADC0_CLPS_bits = bitpacked record
    CLPS                 : TBits_6;                    // [0:5] no description available
    RESERVED0            : TBits_26;                   // [6:31] no description available
  end;

  TADC0_CLPS_bitbanded = record
    CLPS                 : array[0..5] of longWord;    // [0:5] no description available
    RESERVED0            : array[0..25] of longWord;   // [6:31] no description available
  end;

  TADC0_CLP4_bits = bitpacked record
    CLP4                 : TBits_10;                   // [0:9] no description available
    RESERVED0            : TBits_22;                   // [10:31] no description available
  end;

  TADC0_CLP4_bitbanded = record
    CLP4                 : array[0..9] of longWord;    // [0:9] no description available
    RESERVED0            : array[0..21] of longWord;   // [10:31] no description available
  end;

  TADC0_CLP3_bits = bitpacked record
    CLP3                 : TBits_9;                    // [0:8] no description available
    RESERVED0            : TBits_23;                   // [9:31] no description available
  end;

  TADC0_CLP3_bitbanded = record
    CLP3                 : array[0..8] of longWord;    // [0:8] no description available
    RESERVED0            : array[0..22] of longWord;   // [9:31] no description available
  end;

  TADC0_CLP2_bits = bitpacked record
    CLP2                 : TBits_8;                    // [0:7] no description available
    RESERVED0            : TBits_24;                   // [8:31] no description available
  end;

  TADC0_CLP2_bitbanded = record
    CLP2                 : array[0..7] of longWord;    // [0:7] no description available
    RESERVED0            : array[0..23] of longWord;   // [8:31] no description available
  end;

  TADC0_CLP1_bits = bitpacked record
    CLP1                 : TBits_7;                    // [0:6] no description available
    RESERVED0            : TBits_25;                   // [7:31] no description available
  end;

  TADC0_CLP1_bitbanded = record
    CLP1                 : array[0..6] of longWord;    // [0:6] no description available
    RESERVED0            : array[0..24] of longWord;   // [7:31] no description available
  end;

  TADC0_CLP0_bits = bitpacked record
    CLP0                 : TBits_6;                    // [0:5] no description available
    RESERVED0            : TBits_26;                   // [6:31] no description available
  end;

  TADC0_CLP0_bitbanded = record
    CLP0                 : array[0..5] of longWord;    // [0:5] no description available
    RESERVED0            : array[0..25] of longWord;   // [6:31] no description available
  end;

  TADC0_PGA_bits = bitpacked record
    RESERVED0            : TBits_16;                   // [0:15] no description available
    PGAG                 : TBits_4;                    // [16:19] PGA gain setting
    PGALPb               : TBits_1;                    // [20:20] PGA low-power mode control
    RESERVED1            : TBits_1;                    // [21:21] no description available
    RESERVED2            : TBits_1;                    // [22:22] no description available
    PGAEN                : TBits_1;                    // [23:23] PGA enable
    RESERVED3            : TBits_8;                    // [24:31] no description available
  end;

  TADC0_PGA_bitbanded = record
    RESERVED0            : array[0..15] of longWord;   // [0:15] no description available
    PGAG                 : array[0..3] of longWord;    // [16:19] PGA gain setting
    PGALPb               : longWord;                   // [20:20] PGA low-power mode control
    RESERVED1            : longWord;                   // [21:21] no description available
    RESERVED2            : longWord;                   // [22:22] no description available
    PGAEN                : longWord;                   // [23:23] PGA enable
    RESERVED3            : array[0..7] of longWord;    // [24:31] no description available
  end;

  TADC0_CLMD_bits = bitpacked record
    CLMD                 : TBits_6;                    // [0:5] no description available
    RESERVED0            : TBits_26;                   // [6:31] no description available
  end;

  TADC0_CLMD_bitbanded = record
    CLMD                 : array[0..5] of longWord;    // [0:5] no description available
    RESERVED0            : array[0..25] of longWord;   // [6:31] no description available
  end;

  TADC0_CLMS_bits = bitpacked record
    CLMS                 : TBits_6;                    // [0:5] no description available
    RESERVED0            : TBits_26;                   // [6:31] no description available
  end;

  TADC0_CLMS_bitbanded = record
    CLMS                 : array[0..5] of longWord;    // [0:5] no description available
    RESERVED0            : array[0..25] of longWord;   // [6:31] no description available
  end;

  TADC0_CLM4_bits = bitpacked record
    CLM4                 : TBits_10;                   // [0:9] no description available
    RESERVED0            : TBits_22;                   // [10:31] no description available
  end;

  TADC0_CLM4_bitbanded = record
    CLM4                 : array[0..9] of longWord;    // [0:9] no description available
    RESERVED0            : array[0..21] of longWord;   // [10:31] no description available
  end;

  TADC0_CLM3_bits = bitpacked record
    CLM3                 : TBits_9;                    // [0:8] no description available
    RESERVED0            : TBits_23;                   // [9:31] no description available
  end;

  TADC0_CLM3_bitbanded = record
    CLM3                 : array[0..8] of longWord;    // [0:8] no description available
    RESERVED0            : array[0..22] of longWord;   // [9:31] no description available
  end;

  TADC0_CLM2_bits = bitpacked record
    CLM2                 : TBits_8;                    // [0:7] no description available
    RESERVED0            : TBits_24;                   // [8:31] no description available
  end;

  TADC0_CLM2_bitbanded = record
    CLM2                 : array[0..7] of longWord;    // [0:7] no description available
    RESERVED0            : array[0..23] of longWord;   // [8:31] no description available
  end;

  TADC0_CLM1_bits = bitpacked record
    CLM1                 : TBits_7;                    // [0:6] no description available
    RESERVED0            : TBits_25;                   // [7:31] no description available
  end;

  TADC0_CLM1_bitbanded = record
    CLM1                 : array[0..6] of longWord;    // [0:6] no description available
    RESERVED0            : array[0..24] of longWord;   // [7:31] no description available
  end;

  TADC0_CLM0_bits = bitpacked record
    CLM0                 : TBits_6;                    // [0:5] no description available
    RESERVED0            : TBits_26;                   // [6:31] no description available
  end;

  TADC0_CLM0_bitbanded = record
    CLM0                 : array[0..5] of longWord;    // [0:5] no description available
    RESERVED0            : array[0..25] of longWord;   // [6:31] no description available
  end;

  TADC0_Registers = record
    case boolean of false: (
    SC1A                 : longWord;                   // 0x00 ADC status and control registers 1
    SC1B                 : longWord;                   // 0x04 ADC status and control registers 1
    CFG1                 : longWord;                   // 0x08 ADC configuration register 1
    CFG2                 : longWord;                   // 0x0C Configuration register 2
    RA                   : longWord;                   // 0x10 ADC data result register
    RB                   : longWord;                   // 0x14 ADC data result register
    CV1                  : longWord;                   // 0x18 Compare value registers
    CV2                  : longWord;                   // 0x1C Compare value registers
    SC2                  : longWord;                   // 0x20 Status and control register 2
    SC3                  : longWord;                   // 0x24 Status and control register 3
    OFS                  : longWord;                   // 0x28 ADC offset correction register
    PG                   : longWord;                   // 0x2C ADC plus-side gain register
    MG                   : longWord;                   // 0x30 ADC minus-side gain register
    CLPD                 : longWord;                   // 0x34 ADC plus-side general calibration value register
    CLPS                 : longWord;                   // 0x38 ADC plus-side general calibration value register
    CLP4                 : longWord;                   // 0x3C ADC plus-side general calibration value register
    CLP3                 : longWord;                   // 0x40 ADC plus-side general calibration value register
    CLP2                 : longWord;                   // 0x44 ADC plus-side general calibration value register
    CLP1                 : longWord;                   // 0x48 ADC plus-side general calibration value register
    CLP0                 : longWord;                   // 0x4C ADC plus-side general calibration value register
    PGA                  : longWord;                   // 0x50 ADC PGA register
    CLMD                 : longWord;                   // 0x54 ADC minus-side general calibration value register
    CLMS                 : longWord;                   // 0x58 ADC minus-side general calibration value register
    CLM4                 : longWord;                   // 0x5C ADC minus-side general calibration value register
    CLM3                 : longWord;                   // 0x60 ADC minus-side general calibration value register
    CLM2                 : longWord;                   // 0x64 ADC minus-side general calibration value register
    CLM1                 : longWord;                   // 0x68 ADC minus-side general calibration value register
    CLM0                 : longWord;                   // 0x6C ADC minus-side general calibration value register
  );
  true : (
  SC1A_bits              : longWord;                   // 0x00 ADC status and control registers 1
  SC1B_bits              : longWord;                   // 0x04 ADC status and control registers 1
  CFG1_bits              : TADC0_CFG1_bits;            // 0x0C ADC configuration register 1
  CFG2_bits              : TADC0_CFG2_bits;            // 0x10 Configuration register 2
  RA_bits                : longWord;                   // 0x10 ADC data result register
  RB_bits                : longWord;                   // 0x14 ADC data result register
  CV1_bits               : TADC0_CV_bits;              // 0x1C Compare value registers
  CV2_bits               : TADC0_CV_bits;              // 0x20 Compare value registers
  SC2_bits               : TADC0_SC2_bits;             // 0x24 Status and control register 2
  SC3_bits               : TADC0_SC3_bits;             // 0x28 Status and control register 3
  OFS_bits               : TADC0_OFS_bits;             // 0x2C ADC offset correction register
  PG_bits                : TADC0_PG_bits;              // 0x30 ADC plus-side gain register
  MG_bits                : TADC0_MG_bits;              // 0x34 ADC minus-side gain register
  CLPD_bits              : TADC0_CLPD_bits;            // 0x38 ADC plus-side general calibration value register
  CLPS_bits              : TADC0_CLPS_bits;            // 0x3C ADC plus-side general calibration value register
  CLP4_bits              : TADC0_CLP4_bits;            // 0x40 ADC plus-side general calibration value register
  CLP3_bits              : TADC0_CLP3_bits;            // 0x44 ADC plus-side general calibration value register
  CLP2_bits              : TADC0_CLP2_bits;            // 0x48 ADC plus-side general calibration value register
  CLP1_bits              : TADC0_CLP1_bits;            // 0x4C ADC plus-side general calibration value register
  CLP0_bits              : TADC0_CLP0_bits;            // 0x50 ADC plus-side general calibration value register
  PGA_bits               : TADC0_PGA_bits;             // 0x54 ADC PGA register
  CLMD_bits              : TADC0_CLMD_bits;            // 0x58 ADC minus-side general calibration value register
  CLMS_bits              : TADC0_CLMS_bits;            // 0x5C ADC minus-side general calibration value register
  CLM4_bits              : TADC0_CLM4_bits;            // 0x60 ADC minus-side general calibration value register
  CLM3_bits              : TADC0_CLM3_bits;            // 0x64 ADC minus-side general calibration value register
  CLM2_bits              : TADC0_CLM2_bits;            // 0x68 ADC minus-side general calibration value register
  CLM1_bits              : TADC0_CLM1_bits;            // 0x6C ADC minus-side general calibration value register
  CLM0_bits              : TADC0_CLM0_bits;            // 0x70 ADC minus-side general calibration value register
);
end;

TADC0Registers_bitbanded = record
  SC1A_bitbanded         : longWord;                   // 0x00 ADC status and control registers 1
  SC1B_bitbanded         : longWord;                   // 0x04 ADC status and control registers 1
  CFG1                   : TADC0_CFG1_bitbanded;       // 0x0C ADC configuration register 1
  CFG2                   : TADC0_CFG2_bitbanded;       // 0x10 Configuration register 2
  RA_bitbanded           : longWord;                   // 0x10 ADC data result register
  RB_bitbanded           : longWord;                   // 0x14 ADC data result register
  CV1                    : TADC0_CV_bitbanded;         // 0x1C Compare value registers
  CV2                    : TADC0_CV_bitbanded;         // 0x20 Compare value registers
  SC2                    : TADC0_SC2_bitbanded;        // 0x24 Status and control register 2
  SC3                    : TADC0_SC3_bitbanded;        // 0x28 Status and control register 3
  OFS                    : TADC0_OFS_bitbanded;        // 0x2C ADC offset correction register
  PG                     : TADC0_PG_bitbanded;         // 0x30 ADC plus-side gain register
  MG                     : TADC0_MG_bitbanded;         // 0x34 ADC minus-side gain register
  CLPD                   : TADC0_CLPD_bitbanded;       // 0x38 ADC plus-side general calibration value register
  CLPS                   : TADC0_CLPS_bitbanded;       // 0x3C ADC plus-side general calibration value register
  CLP4                   : TADC0_CLP4_bitbanded;       // 0x40 ADC plus-side general calibration value register
  CLP3                   : TADC0_CLP3_bitbanded;       // 0x44 ADC plus-side general calibration value register
  CLP2                   : TADC0_CLP2_bitbanded;       // 0x48 ADC plus-side general calibration value register
  CLP1                   : TADC0_CLP1_bitbanded;       // 0x4C ADC plus-side general calibration value register
  CLP0                   : TADC0_CLP0_bitbanded;       // 0x50 ADC plus-side general calibration value register
  PGA                    : TADC0_PGA_bitbanded;        // 0x54 ADC PGA register
  CLMD                   : TADC0_CLMD_bitbanded;       // 0x58 ADC minus-side general calibration value register
  CLMS                   : TADC0_CLMS_bitbanded;       // 0x5C ADC minus-side general calibration value register
  CLM4                   : TADC0_CLM4_bitbanded;       // 0x60 ADC minus-side general calibration value register
  CLM3                   : TADC0_CLM3_bitbanded;       // 0x64 ADC minus-side general calibration value register
  CLM2                   : TADC0_CLM2_bitbanded;       // 0x68 ADC minus-side general calibration value register
  CLM1                   : TADC0_CLM1_bitbanded;       // 0x6C ADC minus-side general calibration value register
  CLM0                   : TADC0_CLM0_bitbanded;       // 0x70 ADC minus-side general calibration value register
end;

// Analog-to-Digital Converter
TADC1_SC1_bits = bitpacked record
  ADCH                   : TBits_5;                    // [0:4] Input channel select
  DIFF                   : TBits_1;                    // [5:5] Differential mode enable
  AIEN                   : TBits_1;                    // [6:6] Interrupt enable
  COCO                   : TBits_1;                    // [7:7] Conversion complete flag
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TADC1_SC1_bitbanded = record
  ADCH                   : array[0..4] of longWord;    // [0:4] Input channel select
  DIFF                   : longWord;                   // [5:5] Differential mode enable
  AIEN                   : longWord;                   // [6:6] Interrupt enable
  COCO                   : longWord;                   // [7:7] Conversion complete flag
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TADC1_CFG1_bits = bitpacked record
  ADICLK                 : TBits_2;                    // [0:1] Input clock select
  MODE                   : TBits_2;                    // [2:3] Conversion mode selection
  ADLSMP                 : TBits_1;                    // [4:4] Sample time configuration
  ADIV                   : TBits_2;                    // [5:6] Clock divide select
  ADLPC                  : TBits_1;                    // [7:7] Low-power configuration
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TADC1_CFG1_bitbanded = record
  ADICLK                 : array[0..1] of longWord;    // [0:1] Input clock select
  MODE                   : array[0..1] of longWord;    // [2:3] Conversion mode selection
  ADLSMP                 : longWord;                   // [4:4] Sample time configuration
  ADIV                   : array[0..1] of longWord;    // [5:6] Clock divide select
  ADLPC                  : longWord;                   // [7:7] Low-power configuration
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TADC1_CFG2_bits = bitpacked record
  ADLSTS                 : TBits_2;                    // [0:1] Long sample time select
  ADHSC                  : TBits_1;                    // [2:2] High speed configuration
  ADACKEN                : TBits_1;                    // [3:3] Asynchronous clock output enable
  MUXSEL                 : TBits_1;                    // [4:4] ADC Mux select
  RESERVED0              : TBits_3;                    // [5:7] no description available
  RESERVED1              : TBits_24;                   // [8:31] no description available
end;

TADC1_CFG2_bitbanded = record
  ADLSTS                 : array[0..1] of longWord;    // [0:1] Long sample time select
  ADHSC                  : longWord;                   // [2:2] High speed configuration
  ADACKEN                : longWord;                   // [3:3] Asynchronous clock output enable
  MUXSEL                 : longWord;                   // [4:4] ADC Mux select
  RESERVED0              : array[0..2] of longWord;    // [5:7] no description available
  RESERVED1              : array[0..23] of longWord;   // [8:31] no description available
end;

TADC1_R_bits = bitpacked record
  D                      : TBits_16;                   // [0:15] Data result
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TADC1_R_bitbanded = record
  D                      : array[0..15] of longWord;   // [0:15] Data result
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TADC1_CV_bits = bitpacked record
  CV                     : TBits_16;                   // [0:15] Compare value
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TADC1_CV_bitbanded = record
  CV                     : array[0..15] of longWord;   // [0:15] Compare value
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TADC1_SC2_bits = bitpacked record
  REFSEL                 : TBits_2;                    // [0:1] Voltage reference selection
  DMAEN                  : TBits_1;                    // [2:2] DMA enable
  ACREN                  : TBits_1;                    // [3:3] Compare function range enable
  ACFGT                  : TBits_1;                    // [4:4] Compare function greater than enable
  ACFE                   : TBits_1;                    // [5:5] Compare function enable
  ADTRG                  : TBits_1;                    // [6:6] Conversion trigger select
  ADACT                  : TBits_1;                    // [7:7] Conversion active
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TADC1_SC2_bitbanded = record
  REFSEL                 : array[0..1] of longWord;    // [0:1] Voltage reference selection
  DMAEN                  : longWord;                   // [2:2] DMA enable
  ACREN                  : longWord;                   // [3:3] Compare function range enable
  ACFGT                  : longWord;                   // [4:4] Compare function greater than enable
  ACFE                   : longWord;                   // [5:5] Compare function enable
  ADTRG                  : longWord;                   // [6:6] Conversion trigger select
  ADACT                  : longWord;                   // [7:7] Conversion active
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TADC1_SC3_bits = bitpacked record
  AVGS                   : TBits_2;                    // [0:1] Hardware average select
  AVGE                   : TBits_1;                    // [2:2] Hardware average enable
  ADCO                   : TBits_1;                    // [3:3] Continuous conversion enable
  RESERVED0              : TBits_2;                    // [4:5] no description available
  CALF                   : TBits_1;                    // [6:6] Calibration failed flag
  CAL                    : TBits_1;                    // [7:7] Calibration
  RESERVED1              : TBits_24;                   // [8:31] no description available
end;

TADC1_SC3_bitbanded = record
  AVGS                   : array[0..1] of longWord;    // [0:1] Hardware average select
  AVGE                   : longWord;                   // [2:2] Hardware average enable
  ADCO                   : longWord;                   // [3:3] Continuous conversion enable
  RESERVED0              : array[0..1] of longWord;    // [4:5] no description available
  CALF                   : longWord;                   // [6:6] Calibration failed flag
  CAL                    : longWord;                   // [7:7] Calibration
  RESERVED1              : array[0..23] of longWord;   // [8:31] no description available
end;

TADC1_OFS_bits = bitpacked record
  OFS                    : TBits_16;                   // [0:15] Offset error correction value
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TADC1_OFS_bitbanded = record
  OFS                    : array[0..15] of longWord;   // [0:15] Offset error correction value
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TADC1_PG_bits = bitpacked record
  PG                     : TBits_16;                   // [0:15] Plus-side gain
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TADC1_PG_bitbanded = record
  PG                     : array[0..15] of longWord;   // [0:15] Plus-side gain
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TADC1_MG_bits = bitpacked record
  MG                     : TBits_16;                   // [0:15] Minus-side gain
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TADC1_MG_bitbanded = record
  MG                     : array[0..15] of longWord;   // [0:15] Minus-side gain
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TADC1_CLPD_bits = bitpacked record
  CLPD                   : TBits_6;                    // [0:5] no description available
  RESERVED0              : TBits_26;                   // [6:31] no description available
end;

TADC1_CLPD_bitbanded = record
  CLPD                   : array[0..5] of longWord;    // [0:5] no description available
  RESERVED0              : array[0..25] of longWord;   // [6:31] no description available
end;

TADC1_CLPS_bits = bitpacked record
  CLPS                   : TBits_6;                    // [0:5] no description available
  RESERVED0              : TBits_26;                   // [6:31] no description available
end;

TADC1_CLPS_bitbanded = record
  CLPS                   : array[0..5] of longWord;    // [0:5] no description available
  RESERVED0              : array[0..25] of longWord;   // [6:31] no description available
end;

TADC1_CLP4_bits = bitpacked record
  CLP4                   : TBits_10;                   // [0:9] no description available
  RESERVED0              : TBits_22;                   // [10:31] no description available
end;

TADC1_CLP4_bitbanded = record
  CLP4                   : array[0..9] of longWord;    // [0:9] no description available
  RESERVED0              : array[0..21] of longWord;   // [10:31] no description available
end;

TADC1_CLP3_bits = bitpacked record
  CLP3                   : TBits_9;                    // [0:8] no description available
  RESERVED0              : TBits_23;                   // [9:31] no description available
end;

TADC1_CLP3_bitbanded = record
  CLP3                   : array[0..8] of longWord;    // [0:8] no description available
  RESERVED0              : array[0..22] of longWord;   // [9:31] no description available
end;

TADC1_CLP2_bits = bitpacked record
  CLP2                   : TBits_8;                    // [0:7] no description available
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TADC1_CLP2_bitbanded = record
  CLP2                   : array[0..7] of longWord;    // [0:7] no description available
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TADC1_CLP1_bits = bitpacked record
  CLP1                   : TBits_7;                    // [0:6] no description available
  RESERVED0              : TBits_25;                   // [7:31] no description available
end;

TADC1_CLP1_bitbanded = record
  CLP1                   : array[0..6] of longWord;    // [0:6] no description available
  RESERVED0              : array[0..24] of longWord;   // [7:31] no description available
end;

TADC1_CLP0_bits = bitpacked record
  CLP0                   : TBits_6;                    // [0:5] no description available
  RESERVED0              : TBits_26;                   // [6:31] no description available
end;

TADC1_CLP0_bitbanded = record
  CLP0                   : array[0..5] of longWord;    // [0:5] no description available
  RESERVED0              : array[0..25] of longWord;   // [6:31] no description available
end;

TADC1_PGA_bits = bitpacked record
  RESERVED0              : TBits_16;                   // [0:15] no description available
  PGAG                   : TBits_4;                    // [16:19] PGA gain setting
  PGALPb                 : TBits_1;                    // [20:20] PGA low-power mode control
  RESERVED1              : TBits_1;                    // [21:21] no description available
  RESERVED2              : TBits_1;                    // [22:22] no description available
  PGAEN                  : TBits_1;                    // [23:23] PGA enable
  RESERVED3              : TBits_8;                    // [24:31] no description available
end;

TADC1_PGA_bitbanded = record
  RESERVED0              : array[0..15] of longWord;   // [0:15] no description available
  PGAG                   : array[0..3] of longWord;    // [16:19] PGA gain setting
  PGALPb                 : longWord;                   // [20:20] PGA low-power mode control
  RESERVED1              : longWord;                   // [21:21] no description available
  RESERVED2              : longWord;                   // [22:22] no description available
  PGAEN                  : longWord;                   // [23:23] PGA enable
  RESERVED3              : array[0..7] of longWord;    // [24:31] no description available
end;

TADC1_CLMD_bits = bitpacked record
  CLMD                   : TBits_6;                    // [0:5] no description available
  RESERVED0              : TBits_26;                   // [6:31] no description available
end;

TADC1_CLMD_bitbanded = record
  CLMD                   : array[0..5] of longWord;    // [0:5] no description available
  RESERVED0              : array[0..25] of longWord;   // [6:31] no description available
end;

TADC1_CLMS_bits = bitpacked record
  CLMS                   : TBits_6;                    // [0:5] no description available
  RESERVED0              : TBits_26;                   // [6:31] no description available
end;

TADC1_CLMS_bitbanded = record
  CLMS                   : array[0..5] of longWord;    // [0:5] no description available
  RESERVED0              : array[0..25] of longWord;   // [6:31] no description available
end;

TADC1_CLM4_bits = bitpacked record
  CLM4                   : TBits_10;                   // [0:9] no description available
  RESERVED0              : TBits_22;                   // [10:31] no description available
end;

TADC1_CLM4_bitbanded = record
  CLM4                   : array[0..9] of longWord;    // [0:9] no description available
  RESERVED0              : array[0..21] of longWord;   // [10:31] no description available
end;

TADC1_CLM3_bits = bitpacked record
  CLM3                   : TBits_9;                    // [0:8] no description available
  RESERVED0              : TBits_23;                   // [9:31] no description available
end;

TADC1_CLM3_bitbanded = record
  CLM3                   : array[0..8] of longWord;    // [0:8] no description available
  RESERVED0              : array[0..22] of longWord;   // [9:31] no description available
end;

TADC1_CLM2_bits = bitpacked record
  CLM2                   : TBits_8;                    // [0:7] no description available
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TADC1_CLM2_bitbanded = record
  CLM2                   : array[0..7] of longWord;    // [0:7] no description available
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TADC1_CLM1_bits = bitpacked record
  CLM1                   : TBits_7;                    // [0:6] no description available
  RESERVED0              : TBits_25;                   // [7:31] no description available
end;

TADC1_CLM1_bitbanded = record
  CLM1                   : array[0..6] of longWord;    // [0:6] no description available
  RESERVED0              : array[0..24] of longWord;   // [7:31] no description available
end;

TADC1_CLM0_bits = bitpacked record
  CLM0                   : TBits_6;                    // [0:5] no description available
  RESERVED0              : TBits_26;                   // [6:31] no description available
end;

TADC1_CLM0_bitbanded = record
  CLM0                   : array[0..5] of longWord;    // [0:5] no description available
  RESERVED0              : array[0..25] of longWord;   // [6:31] no description available
end;

TADC1_Registers = record
  case boolean of false: (
  SC1A                   : longWord;                   // 0x00 ADC status and control registers 1
  SC1B                   : longWord;                   // 0x04 ADC status and control registers 1
  CFG1                   : longWord;                   // 0x08 ADC configuration register 1
  CFG2                   : longWord;                   // 0x0C Configuration register 2
  RA                     : longWord;                   // 0x10 ADC data result register
  RB                     : longWord;                   // 0x14 ADC data result register
  CV1                    : longWord;                   // 0x18 Compare value registers
  CV2                    : longWord;                   // 0x1C Compare value registers
  SC2                    : longWord;                   // 0x20 Status and control register 2
  SC3                    : longWord;                   // 0x24 Status and control register 3
  OFS                    : longWord;                   // 0x28 ADC offset correction register
  PG                     : longWord;                   // 0x2C ADC plus-side gain register
  MG                     : longWord;                   // 0x30 ADC minus-side gain register
  CLPD                   : longWord;                   // 0x34 ADC plus-side general calibration value register
  CLPS                   : longWord;                   // 0x38 ADC plus-side general calibration value register
  CLP4                   : longWord;                   // 0x3C ADC plus-side general calibration value register
  CLP3                   : longWord;                   // 0x40 ADC plus-side general calibration value register
  CLP2                   : longWord;                   // 0x44 ADC plus-side general calibration value register
  CLP1                   : longWord;                   // 0x48 ADC plus-side general calibration value register
  CLP0                   : longWord;                   // 0x4C ADC plus-side general calibration value register
  PGA                    : longWord;                   // 0x50 ADC PGA register
  CLMD                   : longWord;                   // 0x54 ADC minus-side general calibration value register
  CLMS                   : longWord;                   // 0x58 ADC minus-side general calibration value register
  CLM4                   : longWord;                   // 0x5C ADC minus-side general calibration value register
  CLM3                   : longWord;                   // 0x60 ADC minus-side general calibration value register
  CLM2                   : longWord;                   // 0x64 ADC minus-side general calibration value register
  CLM1                   : longWord;                   // 0x68 ADC minus-side general calibration value register
  CLM0                   : longWord;                   // 0x6C ADC minus-side general calibration value register
);
true : (
SC1A_bits                : longWord;                   // 0x00 ADC status and control registers 1
SC1B_bits                : longWord;                   // 0x04 ADC status and control registers 1
CFG1_bits                : TADC1_CFG1_bits;            // 0x0C ADC configuration register 1
CFG2_bits                : TADC1_CFG2_bits;            // 0x10 Configuration register 2
RA_bits                  : longWord;                   // 0x10 ADC data result register
RB_bits                  : longWord;                   // 0x14 ADC data result register
CV1_bits                 : TADC1_CV_bits;              // 0x1C Compare value registers
CV2_bits                 : TADC1_CV_bits;              // 0x20 Compare value registers
SC2_bits                 : TADC1_SC2_bits;             // 0x24 Status and control register 2
SC3_bits                 : TADC1_SC3_bits;             // 0x28 Status and control register 3
OFS_bits                 : TADC1_OFS_bits;             // 0x2C ADC offset correction register
PG_bits                  : TADC1_PG_bits;              // 0x30 ADC plus-side gain register
MG_bits                  : TADC1_MG_bits;              // 0x34 ADC minus-side gain register
CLPD_bits                : TADC1_CLPD_bits;            // 0x38 ADC plus-side general calibration value register
CLPS_bits                : TADC1_CLPS_bits;            // 0x3C ADC plus-side general calibration value register
CLP4_bits                : TADC1_CLP4_bits;            // 0x40 ADC plus-side general calibration value register
CLP3_bits                : TADC1_CLP3_bits;            // 0x44 ADC plus-side general calibration value register
CLP2_bits                : TADC1_CLP2_bits;            // 0x48 ADC plus-side general calibration value register
CLP1_bits                : TADC1_CLP1_bits;            // 0x4C ADC plus-side general calibration value register
CLP0_bits                : TADC1_CLP0_bits;            // 0x50 ADC plus-side general calibration value register
PGA_bits                 : TADC1_PGA_bits;             // 0x54 ADC PGA register
CLMD_bits                : TADC1_CLMD_bits;            // 0x58 ADC minus-side general calibration value register
CLMS_bits                : TADC1_CLMS_bits;            // 0x5C ADC minus-side general calibration value register
CLM4_bits                : TADC1_CLM4_bits;            // 0x60 ADC minus-side general calibration value register
CLM3_bits                : TADC1_CLM3_bits;            // 0x64 ADC minus-side general calibration value register
CLM2_bits                : TADC1_CLM2_bits;            // 0x68 ADC minus-side general calibration value register
CLM1_bits                : TADC1_CLM1_bits;            // 0x6C ADC minus-side general calibration value register
CLM0_bits                : TADC1_CLM0_bits;            // 0x70 ADC minus-side general calibration value register
);
end;

TADC1Registers_bitbanded = record
  SC1A_bitbanded         : longWord;                   // 0x00 ADC status and control registers 1
  SC1B_bitbanded         : longWord;                   // 0x04 ADC status and control registers 1
  CFG1                   : TADC1_CFG1_bitbanded;       // 0x0C ADC configuration register 1
  CFG2                   : TADC1_CFG2_bitbanded;       // 0x10 Configuration register 2
  RA_bitbanded           : longWord;                   // 0x10 ADC data result register
  RB_bitbanded           : longWord;                   // 0x14 ADC data result register
  CV1                    : TADC1_CV_bitbanded;         // 0x1C Compare value registers
  CV2                    : TADC1_CV_bitbanded;         // 0x20 Compare value registers
  SC2                    : TADC1_SC2_bitbanded;        // 0x24 Status and control register 2
  SC3                    : TADC1_SC3_bitbanded;        // 0x28 Status and control register 3
  OFS                    : TADC1_OFS_bitbanded;        // 0x2C ADC offset correction register
  PG                     : TADC1_PG_bitbanded;         // 0x30 ADC plus-side gain register
  MG                     : TADC1_MG_bitbanded;         // 0x34 ADC minus-side gain register
  CLPD                   : TADC1_CLPD_bitbanded;       // 0x38 ADC plus-side general calibration value register
  CLPS                   : TADC1_CLPS_bitbanded;       // 0x3C ADC plus-side general calibration value register
  CLP4                   : TADC1_CLP4_bitbanded;       // 0x40 ADC plus-side general calibration value register
  CLP3                   : TADC1_CLP3_bitbanded;       // 0x44 ADC plus-side general calibration value register
  CLP2                   : TADC1_CLP2_bitbanded;       // 0x48 ADC plus-side general calibration value register
  CLP1                   : TADC1_CLP1_bitbanded;       // 0x4C ADC plus-side general calibration value register
  CLP0                   : TADC1_CLP0_bitbanded;       // 0x50 ADC plus-side general calibration value register
  PGA                    : TADC1_PGA_bitbanded;        // 0x54 ADC PGA register
  CLMD                   : TADC1_CLMD_bitbanded;       // 0x58 ADC minus-side general calibration value register
  CLMS                   : TADC1_CLMS_bitbanded;       // 0x5C ADC minus-side general calibration value register
  CLM4                   : TADC1_CLM4_bitbanded;       // 0x60 ADC minus-side general calibration value register
  CLM3                   : TADC1_CLM3_bitbanded;       // 0x64 ADC minus-side general calibration value register
  CLM2                   : TADC1_CLM2_bitbanded;       // 0x68 ADC minus-side general calibration value register
  CLM1                   : TADC1_CLM1_bitbanded;       // 0x6C ADC minus-side general calibration value register
  CLM0                   : TADC1_CLM0_bitbanded;       // 0x70 ADC minus-side general calibration value register
end;

// AIPS-Lite Bridge
TAIPS0_MPRA_bits = bitpacked record
  RESERVED0              : TBits_4;                    // [0:3] no description available
  RESERVED1              : TBits_4;                    // [4:7] no description available
  RESERVED2              : TBits_4;                    // [8:11] no description available
  RESERVED3              : TBits_4;                    // [12:15] no description available
  MPL3                   : TBits_1;                    // [16:16] Master privilege level
  MTW3                   : TBits_1;                    // [17:17] Master trusted for writes
  MTR3                   : TBits_1;                    // [18:18] Master trusted for read
  RESERVED4              : TBits_1;                    // [19:19] no description available
  MPL2                   : TBits_1;                    // [20:20] Master privilege level
  MTW2                   : TBits_1;                    // [21:21] Master trusted for writes
  MTR2                   : TBits_1;                    // [22:22] Master trusted for read
  RESERVED5              : TBits_1;                    // [23:23] no description available
  MPL1                   : TBits_1;                    // [24:24] Master privilege level
  MTW1                   : TBits_1;                    // [25:25] Master trusted for writes
  MTR1                   : TBits_1;                    // [26:26] Master trusted for read
  RESERVED6              : TBits_1;                    // [27:27] no description available
  MPL0                   : TBits_1;                    // [28:28] Master privilege level
  MTW0                   : TBits_1;                    // [29:29] Master trusted for writes
  MTR0                   : TBits_1;                    // [30:30] Master trusted for read
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_MPRA_bitbanded = record
  RESERVED0              : array[0..3] of longWord;    // [0:3] no description available
  RESERVED1              : array[0..3] of longWord;    // [4:7] no description available
  RESERVED2              : array[0..3] of longWord;    // [8:11] no description available
  RESERVED3              : array[0..3] of longWord;    // [12:15] no description available
  MPL3                   : longWord;                   // [16:16] Master privilege level
  MTW3                   : longWord;                   // [17:17] Master trusted for writes
  MTR3                   : longWord;                   // [18:18] Master trusted for read
  RESERVED4              : longWord;                   // [19:19] no description available
  MPL2                   : longWord;                   // [20:20] Master privilege level
  MTW2                   : longWord;                   // [21:21] Master trusted for writes
  MTR2                   : longWord;                   // [22:22] Master trusted for read
  RESERVED5              : longWord;                   // [23:23] no description available
  MPL1                   : longWord;                   // [24:24] Master privilege level
  MTW1                   : longWord;                   // [25:25] Master trusted for writes
  MTR1                   : longWord;                   // [26:26] Master trusted for read
  RESERVED6              : longWord;                   // [27:27] no description available
  MPL0                   : longWord;                   // [28:28] Master privilege level
  MTW0                   : longWord;                   // [29:29] Master trusted for writes
  MTR0                   : longWord;                   // [30:30] Master trusted for read
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_PACRA_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_PACRA_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_PACRB_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_PACRB_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_PACRC_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_PACRC_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_PACRD_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_PACRD_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_PACRE_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_PACRE_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_PACRF_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_PACRF_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_PACRG_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_PACRG_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_PACRH_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_PACRH_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_PACRI_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_PACRI_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_PACRJ_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_PACRJ_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_PACRK_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_PACRK_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_PACRL_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_PACRL_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_PACRM_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_PACRM_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_PACRN_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_PACRN_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_PACRO_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_PACRO_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_PACRP_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS0_PACRP_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS0_Registers = record
  case boolean of false: (
  MPRA                   : longWord;                   // 0x00 Master Privilege Register A
  RESERVED0              : array[0..6] of longWord;    // 0x04
  PACRA                  : longWord;                   // 0x20 Peripheral Access Control Register
  PACRB                  : longWord;                   // 0x24 Peripheral Access Control Register
  PACRC                  : longWord;                   // 0x28 Peripheral Access Control Register
  PACRD                  : longWord;                   // 0x2C Peripheral Access Control Register
  RESERVED1              : array[0..3] of longWord;    // 0x30
  PACRE                  : longWord;                   // 0x40 Peripheral Access Control Register
  PACRF                  : longWord;                   // 0x44 Peripheral Access Control Register
  PACRG                  : longWord;                   // 0x48 Peripheral Access Control Register
  PACRH                  : longWord;                   // 0x4C Peripheral Access Control Register
  PACRI                  : longWord;                   // 0x50 Peripheral Access Control Register
  PACRJ                  : longWord;                   // 0x54 Peripheral Access Control Register
  PACRK                  : longWord;                   // 0x58 Peripheral Access Control Register
  PACRL                  : longWord;                   // 0x5C Peripheral Access Control Register
  PACRM                  : longWord;                   // 0x60 Peripheral Access Control Register
  PACRN                  : longWord;                   // 0x64 Peripheral Access Control Register
  PACRO                  : longWord;                   // 0x68 Peripheral Access Control Register
  PACRP                  : longWord;                   // 0x6C Peripheral Access Control Register
);
true : (
MPRA_bits                : TAIPS0_MPRA_bits;           // 0x04 Master Privilege Register A
RESERVED_bits0           : array[0..6] of longWord;
PACRA_bits               : TAIPS0_PACRA_bits;          // 0x24 Peripheral Access Control Register
PACRB_bits               : TAIPS0_PACRB_bits;          // 0x28 Peripheral Access Control Register
PACRC_bits               : TAIPS0_PACRC_bits;          // 0x2C Peripheral Access Control Register
PACRD_bits               : TAIPS0_PACRD_bits;          // 0x30 Peripheral Access Control Register
RESERVED_bits1           : array[0..3] of longWord;
PACRE_bits               : TAIPS0_PACRE_bits;          // 0x44 Peripheral Access Control Register
PACRF_bits               : TAIPS0_PACRF_bits;          // 0x48 Peripheral Access Control Register
PACRG_bits               : TAIPS0_PACRG_bits;          // 0x4C Peripheral Access Control Register
PACRH_bits               : TAIPS0_PACRH_bits;          // 0x50 Peripheral Access Control Register
PACRI_bits               : TAIPS0_PACRI_bits;          // 0x54 Peripheral Access Control Register
PACRJ_bits               : TAIPS0_PACRJ_bits;          // 0x58 Peripheral Access Control Register
PACRK_bits               : TAIPS0_PACRK_bits;          // 0x5C Peripheral Access Control Register
PACRL_bits               : TAIPS0_PACRL_bits;          // 0x60 Peripheral Access Control Register
PACRM_bits               : TAIPS0_PACRM_bits;          // 0x64 Peripheral Access Control Register
PACRN_bits               : TAIPS0_PACRN_bits;          // 0x68 Peripheral Access Control Register
PACRO_bits               : TAIPS0_PACRO_bits;          // 0x6C Peripheral Access Control Register
PACRP_bits               : TAIPS0_PACRP_bits;          // 0x70 Peripheral Access Control Register
);
end;

TAIPS0Registers_bitbanded = record
  MPRA                   : TAIPS0_MPRA_bitbanded;      // 0x04 Master Privilege Register A
  RESERVED0              : array[0..27] of array[0..7] of longWord;
  PACRA                  : TAIPS0_PACRA_bitbanded;     // 0x24 Peripheral Access Control Register
  PACRB                  : TAIPS0_PACRB_bitbanded;     // 0x28 Peripheral Access Control Register
  PACRC                  : TAIPS0_PACRC_bitbanded;     // 0x2C Peripheral Access Control Register
  PACRD                  : TAIPS0_PACRD_bitbanded;     // 0x30 Peripheral Access Control Register
  RESERVED1              : array[0..15] of array[0..7] of longWord;
  PACRE                  : TAIPS0_PACRE_bitbanded;     // 0x44 Peripheral Access Control Register
  PACRF                  : TAIPS0_PACRF_bitbanded;     // 0x48 Peripheral Access Control Register
  PACRG                  : TAIPS0_PACRG_bitbanded;     // 0x4C Peripheral Access Control Register
  PACRH                  : TAIPS0_PACRH_bitbanded;     // 0x50 Peripheral Access Control Register
  PACRI                  : TAIPS0_PACRI_bitbanded;     // 0x54 Peripheral Access Control Register
  PACRJ                  : TAIPS0_PACRJ_bitbanded;     // 0x58 Peripheral Access Control Register
  PACRK                  : TAIPS0_PACRK_bitbanded;     // 0x5C Peripheral Access Control Register
  PACRL                  : TAIPS0_PACRL_bitbanded;     // 0x60 Peripheral Access Control Register
  PACRM                  : TAIPS0_PACRM_bitbanded;     // 0x64 Peripheral Access Control Register
  PACRN                  : TAIPS0_PACRN_bitbanded;     // 0x68 Peripheral Access Control Register
  PACRO                  : TAIPS0_PACRO_bitbanded;     // 0x6C Peripheral Access Control Register
  PACRP                  : TAIPS0_PACRP_bitbanded;     // 0x70 Peripheral Access Control Register
end;

// AIPS-Lite Bridge
TAIPS1_MPRA_bits = bitpacked record
  RESERVED0              : TBits_4;                    // [0:3] no description available
  RESERVED1              : TBits_4;                    // [4:7] no description available
  RESERVED2              : TBits_4;                    // [8:11] no description available
  RESERVED3              : TBits_4;                    // [12:15] no description available
  MPL3                   : TBits_1;                    // [16:16] Master privilege level
  MTW3                   : TBits_1;                    // [17:17] Master trusted for writes
  MTR3                   : TBits_1;                    // [18:18] Master trusted for read
  RESERVED4              : TBits_1;                    // [19:19] no description available
  MPL2                   : TBits_1;                    // [20:20] Master privilege level
  MTW2                   : TBits_1;                    // [21:21] Master trusted for writes
  MTR2                   : TBits_1;                    // [22:22] Master trusted for read
  RESERVED5              : TBits_1;                    // [23:23] no description available
  MPL1                   : TBits_1;                    // [24:24] Master privilege level
  MTW1                   : TBits_1;                    // [25:25] Master trusted for writes
  MTR1                   : TBits_1;                    // [26:26] Master trusted for read
  RESERVED6              : TBits_1;                    // [27:27] no description available
  MPL0                   : TBits_1;                    // [28:28] Master privilege level
  MTW0                   : TBits_1;                    // [29:29] Master trusted for writes
  MTR0                   : TBits_1;                    // [30:30] Master trusted for read
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_MPRA_bitbanded = record
  RESERVED0              : array[0..3] of longWord;    // [0:3] no description available
  RESERVED1              : array[0..3] of longWord;    // [4:7] no description available
  RESERVED2              : array[0..3] of longWord;    // [8:11] no description available
  RESERVED3              : array[0..3] of longWord;    // [12:15] no description available
  MPL3                   : longWord;                   // [16:16] Master privilege level
  MTW3                   : longWord;                   // [17:17] Master trusted for writes
  MTR3                   : longWord;                   // [18:18] Master trusted for read
  RESERVED4              : longWord;                   // [19:19] no description available
  MPL2                   : longWord;                   // [20:20] Master privilege level
  MTW2                   : longWord;                   // [21:21] Master trusted for writes
  MTR2                   : longWord;                   // [22:22] Master trusted for read
  RESERVED5              : longWord;                   // [23:23] no description available
  MPL1                   : longWord;                   // [24:24] Master privilege level
  MTW1                   : longWord;                   // [25:25] Master trusted for writes
  MTR1                   : longWord;                   // [26:26] Master trusted for read
  RESERVED6              : longWord;                   // [27:27] no description available
  MPL0                   : longWord;                   // [28:28] Master privilege level
  MTW0                   : longWord;                   // [29:29] Master trusted for writes
  MTR0                   : longWord;                   // [30:30] Master trusted for read
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_PACRA_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_PACRA_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_PACRB_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_PACRB_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_PACRC_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_PACRC_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_PACRD_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_PACRD_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_PACRE_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_PACRE_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_PACRF_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_PACRF_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_PACRG_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_PACRG_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_PACRH_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_PACRH_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_PACRI_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_PACRI_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_PACRJ_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_PACRJ_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_PACRK_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_PACRK_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_PACRL_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_PACRL_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_PACRM_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_PACRM_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_PACRN_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_PACRN_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_PACRO_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_PACRO_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_PACRP_bits = bitpacked record
  TP7                    : TBits_1;                    // [0:0] Trusted protect
  WP7                    : TBits_1;                    // [1:1] Write protect
  SP7                    : TBits_1;                    // [2:2] Supervisor protect
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TP6                    : TBits_1;                    // [4:4] Trusted protect
  WP6                    : TBits_1;                    // [5:5] Write protect
  SP6                    : TBits_1;                    // [6:6] Supervisor protect
  RESERVED1              : TBits_1;                    // [7:7] no description available
  TP5                    : TBits_1;                    // [8:8] Trusted protect
  WP5                    : TBits_1;                    // [9:9] Write protect
  SP5                    : TBits_1;                    // [10:10] Supervisor protect
  RESERVED2              : TBits_1;                    // [11:11] no description available
  TP4                    : TBits_1;                    // [12:12] Trusted protect
  WP4                    : TBits_1;                    // [13:13] Write protect
  SP4                    : TBits_1;                    // [14:14] Supervisor protect
  RESERVED3              : TBits_1;                    // [15:15] no description available
  TP3                    : TBits_1;                    // [16:16] Trusted protect
  WP3                    : TBits_1;                    // [17:17] Write protect
  SP3                    : TBits_1;                    // [18:18] Supervisor protect
  RESERVED4              : TBits_1;                    // [19:19] no description available
  TP2                    : TBits_1;                    // [20:20] Trusted protect
  WP2                    : TBits_1;                    // [21:21] Write protect
  SP2                    : TBits_1;                    // [22:22] Supervisor protect
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TP1                    : TBits_1;                    // [24:24] Trusted protect
  WP1                    : TBits_1;                    // [25:25] Write protect
  SP1                    : TBits_1;                    // [26:26] Supervisor protect
  RESERVED6              : TBits_1;                    // [27:27] no description available
  TP0                    : TBits_1;                    // [28:28] Trusted protect
  WP0                    : TBits_1;                    // [29:29] Write protect
  SP0                    : TBits_1;                    // [30:30] Supervisor protect
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TAIPS1_PACRP_bitbanded = record
  TP7                    : longWord;                   // [0:0] Trusted protect
  WP7                    : longWord;                   // [1:1] Write protect
  SP7                    : longWord;                   // [2:2] Supervisor protect
  RESERVED0              : longWord;                   // [3:3] no description available
  TP6                    : longWord;                   // [4:4] Trusted protect
  WP6                    : longWord;                   // [5:5] Write protect
  SP6                    : longWord;                   // [6:6] Supervisor protect
  RESERVED1              : longWord;                   // [7:7] no description available
  TP5                    : longWord;                   // [8:8] Trusted protect
  WP5                    : longWord;                   // [9:9] Write protect
  SP5                    : longWord;                   // [10:10] Supervisor protect
  RESERVED2              : longWord;                   // [11:11] no description available
  TP4                    : longWord;                   // [12:12] Trusted protect
  WP4                    : longWord;                   // [13:13] Write protect
  SP4                    : longWord;                   // [14:14] Supervisor protect
  RESERVED3              : longWord;                   // [15:15] no description available
  TP3                    : longWord;                   // [16:16] Trusted protect
  WP3                    : longWord;                   // [17:17] Write protect
  SP3                    : longWord;                   // [18:18] Supervisor protect
  RESERVED4              : longWord;                   // [19:19] no description available
  TP2                    : longWord;                   // [20:20] Trusted protect
  WP2                    : longWord;                   // [21:21] Write protect
  SP2                    : longWord;                   // [22:22] Supervisor protect
  RESERVED5              : longWord;                   // [23:23] no description available
  TP1                    : longWord;                   // [24:24] Trusted protect
  WP1                    : longWord;                   // [25:25] Write protect
  SP1                    : longWord;                   // [26:26] Supervisor protect
  RESERVED6              : longWord;                   // [27:27] no description available
  TP0                    : longWord;                   // [28:28] Trusted protect
  WP0                    : longWord;                   // [29:29] Write protect
  SP0                    : longWord;                   // [30:30] Supervisor protect
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TAIPS1_Registers = record
  case boolean of false: (
  MPRA                   : longWord;                   // 0x00 Master Privilege Register A
  RESERVED0              : array[0..6] of longWord;    // 0x04
  PACRA                  : longWord;                   // 0x20 Peripheral Access Control Register
  PACRB                  : longWord;                   // 0x24 Peripheral Access Control Register
  PACRC                  : longWord;                   // 0x28 Peripheral Access Control Register
  PACRD                  : longWord;                   // 0x2C Peripheral Access Control Register
  RESERVED1              : array[0..3] of longWord;    // 0x30
  PACRE                  : longWord;                   // 0x40 Peripheral Access Control Register
  PACRF                  : longWord;                   // 0x44 Peripheral Access Control Register
  PACRG                  : longWord;                   // 0x48 Peripheral Access Control Register
  PACRH                  : longWord;                   // 0x4C Peripheral Access Control Register
  PACRI                  : longWord;                   // 0x50 Peripheral Access Control Register
  PACRJ                  : longWord;                   // 0x54 Peripheral Access Control Register
  PACRK                  : longWord;                   // 0x58 Peripheral Access Control Register
  PACRL                  : longWord;                   // 0x5C Peripheral Access Control Register
  PACRM                  : longWord;                   // 0x60 Peripheral Access Control Register
  PACRN                  : longWord;                   // 0x64 Peripheral Access Control Register
  PACRO                  : longWord;                   // 0x68 Peripheral Access Control Register
  PACRP                  : longWord;                   // 0x6C Peripheral Access Control Register
);
true : (
MPRA_bits                : TAIPS1_MPRA_bits;           // 0x04 Master Privilege Register A
RESERVED_bits0           : array[0..6] of longWord;
PACRA_bits               : TAIPS1_PACRA_bits;          // 0x24 Peripheral Access Control Register
PACRB_bits               : TAIPS1_PACRB_bits;          // 0x28 Peripheral Access Control Register
PACRC_bits               : TAIPS1_PACRC_bits;          // 0x2C Peripheral Access Control Register
PACRD_bits               : TAIPS1_PACRD_bits;          // 0x30 Peripheral Access Control Register
RESERVED_bits1           : array[0..3] of longWord;
PACRE_bits               : TAIPS1_PACRE_bits;          // 0x44 Peripheral Access Control Register
PACRF_bits               : TAIPS1_PACRF_bits;          // 0x48 Peripheral Access Control Register
PACRG_bits               : TAIPS1_PACRG_bits;          // 0x4C Peripheral Access Control Register
PACRH_bits               : TAIPS1_PACRH_bits;          // 0x50 Peripheral Access Control Register
PACRI_bits               : TAIPS1_PACRI_bits;          // 0x54 Peripheral Access Control Register
PACRJ_bits               : TAIPS1_PACRJ_bits;          // 0x58 Peripheral Access Control Register
PACRK_bits               : TAIPS1_PACRK_bits;          // 0x5C Peripheral Access Control Register
PACRL_bits               : TAIPS1_PACRL_bits;          // 0x60 Peripheral Access Control Register
PACRM_bits               : TAIPS1_PACRM_bits;          // 0x64 Peripheral Access Control Register
PACRN_bits               : TAIPS1_PACRN_bits;          // 0x68 Peripheral Access Control Register
PACRO_bits               : TAIPS1_PACRO_bits;          // 0x6C Peripheral Access Control Register
PACRP_bits               : TAIPS1_PACRP_bits;          // 0x70 Peripheral Access Control Register
);
end;

TAIPS1Registers_bitbanded = record
  MPRA                   : TAIPS1_MPRA_bitbanded;      // 0x04 Master Privilege Register A
  RESERVED0              : array[0..27] of array[0..7] of longWord;
  PACRA                  : TAIPS1_PACRA_bitbanded;     // 0x24 Peripheral Access Control Register
  PACRB                  : TAIPS1_PACRB_bitbanded;     // 0x28 Peripheral Access Control Register
  PACRC                  : TAIPS1_PACRC_bitbanded;     // 0x2C Peripheral Access Control Register
  PACRD                  : TAIPS1_PACRD_bitbanded;     // 0x30 Peripheral Access Control Register
  RESERVED1              : array[0..15] of array[0..7] of longWord;
  PACRE                  : TAIPS1_PACRE_bitbanded;     // 0x44 Peripheral Access Control Register
  PACRF                  : TAIPS1_PACRF_bitbanded;     // 0x48 Peripheral Access Control Register
  PACRG                  : TAIPS1_PACRG_bitbanded;     // 0x4C Peripheral Access Control Register
  PACRH                  : TAIPS1_PACRH_bitbanded;     // 0x50 Peripheral Access Control Register
  PACRI                  : TAIPS1_PACRI_bitbanded;     // 0x54 Peripheral Access Control Register
  PACRJ                  : TAIPS1_PACRJ_bitbanded;     // 0x58 Peripheral Access Control Register
  PACRK                  : TAIPS1_PACRK_bitbanded;     // 0x5C Peripheral Access Control Register
  PACRL                  : TAIPS1_PACRL_bitbanded;     // 0x60 Peripheral Access Control Register
  PACRM                  : TAIPS1_PACRM_bitbanded;     // 0x64 Peripheral Access Control Register
  PACRN                  : TAIPS1_PACRN_bitbanded;     // 0x68 Peripheral Access Control Register
  PACRO                  : TAIPS1_PACRO_bitbanded;     // 0x6C Peripheral Access Control Register
  PACRP                  : TAIPS1_PACRP_bitbanded;     // 0x70 Peripheral Access Control Register
end;

// Crossbar switch
TAXBS_PRS_bits = bitpacked record
  M0                     : TBits_3;                    // [0:2] Master 0 priority. Sets the arbitration priority for this port on the associated slave port.
  RESERVED0              : TBits_1;                    // [3:3] no description available
  M1                     : TBits_3;                    // [4:6] Master 1 priority. Sets the arbitration priority for this port on the associated slave port.
  RESERVED1              : TBits_1;                    // [7:7] no description available
  M2                     : TBits_3;                    // [8:10] Master 2 priority. Sets the arbitration priority for this port on the associated slave port.
  RESERVED2              : TBits_1;                    // [11:11] no description available
  M3                     : TBits_3;                    // [12:14] Master 3 priority. Sets the arbitration priority for this port on the associated slave port.
  RESERVED3              : TBits_1;                    // [15:15] no description available
  M4                     : TBits_3;                    // [16:18] Master 4 priority. Sets the arbitration priority for this port on the associated slave port.
  RESERVED4              : TBits_1;                    // [19:19] no description available
  M5                     : TBits_3;                    // [20:22] Master 5 priority. Sets the arbitration priority for this port on the associated slave port.
  RESERVED5              : TBits_1;                    // [23:23] no description available
  RESERVED6              : TBits_4;                    // [24:27] no description available
  RESERVED7              : TBits_4;                    // [28:31] no description available
end;

TAXBS_PRS_bitbanded = record
  M0                     : array[0..2] of longWord;    // [0:2] Master 0 priority. Sets the arbitration priority for this port on the associated slave port.
  RESERVED0              : longWord;                   // [3:3] no description available
  M1                     : array[0..2] of longWord;    // [4:6] Master 1 priority. Sets the arbitration priority for this port on the associated slave port.
  RESERVED1              : longWord;                   // [7:7] no description available
  M2                     : array[0..2] of longWord;    // [8:10] Master 2 priority. Sets the arbitration priority for this port on the associated slave port.
  RESERVED2              : longWord;                   // [11:11] no description available
  M3                     : array[0..2] of longWord;    // [12:14] Master 3 priority. Sets the arbitration priority for this port on the associated slave port.
  RESERVED3              : longWord;                   // [15:15] no description available
  M4                     : array[0..2] of longWord;    // [16:18] Master 4 priority. Sets the arbitration priority for this port on the associated slave port.
  RESERVED4              : longWord;                   // [19:19] no description available
  M5                     : array[0..2] of longWord;    // [20:22] Master 5 priority. Sets the arbitration priority for this port on the associated slave port.
  RESERVED5              : longWord;                   // [23:23] no description available
  RESERVED6              : array[0..3] of longWord;    // [24:27] no description available
  RESERVED7              : array[0..3] of longWord;    // [28:31] no description available
end;

TAXBS_CRS_bits = bitpacked record
  PARK                   : TBits_3;                    // [0:2] Park
  RESERVED0              : TBits_1;                    // [3:3] no description available
  PCTL                   : TBits_2;                    // [4:5] Parking control
  RESERVED1              : TBits_2;                    // [6:7] no description available
  ARB                    : TBits_2;                    // [8:9] Arbitration mode
  RESERVED2              : TBits_20;                   // [10:29] no description available
  HLP                    : TBits_1;                    // [30:30] Halt low priority
  RO                     : TBits_1;                    // [31:31] Read only
end;

TAXBS_CRS_bitbanded = record
  PARK                   : array[0..2] of longWord;    // [0:2] Park
  RESERVED0              : longWord;                   // [3:3] no description available
  PCTL                   : array[0..1] of longWord;    // [4:5] Parking control
  RESERVED1              : array[0..1] of longWord;    // [6:7] no description available
  ARB                    : array[0..1] of longWord;    // [8:9] Arbitration mode
  RESERVED2              : array[0..19] of longWord;   // [10:29] no description available
  HLP                    : longWord;                   // [30:30] Halt low priority
  RO                     : longWord;                   // [31:31] Read only
end;

TAXBS_MGPCR_bits = bitpacked record
  AULB                   : TBits_3;                    // [0:2] Arbitrates on undefined length bursts
  RESERVED0              : TBits_29;                   // [3:31] no description available
end;

TAXBS_MGPCR_bitbanded = record
  AULB                   : array[0..2] of longWord;    // [0:2] Arbitrates on undefined length bursts
  RESERVED0              : array[0..28] of longWord;   // [3:31] no description available
end;

TAXBS_Registers = record
  case boolean of false: (
  PRS0                   : longWord;                   // 0x00 Priority Registers Slave
  RESERVED0              : array[0..2] of longWord;    // 0x04
  CRS0                   : longWord;                   // 0x10 Control Register
  RESERVED1              : array[0..58] of longWord;   // 0x14
  PRS1                   : longWord;                   // 0x100 Priority Registers Slave
  RESERVED2              : array[0..2] of longWord;    // 0x104
  CRS1                   : longWord;                   // 0x110 Control Register
  RESERVED3              : array[0..58] of longWord;   // 0x114
  PRS2                   : longWord;                   // 0x200 Priority Registers Slave
  RESERVED4              : array[0..2] of longWord;    // 0x204
  CRS2                   : longWord;                   // 0x210 Control Register
  RESERVED5              : array[0..58] of longWord;   // 0x214
  PRS3                   : longWord;                   // 0x300 Priority Registers Slave
  RESERVED6              : array[0..2] of longWord;    // 0x304
  CRS3                   : longWord;                   // 0x310 Control Register
  RESERVED7              : array[0..314] of longWord;  // 0x314
  MGPCR0                 : longWord;                   // 0x800 Master General Purpose Control Register
  RESERVED8              : array[0..62] of longWord;   // 0x804
  MGPCR1                 : longWord;                   // 0x900 Master General Purpose Control Register
  RESERVED9              : array[0..62] of longWord;   // 0x904
  MGPCR2                 : longWord;                   // 0xA00 Master General Purpose Control Register
  RESERVED10             : array[0..62] of longWord;   // 0xA04
  MGPCR3                 : longWord;                   // 0xB00 Master General Purpose Control Register
);
true : (
PRS0_bits                : TAXBS_PRS_bits;             // 0x04 Priority Registers Slave
RESERVED_bits0           : array[0..2] of longWord;
CRS0_bits                : TAXBS_CRS_bits;             // 0x14 Control Register
RESERVED_bits1           : array[0..58] of longWord;
PRS1_bits                : TAXBS_PRS_bits;             // 0x104 Priority Registers Slave
RESERVED_bits2           : array[0..2] of longWord;
CRS1_bits                : TAXBS_CRS_bits;             // 0x114 Control Register
RESERVED_bits3           : array[0..58] of longWord;
PRS2_bits                : TAXBS_PRS_bits;             // 0x204 Priority Registers Slave
RESERVED_bits4           : array[0..2] of longWord;
CRS2_bits                : TAXBS_CRS_bits;             // 0x214 Control Register
RESERVED_bits5           : array[0..58] of longWord;
PRS3_bits                : TAXBS_PRS_bits;             // 0x304 Priority Registers Slave
RESERVED_bits6           : array[0..2] of longWord;
CRS3_bits                : TAXBS_CRS_bits;             // 0x314 Control Register
RESERVED_bits7           : array[0..314] of longWord;
MGPCR0_bits              : TAXBS_MGPCR_bits;           // 0x804 Master General Purpose Control Register
RESERVED_bits8           : array[0..62] of longWord;
MGPCR1_bits              : TAXBS_MGPCR_bits;           // 0x904 Master General Purpose Control Register
RESERVED_bits9           : array[0..62] of longWord;
MGPCR2_bits              : TAXBS_MGPCR_bits;           // 0xA04 Master General Purpose Control Register
RESERVED_bits10          : array[0..62] of longWord;
MGPCR3_bits              : TAXBS_MGPCR_bits;           // 0xB04 Master General Purpose Control Register
);
end;

TAXBSRegisters_bitbanded = record
  PRS0                   : TAXBS_PRS_bitbanded;        // 0x04 Priority Registers Slave
  RESERVED0              : array[0..11] of array[0..7] of longWord;
  CRS0                   : TAXBS_CRS_bitbanded;        // 0x14 Control Register
  RESERVED1              : array[0..235] of array[0..7] of longWord;
  PRS1                   : TAXBS_PRS_bitbanded;        // 0x104 Priority Registers Slave
  RESERVED2              : array[0..11] of array[0..7] of longWord;
  CRS1                   : TAXBS_CRS_bitbanded;        // 0x114 Control Register
  RESERVED3              : array[0..235] of array[0..7] of longWord;
  PRS2                   : TAXBS_PRS_bitbanded;        // 0x204 Priority Registers Slave
  RESERVED4              : array[0..11] of array[0..7] of longWord;
  CRS2                   : TAXBS_CRS_bitbanded;        // 0x214 Control Register
  RESERVED5              : array[0..235] of array[0..7] of longWord;
  PRS3                   : TAXBS_PRS_bitbanded;        // 0x304 Priority Registers Slave
  RESERVED6              : array[0..11] of array[0..7] of longWord;
  CRS3                   : TAXBS_CRS_bitbanded;        // 0x314 Control Register
  RESERVED7              : array[0..1259] of array[0..7] of longWord;
  MGPCR0                 : TAXBS_MGPCR_bitbanded;      // 0x804 Master General Purpose Control Register
  RESERVED8              : array[0..251] of array[0..7] of longWord;
  MGPCR1                 : TAXBS_MGPCR_bitbanded;      // 0x904 Master General Purpose Control Register
  RESERVED9              : array[0..251] of array[0..7] of longWord;
  MGPCR2                 : TAXBS_MGPCR_bitbanded;      // 0xA04 Master General Purpose Control Register
  RESERVED10             : array[0..251] of array[0..7] of longWord;
  MGPCR3                 : TAXBS_MGPCR_bitbanded;      // 0xB04 Master General Purpose Control Register
end;

// Flex Controller Area Network module
TCAN0_MCR_bits = bitpacked record
  MAXMB                  : TBits_7;                    // [0:6] Number of the Last Message Buffer
  RESERVED0              : TBits_1;                    // [7:7] no description available
  IDAM                   : TBits_2;                    // [8:9] ID Acceptance Mode
  RESERVED1              : TBits_2;                    // [10:11] no description available
  AEN                    : TBits_1;                    // [12:12] Abort Enable
  LPRIOEN                : TBits_1;                    // [13:13] Local Priority Enable
  RESERVED2              : TBits_2;                    // [14:15] no description available
  IRMQ                   : TBits_1;                    // [16:16] Individual Rx Masking and Queue Enable
  SRXDIS                 : TBits_1;                    // [17:17] Self Reception Disable
  RESERVED3              : TBits_1;                    // [18:18] no description available
  RESERVED4              : TBits_1;                    // [19:19] no description available
  LPMACK                 : TBits_1;                    // [20:20] Low Power Mode Acknowledge
  WRNEN                  : TBits_1;                    // [21:21] Warning Interrupt Enable
  SLFWAK                 : TBits_1;                    // [22:22] Self Wake Up
  SUPV                   : TBits_1;                    // [23:23] Supervisor Mode
  FRZACK                 : TBits_1;                    // [24:24] Freeze Mode Acknowledge
  SOFTRST                : TBits_1;                    // [25:25] Soft Reset
  WAKMSK                 : TBits_1;                    // [26:26] Wake Up Interrupt Mask
  NOTRDY                 : TBits_1;                    // [27:27] FlexCAN Not Ready
  HALT                   : TBits_1;                    // [28:28] Halt FlexCAN
  RFEN                   : TBits_1;                    // [29:29] Rx FIFO Enable
  FRZ                    : TBits_1;                    // [30:30] Freeze Enable
  MDIS                   : TBits_1;                    // [31:31] Module Disable
end;

TCAN0_MCR_bitbanded = record
  MAXMB                  : array[0..6] of longWord;    // [0:6] Number of the Last Message Buffer
  RESERVED0              : longWord;                   // [7:7] no description available
  IDAM                   : array[0..1] of longWord;    // [8:9] ID Acceptance Mode
  RESERVED1              : array[0..1] of longWord;    // [10:11] no description available
  AEN                    : longWord;                   // [12:12] Abort Enable
  LPRIOEN                : longWord;                   // [13:13] Local Priority Enable
  RESERVED2              : array[0..1] of longWord;    // [14:15] no description available
  IRMQ                   : longWord;                   // [16:16] Individual Rx Masking and Queue Enable
  SRXDIS                 : longWord;                   // [17:17] Self Reception Disable
  RESERVED3              : longWord;                   // [18:18] no description available
  RESERVED4              : longWord;                   // [19:19] no description available
  LPMACK                 : longWord;                   // [20:20] Low Power Mode Acknowledge
  WRNEN                  : longWord;                   // [21:21] Warning Interrupt Enable
  SLFWAK                 : longWord;                   // [22:22] Self Wake Up
  SUPV                   : longWord;                   // [23:23] Supervisor Mode
  FRZACK                 : longWord;                   // [24:24] Freeze Mode Acknowledge
  SOFTRST                : longWord;                   // [25:25] Soft Reset
  WAKMSK                 : longWord;                   // [26:26] Wake Up Interrupt Mask
  NOTRDY                 : longWord;                   // [27:27] FlexCAN Not Ready
  HALT                   : longWord;                   // [28:28] Halt FlexCAN
  RFEN                   : longWord;                   // [29:29] Rx FIFO Enable
  FRZ                    : longWord;                   // [30:30] Freeze Enable
  MDIS                   : longWord;                   // [31:31] Module Disable
end;

TCAN0_CTRL1_bits = bitpacked record
  PROPSEG                : TBits_3;                    // [0:2] Propagation Segment
  LOM                    : TBits_1;                    // [3:3] Listen-Only Mode
  LBUF                   : TBits_1;                    // [4:4] Lowest Buffer Transmitted First
  TSYN                   : TBits_1;                    // [5:5] Timer Sync
  BOFFREC                : TBits_1;                    // [6:6] Bus Off Recovery
  SMP                    : TBits_1;                    // [7:7] CAN Bit Sampling
  RESERVED0              : TBits_2;                    // [8:9] no description available
  RWRNMSK                : TBits_1;                    // [10:10] Rx Warning Interrupt Mask
  TWRNMSK                : TBits_1;                    // [11:11] Tx Warning Interrupt Mask
  LPB                    : TBits_1;                    // [12:12] Loop Back Mode
  CLKSRC                 : TBits_1;                    // [13:13] CAN Engine Clock Source
  ERRMSK                 : TBits_1;                    // [14:14] Error Mask
  BOFFMSK                : TBits_1;                    // [15:15] Bus Off Mask
  PSEG2                  : TBits_3;                    // [16:18] Phase Segment 2
  PSEG1                  : TBits_3;                    // [19:21] Phase Segment 1
  RJW                    : TBits_2;                    // [22:23] Resync Jump Width
  PRESDIV                : TBits_8;                    // [24:31] Prescaler Division Factor
end;

TCAN0_CTRL1_bitbanded = record
  PROPSEG                : array[0..2] of longWord;    // [0:2] Propagation Segment
  LOM                    : longWord;                   // [3:3] Listen-Only Mode
  LBUF                   : longWord;                   // [4:4] Lowest Buffer Transmitted First
  TSYN                   : longWord;                   // [5:5] Timer Sync
  BOFFREC                : longWord;                   // [6:6] Bus Off Recovery
  SMP                    : longWord;                   // [7:7] CAN Bit Sampling
  RESERVED0              : array[0..1] of longWord;    // [8:9] no description available
  RWRNMSK                : longWord;                   // [10:10] Rx Warning Interrupt Mask
  TWRNMSK                : longWord;                   // [11:11] Tx Warning Interrupt Mask
  LPB                    : longWord;                   // [12:12] Loop Back Mode
  CLKSRC                 : longWord;                   // [13:13] CAN Engine Clock Source
  ERRMSK                 : longWord;                   // [14:14] Error Mask
  BOFFMSK                : longWord;                   // [15:15] Bus Off Mask
  PSEG2                  : array[0..2] of longWord;    // [16:18] Phase Segment 2
  PSEG1                  : array[0..2] of longWord;    // [19:21] Phase Segment 1
  RJW                    : array[0..1] of longWord;    // [22:23] Resync Jump Width
  PRESDIV                : array[0..7] of longWord;    // [24:31] Prescaler Division Factor
end;

TCAN0_TIMER_bits = bitpacked record
  TIMER                  : TBits_16;                   // [0:15] Timer value
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TCAN0_TIMER_bitbanded = record
  TIMER                  : array[0..15] of longWord;   // [0:15] Timer value
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TCAN0_RXMGMASK_bits = bitpacked record
  MG                     : TBits_32;                   // [0:31] Rx Mailboxes Global Mask Bits
end;

TCAN0_RXMGMASK_bitbanded = record
  MG                     : array[0..31] of longWord;   // [0:31] Rx Mailboxes Global Mask Bits
end;

TCAN0_RX14MASK_bits = bitpacked record
  RX14M                  : TBits_32;                   // [0:31] Rx Buffer 14 Mask Bits
end;

TCAN0_RX14MASK_bitbanded = record
  RX14M                  : array[0..31] of longWord;   // [0:31] Rx Buffer 14 Mask Bits
end;

TCAN0_RX15MASK_bits = bitpacked record
  RX15M                  : TBits_32;                   // [0:31] Rx Buffer 15 Mask Bits
end;

TCAN0_RX15MASK_bitbanded = record
  RX15M                  : array[0..31] of longWord;   // [0:31] Rx Buffer 15 Mask Bits
end;

TCAN0_ECR_bits = bitpacked record
  TXERRCNT               : TBits_8;                    // [0:7] Transmit Error Counter
  RXERRCNT               : TBits_8;                    // [8:15] Receive Error Counter
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TCAN0_ECR_bitbanded = record
  TXERRCNT               : array[0..7] of longWord;    // [0:7] Transmit Error Counter
  RXERRCNT               : array[0..7] of longWord;    // [8:15] Receive Error Counter
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TCAN0_ESR1_bits = bitpacked record
  WAKINT                 : TBits_1;                    // [0:0] Wake-Up Interrupt
  ERRINT                 : TBits_1;                    // [1:1] Error Interrupt
  BOFFINT                : TBits_1;                    // [2:2] 'Bus Off' Interrupt
  RX                     : TBits_1;                    // [3:3] FlexCAN in Reception
  FLTCONF                : TBits_2;                    // [4:5] Fault Confinement State
  TX                     : TBits_1;                    // [6:6] FlexCAN in Transmission
  IDLE                   : TBits_1;                    // [7:7] no description available
  RXWRN                  : TBits_1;                    // [8:8] Rx Error Warning
  TXWRN                  : TBits_1;                    // [9:9] TX Error Warning
  STFERR                 : TBits_1;                    // [10:10] Stuffing Error
  FRMERR                 : TBits_1;                    // [11:11] Form Error
  CRCERR                 : TBits_1;                    // [12:12] Cyclic Redundancy Check Error
  ACKERR                 : TBits_1;                    // [13:13] Acknowledge Error
  BIT0ERR                : TBits_1;                    // [14:14] Bit0 Error
  BIT1ERR                : TBits_1;                    // [15:15] Bit1 Error
  RWRNINT                : TBits_1;                    // [16:16] Rx Warning Interrupt Flag
  TWRNINT                : TBits_1;                    // [17:17] Tx Warning Interrupt Flag
  SYNCH                  : TBits_1;                    // [18:18] CAN Synchronization Status
  RESERVED0              : TBits_13;                   // [19:31] no description available
end;

TCAN0_ESR1_bitbanded = record
  WAKINT                 : longWord;                   // [0:0] Wake-Up Interrupt
  ERRINT                 : longWord;                   // [1:1] Error Interrupt
  BOFFINT                : longWord;                   // [2:2] 'Bus Off' Interrupt
  RX                     : longWord;                   // [3:3] FlexCAN in Reception
  FLTCONF                : array[0..1] of longWord;    // [4:5] Fault Confinement State
  TX                     : longWord;                   // [6:6] FlexCAN in Transmission
  IDLE                   : longWord;                   // [7:7] no description available
  RXWRN                  : longWord;                   // [8:8] Rx Error Warning
  TXWRN                  : longWord;                   // [9:9] TX Error Warning
  STFERR                 : longWord;                   // [10:10] Stuffing Error
  FRMERR                 : longWord;                   // [11:11] Form Error
  CRCERR                 : longWord;                   // [12:12] Cyclic Redundancy Check Error
  ACKERR                 : longWord;                   // [13:13] Acknowledge Error
  BIT0ERR                : longWord;                   // [14:14] Bit0 Error
  BIT1ERR                : longWord;                   // [15:15] Bit1 Error
  RWRNINT                : longWord;                   // [16:16] Rx Warning Interrupt Flag
  TWRNINT                : longWord;                   // [17:17] Tx Warning Interrupt Flag
  SYNCH                  : longWord;                   // [18:18] CAN Synchronization Status
  RESERVED0              : array[0..12] of longWord;   // [19:31] no description available
end;

TCAN0_IMASK2_bits = bitpacked record
  BUFHM                  : TBits_32;                   // [0:31] Buffer MBi Mask
end;

TCAN0_IMASK2_bitbanded = record
  BUFHM                  : array[0..31] of longWord;   // [0:31] Buffer MBi Mask
end;

TCAN0_IMASK1_bits = bitpacked record
  BUFLM                  : TBits_32;                   // [0:31] Buffer MBi Mask
end;

TCAN0_IMASK1_bitbanded = record
  BUFLM                  : array[0..31] of longWord;   // [0:31] Buffer MBi Mask
end;

TCAN0_IFLAG2_bits = bitpacked record
  BUFHI                  : TBits_32;                   // [0:31] Buffer MBi Interrupt
end;

TCAN0_IFLAG2_bitbanded = record
  BUFHI                  : array[0..31] of longWord;   // [0:31] Buffer MBi Interrupt
end;

TCAN0_IFLAG1_bits = bitpacked record
  BUF4TO0I               : TBits_5;                    // [0:4] Buffer MBi Interrupt or "reserved"
  BUF5I                  : TBits_1;                    // [5:5] Buffer MB5 Interrupt or "Frames available in Rx FIFO"
  BUF6I                  : TBits_1;                    // [6:6] Buffer MB6 Interrupt or "Rx FIFO Warning"
  BUF7I                  : TBits_1;                    // [7:7] Buffer MB7 Interrupt or "Rx FIFO Overflow"
  BUF31TO8I              : TBits_24;                   // [8:31] Buffer MBi Interrupt
end;

TCAN0_IFLAG1_bitbanded = record
  BUF4TO0I               : array[0..4] of longWord;    // [0:4] Buffer MBi Interrupt or "reserved"
  BUF5I                  : longWord;                   // [5:5] Buffer MB5 Interrupt or "Frames available in Rx FIFO"
  BUF6I                  : longWord;                   // [6:6] Buffer MB6 Interrupt or "Rx FIFO Warning"
  BUF7I                  : longWord;                   // [7:7] Buffer MB7 Interrupt or "Rx FIFO Overflow"
  BUF31TO8I              : array[0..23] of longWord;   // [8:31] Buffer MBi Interrupt
end;

TCAN0_CTRL2_bits = bitpacked record
  RESERVED0              : TBits_16;                   // [0:15] no description available
  EACEN                  : TBits_1;                    // [16:16] Entire Frame Arbitration Field Comparison Enable for Rx Mailboxes
  RRS                    : TBits_1;                    // [17:17] Remote Request Storing
  MRP                    : TBits_1;                    // [18:18] Mailboxes Reception Priority
  TASD                   : TBits_5;                    // [19:23] Tx Arbitration Start Delay
  RFFN                   : TBits_4;                    // [24:27] Number of Rx FIFO Filters
  WRMFRZ                 : TBits_1;                    // [28:28] Write-Access to Memory in Freeze mode
  RESERVED1              : TBits_2;                    // [29:30] no description available
  RESERVED2              : TBits_1;                    // [31:31] no description available
end;

TCAN0_CTRL2_bitbanded = record
  RESERVED0              : array[0..15] of longWord;   // [0:15] no description available
  EACEN                  : longWord;                   // [16:16] Entire Frame Arbitration Field Comparison Enable for Rx Mailboxes
  RRS                    : longWord;                   // [17:17] Remote Request Storing
  MRP                    : longWord;                   // [18:18] Mailboxes Reception Priority
  TASD                   : array[0..4] of longWord;    // [19:23] Tx Arbitration Start Delay
  RFFN                   : array[0..3] of longWord;    // [24:27] Number of Rx FIFO Filters
  WRMFRZ                 : longWord;                   // [28:28] Write-Access to Memory in Freeze mode
  RESERVED1              : array[0..1] of longWord;    // [29:30] no description available
  RESERVED2              : longWord;                   // [31:31] no description available
end;

TCAN0_ESR2_bits = bitpacked record
  RESERVED0              : TBits_13;                   // [0:12] no description available
  IMB                    : TBits_1;                    // [13:13] Inactive Mailbox
  VPS                    : TBits_1;                    // [14:14] Valid Priority Status
  RESERVED1              : TBits_1;                    // [15:15] no description available
  LPTM                   : TBits_7;                    // [16:22] Lowest Priority Tx Mailbox
  RESERVED2              : TBits_9;                    // [23:31] no description available
end;

TCAN0_ESR2_bitbanded = record
  RESERVED0              : array[0..12] of longWord;   // [0:12] no description available
  IMB                    : longWord;                   // [13:13] Inactive Mailbox
  VPS                    : longWord;                   // [14:14] Valid Priority Status
  RESERVED1              : longWord;                   // [15:15] no description available
  LPTM                   : array[0..6] of longWord;    // [16:22] Lowest Priority Tx Mailbox
  RESERVED2              : array[0..8] of longWord;    // [23:31] no description available
end;

TCAN0_CRCR_bits = bitpacked record
  TXCRC                  : TBits_15;                   // [0:14] CRC Transmitted
  RESERVED0              : TBits_1;                    // [15:15] no description available
  MBCRC                  : TBits_7;                    // [16:22] CRC Mailbox
  RESERVED1              : TBits_9;                    // [23:31] no description available
end;

TCAN0_CRCR_bitbanded = record
  TXCRC                  : array[0..14] of longWord;   // [0:14] CRC Transmitted
  RESERVED0              : longWord;                   // [15:15] no description available
  MBCRC                  : array[0..6] of longWord;    // [16:22] CRC Mailbox
  RESERVED1              : array[0..8] of longWord;    // [23:31] no description available
end;

TCAN0_RXFGMASK_bits = bitpacked record
  FGM                    : TBits_32;                   // [0:31] Rx FIFO Global Mask Bits
end;

TCAN0_RXFGMASK_bitbanded = record
  FGM                    : array[0..31] of longWord;   // [0:31] Rx FIFO Global Mask Bits
end;

TCAN0_RXFIR_bits = bitpacked record
  IDHIT                  : TBits_9;                    // [0:8] Identifier Acceptance Filter Hit Indicator
  RESERVED0              : TBits_23;                   // [9:31] no description available
end;

TCAN0_RXFIR_bitbanded = record
  IDHIT                  : array[0..8] of longWord;    // [0:8] Identifier Acceptance Filter Hit Indicator
  RESERVED0              : array[0..22] of longWord;   // [9:31] no description available
end;

TCAN0_CS0_bits = bitpacked record
  TIME_STAMP             : TBits_16;                   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : TBits_4;                    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : TBits_1;                    // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : TBits_1;                    // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : TBits_1;                    // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : TBits_1;                    // [23:23] Reserved
  CODE                   : TBits_4;                    // [24:27] Reserved
  RESERVED1              : TBits_1;                    // [28:28] Reserved
  RESERVED2              : TBits_1;                    // [29:29] Reserved
  RESERVED3              : TBits_1;                    // [30:30] Reserved
  RESERVED4              : TBits_1;                    // [31:31] Reserved
end;

TCAN0_CS0_bitbanded = record
  TIME_STAMP             : array[0..15] of longWord;   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : array[0..3] of longWord;    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : longWord;                   // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : longWord;                   // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : longWord;                   // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : longWord;                   // [23:23] Reserved
  CODE                   : array[0..3] of longWord;    // [24:27] Reserved
  RESERVED1              : longWord;                   // [28:28] Reserved
  RESERVED2              : longWord;                   // [29:29] Reserved
  RESERVED3              : longWord;                   // [30:30] Reserved
  RESERVED4              : longWord;                   // [31:31] Reserved
end;

TCAN0_ID0_bits = bitpacked record
  EXT                    : TBits_18;                   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : TBits_11;                   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : TBits_3;                    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_ID0_bitbanded = record
  EXT                    : array[0..17] of longWord;   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : array[0..10] of longWord;   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : array[0..2] of longWord;    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_WORD00_bits = bitpacked record
  DATA_BYTE_3            : TBits_8;                    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : TBits_8;                    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : TBits_8;                    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : TBits_8;                    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD00_bitbanded = record
  DATA_BYTE_3            : array[0..7] of longWord;    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : array[0..7] of longWord;    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : array[0..7] of longWord;    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : array[0..7] of longWord;    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD10_bits = bitpacked record
  DATA_BYTE_7            : TBits_8;                    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : TBits_8;                    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : TBits_8;                    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : TBits_8;                    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_WORD10_bitbanded = record
  DATA_BYTE_7            : array[0..7] of longWord;    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : array[0..7] of longWord;    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : array[0..7] of longWord;    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : array[0..7] of longWord;    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_CS1_bits = bitpacked record
  TIME_STAMP             : TBits_16;                   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : TBits_4;                    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : TBits_1;                    // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : TBits_1;                    // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : TBits_1;                    // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : TBits_1;                    // [23:23] Reserved
  CODE                   : TBits_4;                    // [24:27] Reserved
  RESERVED1              : TBits_1;                    // [28:28] Reserved
  RESERVED2              : TBits_1;                    // [29:29] Reserved
  RESERVED3              : TBits_1;                    // [30:30] Reserved
  RESERVED4              : TBits_1;                    // [31:31] Reserved
end;

TCAN0_CS1_bitbanded = record
  TIME_STAMP             : array[0..15] of longWord;   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : array[0..3] of longWord;    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : longWord;                   // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : longWord;                   // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : longWord;                   // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : longWord;                   // [23:23] Reserved
  CODE                   : array[0..3] of longWord;    // [24:27] Reserved
  RESERVED1              : longWord;                   // [28:28] Reserved
  RESERVED2              : longWord;                   // [29:29] Reserved
  RESERVED3              : longWord;                   // [30:30] Reserved
  RESERVED4              : longWord;                   // [31:31] Reserved
end;

TCAN0_ID1_bits = bitpacked record
  EXT                    : TBits_18;                   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : TBits_11;                   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : TBits_3;                    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_ID1_bitbanded = record
  EXT                    : array[0..17] of longWord;   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : array[0..10] of longWord;   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : array[0..2] of longWord;    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_WORD01_bits = bitpacked record
  DATA_BYTE_3            : TBits_8;                    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : TBits_8;                    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : TBits_8;                    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : TBits_8;                    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD01_bitbanded = record
  DATA_BYTE_3            : array[0..7] of longWord;    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : array[0..7] of longWord;    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : array[0..7] of longWord;    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : array[0..7] of longWord;    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD11_bits = bitpacked record
  DATA_BYTE_7            : TBits_8;                    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : TBits_8;                    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : TBits_8;                    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : TBits_8;                    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_WORD11_bitbanded = record
  DATA_BYTE_7            : array[0..7] of longWord;    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : array[0..7] of longWord;    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : array[0..7] of longWord;    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : array[0..7] of longWord;    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_CS2_bits = bitpacked record
  TIME_STAMP             : TBits_16;                   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : TBits_4;                    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : TBits_1;                    // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : TBits_1;                    // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : TBits_1;                    // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : TBits_1;                    // [23:23] Reserved
  CODE                   : TBits_4;                    // [24:27] Reserved
  RESERVED1              : TBits_1;                    // [28:28] Reserved
  RESERVED2              : TBits_1;                    // [29:29] Reserved
  RESERVED3              : TBits_1;                    // [30:30] Reserved
  RESERVED4              : TBits_1;                    // [31:31] Reserved
end;

TCAN0_CS2_bitbanded = record
  TIME_STAMP             : array[0..15] of longWord;   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : array[0..3] of longWord;    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : longWord;                   // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : longWord;                   // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : longWord;                   // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : longWord;                   // [23:23] Reserved
  CODE                   : array[0..3] of longWord;    // [24:27] Reserved
  RESERVED1              : longWord;                   // [28:28] Reserved
  RESERVED2              : longWord;                   // [29:29] Reserved
  RESERVED3              : longWord;                   // [30:30] Reserved
  RESERVED4              : longWord;                   // [31:31] Reserved
end;

TCAN0_ID2_bits = bitpacked record
  EXT                    : TBits_18;                   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : TBits_11;                   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : TBits_3;                    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_ID2_bitbanded = record
  EXT                    : array[0..17] of longWord;   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : array[0..10] of longWord;   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : array[0..2] of longWord;    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_WORD02_bits = bitpacked record
  DATA_BYTE_3            : TBits_8;                    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : TBits_8;                    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : TBits_8;                    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : TBits_8;                    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD02_bitbanded = record
  DATA_BYTE_3            : array[0..7] of longWord;    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : array[0..7] of longWord;    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : array[0..7] of longWord;    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : array[0..7] of longWord;    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD12_bits = bitpacked record
  DATA_BYTE_7            : TBits_8;                    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : TBits_8;                    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : TBits_8;                    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : TBits_8;                    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_WORD12_bitbanded = record
  DATA_BYTE_7            : array[0..7] of longWord;    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : array[0..7] of longWord;    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : array[0..7] of longWord;    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : array[0..7] of longWord;    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_CS3_bits = bitpacked record
  TIME_STAMP             : TBits_16;                   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : TBits_4;                    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : TBits_1;                    // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : TBits_1;                    // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : TBits_1;                    // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : TBits_1;                    // [23:23] Reserved
  CODE                   : TBits_4;                    // [24:27] Reserved
  RESERVED1              : TBits_1;                    // [28:28] Reserved
  RESERVED2              : TBits_1;                    // [29:29] Reserved
  RESERVED3              : TBits_1;                    // [30:30] Reserved
  RESERVED4              : TBits_1;                    // [31:31] Reserved
end;

TCAN0_CS3_bitbanded = record
  TIME_STAMP             : array[0..15] of longWord;   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : array[0..3] of longWord;    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : longWord;                   // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : longWord;                   // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : longWord;                   // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : longWord;                   // [23:23] Reserved
  CODE                   : array[0..3] of longWord;    // [24:27] Reserved
  RESERVED1              : longWord;                   // [28:28] Reserved
  RESERVED2              : longWord;                   // [29:29] Reserved
  RESERVED3              : longWord;                   // [30:30] Reserved
  RESERVED4              : longWord;                   // [31:31] Reserved
end;

TCAN0_ID3_bits = bitpacked record
  EXT                    : TBits_18;                   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : TBits_11;                   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : TBits_3;                    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_ID3_bitbanded = record
  EXT                    : array[0..17] of longWord;   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : array[0..10] of longWord;   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : array[0..2] of longWord;    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_WORD03_bits = bitpacked record
  DATA_BYTE_3            : TBits_8;                    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : TBits_8;                    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : TBits_8;                    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : TBits_8;                    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD03_bitbanded = record
  DATA_BYTE_3            : array[0..7] of longWord;    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : array[0..7] of longWord;    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : array[0..7] of longWord;    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : array[0..7] of longWord;    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD13_bits = bitpacked record
  DATA_BYTE_7            : TBits_8;                    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : TBits_8;                    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : TBits_8;                    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : TBits_8;                    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_WORD13_bitbanded = record
  DATA_BYTE_7            : array[0..7] of longWord;    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : array[0..7] of longWord;    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : array[0..7] of longWord;    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : array[0..7] of longWord;    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_CS4_bits = bitpacked record
  TIME_STAMP             : TBits_16;                   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : TBits_4;                    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : TBits_1;                    // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : TBits_1;                    // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : TBits_1;                    // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : TBits_1;                    // [23:23] Reserved
  CODE                   : TBits_4;                    // [24:27] Reserved
  RESERVED1              : TBits_1;                    // [28:28] Reserved
  RESERVED2              : TBits_1;                    // [29:29] Reserved
  RESERVED3              : TBits_1;                    // [30:30] Reserved
  RESERVED4              : TBits_1;                    // [31:31] Reserved
end;

TCAN0_CS4_bitbanded = record
  TIME_STAMP             : array[0..15] of longWord;   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : array[0..3] of longWord;    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : longWord;                   // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : longWord;                   // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : longWord;                   // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : longWord;                   // [23:23] Reserved
  CODE                   : array[0..3] of longWord;    // [24:27] Reserved
  RESERVED1              : longWord;                   // [28:28] Reserved
  RESERVED2              : longWord;                   // [29:29] Reserved
  RESERVED3              : longWord;                   // [30:30] Reserved
  RESERVED4              : longWord;                   // [31:31] Reserved
end;

TCAN0_ID4_bits = bitpacked record
  EXT                    : TBits_18;                   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : TBits_11;                   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : TBits_3;                    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_ID4_bitbanded = record
  EXT                    : array[0..17] of longWord;   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : array[0..10] of longWord;   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : array[0..2] of longWord;    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_WORD04_bits = bitpacked record
  DATA_BYTE_3            : TBits_8;                    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : TBits_8;                    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : TBits_8;                    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : TBits_8;                    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD04_bitbanded = record
  DATA_BYTE_3            : array[0..7] of longWord;    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : array[0..7] of longWord;    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : array[0..7] of longWord;    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : array[0..7] of longWord;    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD14_bits = bitpacked record
  DATA_BYTE_7            : TBits_8;                    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : TBits_8;                    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : TBits_8;                    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : TBits_8;                    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_WORD14_bitbanded = record
  DATA_BYTE_7            : array[0..7] of longWord;    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : array[0..7] of longWord;    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : array[0..7] of longWord;    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : array[0..7] of longWord;    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_CS5_bits = bitpacked record
  TIME_STAMP             : TBits_16;                   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : TBits_4;                    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : TBits_1;                    // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : TBits_1;                    // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : TBits_1;                    // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : TBits_1;                    // [23:23] Reserved
  CODE                   : TBits_4;                    // [24:27] Reserved
  RESERVED1              : TBits_1;                    // [28:28] Reserved
  RESERVED2              : TBits_1;                    // [29:29] Reserved
  RESERVED3              : TBits_1;                    // [30:30] Reserved
  RESERVED4              : TBits_1;                    // [31:31] Reserved
end;

TCAN0_CS5_bitbanded = record
  TIME_STAMP             : array[0..15] of longWord;   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : array[0..3] of longWord;    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : longWord;                   // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : longWord;                   // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : longWord;                   // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : longWord;                   // [23:23] Reserved
  CODE                   : array[0..3] of longWord;    // [24:27] Reserved
  RESERVED1              : longWord;                   // [28:28] Reserved
  RESERVED2              : longWord;                   // [29:29] Reserved
  RESERVED3              : longWord;                   // [30:30] Reserved
  RESERVED4              : longWord;                   // [31:31] Reserved
end;

TCAN0_ID5_bits = bitpacked record
  EXT                    : TBits_18;                   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : TBits_11;                   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : TBits_3;                    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_ID5_bitbanded = record
  EXT                    : array[0..17] of longWord;   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : array[0..10] of longWord;   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : array[0..2] of longWord;    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_WORD05_bits = bitpacked record
  DATA_BYTE_3            : TBits_8;                    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : TBits_8;                    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : TBits_8;                    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : TBits_8;                    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD05_bitbanded = record
  DATA_BYTE_3            : array[0..7] of longWord;    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : array[0..7] of longWord;    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : array[0..7] of longWord;    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : array[0..7] of longWord;    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD15_bits = bitpacked record
  DATA_BYTE_7            : TBits_8;                    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : TBits_8;                    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : TBits_8;                    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : TBits_8;                    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_WORD15_bitbanded = record
  DATA_BYTE_7            : array[0..7] of longWord;    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : array[0..7] of longWord;    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : array[0..7] of longWord;    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : array[0..7] of longWord;    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_CS6_bits = bitpacked record
  TIME_STAMP             : TBits_16;                   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : TBits_4;                    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : TBits_1;                    // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : TBits_1;                    // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : TBits_1;                    // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : TBits_1;                    // [23:23] Reserved
  CODE                   : TBits_4;                    // [24:27] Reserved
  RESERVED1              : TBits_1;                    // [28:28] Reserved
  RESERVED2              : TBits_1;                    // [29:29] Reserved
  RESERVED3              : TBits_1;                    // [30:30] Reserved
  RESERVED4              : TBits_1;                    // [31:31] Reserved
end;

TCAN0_CS6_bitbanded = record
  TIME_STAMP             : array[0..15] of longWord;   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : array[0..3] of longWord;    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : longWord;                   // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : longWord;                   // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : longWord;                   // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : longWord;                   // [23:23] Reserved
  CODE                   : array[0..3] of longWord;    // [24:27] Reserved
  RESERVED1              : longWord;                   // [28:28] Reserved
  RESERVED2              : longWord;                   // [29:29] Reserved
  RESERVED3              : longWord;                   // [30:30] Reserved
  RESERVED4              : longWord;                   // [31:31] Reserved
end;

TCAN0_ID6_bits = bitpacked record
  EXT                    : TBits_18;                   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : TBits_11;                   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : TBits_3;                    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_ID6_bitbanded = record
  EXT                    : array[0..17] of longWord;   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : array[0..10] of longWord;   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : array[0..2] of longWord;    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_WORD06_bits = bitpacked record
  DATA_BYTE_3            : TBits_8;                    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : TBits_8;                    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : TBits_8;                    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : TBits_8;                    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD06_bitbanded = record
  DATA_BYTE_3            : array[0..7] of longWord;    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : array[0..7] of longWord;    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : array[0..7] of longWord;    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : array[0..7] of longWord;    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD16_bits = bitpacked record
  DATA_BYTE_7            : TBits_8;                    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : TBits_8;                    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : TBits_8;                    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : TBits_8;                    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_WORD16_bitbanded = record
  DATA_BYTE_7            : array[0..7] of longWord;    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : array[0..7] of longWord;    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : array[0..7] of longWord;    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : array[0..7] of longWord;    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_CS7_bits = bitpacked record
  TIME_STAMP             : TBits_16;                   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : TBits_4;                    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : TBits_1;                    // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : TBits_1;                    // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : TBits_1;                    // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : TBits_1;                    // [23:23] Reserved
  CODE                   : TBits_4;                    // [24:27] Reserved
  RESERVED1              : TBits_1;                    // [28:28] Reserved
  RESERVED2              : TBits_1;                    // [29:29] Reserved
  RESERVED3              : TBits_1;                    // [30:30] Reserved
  RESERVED4              : TBits_1;                    // [31:31] Reserved
end;

TCAN0_CS7_bitbanded = record
  TIME_STAMP             : array[0..15] of longWord;   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : array[0..3] of longWord;    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : longWord;                   // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : longWord;                   // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : longWord;                   // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : longWord;                   // [23:23] Reserved
  CODE                   : array[0..3] of longWord;    // [24:27] Reserved
  RESERVED1              : longWord;                   // [28:28] Reserved
  RESERVED2              : longWord;                   // [29:29] Reserved
  RESERVED3              : longWord;                   // [30:30] Reserved
  RESERVED4              : longWord;                   // [31:31] Reserved
end;

TCAN0_ID7_bits = bitpacked record
  EXT                    : TBits_18;                   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : TBits_11;                   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : TBits_3;                    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_ID7_bitbanded = record
  EXT                    : array[0..17] of longWord;   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : array[0..10] of longWord;   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : array[0..2] of longWord;    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_WORD07_bits = bitpacked record
  DATA_BYTE_3            : TBits_8;                    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : TBits_8;                    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : TBits_8;                    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : TBits_8;                    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD07_bitbanded = record
  DATA_BYTE_3            : array[0..7] of longWord;    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : array[0..7] of longWord;    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : array[0..7] of longWord;    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : array[0..7] of longWord;    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD17_bits = bitpacked record
  DATA_BYTE_7            : TBits_8;                    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : TBits_8;                    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : TBits_8;                    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : TBits_8;                    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_WORD17_bitbanded = record
  DATA_BYTE_7            : array[0..7] of longWord;    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : array[0..7] of longWord;    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : array[0..7] of longWord;    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : array[0..7] of longWord;    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_CS8_bits = bitpacked record
  TIME_STAMP             : TBits_16;                   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : TBits_4;                    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : TBits_1;                    // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : TBits_1;                    // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : TBits_1;                    // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : TBits_1;                    // [23:23] Reserved
  CODE                   : TBits_4;                    // [24:27] Reserved
  RESERVED1              : TBits_1;                    // [28:28] Reserved
  RESERVED2              : TBits_1;                    // [29:29] Reserved
  RESERVED3              : TBits_1;                    // [30:30] Reserved
  RESERVED4              : TBits_1;                    // [31:31] Reserved
end;

TCAN0_CS8_bitbanded = record
  TIME_STAMP             : array[0..15] of longWord;   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : array[0..3] of longWord;    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : longWord;                   // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : longWord;                   // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : longWord;                   // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : longWord;                   // [23:23] Reserved
  CODE                   : array[0..3] of longWord;    // [24:27] Reserved
  RESERVED1              : longWord;                   // [28:28] Reserved
  RESERVED2              : longWord;                   // [29:29] Reserved
  RESERVED3              : longWord;                   // [30:30] Reserved
  RESERVED4              : longWord;                   // [31:31] Reserved
end;

TCAN0_ID8_bits = bitpacked record
  EXT                    : TBits_18;                   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : TBits_11;                   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : TBits_3;                    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_ID8_bitbanded = record
  EXT                    : array[0..17] of longWord;   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : array[0..10] of longWord;   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : array[0..2] of longWord;    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_WORD08_bits = bitpacked record
  DATA_BYTE_3            : TBits_8;                    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : TBits_8;                    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : TBits_8;                    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : TBits_8;                    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD08_bitbanded = record
  DATA_BYTE_3            : array[0..7] of longWord;    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : array[0..7] of longWord;    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : array[0..7] of longWord;    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : array[0..7] of longWord;    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD18_bits = bitpacked record
  DATA_BYTE_7            : TBits_8;                    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : TBits_8;                    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : TBits_8;                    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : TBits_8;                    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_WORD18_bitbanded = record
  DATA_BYTE_7            : array[0..7] of longWord;    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : array[0..7] of longWord;    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : array[0..7] of longWord;    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : array[0..7] of longWord;    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_CS9_bits = bitpacked record
  TIME_STAMP             : TBits_16;                   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : TBits_4;                    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : TBits_1;                    // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : TBits_1;                    // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : TBits_1;                    // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : TBits_1;                    // [23:23] Reserved
  CODE                   : TBits_4;                    // [24:27] Reserved
  RESERVED1              : TBits_1;                    // [28:28] Reserved
  RESERVED2              : TBits_1;                    // [29:29] Reserved
  RESERVED3              : TBits_1;                    // [30:30] Reserved
  RESERVED4              : TBits_1;                    // [31:31] Reserved
end;

TCAN0_CS9_bitbanded = record
  TIME_STAMP             : array[0..15] of longWord;   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : array[0..3] of longWord;    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : longWord;                   // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : longWord;                   // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : longWord;                   // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : longWord;                   // [23:23] Reserved
  CODE                   : array[0..3] of longWord;    // [24:27] Reserved
  RESERVED1              : longWord;                   // [28:28] Reserved
  RESERVED2              : longWord;                   // [29:29] Reserved
  RESERVED3              : longWord;                   // [30:30] Reserved
  RESERVED4              : longWord;                   // [31:31] Reserved
end;

TCAN0_ID9_bits = bitpacked record
  EXT                    : TBits_18;                   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : TBits_11;                   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : TBits_3;                    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_ID9_bitbanded = record
  EXT                    : array[0..17] of longWord;   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : array[0..10] of longWord;   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : array[0..2] of longWord;    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_WORD09_bits = bitpacked record
  DATA_BYTE_3            : TBits_8;                    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : TBits_8;                    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : TBits_8;                    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : TBits_8;                    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD09_bitbanded = record
  DATA_BYTE_3            : array[0..7] of longWord;    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : array[0..7] of longWord;    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : array[0..7] of longWord;    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : array[0..7] of longWord;    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD19_bits = bitpacked record
  DATA_BYTE_7            : TBits_8;                    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : TBits_8;                    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : TBits_8;                    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : TBits_8;                    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_WORD19_bitbanded = record
  DATA_BYTE_7            : array[0..7] of longWord;    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : array[0..7] of longWord;    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : array[0..7] of longWord;    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : array[0..7] of longWord;    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_CS10_bits = bitpacked record
  TIME_STAMP             : TBits_16;                   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : TBits_4;                    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : TBits_1;                    // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : TBits_1;                    // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : TBits_1;                    // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : TBits_1;                    // [23:23] Reserved
  CODE                   : TBits_4;                    // [24:27] Reserved
  RESERVED1              : TBits_1;                    // [28:28] Reserved
  RESERVED2              : TBits_1;                    // [29:29] Reserved
  RESERVED3              : TBits_1;                    // [30:30] Reserved
  RESERVED4              : TBits_1;                    // [31:31] Reserved
end;

TCAN0_CS10_bitbanded = record
  TIME_STAMP             : array[0..15] of longWord;   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : array[0..3] of longWord;    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : longWord;                   // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : longWord;                   // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : longWord;                   // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : longWord;                   // [23:23] Reserved
  CODE                   : array[0..3] of longWord;    // [24:27] Reserved
  RESERVED1              : longWord;                   // [28:28] Reserved
  RESERVED2              : longWord;                   // [29:29] Reserved
  RESERVED3              : longWord;                   // [30:30] Reserved
  RESERVED4              : longWord;                   // [31:31] Reserved
end;

TCAN0_ID10_bits = bitpacked record
  EXT                    : TBits_18;                   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : TBits_11;                   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : TBits_3;                    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_ID10_bitbanded = record
  EXT                    : array[0..17] of longWord;   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : array[0..10] of longWord;   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : array[0..2] of longWord;    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_WORD010_bits = bitpacked record
  DATA_BYTE_3            : TBits_8;                    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : TBits_8;                    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : TBits_8;                    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : TBits_8;                    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD010_bitbanded = record
  DATA_BYTE_3            : array[0..7] of longWord;    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : array[0..7] of longWord;    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : array[0..7] of longWord;    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : array[0..7] of longWord;    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD110_bits = bitpacked record
  DATA_BYTE_7            : TBits_8;                    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : TBits_8;                    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : TBits_8;                    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : TBits_8;                    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_WORD110_bitbanded = record
  DATA_BYTE_7            : array[0..7] of longWord;    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : array[0..7] of longWord;    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : array[0..7] of longWord;    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : array[0..7] of longWord;    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_CS11_bits = bitpacked record
  TIME_STAMP             : TBits_16;                   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : TBits_4;                    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : TBits_1;                    // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : TBits_1;                    // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : TBits_1;                    // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : TBits_1;                    // [23:23] Reserved
  CODE                   : TBits_4;                    // [24:27] Reserved
  RESERVED1              : TBits_1;                    // [28:28] Reserved
  RESERVED2              : TBits_1;                    // [29:29] Reserved
  RESERVED3              : TBits_1;                    // [30:30] Reserved
  RESERVED4              : TBits_1;                    // [31:31] Reserved
end;

TCAN0_CS11_bitbanded = record
  TIME_STAMP             : array[0..15] of longWord;   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : array[0..3] of longWord;    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : longWord;                   // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : longWord;                   // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : longWord;                   // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : longWord;                   // [23:23] Reserved
  CODE                   : array[0..3] of longWord;    // [24:27] Reserved
  RESERVED1              : longWord;                   // [28:28] Reserved
  RESERVED2              : longWord;                   // [29:29] Reserved
  RESERVED3              : longWord;                   // [30:30] Reserved
  RESERVED4              : longWord;                   // [31:31] Reserved
end;

TCAN0_ID11_bits = bitpacked record
  EXT                    : TBits_18;                   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : TBits_11;                   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : TBits_3;                    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_ID11_bitbanded = record
  EXT                    : array[0..17] of longWord;   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : array[0..10] of longWord;   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : array[0..2] of longWord;    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_WORD011_bits = bitpacked record
  DATA_BYTE_3            : TBits_8;                    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : TBits_8;                    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : TBits_8;                    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : TBits_8;                    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD011_bitbanded = record
  DATA_BYTE_3            : array[0..7] of longWord;    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : array[0..7] of longWord;    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : array[0..7] of longWord;    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : array[0..7] of longWord;    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD111_bits = bitpacked record
  DATA_BYTE_7            : TBits_8;                    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : TBits_8;                    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : TBits_8;                    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : TBits_8;                    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_WORD111_bitbanded = record
  DATA_BYTE_7            : array[0..7] of longWord;    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : array[0..7] of longWord;    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : array[0..7] of longWord;    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : array[0..7] of longWord;    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_CS12_bits = bitpacked record
  TIME_STAMP             : TBits_16;                   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : TBits_4;                    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : TBits_1;                    // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : TBits_1;                    // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : TBits_1;                    // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : TBits_1;                    // [23:23] Reserved
  CODE                   : TBits_4;                    // [24:27] Reserved
  RESERVED1              : TBits_1;                    // [28:28] Reserved
  RESERVED2              : TBits_1;                    // [29:29] Reserved
  RESERVED3              : TBits_1;                    // [30:30] Reserved
  RESERVED4              : TBits_1;                    // [31:31] Reserved
end;

TCAN0_CS12_bitbanded = record
  TIME_STAMP             : array[0..15] of longWord;   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : array[0..3] of longWord;    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : longWord;                   // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : longWord;                   // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : longWord;                   // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : longWord;                   // [23:23] Reserved
  CODE                   : array[0..3] of longWord;    // [24:27] Reserved
  RESERVED1              : longWord;                   // [28:28] Reserved
  RESERVED2              : longWord;                   // [29:29] Reserved
  RESERVED3              : longWord;                   // [30:30] Reserved
  RESERVED4              : longWord;                   // [31:31] Reserved
end;

TCAN0_ID12_bits = bitpacked record
  EXT                    : TBits_18;                   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : TBits_11;                   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : TBits_3;                    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_ID12_bitbanded = record
  EXT                    : array[0..17] of longWord;   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : array[0..10] of longWord;   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : array[0..2] of longWord;    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_WORD012_bits = bitpacked record
  DATA_BYTE_3            : TBits_8;                    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : TBits_8;                    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : TBits_8;                    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : TBits_8;                    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD012_bitbanded = record
  DATA_BYTE_3            : array[0..7] of longWord;    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : array[0..7] of longWord;    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : array[0..7] of longWord;    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : array[0..7] of longWord;    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD112_bits = bitpacked record
  DATA_BYTE_7            : TBits_8;                    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : TBits_8;                    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : TBits_8;                    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : TBits_8;                    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_WORD112_bitbanded = record
  DATA_BYTE_7            : array[0..7] of longWord;    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : array[0..7] of longWord;    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : array[0..7] of longWord;    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : array[0..7] of longWord;    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_CS13_bits = bitpacked record
  TIME_STAMP             : TBits_16;                   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : TBits_4;                    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : TBits_1;                    // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : TBits_1;                    // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : TBits_1;                    // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : TBits_1;                    // [23:23] Reserved
  CODE                   : TBits_4;                    // [24:27] Reserved
  RESERVED1              : TBits_1;                    // [28:28] Reserved
  RESERVED2              : TBits_1;                    // [29:29] Reserved
  RESERVED3              : TBits_1;                    // [30:30] Reserved
  RESERVED4              : TBits_1;                    // [31:31] Reserved
end;

TCAN0_CS13_bitbanded = record
  TIME_STAMP             : array[0..15] of longWord;   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : array[0..3] of longWord;    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : longWord;                   // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : longWord;                   // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : longWord;                   // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : longWord;                   // [23:23] Reserved
  CODE                   : array[0..3] of longWord;    // [24:27] Reserved
  RESERVED1              : longWord;                   // [28:28] Reserved
  RESERVED2              : longWord;                   // [29:29] Reserved
  RESERVED3              : longWord;                   // [30:30] Reserved
  RESERVED4              : longWord;                   // [31:31] Reserved
end;

TCAN0_ID13_bits = bitpacked record
  EXT                    : TBits_18;                   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : TBits_11;                   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : TBits_3;                    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_ID13_bitbanded = record
  EXT                    : array[0..17] of longWord;   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : array[0..10] of longWord;   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : array[0..2] of longWord;    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_WORD013_bits = bitpacked record
  DATA_BYTE_3            : TBits_8;                    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : TBits_8;                    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : TBits_8;                    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : TBits_8;                    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD013_bitbanded = record
  DATA_BYTE_3            : array[0..7] of longWord;    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : array[0..7] of longWord;    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : array[0..7] of longWord;    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : array[0..7] of longWord;    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD113_bits = bitpacked record
  DATA_BYTE_7            : TBits_8;                    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : TBits_8;                    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : TBits_8;                    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : TBits_8;                    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_WORD113_bitbanded = record
  DATA_BYTE_7            : array[0..7] of longWord;    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : array[0..7] of longWord;    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : array[0..7] of longWord;    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : array[0..7] of longWord;    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_CS14_bits = bitpacked record
  TIME_STAMP             : TBits_16;                   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : TBits_4;                    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : TBits_1;                    // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : TBits_1;                    // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : TBits_1;                    // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : TBits_1;                    // [23:23] Reserved
  CODE                   : TBits_4;                    // [24:27] Reserved
  RESERVED1              : TBits_1;                    // [28:28] Reserved
  RESERVED2              : TBits_1;                    // [29:29] Reserved
  RESERVED3              : TBits_1;                    // [30:30] Reserved
  RESERVED4              : TBits_1;                    // [31:31] Reserved
end;

TCAN0_CS14_bitbanded = record
  TIME_STAMP             : array[0..15] of longWord;   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : array[0..3] of longWord;    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : longWord;                   // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : longWord;                   // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : longWord;                   // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : longWord;                   // [23:23] Reserved
  CODE                   : array[0..3] of longWord;    // [24:27] Reserved
  RESERVED1              : longWord;                   // [28:28] Reserved
  RESERVED2              : longWord;                   // [29:29] Reserved
  RESERVED3              : longWord;                   // [30:30] Reserved
  RESERVED4              : longWord;                   // [31:31] Reserved
end;

TCAN0_ID14_bits = bitpacked record
  EXT                    : TBits_18;                   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : TBits_11;                   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : TBits_3;                    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_ID14_bitbanded = record
  EXT                    : array[0..17] of longWord;   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : array[0..10] of longWord;   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : array[0..2] of longWord;    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_WORD014_bits = bitpacked record
  DATA_BYTE_3            : TBits_8;                    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : TBits_8;                    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : TBits_8;                    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : TBits_8;                    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD014_bitbanded = record
  DATA_BYTE_3            : array[0..7] of longWord;    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : array[0..7] of longWord;    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : array[0..7] of longWord;    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : array[0..7] of longWord;    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD114_bits = bitpacked record
  DATA_BYTE_7            : TBits_8;                    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : TBits_8;                    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : TBits_8;                    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : TBits_8;                    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_WORD114_bitbanded = record
  DATA_BYTE_7            : array[0..7] of longWord;    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : array[0..7] of longWord;    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : array[0..7] of longWord;    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : array[0..7] of longWord;    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_CS15_bits = bitpacked record
  TIME_STAMP             : TBits_16;                   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : TBits_4;                    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : TBits_1;                    // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : TBits_1;                    // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : TBits_1;                    // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : TBits_1;                    // [23:23] Reserved
  CODE                   : TBits_4;                    // [24:27] Reserved
  RESERVED1              : TBits_1;                    // [28:28] Reserved
  RESERVED2              : TBits_1;                    // [29:29] Reserved
  RESERVED3              : TBits_1;                    // [30:30] Reserved
  RESERVED4              : TBits_1;                    // [31:31] Reserved
end;

TCAN0_CS15_bitbanded = record
  TIME_STAMP             : array[0..15] of longWord;   // [0:15] Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.
  DLC                    : array[0..3] of longWord;    // [16:19] Length of the data to be stored/transmitted.
  RTR                    : longWord;                   // [20:20] Remote Transmission Request. One/zero for remote/data frame.
  IDE                    : longWord;                   // [21:21] ID Extended. One/zero for extended/standard format frame.
  SRR                    : longWord;                   // [22:22] Substitute Remote Request. Contains a fixed recessive bit.
  RESERVED0              : longWord;                   // [23:23] Reserved
  CODE                   : array[0..3] of longWord;    // [24:27] Reserved
  RESERVED1              : longWord;                   // [28:28] Reserved
  RESERVED2              : longWord;                   // [29:29] Reserved
  RESERVED3              : longWord;                   // [30:30] Reserved
  RESERVED4              : longWord;                   // [31:31] Reserved
end;

TCAN0_ID15_bits = bitpacked record
  EXT                    : TBits_18;                   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : TBits_11;                   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : TBits_3;                    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_ID15_bitbanded = record
  EXT                    : array[0..17] of longWord;   // [0:17] Contains extended (LOW word) identifier of message buffer.
  STD                    : array[0..10] of longWord;   // [18:28] Contains standard/extended (HIGH word) identifier of message buffer.
  PRIO                   : array[0..2] of longWord;    // [29:31] Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
end;

TCAN0_WORD015_bits = bitpacked record
  DATA_BYTE_3            : TBits_8;                    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : TBits_8;                    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : TBits_8;                    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : TBits_8;                    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD015_bitbanded = record
  DATA_BYTE_3            : array[0..7] of longWord;    // [0:7] Data byte 3 of Rx/Tx frame.
  DATA_BYTE_2            : array[0..7] of longWord;    // [8:15] Data byte 2 of Rx/Tx frame.
  DATA_BYTE_1            : array[0..7] of longWord;    // [16:23] Data byte 1 of Rx/Tx frame.
  DATA_BYTE_0            : array[0..7] of longWord;    // [24:31] Data byte 0 of Rx/Tx frame.
end;

TCAN0_WORD115_bits = bitpacked record
  DATA_BYTE_7            : TBits_8;                    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : TBits_8;                    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : TBits_8;                    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : TBits_8;                    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_WORD115_bitbanded = record
  DATA_BYTE_7            : array[0..7] of longWord;    // [0:7] Data byte 7 of Rx/Tx frame.
  DATA_BYTE_6            : array[0..7] of longWord;    // [8:15] Data byte 6 of Rx/Tx frame.
  DATA_BYTE_5            : array[0..7] of longWord;    // [16:23] Data byte 5 of Rx/Tx frame.
  DATA_BYTE_4            : array[0..7] of longWord;    // [24:31] Data byte 4 of Rx/Tx frame.
end;

TCAN0_RXIMR_bits = bitpacked record
  MI                     : TBits_32;                   // [0:31] Individual Mask Bits
end;

TCAN0_RXIMR_bitbanded = record
  MI                     : array[0..31] of longWord;   // [0:31] Individual Mask Bits
end;

TCAN0_Registers = record
  case boolean of false: (
  MCR                    : longWord;                   // 0x00 Module Configuration Register
  CTRL1                  : longWord;                   // 0x04 Control 1 Register
  TIMER                  : longWord;                   // 0x08 Free Running Timer
  RESERVED0              : longWord;                   // 0x0C
  RXMGMASK               : longWord;                   // 0x10 Rx Mailboxes Global Mask Register
  RX14MASK               : longWord;                   // 0x14 Rx 14 Mask Register
  RX15MASK               : longWord;                   // 0x18 Rx 15 Mask Register
  ECR                    : longWord;                   // 0x1C Error Counter
  ESR1                   : longWord;                   // 0x20 Error and Status 1 Register
  IMASK2                 : longWord;                   // 0x24 Interrupt Masks 2 Register
  IMASK1                 : longWord;                   // 0x28 Interrupt Masks 1 Register
  IFLAG2                 : longWord;                   // 0x2C Interrupt Flags 2 Register
  IFLAG1                 : longWord;                   // 0x30 Interrupt Flags 1 Register
  CTRL2                  : longWord;                   // 0x34 Control 2 Register
  ESR2                   : longWord;                   // 0x38 Error and Status 2 Register
  RESERVED1              : array[0..1] of longWord;    // 0x3C
  CRCR                   : longWord;                   // 0x44 CRC Register
  RXFGMASK               : longWord;                   // 0x48 Rx FIFO Global Mask Register
  RXFIR                  : longWord;                   // 0x4C Rx FIFO Information Register
  RESERVED2              : array[0..11] of longWord;   // 0x50
  CS0                    : longWord;                   // 0x80 Message Buffer 0 CS Register
  ID0                    : longWord;                   // 0x84 Message Buffer 0 ID Register
  WORD00                 : longWord;                   // 0x88 Message Buffer 0 WORD0 Register
  WORD10                 : longWord;                   // 0x8C Message Buffer 0 WORD1 Register
  CS1                    : longWord;                   // 0x90 Message Buffer 1 CS Register
  ID1                    : longWord;                   // 0x94 Message Buffer 1 ID Register
  WORD01                 : longWord;                   // 0x98 Message Buffer 1 WORD0 Register
  WORD11                 : longWord;                   // 0x9C Message Buffer 1 WORD1 Register
  CS2                    : longWord;                   // 0xA0 Message Buffer 2 CS Register
  ID2                    : longWord;                   // 0xA4 Message Buffer 2 ID Register
  WORD02                 : longWord;                   // 0xA8 Message Buffer 2 WORD0 Register
  WORD12                 : longWord;                   // 0xAC Message Buffer 2 WORD1 Register
  CS3                    : longWord;                   // 0xB0 Message Buffer 3 CS Register
  ID3                    : longWord;                   // 0xB4 Message Buffer 3 ID Register
  WORD03                 : longWord;                   // 0xB8 Message Buffer 3 WORD0 Register
  WORD13                 : longWord;                   // 0xBC Message Buffer 3 WORD1 Register
  CS4                    : longWord;                   // 0xC0 Message Buffer 4 CS Register
  ID4                    : longWord;                   // 0xC4 Message Buffer 4 ID Register
  WORD04                 : longWord;                   // 0xC8 Message Buffer 4 WORD0 Register
  WORD14                 : longWord;                   // 0xCC Message Buffer 4 WORD1 Register
  CS5                    : longWord;                   // 0xD0 Message Buffer 5 CS Register
  ID5                    : longWord;                   // 0xD4 Message Buffer 5 ID Register
  WORD05                 : longWord;                   // 0xD8 Message Buffer 5 WORD0 Register
  WORD15                 : longWord;                   // 0xDC Message Buffer 5 WORD1 Register
  CS6                    : longWord;                   // 0xE0 Message Buffer 6 CS Register
  ID6                    : longWord;                   // 0xE4 Message Buffer 6 ID Register
  WORD06                 : longWord;                   // 0xE8 Message Buffer 6 WORD0 Register
  WORD16                 : longWord;                   // 0xEC Message Buffer 6 WORD1 Register
  CS7                    : longWord;                   // 0xF0 Message Buffer 7 CS Register
  ID7                    : longWord;                   // 0xF4 Message Buffer 7 ID Register
  WORD07                 : longWord;                   // 0xF8 Message Buffer 7 WORD0 Register
  WORD17                 : longWord;                   // 0xFC Message Buffer 7 WORD1 Register
  CS8                    : longWord;                   // 0x100 Message Buffer 8 CS Register
  ID8                    : longWord;                   // 0x104 Message Buffer 8 ID Register
  WORD08                 : longWord;                   // 0x108 Message Buffer 8 WORD0 Register
  WORD18                 : longWord;                   // 0x10C Message Buffer 8 WORD1 Register
  CS9                    : longWord;                   // 0x110 Message Buffer 9 CS Register
  ID9                    : longWord;                   // 0x114 Message Buffer 9 ID Register
  WORD09                 : longWord;                   // 0x118 Message Buffer 9 WORD0 Register
  WORD19                 : longWord;                   // 0x11C Message Buffer 9 WORD1 Register
  CS10                   : longWord;                   // 0x120 Message Buffer 10 CS Register
  ID10                   : longWord;                   // 0x124 Message Buffer 10 ID Register
  WORD010                : longWord;                   // 0x128 Message Buffer 10 WORD0 Register
  WORD110                : longWord;                   // 0x12C Message Buffer 10 WORD1 Register
  CS11                   : longWord;                   // 0x130 Message Buffer 11 CS Register
  ID11                   : longWord;                   // 0x134 Message Buffer 11 ID Register
  WORD011                : longWord;                   // 0x138 Message Buffer 11 WORD0 Register
  WORD111                : longWord;                   // 0x13C Message Buffer 11 WORD1 Register
  CS12                   : longWord;                   // 0x140 Message Buffer 12 CS Register
  ID12                   : longWord;                   // 0x144 Message Buffer 12 ID Register
  WORD012                : longWord;                   // 0x148 Message Buffer 12 WORD0 Register
  WORD112                : longWord;                   // 0x14C Message Buffer 12 WORD1 Register
  CS13                   : longWord;                   // 0x150 Message Buffer 13 CS Register
  ID13                   : longWord;                   // 0x154 Message Buffer 13 ID Register
  WORD013                : longWord;                   // 0x158 Message Buffer 13 WORD0 Register
  WORD113                : longWord;                   // 0x15C Message Buffer 13 WORD1 Register
  CS14                   : longWord;                   // 0x160 Message Buffer 14 CS Register
  ID14                   : longWord;                   // 0x164 Message Buffer 14 ID Register
  WORD014                : longWord;                   // 0x168 Message Buffer 14 WORD0 Register
  WORD114                : longWord;                   // 0x16C Message Buffer 14 WORD1 Register
  CS15                   : longWord;                   // 0x170 Message Buffer 15 CS Register
  ID15                   : longWord;                   // 0x174 Message Buffer 15 ID Register
  WORD015                : longWord;                   // 0x178 Message Buffer 15 WORD0 Register
  WORD115                : longWord;                   // 0x17C Message Buffer 15 WORD1 Register
  RESERVED3              : array[0..447] of longWord;  // 0x180
  RXIMR0                 : longWord;                   // 0x880 Rx Individual Mask Registers
  RXIMR1                 : longWord;                   // 0x884 Rx Individual Mask Registers
  RXIMR2                 : longWord;                   // 0x888 Rx Individual Mask Registers
  RXIMR3                 : longWord;                   // 0x88C Rx Individual Mask Registers
  RXIMR4                 : longWord;                   // 0x890 Rx Individual Mask Registers
  RXIMR5                 : longWord;                   // 0x894 Rx Individual Mask Registers
  RXIMR6                 : longWord;                   // 0x898 Rx Individual Mask Registers
  RXIMR7                 : longWord;                   // 0x89C Rx Individual Mask Registers
  RXIMR8                 : longWord;                   // 0x8A0 Rx Individual Mask Registers
  RXIMR9                 : longWord;                   // 0x8A4 Rx Individual Mask Registers
  RXIMR10                : longWord;                   // 0x8A8 Rx Individual Mask Registers
  RXIMR11                : longWord;                   // 0x8AC Rx Individual Mask Registers
  RXIMR12                : longWord;                   // 0x8B0 Rx Individual Mask Registers
  RXIMR13                : longWord;                   // 0x8B4 Rx Individual Mask Registers
  RXIMR14                : longWord;                   // 0x8B8 Rx Individual Mask Registers
  RXIMR15                : longWord;                   // 0x8BC Rx Individual Mask Registers
);
true : (
MCR_bits                 : TCAN0_MCR_bits;             // 0x04 Module Configuration Register
CTRL1_bits               : TCAN0_CTRL1_bits;           // 0x08 Control 1 Register
TIMER_bits               : TCAN0_TIMER_bits;           // 0x0C Free Running Timer
RESERVED_bits0           : longWord;
RXMGMASK_bits            : TCAN0_RXMGMASK_bits;        // 0x14 Rx Mailboxes Global Mask Register
RX14MASK_bits            : TCAN0_RX14MASK_bits;        // 0x18 Rx 14 Mask Register
RX15MASK_bits            : TCAN0_RX15MASK_bits;        // 0x1C Rx 15 Mask Register
ECR_bits                 : TCAN0_ECR_bits;             // 0x20 Error Counter
ESR1_bits                : TCAN0_ESR1_bits;            // 0x24 Error and Status 1 Register
IMASK2_bits              : TCAN0_IMASK2_bits;          // 0x28 Interrupt Masks 2 Register
IMASK1_bits              : TCAN0_IMASK1_bits;          // 0x2C Interrupt Masks 1 Register
IFLAG2_bits              : TCAN0_IFLAG2_bits;          // 0x30 Interrupt Flags 2 Register
IFLAG1_bits              : TCAN0_IFLAG1_bits;          // 0x34 Interrupt Flags 1 Register
CTRL2_bits               : TCAN0_CTRL2_bits;           // 0x38 Control 2 Register
ESR2_bits                : TCAN0_ESR2_bits;            // 0x3C Error and Status 2 Register
RESERVED_bits1           : array[0..1] of longWord;
CRCR_bits                : TCAN0_CRCR_bits;            // 0x48 CRC Register
RXFGMASK_bits            : TCAN0_RXFGMASK_bits;        // 0x4C Rx FIFO Global Mask Register
RXFIR_bits               : TCAN0_RXFIR_bits;           // 0x50 Rx FIFO Information Register
RESERVED_bits2           : array[0..11] of longWord;
CS0_bits                 : TCAN0_CS0_bits;             // 0x84 Message Buffer 0 CS Register
ID0_bits                 : TCAN0_ID0_bits;             // 0x88 Message Buffer 0 ID Register
WORD00_bits              : TCAN0_WORD00_bits;          // 0x8C Message Buffer 0 WORD0 Register
WORD10_bits              : TCAN0_WORD10_bits;          // 0x90 Message Buffer 0 WORD1 Register
CS1_bits                 : TCAN0_CS1_bits;             // 0x94 Message Buffer 1 CS Register
ID1_bits                 : TCAN0_ID1_bits;             // 0x98 Message Buffer 1 ID Register
WORD01_bits              : TCAN0_WORD01_bits;          // 0x9C Message Buffer 1 WORD0 Register
WORD11_bits              : TCAN0_WORD11_bits;          // 0xA0 Message Buffer 1 WORD1 Register
CS2_bits                 : TCAN0_CS2_bits;             // 0xA4 Message Buffer 2 CS Register
ID2_bits                 : TCAN0_ID2_bits;             // 0xA8 Message Buffer 2 ID Register
WORD02_bits              : TCAN0_WORD02_bits;          // 0xAC Message Buffer 2 WORD0 Register
WORD12_bits              : TCAN0_WORD12_bits;          // 0xB0 Message Buffer 2 WORD1 Register
CS3_bits                 : TCAN0_CS3_bits;             // 0xB4 Message Buffer 3 CS Register
ID3_bits                 : TCAN0_ID3_bits;             // 0xB8 Message Buffer 3 ID Register
WORD03_bits              : TCAN0_WORD03_bits;          // 0xBC Message Buffer 3 WORD0 Register
WORD13_bits              : TCAN0_WORD13_bits;          // 0xC0 Message Buffer 3 WORD1 Register
CS4_bits                 : TCAN0_CS4_bits;             // 0xC4 Message Buffer 4 CS Register
ID4_bits                 : TCAN0_ID4_bits;             // 0xC8 Message Buffer 4 ID Register
WORD04_bits              : TCAN0_WORD04_bits;          // 0xCC Message Buffer 4 WORD0 Register
WORD14_bits              : TCAN0_WORD14_bits;          // 0xD0 Message Buffer 4 WORD1 Register
CS5_bits                 : TCAN0_CS5_bits;             // 0xD4 Message Buffer 5 CS Register
ID5_bits                 : TCAN0_ID5_bits;             // 0xD8 Message Buffer 5 ID Register
WORD05_bits              : TCAN0_WORD05_bits;          // 0xDC Message Buffer 5 WORD0 Register
WORD15_bits              : TCAN0_WORD15_bits;          // 0xE0 Message Buffer 5 WORD1 Register
CS6_bits                 : TCAN0_CS6_bits;             // 0xE4 Message Buffer 6 CS Register
ID6_bits                 : TCAN0_ID6_bits;             // 0xE8 Message Buffer 6 ID Register
WORD06_bits              : TCAN0_WORD06_bits;          // 0xEC Message Buffer 6 WORD0 Register
WORD16_bits              : TCAN0_WORD16_bits;          // 0xF0 Message Buffer 6 WORD1 Register
CS7_bits                 : TCAN0_CS7_bits;             // 0xF4 Message Buffer 7 CS Register
ID7_bits                 : TCAN0_ID7_bits;             // 0xF8 Message Buffer 7 ID Register
WORD07_bits              : TCAN0_WORD07_bits;          // 0xFC Message Buffer 7 WORD0 Register
WORD17_bits              : TCAN0_WORD17_bits;          // 0x100 Message Buffer 7 WORD1 Register
CS8_bits                 : TCAN0_CS8_bits;             // 0x104 Message Buffer 8 CS Register
ID8_bits                 : TCAN0_ID8_bits;             // 0x108 Message Buffer 8 ID Register
WORD08_bits              : TCAN0_WORD08_bits;          // 0x10C Message Buffer 8 WORD0 Register
WORD18_bits              : TCAN0_WORD18_bits;          // 0x110 Message Buffer 8 WORD1 Register
CS9_bits                 : TCAN0_CS9_bits;             // 0x114 Message Buffer 9 CS Register
ID9_bits                 : TCAN0_ID9_bits;             // 0x118 Message Buffer 9 ID Register
WORD09_bits              : TCAN0_WORD09_bits;          // 0x11C Message Buffer 9 WORD0 Register
WORD19_bits              : TCAN0_WORD19_bits;          // 0x120 Message Buffer 9 WORD1 Register
CS10_bits                : TCAN0_CS10_bits;            // 0x124 Message Buffer 10 CS Register
ID10_bits                : TCAN0_ID10_bits;            // 0x128 Message Buffer 10 ID Register
WORD010_bits             : TCAN0_WORD010_bits;         // 0x12C Message Buffer 10 WORD0 Register
WORD110_bits             : TCAN0_WORD110_bits;         // 0x130 Message Buffer 10 WORD1 Register
CS11_bits                : TCAN0_CS11_bits;            // 0x134 Message Buffer 11 CS Register
ID11_bits                : TCAN0_ID11_bits;            // 0x138 Message Buffer 11 ID Register
WORD011_bits             : TCAN0_WORD011_bits;         // 0x13C Message Buffer 11 WORD0 Register
WORD111_bits             : TCAN0_WORD111_bits;         // 0x140 Message Buffer 11 WORD1 Register
CS12_bits                : TCAN0_CS12_bits;            // 0x144 Message Buffer 12 CS Register
ID12_bits                : TCAN0_ID12_bits;            // 0x148 Message Buffer 12 ID Register
WORD012_bits             : TCAN0_WORD012_bits;         // 0x14C Message Buffer 12 WORD0 Register
WORD112_bits             : TCAN0_WORD112_bits;         // 0x150 Message Buffer 12 WORD1 Register
CS13_bits                : TCAN0_CS13_bits;            // 0x154 Message Buffer 13 CS Register
ID13_bits                : TCAN0_ID13_bits;            // 0x158 Message Buffer 13 ID Register
WORD013_bits             : TCAN0_WORD013_bits;         // 0x15C Message Buffer 13 WORD0 Register
WORD113_bits             : TCAN0_WORD113_bits;         // 0x160 Message Buffer 13 WORD1 Register
CS14_bits                : TCAN0_CS14_bits;            // 0x164 Message Buffer 14 CS Register
ID14_bits                : TCAN0_ID14_bits;            // 0x168 Message Buffer 14 ID Register
WORD014_bits             : TCAN0_WORD014_bits;         // 0x16C Message Buffer 14 WORD0 Register
WORD114_bits             : TCAN0_WORD114_bits;         // 0x170 Message Buffer 14 WORD1 Register
CS15_bits                : TCAN0_CS15_bits;            // 0x174 Message Buffer 15 CS Register
ID15_bits                : TCAN0_ID15_bits;            // 0x178 Message Buffer 15 ID Register
WORD015_bits             : TCAN0_WORD015_bits;         // 0x17C Message Buffer 15 WORD0 Register
WORD115_bits             : TCAN0_WORD115_bits;         // 0x180 Message Buffer 15 WORD1 Register
RESERVED_bits3           : array[0..447] of longWord;
RXIMR0_bits              : TCAN0_RXIMR_bits;           // 0x884 Rx Individual Mask Registers
RXIMR1_bits              : TCAN0_RXIMR_bits;           // 0x888 Rx Individual Mask Registers
RXIMR2_bits              : TCAN0_RXIMR_bits;           // 0x88C Rx Individual Mask Registers
RXIMR3_bits              : TCAN0_RXIMR_bits;           // 0x890 Rx Individual Mask Registers
RXIMR4_bits              : TCAN0_RXIMR_bits;           // 0x894 Rx Individual Mask Registers
RXIMR5_bits              : TCAN0_RXIMR_bits;           // 0x898 Rx Individual Mask Registers
RXIMR6_bits              : TCAN0_RXIMR_bits;           // 0x89C Rx Individual Mask Registers
RXIMR7_bits              : TCAN0_RXIMR_bits;           // 0x8A0 Rx Individual Mask Registers
RXIMR8_bits              : TCAN0_RXIMR_bits;           // 0x8A4 Rx Individual Mask Registers
RXIMR9_bits              : TCAN0_RXIMR_bits;           // 0x8A8 Rx Individual Mask Registers
RXIMR10_bits             : TCAN0_RXIMR_bits;           // 0x8AC Rx Individual Mask Registers
RXIMR11_bits             : TCAN0_RXIMR_bits;           // 0x8B0 Rx Individual Mask Registers
RXIMR12_bits             : TCAN0_RXIMR_bits;           // 0x8B4 Rx Individual Mask Registers
RXIMR13_bits             : TCAN0_RXIMR_bits;           // 0x8B8 Rx Individual Mask Registers
RXIMR14_bits             : TCAN0_RXIMR_bits;           // 0x8BC Rx Individual Mask Registers
RXIMR15_bits             : TCAN0_RXIMR_bits;           // 0x8C0 Rx Individual Mask Registers
);
end;

TCAN0Registers_bitbanded = record
  MCR                    : TCAN0_MCR_bitbanded;        // 0x04 Module Configuration Register
  CTRL1                  : TCAN0_CTRL1_bitbanded;      // 0x08 Control 1 Register
  TIMER                  : TCAN0_TIMER_bitbanded;      // 0x0C Free Running Timer
  RESERVED0              : array[0..3] of array[0..7] of longWord;
  RXMGMASK               : TCAN0_RXMGMASK_bitbanded;   // 0x14 Rx Mailboxes Global Mask Register
  RX14MASK               : TCAN0_RX14MASK_bitbanded;   // 0x18 Rx 14 Mask Register
  RX15MASK               : TCAN0_RX15MASK_bitbanded;   // 0x1C Rx 15 Mask Register
  ECR                    : TCAN0_ECR_bitbanded;        // 0x20 Error Counter
  ESR1                   : TCAN0_ESR1_bitbanded;       // 0x24 Error and Status 1 Register
  IMASK2                 : TCAN0_IMASK2_bitbanded;     // 0x28 Interrupt Masks 2 Register
  IMASK1                 : TCAN0_IMASK1_bitbanded;     // 0x2C Interrupt Masks 1 Register
  IFLAG2                 : TCAN0_IFLAG2_bitbanded;     // 0x30 Interrupt Flags 2 Register
  IFLAG1                 : TCAN0_IFLAG1_bitbanded;     // 0x34 Interrupt Flags 1 Register
  CTRL2                  : TCAN0_CTRL2_bitbanded;      // 0x38 Control 2 Register
  ESR2                   : TCAN0_ESR2_bitbanded;       // 0x3C Error and Status 2 Register
  RESERVED1              : array[0..7] of array[0..7] of longWord;
  CRCR                   : TCAN0_CRCR_bitbanded;       // 0x48 CRC Register
  RXFGMASK               : TCAN0_RXFGMASK_bitbanded;   // 0x4C Rx FIFO Global Mask Register
  RXFIR                  : TCAN0_RXFIR_bitbanded;      // 0x50 Rx FIFO Information Register
  RESERVED2              : array[0..47] of array[0..7] of longWord;
  CS0                    : TCAN0_CS0_bitbanded;        // 0x84 Message Buffer 0 CS Register
  ID0                    : TCAN0_ID0_bitbanded;        // 0x88 Message Buffer 0 ID Register
  WORD00                 : TCAN0_WORD00_bitbanded;     // 0x8C Message Buffer 0 WORD0 Register
  WORD10                 : TCAN0_WORD10_bitbanded;     // 0x90 Message Buffer 0 WORD1 Register
  CS1                    : TCAN0_CS1_bitbanded;        // 0x94 Message Buffer 1 CS Register
  ID1                    : TCAN0_ID1_bitbanded;        // 0x98 Message Buffer 1 ID Register
  WORD01                 : TCAN0_WORD01_bitbanded;     // 0x9C Message Buffer 1 WORD0 Register
  WORD11                 : TCAN0_WORD11_bitbanded;     // 0xA0 Message Buffer 1 WORD1 Register
  CS2                    : TCAN0_CS2_bitbanded;        // 0xA4 Message Buffer 2 CS Register
  ID2                    : TCAN0_ID2_bitbanded;        // 0xA8 Message Buffer 2 ID Register
  WORD02                 : TCAN0_WORD02_bitbanded;     // 0xAC Message Buffer 2 WORD0 Register
  WORD12                 : TCAN0_WORD12_bitbanded;     // 0xB0 Message Buffer 2 WORD1 Register
  CS3                    : TCAN0_CS3_bitbanded;        // 0xB4 Message Buffer 3 CS Register
  ID3                    : TCAN0_ID3_bitbanded;        // 0xB8 Message Buffer 3 ID Register
  WORD03                 : TCAN0_WORD03_bitbanded;     // 0xBC Message Buffer 3 WORD0 Register
  WORD13                 : TCAN0_WORD13_bitbanded;     // 0xC0 Message Buffer 3 WORD1 Register
  CS4                    : TCAN0_CS4_bitbanded;        // 0xC4 Message Buffer 4 CS Register
  ID4                    : TCAN0_ID4_bitbanded;        // 0xC8 Message Buffer 4 ID Register
  WORD04                 : TCAN0_WORD04_bitbanded;     // 0xCC Message Buffer 4 WORD0 Register
  WORD14                 : TCAN0_WORD14_bitbanded;     // 0xD0 Message Buffer 4 WORD1 Register
  CS5                    : TCAN0_CS5_bitbanded;        // 0xD4 Message Buffer 5 CS Register
  ID5                    : TCAN0_ID5_bitbanded;        // 0xD8 Message Buffer 5 ID Register
  WORD05                 : TCAN0_WORD05_bitbanded;     // 0xDC Message Buffer 5 WORD0 Register
  WORD15                 : TCAN0_WORD15_bitbanded;     // 0xE0 Message Buffer 5 WORD1 Register
  CS6                    : TCAN0_CS6_bitbanded;        // 0xE4 Message Buffer 6 CS Register
  ID6                    : TCAN0_ID6_bitbanded;        // 0xE8 Message Buffer 6 ID Register
  WORD06                 : TCAN0_WORD06_bitbanded;     // 0xEC Message Buffer 6 WORD0 Register
  WORD16                 : TCAN0_WORD16_bitbanded;     // 0xF0 Message Buffer 6 WORD1 Register
  CS7                    : TCAN0_CS7_bitbanded;        // 0xF4 Message Buffer 7 CS Register
  ID7                    : TCAN0_ID7_bitbanded;        // 0xF8 Message Buffer 7 ID Register
  WORD07                 : TCAN0_WORD07_bitbanded;     // 0xFC Message Buffer 7 WORD0 Register
  WORD17                 : TCAN0_WORD17_bitbanded;     // 0x100 Message Buffer 7 WORD1 Register
  CS8                    : TCAN0_CS8_bitbanded;        // 0x104 Message Buffer 8 CS Register
  ID8                    : TCAN0_ID8_bitbanded;        // 0x108 Message Buffer 8 ID Register
  WORD08                 : TCAN0_WORD08_bitbanded;     // 0x10C Message Buffer 8 WORD0 Register
  WORD18                 : TCAN0_WORD18_bitbanded;     // 0x110 Message Buffer 8 WORD1 Register
  CS9                    : TCAN0_CS9_bitbanded;        // 0x114 Message Buffer 9 CS Register
  ID9                    : TCAN0_ID9_bitbanded;        // 0x118 Message Buffer 9 ID Register
  WORD09                 : TCAN0_WORD09_bitbanded;     // 0x11C Message Buffer 9 WORD0 Register
  WORD19                 : TCAN0_WORD19_bitbanded;     // 0x120 Message Buffer 9 WORD1 Register
  CS10                   : TCAN0_CS10_bitbanded;       // 0x124 Message Buffer 10 CS Register
  ID10                   : TCAN0_ID10_bitbanded;       // 0x128 Message Buffer 10 ID Register
  WORD010                : TCAN0_WORD010_bitbanded;    // 0x12C Message Buffer 10 WORD0 Register
  WORD110                : TCAN0_WORD110_bitbanded;    // 0x130 Message Buffer 10 WORD1 Register
  CS11                   : TCAN0_CS11_bitbanded;       // 0x134 Message Buffer 11 CS Register
  ID11                   : TCAN0_ID11_bitbanded;       // 0x138 Message Buffer 11 ID Register
  WORD011                : TCAN0_WORD011_bitbanded;    // 0x13C Message Buffer 11 WORD0 Register
  WORD111                : TCAN0_WORD111_bitbanded;    // 0x140 Message Buffer 11 WORD1 Register
  CS12                   : TCAN0_CS12_bitbanded;       // 0x144 Message Buffer 12 CS Register
  ID12                   : TCAN0_ID12_bitbanded;       // 0x148 Message Buffer 12 ID Register
  WORD012                : TCAN0_WORD012_bitbanded;    // 0x14C Message Buffer 12 WORD0 Register
  WORD112                : TCAN0_WORD112_bitbanded;    // 0x150 Message Buffer 12 WORD1 Register
  CS13                   : TCAN0_CS13_bitbanded;       // 0x154 Message Buffer 13 CS Register
  ID13                   : TCAN0_ID13_bitbanded;       // 0x158 Message Buffer 13 ID Register
  WORD013                : TCAN0_WORD013_bitbanded;    // 0x15C Message Buffer 13 WORD0 Register
  WORD113                : TCAN0_WORD113_bitbanded;    // 0x160 Message Buffer 13 WORD1 Register
  CS14                   : TCAN0_CS14_bitbanded;       // 0x164 Message Buffer 14 CS Register
  ID14                   : TCAN0_ID14_bitbanded;       // 0x168 Message Buffer 14 ID Register
  WORD014                : TCAN0_WORD014_bitbanded;    // 0x16C Message Buffer 14 WORD0 Register
  WORD114                : TCAN0_WORD114_bitbanded;    // 0x170 Message Buffer 14 WORD1 Register
  CS15                   : TCAN0_CS15_bitbanded;       // 0x174 Message Buffer 15 CS Register
  ID15                   : TCAN0_ID15_bitbanded;       // 0x178 Message Buffer 15 ID Register
  WORD015                : TCAN0_WORD015_bitbanded;    // 0x17C Message Buffer 15 WORD0 Register
  WORD115                : TCAN0_WORD115_bitbanded;    // 0x180 Message Buffer 15 WORD1 Register
  RESERVED3              : array[0..1791] of array[0..7] of longWord;
  RXIMR0                 : TCAN0_RXIMR_bitbanded;      // 0x884 Rx Individual Mask Registers
  RXIMR1                 : TCAN0_RXIMR_bitbanded;      // 0x888 Rx Individual Mask Registers
  RXIMR2                 : TCAN0_RXIMR_bitbanded;      // 0x88C Rx Individual Mask Registers
  RXIMR3                 : TCAN0_RXIMR_bitbanded;      // 0x890 Rx Individual Mask Registers
  RXIMR4                 : TCAN0_RXIMR_bitbanded;      // 0x894 Rx Individual Mask Registers
  RXIMR5                 : TCAN0_RXIMR_bitbanded;      // 0x898 Rx Individual Mask Registers
  RXIMR6                 : TCAN0_RXIMR_bitbanded;      // 0x89C Rx Individual Mask Registers
  RXIMR7                 : TCAN0_RXIMR_bitbanded;      // 0x8A0 Rx Individual Mask Registers
  RXIMR8                 : TCAN0_RXIMR_bitbanded;      // 0x8A4 Rx Individual Mask Registers
  RXIMR9                 : TCAN0_RXIMR_bitbanded;      // 0x8A8 Rx Individual Mask Registers
  RXIMR10                : TCAN0_RXIMR_bitbanded;      // 0x8AC Rx Individual Mask Registers
  RXIMR11                : TCAN0_RXIMR_bitbanded;      // 0x8B0 Rx Individual Mask Registers
  RXIMR12                : TCAN0_RXIMR_bitbanded;      // 0x8B4 Rx Individual Mask Registers
  RXIMR13                : TCAN0_RXIMR_bitbanded;      // 0x8B8 Rx Individual Mask Registers
  RXIMR14                : TCAN0_RXIMR_bitbanded;      // 0x8BC Rx Individual Mask Registers
  RXIMR15                : TCAN0_RXIMR_bitbanded;      // 0x8C0 Rx Individual Mask Registers
end;

// High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
TCMP0_CR0_bits = bitpacked record
  HYSTCTR                : TBits_2;                    // [0:1] Comparator hard block hysteresis control
  RESERVED0              : TBits_1;                    // [2:2] no description available
  RESERVED1              : TBits_1;                    // [3:3] no description available
  FILTER_CNT             : TBits_3;                    // [4:6] Filter Sample Count
  RESERVED2              : TBits_1;                    // [7:7] no description available
end;

TCMP0_CR0_bitbanded = record
  HYSTCTR                : array[0..1] of longWord;    // [0:1] Comparator hard block hysteresis control
  RESERVED0              : longWord;                   // [2:2] no description available
  RESERVED1              : longWord;                   // [3:3] no description available
  FILTER_CNT             : array[0..2] of longWord;    // [4:6] Filter Sample Count
  RESERVED2              : longWord;                   // [7:7] no description available
end;

TCMP0_CR1_bits = bitpacked record
  EN                     : TBits_1;                    // [0:0] Comparator Module Enable
  OPE                    : TBits_1;                    // [1:1] Comparator Output Pin Enable
  COS                    : TBits_1;                    // [2:2] Comparator Output Select
  INV                    : TBits_1;                    // [3:3] Comparator INVERT
  PMODE                  : TBits_1;                    // [4:4] Power Mode Select
  RESERVED0              : TBits_1;                    // [5:5] no description available
  WE                     : TBits_1;                    // [6:6] Windowing Enable
  SE                     : TBits_1;                    // [7:7] Sample Enable
end;

TCMP0_CR1_bitbanded = record
  EN                     : longWord;                   // [0:0] Comparator Module Enable
  OPE                    : longWord;                   // [1:1] Comparator Output Pin Enable
  COS                    : longWord;                   // [2:2] Comparator Output Select
  INV                    : longWord;                   // [3:3] Comparator INVERT
  PMODE                  : longWord;                   // [4:4] Power Mode Select
  RESERVED0              : longWord;                   // [5:5] no description available
  WE                     : longWord;                   // [6:6] Windowing Enable
  SE                     : longWord;                   // [7:7] Sample Enable
end;

TCMP0_FPR_bits = bitpacked record
  FILT_PER               : TBits_8;                    // [0:7] Filter Sample Period
end;

TCMP0_FPR_bitbanded = record
  FILT_PER               : array[0..7] of longWord;    // [0:7] Filter Sample Period
end;

TCMP0_SCR_bits = bitpacked record
  COUT                   : TBits_1;                    // [0:0] Analog Comparator Output
  CFF                    : TBits_1;                    // [1:1] Analog Comparator Flag Falling
  CFR                    : TBits_1;                    // [2:2] Analog Comparator Flag Rising
  IEF                    : TBits_1;                    // [3:3] Comparator Interrupt Enable Falling
  IER                    : TBits_1;                    // [4:4] Comparator Interrupt Enable Rising
  RESERVED0              : TBits_1;                    // [5:5] no description available
  DMAEN                  : TBits_1;                    // [6:6] DMA Enable Control
  RESERVED1              : TBits_1;                    // [7:7] no description available
end;

TCMP0_SCR_bitbanded = record
  COUT                   : longWord;                   // [0:0] Analog Comparator Output
  CFF                    : longWord;                   // [1:1] Analog Comparator Flag Falling
  CFR                    : longWord;                   // [2:2] Analog Comparator Flag Rising
  IEF                    : longWord;                   // [3:3] Comparator Interrupt Enable Falling
  IER                    : longWord;                   // [4:4] Comparator Interrupt Enable Rising
  RESERVED0              : longWord;                   // [5:5] no description available
  DMAEN                  : longWord;                   // [6:6] DMA Enable Control
  RESERVED1              : longWord;                   // [7:7] no description available
end;

TCMP0_DACCR_bits = bitpacked record
  VOSEL                  : TBits_6;                    // [0:5] DAC Output Voltage Select
  VRSEL                  : TBits_1;                    // [6:6] Supply Voltage Reference Source Select
  DACEN                  : TBits_1;                    // [7:7] DAC Enable
end;

TCMP0_DACCR_bitbanded = record
  VOSEL                  : array[0..5] of longWord;    // [0:5] DAC Output Voltage Select
  VRSEL                  : longWord;                   // [6:6] Supply Voltage Reference Source Select
  DACEN                  : longWord;                   // [7:7] DAC Enable
end;

TCMP0_MUXCR_bits = bitpacked record
  MSEL                   : TBits_3;                    // [0:2] Minus Input MUX Control
  PSEL                   : TBits_3;                    // [3:5] Plus Input MUX Control
  RESERVED0              : TBits_2;                    // [6:7] no description available
end;

TCMP0_MUXCR_bitbanded = record
  MSEL                   : array[0..2] of longWord;    // [0:2] Minus Input MUX Control
  PSEL                   : array[0..2] of longWord;    // [3:5] Plus Input MUX Control
  RESERVED0              : array[0..1] of longWord;    // [6:7] no description available
end;

TCMP0_Registers = record
  case boolean of false: (
  CR0                    : byte;                       // 0x00 CMP Control Register 0
  CR1                    : byte;                       // 0x01 CMP Control Register 1
  FPR                    : byte;                       // 0x02 CMP Filter Period Register
  SCR                    : byte;                       // 0x03 CMP Status and Control Register
  DACCR                  : byte;                       // 0x04 DAC Control Register
  MUXCR                  : byte;                       // 0x05 MUX Control Register
);
true : (
CR0_bits                 : TCMP0_CR0_bits;             // 0x01 CMP Control Register 0
CR1_bits                 : TCMP0_CR1_bits;             // 0x02 CMP Control Register 1
FPR_bits                 : TCMP0_FPR_bits;             // 0x03 CMP Filter Period Register
SCR_bits                 : TCMP0_SCR_bits;             // 0x04 CMP Status and Control Register
DACCR_bits               : TCMP0_DACCR_bits;           // 0x05 DAC Control Register
MUXCR_bits               : TCMP0_MUXCR_bits;           // 0x06 MUX Control Register
);
end;

TCMP0Registers_bitbanded = record
  CR0                    : TCMP0_CR0_bitbanded;        // 0x01 CMP Control Register 0
  CR1                    : TCMP0_CR1_bitbanded;        // 0x02 CMP Control Register 1
  FPR                    : TCMP0_FPR_bitbanded;        // 0x03 CMP Filter Period Register
  SCR                    : TCMP0_SCR_bitbanded;        // 0x04 CMP Status and Control Register
  DACCR                  : TCMP0_DACCR_bitbanded;      // 0x05 DAC Control Register
  MUXCR                  : TCMP0_MUXCR_bitbanded;      // 0x06 MUX Control Register
end;

// High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
TCMP1_CR0_bits = bitpacked record
  HYSTCTR                : TBits_2;                    // [0:1] Comparator hard block hysteresis control
  RESERVED0              : TBits_1;                    // [2:2] no description available
  RESERVED1              : TBits_1;                    // [3:3] no description available
  FILTER_CNT             : TBits_3;                    // [4:6] Filter Sample Count
  RESERVED2              : TBits_1;                    // [7:7] no description available
end;

TCMP1_CR0_bitbanded = record
  HYSTCTR                : array[0..1] of longWord;    // [0:1] Comparator hard block hysteresis control
  RESERVED0              : longWord;                   // [2:2] no description available
  RESERVED1              : longWord;                   // [3:3] no description available
  FILTER_CNT             : array[0..2] of longWord;    // [4:6] Filter Sample Count
  RESERVED2              : longWord;                   // [7:7] no description available
end;

TCMP1_CR1_bits = bitpacked record
  EN                     : TBits_1;                    // [0:0] Comparator Module Enable
  OPE                    : TBits_1;                    // [1:1] Comparator Output Pin Enable
  COS                    : TBits_1;                    // [2:2] Comparator Output Select
  INV                    : TBits_1;                    // [3:3] Comparator INVERT
  PMODE                  : TBits_1;                    // [4:4] Power Mode Select
  RESERVED0              : TBits_1;                    // [5:5] no description available
  WE                     : TBits_1;                    // [6:6] Windowing Enable
  SE                     : TBits_1;                    // [7:7] Sample Enable
end;

TCMP1_CR1_bitbanded = record
  EN                     : longWord;                   // [0:0] Comparator Module Enable
  OPE                    : longWord;                   // [1:1] Comparator Output Pin Enable
  COS                    : longWord;                   // [2:2] Comparator Output Select
  INV                    : longWord;                   // [3:3] Comparator INVERT
  PMODE                  : longWord;                   // [4:4] Power Mode Select
  RESERVED0              : longWord;                   // [5:5] no description available
  WE                     : longWord;                   // [6:6] Windowing Enable
  SE                     : longWord;                   // [7:7] Sample Enable
end;

TCMP1_FPR_bits = bitpacked record
  FILT_PER               : TBits_8;                    // [0:7] Filter Sample Period
end;

TCMP1_FPR_bitbanded = record
  FILT_PER               : array[0..7] of longWord;    // [0:7] Filter Sample Period
end;

TCMP1_SCR_bits = bitpacked record
  COUT                   : TBits_1;                    // [0:0] Analog Comparator Output
  CFF                    : TBits_1;                    // [1:1] Analog Comparator Flag Falling
  CFR                    : TBits_1;                    // [2:2] Analog Comparator Flag Rising
  IEF                    : TBits_1;                    // [3:3] Comparator Interrupt Enable Falling
  IER                    : TBits_1;                    // [4:4] Comparator Interrupt Enable Rising
  RESERVED0              : TBits_1;                    // [5:5] no description available
  DMAEN                  : TBits_1;                    // [6:6] DMA Enable Control
  RESERVED1              : TBits_1;                    // [7:7] no description available
end;

TCMP1_SCR_bitbanded = record
  COUT                   : longWord;                   // [0:0] Analog Comparator Output
  CFF                    : longWord;                   // [1:1] Analog Comparator Flag Falling
  CFR                    : longWord;                   // [2:2] Analog Comparator Flag Rising
  IEF                    : longWord;                   // [3:3] Comparator Interrupt Enable Falling
  IER                    : longWord;                   // [4:4] Comparator Interrupt Enable Rising
  RESERVED0              : longWord;                   // [5:5] no description available
  DMAEN                  : longWord;                   // [6:6] DMA Enable Control
  RESERVED1              : longWord;                   // [7:7] no description available
end;

TCMP1_DACCR_bits = bitpacked record
  VOSEL                  : TBits_6;                    // [0:5] DAC Output Voltage Select
  VRSEL                  : TBits_1;                    // [6:6] Supply Voltage Reference Source Select
  DACEN                  : TBits_1;                    // [7:7] DAC Enable
end;

TCMP1_DACCR_bitbanded = record
  VOSEL                  : array[0..5] of longWord;    // [0:5] DAC Output Voltage Select
  VRSEL                  : longWord;                   // [6:6] Supply Voltage Reference Source Select
  DACEN                  : longWord;                   // [7:7] DAC Enable
end;

TCMP1_MUXCR_bits = bitpacked record
  MSEL                   : TBits_3;                    // [0:2] Minus Input MUX Control
  PSEL                   : TBits_3;                    // [3:5] Plus Input MUX Control
  RESERVED0              : TBits_2;                    // [6:7] no description available
end;

TCMP1_MUXCR_bitbanded = record
  MSEL                   : array[0..2] of longWord;    // [0:2] Minus Input MUX Control
  PSEL                   : array[0..2] of longWord;    // [3:5] Plus Input MUX Control
  RESERVED0              : array[0..1] of longWord;    // [6:7] no description available
end;

TCMP1_Registers = record
  case boolean of false: (
  CR0                    : byte;                       // 0x00 CMP Control Register 0
  CR1                    : byte;                       // 0x01 CMP Control Register 1
  FPR                    : byte;                       // 0x02 CMP Filter Period Register
  SCR                    : byte;                       // 0x03 CMP Status and Control Register
  DACCR                  : byte;                       // 0x04 DAC Control Register
  MUXCR                  : byte;                       // 0x05 MUX Control Register
);
true : (
CR0_bits                 : TCMP1_CR0_bits;             // 0x01 CMP Control Register 0
CR1_bits                 : TCMP1_CR1_bits;             // 0x02 CMP Control Register 1
FPR_bits                 : TCMP1_FPR_bits;             // 0x03 CMP Filter Period Register
SCR_bits                 : TCMP1_SCR_bits;             // 0x04 CMP Status and Control Register
DACCR_bits               : TCMP1_DACCR_bits;           // 0x05 DAC Control Register
MUXCR_bits               : TCMP1_MUXCR_bits;           // 0x06 MUX Control Register
);
end;

TCMP1Registers_bitbanded = record
  CR0                    : TCMP1_CR0_bitbanded;        // 0x01 CMP Control Register 0
  CR1                    : TCMP1_CR1_bitbanded;        // 0x02 CMP Control Register 1
  FPR                    : TCMP1_FPR_bitbanded;        // 0x03 CMP Filter Period Register
  SCR                    : TCMP1_SCR_bitbanded;        // 0x04 CMP Status and Control Register
  DACCR                  : TCMP1_DACCR_bitbanded;      // 0x05 DAC Control Register
  MUXCR                  : TCMP1_MUXCR_bitbanded;      // 0x06 MUX Control Register
end;

// High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
TCMP2_CR0_bits = bitpacked record
  HYSTCTR                : TBits_2;                    // [0:1] Comparator hard block hysteresis control
  RESERVED0              : TBits_1;                    // [2:2] no description available
  RESERVED1              : TBits_1;                    // [3:3] no description available
  FILTER_CNT             : TBits_3;                    // [4:6] Filter Sample Count
  RESERVED2              : TBits_1;                    // [7:7] no description available
end;

TCMP2_CR0_bitbanded = record
  HYSTCTR                : array[0..1] of longWord;    // [0:1] Comparator hard block hysteresis control
  RESERVED0              : longWord;                   // [2:2] no description available
  RESERVED1              : longWord;                   // [3:3] no description available
  FILTER_CNT             : array[0..2] of longWord;    // [4:6] Filter Sample Count
  RESERVED2              : longWord;                   // [7:7] no description available
end;

TCMP2_CR1_bits = bitpacked record
  EN                     : TBits_1;                    // [0:0] Comparator Module Enable
  OPE                    : TBits_1;                    // [1:1] Comparator Output Pin Enable
  COS                    : TBits_1;                    // [2:2] Comparator Output Select
  INV                    : TBits_1;                    // [3:3] Comparator INVERT
  PMODE                  : TBits_1;                    // [4:4] Power Mode Select
  RESERVED0              : TBits_1;                    // [5:5] no description available
  WE                     : TBits_1;                    // [6:6] Windowing Enable
  SE                     : TBits_1;                    // [7:7] Sample Enable
end;

TCMP2_CR1_bitbanded = record
  EN                     : longWord;                   // [0:0] Comparator Module Enable
  OPE                    : longWord;                   // [1:1] Comparator Output Pin Enable
  COS                    : longWord;                   // [2:2] Comparator Output Select
  INV                    : longWord;                   // [3:3] Comparator INVERT
  PMODE                  : longWord;                   // [4:4] Power Mode Select
  RESERVED0              : longWord;                   // [5:5] no description available
  WE                     : longWord;                   // [6:6] Windowing Enable
  SE                     : longWord;                   // [7:7] Sample Enable
end;

TCMP2_FPR_bits = bitpacked record
  FILT_PER               : TBits_8;                    // [0:7] Filter Sample Period
end;

TCMP2_FPR_bitbanded = record
  FILT_PER               : array[0..7] of longWord;    // [0:7] Filter Sample Period
end;

TCMP2_SCR_bits = bitpacked record
  COUT                   : TBits_1;                    // [0:0] Analog Comparator Output
  CFF                    : TBits_1;                    // [1:1] Analog Comparator Flag Falling
  CFR                    : TBits_1;                    // [2:2] Analog Comparator Flag Rising
  IEF                    : TBits_1;                    // [3:3] Comparator Interrupt Enable Falling
  IER                    : TBits_1;                    // [4:4] Comparator Interrupt Enable Rising
  RESERVED0              : TBits_1;                    // [5:5] no description available
  DMAEN                  : TBits_1;                    // [6:6] DMA Enable Control
  RESERVED1              : TBits_1;                    // [7:7] no description available
end;

TCMP2_SCR_bitbanded = record
  COUT                   : longWord;                   // [0:0] Analog Comparator Output
  CFF                    : longWord;                   // [1:1] Analog Comparator Flag Falling
  CFR                    : longWord;                   // [2:2] Analog Comparator Flag Rising
  IEF                    : longWord;                   // [3:3] Comparator Interrupt Enable Falling
  IER                    : longWord;                   // [4:4] Comparator Interrupt Enable Rising
  RESERVED0              : longWord;                   // [5:5] no description available
  DMAEN                  : longWord;                   // [6:6] DMA Enable Control
  RESERVED1              : longWord;                   // [7:7] no description available
end;

TCMP2_DACCR_bits = bitpacked record
  VOSEL                  : TBits_6;                    // [0:5] DAC Output Voltage Select
  VRSEL                  : TBits_1;                    // [6:6] Supply Voltage Reference Source Select
  DACEN                  : TBits_1;                    // [7:7] DAC Enable
end;

TCMP2_DACCR_bitbanded = record
  VOSEL                  : array[0..5] of longWord;    // [0:5] DAC Output Voltage Select
  VRSEL                  : longWord;                   // [6:6] Supply Voltage Reference Source Select
  DACEN                  : longWord;                   // [7:7] DAC Enable
end;

TCMP2_MUXCR_bits = bitpacked record
  MSEL                   : TBits_3;                    // [0:2] Minus Input MUX Control
  PSEL                   : TBits_3;                    // [3:5] Plus Input MUX Control
  RESERVED0              : TBits_2;                    // [6:7] no description available
end;

TCMP2_MUXCR_bitbanded = record
  MSEL                   : array[0..2] of longWord;    // [0:2] Minus Input MUX Control
  PSEL                   : array[0..2] of longWord;    // [3:5] Plus Input MUX Control
  RESERVED0              : array[0..1] of longWord;    // [6:7] no description available
end;

TCMP2_Registers = record
  case boolean of false: (
  CR0                    : byte;                       // 0x00 CMP Control Register 0
  CR1                    : byte;                       // 0x01 CMP Control Register 1
  FPR                    : byte;                       // 0x02 CMP Filter Period Register
  SCR                    : byte;                       // 0x03 CMP Status and Control Register
  DACCR                  : byte;                       // 0x04 DAC Control Register
  MUXCR                  : byte;                       // 0x05 MUX Control Register
);
true : (
CR0_bits                 : TCMP2_CR0_bits;             // 0x01 CMP Control Register 0
CR1_bits                 : TCMP2_CR1_bits;             // 0x02 CMP Control Register 1
FPR_bits                 : TCMP2_FPR_bits;             // 0x03 CMP Filter Period Register
SCR_bits                 : TCMP2_SCR_bits;             // 0x04 CMP Status and Control Register
DACCR_bits               : TCMP2_DACCR_bits;           // 0x05 DAC Control Register
MUXCR_bits               : TCMP2_MUXCR_bits;           // 0x06 MUX Control Register
);
end;

TCMP2Registers_bitbanded = record
  CR0                    : TCMP2_CR0_bitbanded;        // 0x01 CMP Control Register 0
  CR1                    : TCMP2_CR1_bitbanded;        // 0x02 CMP Control Register 1
  FPR                    : TCMP2_FPR_bitbanded;        // 0x03 CMP Filter Period Register
  SCR                    : TCMP2_SCR_bitbanded;        // 0x04 CMP Status and Control Register
  DACCR                  : TCMP2_DACCR_bitbanded;      // 0x05 DAC Control Register
  MUXCR                  : TCMP2_MUXCR_bitbanded;      // 0x06 MUX Control Register
end;

// Carrier Modulator Transmitter
TCMT_CGH1_bits = bitpacked record
  PH                     : TBits_8;                    // [0:7] Primary Carrier High Time Data Value
end;

TCMT_CGH1_bitbanded = record
  PH                     : array[0..7] of longWord;    // [0:7] Primary Carrier High Time Data Value
end;

TCMT_CGL1_bits = bitpacked record
  PL                     : TBits_8;                    // [0:7] Primary Carrier Low Time Data Value
end;

TCMT_CGL1_bitbanded = record
  PL                     : array[0..7] of longWord;    // [0:7] Primary Carrier Low Time Data Value
end;

TCMT_CGH2_bits = bitpacked record
  SH                     : TBits_8;                    // [0:7] Secondary Carrier High Time Data Value
end;

TCMT_CGH2_bitbanded = record
  SH                     : array[0..7] of longWord;    // [0:7] Secondary Carrier High Time Data Value
end;

TCMT_CGL2_bits = bitpacked record
  SL                     : TBits_8;                    // [0:7] Secondary Carrier Low Time Data Value
end;

TCMT_CGL2_bitbanded = record
  SL                     : array[0..7] of longWord;    // [0:7] Secondary Carrier Low Time Data Value
end;

TCMT_OC_bits = bitpacked record
  RESERVED0              : TBits_5;                    // [0:4] no description available
  IROPEN                 : TBits_1;                    // [5:5] IRO Pin Enable
  CMTPOL                 : TBits_1;                    // [6:6] CMT Output Polarity
  IROL                   : TBits_1;                    // [7:7] IRO Latch Control
end;

TCMT_OC_bitbanded = record
  RESERVED0              : array[0..4] of longWord;    // [0:4] no description available
  IROPEN                 : longWord;                   // [5:5] IRO Pin Enable
  CMTPOL                 : longWord;                   // [6:6] CMT Output Polarity
  IROL                   : longWord;                   // [7:7] IRO Latch Control
end;

TCMT_MSC_bits = bitpacked record
  MCGEN                  : TBits_1;                    // [0:0] Modulator and Carrier Generator Enable
  EOCIE                  : TBits_1;                    // [1:1] End of Cycle Interrupt Enable
  FSK                    : TBits_1;                    // [2:2] FSK Mode Select
  BASE                   : TBits_1;                    // [3:3] Baseband Enable
  EXSPC                  : TBits_1;                    // [4:4] Extended Space Enable
  CMTDIV                 : TBits_2;                    // [5:6] CMT Clock Divide Prescaler
  EOCF                   : TBits_1;                    // [7:7] End Of Cycle Status Flag
end;

TCMT_MSC_bitbanded = record
  MCGEN                  : longWord;                   // [0:0] Modulator and Carrier Generator Enable
  EOCIE                  : longWord;                   // [1:1] End of Cycle Interrupt Enable
  FSK                    : longWord;                   // [2:2] FSK Mode Select
  BASE                   : longWord;                   // [3:3] Baseband Enable
  EXSPC                  : longWord;                   // [4:4] Extended Space Enable
  CMTDIV                 : array[0..1] of longWord;    // [5:6] CMT Clock Divide Prescaler
  EOCF                   : longWord;                   // [7:7] End Of Cycle Status Flag
end;

TCMT_CMD1_bits = bitpacked record
  MB                     : TBits_8;                    // [0:7] no description available
end;

TCMT_CMD1_bitbanded = record
  MB                     : array[0..7] of longWord;    // [0:7] no description available
end;

TCMT_CMD2_bits = bitpacked record
  MB                     : TBits_8;                    // [0:7] no description available
end;

TCMT_CMD2_bitbanded = record
  MB                     : array[0..7] of longWord;    // [0:7] no description available
end;

TCMT_CMD3_bits = bitpacked record
  SB                     : TBits_8;                    // [0:7] no description available
end;

TCMT_CMD3_bitbanded = record
  SB                     : array[0..7] of longWord;    // [0:7] no description available
end;

TCMT_CMD4_bits = bitpacked record
  SB                     : TBits_8;                    // [0:7] no description available
end;

TCMT_CMD4_bitbanded = record
  SB                     : array[0..7] of longWord;    // [0:7] no description available
end;

TCMT_PPS_bits = bitpacked record
  PPSDIV                 : TBits_4;                    // [0:3] Primary Prescaler Divider
  RESERVED0              : TBits_4;                    // [4:7] no description available
end;

TCMT_PPS_bitbanded = record
  PPSDIV                 : array[0..3] of longWord;    // [0:3] Primary Prescaler Divider
  RESERVED0              : array[0..3] of longWord;    // [4:7] no description available
end;

TCMT_DMA_bits = bitpacked record
  DMA                    : TBits_1;                    // [0:0] DMA Enable
  RESERVED0              : TBits_7;                    // [1:7] no description available
end;

TCMT_DMA_bitbanded = record
  DMA                    : longWord;                   // [0:0] DMA Enable
  RESERVED0              : array[0..6] of longWord;    // [1:7] no description available
end;

TCMT_Registers = record
  case boolean of false: (
  CGH1                   : byte;                       // 0x00 CMT Carrier Generator High Data Register 1
  CGL1                   : byte;                       // 0x01 CMT Carrier Generator Low Data Register 1
  CGH2                   : byte;                       // 0x02 CMT Carrier Generator High Data Register 2
  CGL2                   : byte;                       // 0x03 CMT Carrier Generator Low Data Register 2
  OC                     : byte;                       // 0x04 CMT Output Control Register
  MSC                    : byte;                       // 0x05 CMT Modulator Status and Control Register
  CMD1                   : byte;                       // 0x06 CMT Modulator Data Register Mark High
  CMD2                   : byte;                       // 0x07 CMT Modulator Data Register Mark Low
  CMD3                   : byte;                       // 0x08 CMT Modulator Data Register Space High
  CMD4                   : byte;                       // 0x09 CMT Modulator Data Register Space Low
  PPS                    : byte;                       // 0x0A CMT Primary Prescaler Register
  DMA                    : byte;                       // 0x0B CMT Direct Memory Access
);
true : (
CGH1_bits                : TCMT_CGH1_bits;             // 0x01 CMT Carrier Generator High Data Register 1
CGL1_bits                : TCMT_CGL1_bits;             // 0x02 CMT Carrier Generator Low Data Register 1
CGH2_bits                : TCMT_CGH2_bits;             // 0x03 CMT Carrier Generator High Data Register 2
CGL2_bits                : TCMT_CGL2_bits;             // 0x04 CMT Carrier Generator Low Data Register 2
OC_bits                  : TCMT_OC_bits;               // 0x05 CMT Output Control Register
MSC_bits                 : TCMT_MSC_bits;              // 0x06 CMT Modulator Status and Control Register
CMD1_bits                : TCMT_CMD1_bits;             // 0x07 CMT Modulator Data Register Mark High
CMD2_bits                : TCMT_CMD2_bits;             // 0x08 CMT Modulator Data Register Mark Low
CMD3_bits                : TCMT_CMD3_bits;             // 0x09 CMT Modulator Data Register Space High
CMD4_bits                : TCMT_CMD4_bits;             // 0x0A CMT Modulator Data Register Space Low
PPS_bits                 : TCMT_PPS_bits;              // 0x0B CMT Primary Prescaler Register
DMA_bits                 : TCMT_DMA_bits;              // 0x0C CMT Direct Memory Access
);
end;

TCMTRegisters_bitbanded = record
  CGH1                   : TCMT_CGH1_bitbanded;        // 0x01 CMT Carrier Generator High Data Register 1
  CGL1                   : TCMT_CGL1_bitbanded;        // 0x02 CMT Carrier Generator Low Data Register 1
  CGH2                   : TCMT_CGH2_bitbanded;        // 0x03 CMT Carrier Generator High Data Register 2
  CGL2                   : TCMT_CGL2_bitbanded;        // 0x04 CMT Carrier Generator Low Data Register 2
  OC                     : TCMT_OC_bitbanded;          // 0x05 CMT Output Control Register
  MSC                    : TCMT_MSC_bitbanded;         // 0x06 CMT Modulator Status and Control Register
  CMD1                   : TCMT_CMD1_bitbanded;        // 0x07 CMT Modulator Data Register Mark High
  CMD2                   : TCMT_CMD2_bitbanded;        // 0x08 CMT Modulator Data Register Mark Low
  CMD3                   : TCMT_CMD3_bitbanded;        // 0x09 CMT Modulator Data Register Space High
  CMD4                   : TCMT_CMD4_bitbanded;        // 0x0A CMT Modulator Data Register Space Low
  PPS                    : TCMT_PPS_bitbanded;         // 0x0B CMT Primary Prescaler Register
  DMA                    : TCMT_DMA_bitbanded;         // 0x0C CMT Direct Memory Access
end;

// Cyclic Redundancy Check
TCRC_CRCLL_bits = bitpacked record
  CRCLL                  : TBits_8;                    // [0:7] CRCLL stores the first 8 bits of the 32 bit CRC
end;

TCRC_CRCLL_bitbanded = record
  CRCLL                  : array[0..7] of longWord;    // [0:7] CRCLL stores the first 8 bits of the 32 bit CRC
end;

TCRC_CRC_bits = bitpacked record
  LL                     : TBits_8;                    // [0:7] CRC Low Lower Byte
  LU                     : TBits_8;                    // [8:15] CRC Low Upper Byte
  HL                     : TBits_8;                    // [16:23] CRC High Lower Byte
  HU                     : TBits_8;                    // [24:31] CRC High Upper Byte
end;

TCRC_CRC_bitbanded = record
  LL                     : array[0..7] of longWord;    // [0:7] CRC Low Lower Byte
  LU                     : array[0..7] of longWord;    // [8:15] CRC Low Upper Byte
  HL                     : array[0..7] of longWord;    // [16:23] CRC High Lower Byte
  HU                     : array[0..7] of longWord;    // [24:31] CRC High Upper Byte
end;

TCRC_CRCL_bits = bitpacked record
  CRCL                   : TBits_16;                   // [0:15] CRCL stores the lower 16 bits of the 16/32 bit CRC
end;

TCRC_CRCL_bitbanded = record
  CRCL                   : array[0..15] of longWord;   // [0:15] CRCL stores the lower 16 bits of the 16/32 bit CRC
end;

TCRC_CRCLU_bits = bitpacked record
  CRCLU                  : TBits_8;                    // [0:7] CRCLL stores the second 8 bits of the 32 bit CRC
end;

TCRC_CRCLU_bitbanded = record
  CRCLU                  : array[0..7] of longWord;    // [0:7] CRCLL stores the second 8 bits of the 32 bit CRC
end;

TCRC_CRCHL_bits = bitpacked record
  CRCHL                  : TBits_8;                    // [0:7] CRCHL stores the third 8 bits of the 32 bit CRC
end;

TCRC_CRCHL_bitbanded = record
  CRCHL                  : array[0..7] of longWord;    // [0:7] CRCHL stores the third 8 bits of the 32 bit CRC
end;

TCRC_CRCH_bits = bitpacked record
  CRCH                   : TBits_16;                   // [0:15] CRCL stores the high 16 bits of the 16/32 bit CRC
end;

TCRC_CRCH_bitbanded = record
  CRCH                   : array[0..15] of longWord;   // [0:15] CRCL stores the high 16 bits of the 16/32 bit CRC
end;

TCRC_CRCHU_bits = bitpacked record
  CRCHU                  : TBits_8;                    // [0:7] CRCHU stores the fourth 8 bits of the 32 bit CRC
end;

TCRC_CRCHU_bitbanded = record
  CRCHU                  : array[0..7] of longWord;    // [0:7] CRCHU stores the fourth 8 bits of the 32 bit CRC
end;

TCRC_GPOLY_bits = bitpacked record
  LOW                    : TBits_16;                   // [0:15] Low polynominal half-word
  HIGH                   : TBits_16;                   // [16:31] High polynominal half-word
end;

TCRC_GPOLY_bitbanded = record
  LOW                    : array[0..15] of longWord;   // [0:15] Low polynominal half-word
  HIGH                   : array[0..15] of longWord;   // [16:31] High polynominal half-word
end;

TCRC_GPOLYLL_bits = bitpacked record
  GPOLYLL                : TBits_8;                    // [0:7] POLYLL stores the first 8 bits of the 32 bit CRC
end;

TCRC_GPOLYLL_bitbanded = record
  GPOLYLL                : array[0..7] of longWord;    // [0:7] POLYLL stores the first 8 bits of the 32 bit CRC
end;

TCRC_GPOLYL_bits = bitpacked record
  GPOLYL                 : TBits_16;                   // [0:15] POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value
end;

TCRC_GPOLYL_bitbanded = record
  GPOLYL                 : array[0..15] of longWord;   // [0:15] POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value
end;

TCRC_GPOLYLU_bits = bitpacked record
  GPOLYLU                : TBits_8;                    // [0:7] POLYLL stores the second 8 bits of the 32 bit CRC
end;

TCRC_GPOLYLU_bitbanded = record
  GPOLYLU                : array[0..7] of longWord;    // [0:7] POLYLL stores the second 8 bits of the 32 bit CRC
end;

TCRC_GPOLYH_bits = bitpacked record
  GPOLYH                 : TBits_16;                   // [0:15] POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value
end;

TCRC_GPOLYH_bitbanded = record
  GPOLYH                 : array[0..15] of longWord;   // [0:15] POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value
end;

TCRC_GPOLYHL_bits = bitpacked record
  GPOLYHL                : TBits_8;                    // [0:7] POLYHL stores the third 8 bits of the 32 bit CRC
end;

TCRC_GPOLYHL_bitbanded = record
  GPOLYHL                : array[0..7] of longWord;    // [0:7] POLYHL stores the third 8 bits of the 32 bit CRC
end;

TCRC_GPOLYHU_bits = bitpacked record
  GPOLYHU                : TBits_8;                    // [0:7] POLYHU stores the fourth 8 bits of the 32 bit CRC
end;

TCRC_GPOLYHU_bitbanded = record
  GPOLYHU                : array[0..7] of longWord;    // [0:7] POLYHU stores the fourth 8 bits of the 32 bit CRC
end;

TCRC_CTRL_bits = bitpacked record
  RESERVED0              : TBits_24;                   // [0:23] no description available
  TCRC                   : TBits_1;                    // [24:24] no description available
  WAS                    : TBits_1;                    // [25:25] Write CRC data register as seed
  FXOR                   : TBits_1;                    // [26:26] Complement Read of CRC data register
  RESERVED1              : TBits_1;                    // [27:27] no description available
  TOTR                   : TBits_2;                    // [28:29] Type of Transpose for Read
  TOT                    : TBits_2;                    // [30:31] Type of Transpose for Writes
end;

TCRC_CTRL_bitbanded = record
  RESERVED0              : array[0..23] of longWord;   // [0:23] no description available
  TCRC                   : longWord;                   // [24:24] no description available
  WAS                    : longWord;                   // [25:25] Write CRC data register as seed
  FXOR                   : longWord;                   // [26:26] Complement Read of CRC data register
  RESERVED1              : longWord;                   // [27:27] no description available
  TOTR                   : array[0..1] of longWord;    // [28:29] Type of Transpose for Read
  TOT                    : array[0..1] of longWord;    // [30:31] Type of Transpose for Writes
end;

TCRC_CTRLHU_bits = bitpacked record
  TCRC                   : TBits_1;                    // [0:0] no description available
  WAS                    : TBits_1;                    // [1:1] no description available
  FXOR                   : TBits_1;                    // [2:2] no description available
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TOTR                   : TBits_2;                    // [4:5] no description available
  TOT                    : TBits_2;                    // [6:7] no description available
end;

TCRC_CTRLHU_bitbanded = record
  TCRC                   : longWord;                   // [0:0] no description available
  WAS                    : longWord;                   // [1:1] no description available
  FXOR                   : longWord;                   // [2:2] no description available
  RESERVED0              : longWord;                   // [3:3] no description available
  TOTR                   : array[0..1] of longWord;    // [4:5] no description available
  TOT                    : array[0..1] of longWord;    // [6:7] no description available
end;

TCRC_Registers = record
  case boolean of false: (
  CRCL                   : word;                       // 0x00 CRC_CRCL register.
  CRCH                   : word;                       // 0x02 CRC_CRCH register.
  GPOLYL                 : word;                       // 0x04 CRC_GPOLYL register.
  GPOLYHL                : byte;                       // 0x06 CRC_GPOLYHL register.
  GPOLYHU                : byte;                       // 0x07 CRC_GPOLYHU register.
  CTRL                   : longWord;                   // 0x08 CRC Control Register
);
true : (
CRCL_bits                : TCRC_CRCL_bits;             // 0x02 CRC_CRCL register.
CRCH_bits                : TCRC_CRCH_bits;             // 0x04 CRC_CRCH register.
GPOLYL_bits              : TCRC_GPOLYL_bits;           // 0x06 CRC_GPOLYL register.
GPOLYHL_bits             : TCRC_GPOLYHL_bits;          // 0x07 CRC_GPOLYHL register.
GPOLYHU_bits             : TCRC_GPOLYHU_bits;          // 0x08 CRC_GPOLYHU register.
CTRL_bits                : TCRC_CTRL_bits;             // 0x0C CRC Control Register
);
end;

TCRCRegisters_bitbanded = record
  CRCL                   : TCRC_CRCL_bitbanded;        // 0x02 CRC_CRCL register.
  CRCH                   : TCRC_CRCH_bitbanded;        // 0x04 CRC_CRCH register.
  GPOLYL                 : TCRC_GPOLYL_bitbanded;      // 0x06 CRC_GPOLYL register.
  GPOLYHL                : TCRC_GPOLYHL_bitbanded;     // 0x07 CRC_GPOLYHL register.
  GPOLYHU                : TCRC_GPOLYHU_bitbanded;     // 0x08 CRC_GPOLYHU register.
  CTRL                   : TCRC_CTRL_bitbanded;        // 0x0C CRC Control Register
end;

// 12-Bit Digital-to-Analog Converter
TDAC0_DATL_bits = bitpacked record
  DATA                   : TBits_8;                    // [0:7] no description available
end;

TDAC0_DATL_bitbanded = record
  DATA                   : array[0..7] of longWord;    // [0:7] no description available
end;

TDAC0_DATH_bits = bitpacked record
  DATA                   : TBits_4;                    // [0:3] no description available
  RESERVED0              : TBits_4;                    // [4:7] no description available
end;

TDAC0_DATH_bitbanded = record
  DATA                   : array[0..3] of longWord;    // [0:3] no description available
  RESERVED0              : array[0..3] of longWord;    // [4:7] no description available
end;

TDAC0_SR_bits = bitpacked record
  DACBFRPBF              : TBits_1;                    // [0:0] DAC buffer read pointer bottom position flag
  DACBFRPTF              : TBits_1;                    // [1:1] DAC buffer read pointer top position flag
  DACBFWMF               : TBits_1;                    // [2:2] DAC buffer watermark flag
  RESERVED0              : TBits_5;                    // [3:7] no description available
end;

TDAC0_SR_bitbanded = record
  DACBFRPBF              : longWord;                   // [0:0] DAC buffer read pointer bottom position flag
  DACBFRPTF              : longWord;                   // [1:1] DAC buffer read pointer top position flag
  DACBFWMF               : longWord;                   // [2:2] DAC buffer watermark flag
  RESERVED0              : array[0..4] of longWord;    // [3:7] no description available
end;

TDAC0_C0_bits = bitpacked record
  DACBBIEN               : TBits_1;                    // [0:0] DAC buffer read pointer bottom flag interrupt enable
  DACBTIEN               : TBits_1;                    // [1:1] DAC buffer read pointer top flag interrupt enable
  DACBWIEN               : TBits_1;                    // [2:2] DAC buffer watermark interrupt enable
  LPEN                   : TBits_1;                    // [3:3] DAC low power control
  DACSWTRG               : TBits_1;                    // [4:4] DAC software trigger
  DACTRGSEL              : TBits_1;                    // [5:5] DAC trigger select
  DACRFS                 : TBits_1;                    // [6:6] DAC Reference Select
  DACEN                  : TBits_1;                    // [7:7] DAC enable
end;

TDAC0_C0_bitbanded = record
  DACBBIEN               : longWord;                   // [0:0] DAC buffer read pointer bottom flag interrupt enable
  DACBTIEN               : longWord;                   // [1:1] DAC buffer read pointer top flag interrupt enable
  DACBWIEN               : longWord;                   // [2:2] DAC buffer watermark interrupt enable
  LPEN                   : longWord;                   // [3:3] DAC low power control
  DACSWTRG               : longWord;                   // [4:4] DAC software trigger
  DACTRGSEL              : longWord;                   // [5:5] DAC trigger select
  DACRFS                 : longWord;                   // [6:6] DAC Reference Select
  DACEN                  : longWord;                   // [7:7] DAC enable
end;

TDAC0_C1_bits = bitpacked record
  DACBFEN                : TBits_1;                    // [0:0] DAC buffer enable
  DACBFMD                : TBits_2;                    // [1:2] DAC buffer work mode select
  DACBFWM                : TBits_2;                    // [3:4] DAC buffer watermark select
  RESERVED0              : TBits_2;                    // [5:6] no description available
  DMAEN                  : TBits_1;                    // [7:7] DMA enable select
end;

TDAC0_C1_bitbanded = record
  DACBFEN                : longWord;                   // [0:0] DAC buffer enable
  DACBFMD                : array[0..1] of longWord;    // [1:2] DAC buffer work mode select
  DACBFWM                : array[0..1] of longWord;    // [3:4] DAC buffer watermark select
  RESERVED0              : array[0..1] of longWord;    // [5:6] no description available
  DMAEN                  : longWord;                   // [7:7] DMA enable select
end;

TDAC0_C2_bits = bitpacked record
  DACBFUP                : TBits_4;                    // [0:3] DAC buffer upper limit
  DACBFRP                : TBits_4;                    // [4:7] DAC buffer read pointer
end;

TDAC0_C2_bitbanded = record
  DACBFUP                : array[0..3] of longWord;    // [0:3] DAC buffer upper limit
  DACBFRP                : array[0..3] of longWord;    // [4:7] DAC buffer read pointer
end;

TDAC0_Registers = record
  case boolean of false: (
  DAT0L                  : byte;                       // 0x00 DAC Data Low Register
  DAT0H                  : byte;                       // 0x01 DAC Data High Register
  DAT1L                  : byte;                       // 0x02 DAC Data Low Register
  DAT1H                  : byte;                       // 0x03 DAC Data High Register
  DAT2L                  : byte;                       // 0x04 DAC Data Low Register
  DAT2H                  : byte;                       // 0x05 DAC Data High Register
  DAT3L                  : byte;                       // 0x06 DAC Data Low Register
  DAT3H                  : byte;                       // 0x07 DAC Data High Register
  DAT4L                  : byte;                       // 0x08 DAC Data Low Register
  DAT4H                  : byte;                       // 0x09 DAC Data High Register
  DAT5L                  : byte;                       // 0x0A DAC Data Low Register
  DAT5H                  : byte;                       // 0x0B DAC Data High Register
  DAT6L                  : byte;                       // 0x0C DAC Data Low Register
  DAT6H                  : byte;                       // 0x0D DAC Data High Register
  DAT7L                  : byte;                       // 0x0E DAC Data Low Register
  DAT7H                  : byte;                       // 0x0F DAC Data High Register
  DAT8L                  : byte;                       // 0x10 DAC Data Low Register
  DAT8H                  : byte;                       // 0x11 DAC Data High Register
  DAT9L                  : byte;                       // 0x12 DAC Data Low Register
  DAT9H                  : byte;                       // 0x13 DAC Data High Register
  DAT10L                 : byte;                       // 0x14 DAC Data Low Register
  DAT10H                 : byte;                       // 0x15 DAC Data High Register
  DAT11L                 : byte;                       // 0x16 DAC Data Low Register
  DAT11H                 : byte;                       // 0x17 DAC Data High Register
  DAT12L                 : byte;                       // 0x18 DAC Data Low Register
  DAT12H                 : byte;                       // 0x19 DAC Data High Register
  DAT13L                 : byte;                       // 0x1A DAC Data Low Register
  DAT13H                 : byte;                       // 0x1B DAC Data High Register
  DAT14L                 : byte;                       // 0x1C DAC Data Low Register
  DAT14H                 : byte;                       // 0x1D DAC Data High Register
  DAT15L                 : byte;                       // 0x1E DAC Data Low Register
  DAT15H                 : byte;                       // 0x1F DAC Data High Register
  SR                     : byte;                       // 0x20 DAC Status Register
  C0                     : byte;                       // 0x21 DAC Control Register
  C1                     : byte;                       // 0x22 DAC Control Register 1
  C2                     : byte;                       // 0x23 DAC Control Register 2
);
true : (
DAT0L_bits               : byte;                       // 0x00 DAC Data Low Register
DAT0H_bits               : byte;                       // 0x01 DAC Data High Register
DAT1L_bits               : byte;                       // 0x02 DAC Data Low Register
DAT1H_bits               : byte;                       // 0x03 DAC Data High Register
DAT2L_bits               : byte;                       // 0x04 DAC Data Low Register
DAT2H_bits               : byte;                       // 0x05 DAC Data High Register
DAT3L_bits               : byte;                       // 0x06 DAC Data Low Register
DAT3H_bits               : byte;                       // 0x07 DAC Data High Register
DAT4L_bits               : byte;                       // 0x08 DAC Data Low Register
DAT4H_bits               : byte;                       // 0x09 DAC Data High Register
DAT5L_bits               : byte;                       // 0x0A DAC Data Low Register
DAT5H_bits               : byte;                       // 0x0B DAC Data High Register
DAT6L_bits               : byte;                       // 0x0C DAC Data Low Register
DAT6H_bits               : byte;                       // 0x0D DAC Data High Register
DAT7L_bits               : byte;                       // 0x0E DAC Data Low Register
DAT7H_bits               : byte;                       // 0x0F DAC Data High Register
DAT8L_bits               : byte;                       // 0x10 DAC Data Low Register
DAT8H_bits               : byte;                       // 0x11 DAC Data High Register
DAT9L_bits               : byte;                       // 0x12 DAC Data Low Register
DAT9H_bits               : byte;                       // 0x13 DAC Data High Register
DAT10L_bits              : byte;                       // 0x14 DAC Data Low Register
DAT10H_bits              : byte;                       // 0x15 DAC Data High Register
DAT11L_bits              : byte;                       // 0x16 DAC Data Low Register
DAT11H_bits              : byte;                       // 0x17 DAC Data High Register
DAT12L_bits              : byte;                       // 0x18 DAC Data Low Register
DAT12H_bits              : byte;                       // 0x19 DAC Data High Register
DAT13L_bits              : byte;                       // 0x1A DAC Data Low Register
DAT13H_bits              : byte;                       // 0x1B DAC Data High Register
DAT14L_bits              : byte;                       // 0x1C DAC Data Low Register
DAT14H_bits              : byte;                       // 0x1D DAC Data High Register
DAT15L_bits              : byte;                       // 0x1E DAC Data Low Register
DAT15H_bits              : byte;                       // 0x1F DAC Data High Register
SR_bits                  : TDAC0_SR_bits;              // 0x21 DAC Status Register
C0_bits                  : TDAC0_C0_bits;              // 0x22 DAC Control Register
C1_bits                  : TDAC0_C1_bits;              // 0x23 DAC Control Register 1
C2_bits                  : TDAC0_C2_bits;              // 0x24 DAC Control Register 2
);
end;

TDAC0Registers_bitbanded = record
  DAT0L_bitbanded        : byte;                       // 0x00 DAC Data Low Register
  DAT0H_bitbanded        : byte;                       // 0x01 DAC Data High Register
  DAT1L_bitbanded        : byte;                       // 0x02 DAC Data Low Register
  DAT1H_bitbanded        : byte;                       // 0x03 DAC Data High Register
  DAT2L_bitbanded        : byte;                       // 0x04 DAC Data Low Register
  DAT2H_bitbanded        : byte;                       // 0x05 DAC Data High Register
  DAT3L_bitbanded        : byte;                       // 0x06 DAC Data Low Register
  DAT3H_bitbanded        : byte;                       // 0x07 DAC Data High Register
  DAT4L_bitbanded        : byte;                       // 0x08 DAC Data Low Register
  DAT4H_bitbanded        : byte;                       // 0x09 DAC Data High Register
  DAT5L_bitbanded        : byte;                       // 0x0A DAC Data Low Register
  DAT5H_bitbanded        : byte;                       // 0x0B DAC Data High Register
  DAT6L_bitbanded        : byte;                       // 0x0C DAC Data Low Register
  DAT6H_bitbanded        : byte;                       // 0x0D DAC Data High Register
  DAT7L_bitbanded        : byte;                       // 0x0E DAC Data Low Register
  DAT7H_bitbanded        : byte;                       // 0x0F DAC Data High Register
  DAT8L_bitbanded        : byte;                       // 0x10 DAC Data Low Register
  DAT8H_bitbanded        : byte;                       // 0x11 DAC Data High Register
  DAT9L_bitbanded        : byte;                       // 0x12 DAC Data Low Register
  DAT9H_bitbanded        : byte;                       // 0x13 DAC Data High Register
  DAT10L_bitbanded       : byte;                       // 0x14 DAC Data Low Register
  DAT10H_bitbanded       : byte;                       // 0x15 DAC Data High Register
  DAT11L_bitbanded       : byte;                       // 0x16 DAC Data Low Register
  DAT11H_bitbanded       : byte;                       // 0x17 DAC Data High Register
  DAT12L_bitbanded       : byte;                       // 0x18 DAC Data Low Register
  DAT12H_bitbanded       : byte;                       // 0x19 DAC Data High Register
  DAT13L_bitbanded       : byte;                       // 0x1A DAC Data Low Register
  DAT13H_bitbanded       : byte;                       // 0x1B DAC Data High Register
  DAT14L_bitbanded       : byte;                       // 0x1C DAC Data Low Register
  DAT14H_bitbanded       : byte;                       // 0x1D DAC Data High Register
  DAT15L_bitbanded       : byte;                       // 0x1E DAC Data Low Register
  DAT15H_bitbanded       : byte;                       // 0x1F DAC Data High Register
  SR                     : TDAC0_SR_bitbanded;         // 0x21 DAC Status Register
  C0                     : TDAC0_C0_bitbanded;         // 0x22 DAC Control Register
  C1                     : TDAC0_C1_bitbanded;         // 0x23 DAC Control Register 1
  C2                     : TDAC0_C2_bitbanded;         // 0x24 DAC Control Register 2
end;

// Enhanced direct memory access controller
TDMA_CR_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] no description available
  EDBG                   : TBits_1;                    // [1:1] Enable Debug
  ERCA                   : TBits_1;                    // [2:2] Enable Round Robin Channel Arbitration
  RESERVED1              : TBits_1;                    // [3:3] no description available
  HOE                    : TBits_1;                    // [4:4] Halt On Error
  HALT                   : TBits_1;                    // [5:5] Halt DMA Operations
  CLM                    : TBits_1;                    // [6:6] Continuous Link Mode
  EMLM                   : TBits_1;                    // [7:7] Enable Minor Loop Mapping
  RESERVED2              : TBits_8;                    // [8:15] no description available
  ECX                    : TBits_1;                    // [16:16] Error Cancel Transfer
  CX                     : TBits_1;                    // [17:17] Cancel Transfer
  RESERVED3              : TBits_14;                   // [18:31] no description available
end;

TDMA_CR_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] no description available
  EDBG                   : longWord;                   // [1:1] Enable Debug
  ERCA                   : longWord;                   // [2:2] Enable Round Robin Channel Arbitration
  RESERVED1              : longWord;                   // [3:3] no description available
  HOE                    : longWord;                   // [4:4] Halt On Error
  HALT                   : longWord;                   // [5:5] Halt DMA Operations
  CLM                    : longWord;                   // [6:6] Continuous Link Mode
  EMLM                   : longWord;                   // [7:7] Enable Minor Loop Mapping
  RESERVED2              : array[0..7] of longWord;    // [8:15] no description available
  ECX                    : longWord;                   // [16:16] Error Cancel Transfer
  CX                     : longWord;                   // [17:17] Cancel Transfer
  RESERVED3              : array[0..13] of longWord;   // [18:31] no description available
end;

TDMA_ES_bits = bitpacked record
  DBE                    : TBits_1;                    // [0:0] Destination Bus Error
  SBE                    : TBits_1;                    // [1:1] Source Bus Error
  SGE                    : TBits_1;                    // [2:2] Scatter/Gather Configuration Error
  NCE                    : TBits_1;                    // [3:3] NBYTES/CITER Configuration Error
  DOE                    : TBits_1;                    // [4:4] Destination Offset Error
  DAE                    : TBits_1;                    // [5:5] Destination Address Error
  SOE                    : TBits_1;                    // [6:6] Source Offset Error
  SAE                    : TBits_1;                    // [7:7] Source Address Error
  ERRCHN                 : TBits_4;                    // [8:11] Error Channel Number or Cancelled Channel Number
  RESERVED0              : TBits_2;                    // [12:13] no description available
  CPE                    : TBits_1;                    // [14:14] Channel Priority Error
  RESERVED1              : TBits_1;                    // [15:15] no description available
  ECX                    : TBits_1;                    // [16:16] Transfer Cancelled
  RESERVED2              : TBits_14;                   // [17:30] no description available
  VLD                    : TBits_1;                    // [31:31] no description available
end;

TDMA_ES_bitbanded = record
  DBE                    : longWord;                   // [0:0] Destination Bus Error
  SBE                    : longWord;                   // [1:1] Source Bus Error
  SGE                    : longWord;                   // [2:2] Scatter/Gather Configuration Error
  NCE                    : longWord;                   // [3:3] NBYTES/CITER Configuration Error
  DOE                    : longWord;                   // [4:4] Destination Offset Error
  DAE                    : longWord;                   // [5:5] Destination Address Error
  SOE                    : longWord;                   // [6:6] Source Offset Error
  SAE                    : longWord;                   // [7:7] Source Address Error
  ERRCHN                 : array[0..3] of longWord;    // [8:11] Error Channel Number or Cancelled Channel Number
  RESERVED0              : array[0..1] of longWord;    // [12:13] no description available
  CPE                    : longWord;                   // [14:14] Channel Priority Error
  RESERVED1              : longWord;                   // [15:15] no description available
  ECX                    : longWord;                   // [16:16] Transfer Cancelled
  RESERVED2              : array[0..13] of longWord;   // [17:30] no description available
  VLD                    : longWord;                   // [31:31] no description available
end;

TDMA_ERQ_bits = bitpacked record
  ERQ0                   : TBits_1;                    // [0:0] Enable DMA Request 0
  ERQ1                   : TBits_1;                    // [1:1] Enable DMA Request 1
  ERQ2                   : TBits_1;                    // [2:2] Enable DMA Request 2
  ERQ3                   : TBits_1;                    // [3:3] Enable DMA Request 3
  ERQ4                   : TBits_1;                    // [4:4] Enable DMA Request 4
  ERQ5                   : TBits_1;                    // [5:5] Enable DMA Request 5
  ERQ6                   : TBits_1;                    // [6:6] Enable DMA Request 6
  ERQ7                   : TBits_1;                    // [7:7] Enable DMA Request 7
  ERQ8                   : TBits_1;                    // [8:8] Enable DMA Request 8
  ERQ9                   : TBits_1;                    // [9:9] Enable DMA Request 9
  ERQ10                  : TBits_1;                    // [10:10] Enable DMA Request 10
  ERQ11                  : TBits_1;                    // [11:11] Enable DMA Request 11
  ERQ12                  : TBits_1;                    // [12:12] Enable DMA Request 12
  ERQ13                  : TBits_1;                    // [13:13] Enable DMA Request 13
  ERQ14                  : TBits_1;                    // [14:14] Enable DMA Request 14
  ERQ15                  : TBits_1;                    // [15:15] Enable DMA Request 15
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TDMA_ERQ_bitbanded = record
  ERQ0                   : longWord;                   // [0:0] Enable DMA Request 0
  ERQ1                   : longWord;                   // [1:1] Enable DMA Request 1
  ERQ2                   : longWord;                   // [2:2] Enable DMA Request 2
  ERQ3                   : longWord;                   // [3:3] Enable DMA Request 3
  ERQ4                   : longWord;                   // [4:4] Enable DMA Request 4
  ERQ5                   : longWord;                   // [5:5] Enable DMA Request 5
  ERQ6                   : longWord;                   // [6:6] Enable DMA Request 6
  ERQ7                   : longWord;                   // [7:7] Enable DMA Request 7
  ERQ8                   : longWord;                   // [8:8] Enable DMA Request 8
  ERQ9                   : longWord;                   // [9:9] Enable DMA Request 9
  ERQ10                  : longWord;                   // [10:10] Enable DMA Request 10
  ERQ11                  : longWord;                   // [11:11] Enable DMA Request 11
  ERQ12                  : longWord;                   // [12:12] Enable DMA Request 12
  ERQ13                  : longWord;                   // [13:13] Enable DMA Request 13
  ERQ14                  : longWord;                   // [14:14] Enable DMA Request 14
  ERQ15                  : longWord;                   // [15:15] Enable DMA Request 15
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TDMA_EEI_bits = bitpacked record
  EEI0                   : TBits_1;                    // [0:0] Enable Error Interrupt 0
  EEI1                   : TBits_1;                    // [1:1] Enable Error Interrupt 1
  EEI2                   : TBits_1;                    // [2:2] Enable Error Interrupt 2
  EEI3                   : TBits_1;                    // [3:3] Enable Error Interrupt 3
  EEI4                   : TBits_1;                    // [4:4] Enable Error Interrupt 4
  EEI5                   : TBits_1;                    // [5:5] Enable Error Interrupt 5
  EEI6                   : TBits_1;                    // [6:6] Enable Error Interrupt 6
  EEI7                   : TBits_1;                    // [7:7] Enable Error Interrupt 7
  EEI8                   : TBits_1;                    // [8:8] Enable Error Interrupt 8
  EEI9                   : TBits_1;                    // [9:9] Enable Error Interrupt 9
  EEI10                  : TBits_1;                    // [10:10] Enable Error Interrupt 10
  EEI11                  : TBits_1;                    // [11:11] Enable Error Interrupt 11
  EEI12                  : TBits_1;                    // [12:12] Enable Error Interrupt 12
  EEI13                  : TBits_1;                    // [13:13] Enable Error Interrupt 13
  EEI14                  : TBits_1;                    // [14:14] Enable Error Interrupt 14
  EEI15                  : TBits_1;                    // [15:15] Enable Error Interrupt 15
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TDMA_EEI_bitbanded = record
  EEI0                   : longWord;                   // [0:0] Enable Error Interrupt 0
  EEI1                   : longWord;                   // [1:1] Enable Error Interrupt 1
  EEI2                   : longWord;                   // [2:2] Enable Error Interrupt 2
  EEI3                   : longWord;                   // [3:3] Enable Error Interrupt 3
  EEI4                   : longWord;                   // [4:4] Enable Error Interrupt 4
  EEI5                   : longWord;                   // [5:5] Enable Error Interrupt 5
  EEI6                   : longWord;                   // [6:6] Enable Error Interrupt 6
  EEI7                   : longWord;                   // [7:7] Enable Error Interrupt 7
  EEI8                   : longWord;                   // [8:8] Enable Error Interrupt 8
  EEI9                   : longWord;                   // [9:9] Enable Error Interrupt 9
  EEI10                  : longWord;                   // [10:10] Enable Error Interrupt 10
  EEI11                  : longWord;                   // [11:11] Enable Error Interrupt 11
  EEI12                  : longWord;                   // [12:12] Enable Error Interrupt 12
  EEI13                  : longWord;                   // [13:13] Enable Error Interrupt 13
  EEI14                  : longWord;                   // [14:14] Enable Error Interrupt 14
  EEI15                  : longWord;                   // [15:15] Enable Error Interrupt 15
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TDMA_CEEI_bits = bitpacked record
  CEEI                   : TBits_4;                    // [0:3] Clear Enable Error Interrupt
  RESERVED0              : TBits_2;                    // [4:5] no description available
  CAEE                   : TBits_1;                    // [6:6] Clear All Enable Error Interrupts
  NOP                    : TBits_1;                    // [7:7] no description available
end;

TDMA_CEEI_bitbanded = record
  CEEI                   : array[0..3] of longWord;    // [0:3] Clear Enable Error Interrupt
  RESERVED0              : array[0..1] of longWord;    // [4:5] no description available
  CAEE                   : longWord;                   // [6:6] Clear All Enable Error Interrupts
  NOP                    : longWord;                   // [7:7] no description available
end;

TDMA_SEEI_bits = bitpacked record
  SEEI                   : TBits_4;                    // [0:3] Set Enable Error Interrupt
  RESERVED0              : TBits_2;                    // [4:5] no description available
  SAEE                   : TBits_1;                    // [6:6] Sets All Enable Error Interrupts
  NOP                    : TBits_1;                    // [7:7] no description available
end;

TDMA_SEEI_bitbanded = record
  SEEI                   : array[0..3] of longWord;    // [0:3] Set Enable Error Interrupt
  RESERVED0              : array[0..1] of longWord;    // [4:5] no description available
  SAEE                   : longWord;                   // [6:6] Sets All Enable Error Interrupts
  NOP                    : longWord;                   // [7:7] no description available
end;

TDMA_CERQ_bits = bitpacked record
  CERQ                   : TBits_4;                    // [0:3] Clear Enable Request
  RESERVED0              : TBits_2;                    // [4:5] no description available
  CAER                   : TBits_1;                    // [6:6] Clear All Enable Requests
  NOP                    : TBits_1;                    // [7:7] no description available
end;

TDMA_CERQ_bitbanded = record
  CERQ                   : array[0..3] of longWord;    // [0:3] Clear Enable Request
  RESERVED0              : array[0..1] of longWord;    // [4:5] no description available
  CAER                   : longWord;                   // [6:6] Clear All Enable Requests
  NOP                    : longWord;                   // [7:7] no description available
end;

TDMA_SERQ_bits = bitpacked record
  SERQ                   : TBits_4;                    // [0:3] Set enable request
  RESERVED0              : TBits_2;                    // [4:5] no description available
  SAER                   : TBits_1;                    // [6:6] Set All Enable Requests
  NOP                    : TBits_1;                    // [7:7] no description available
end;

TDMA_SERQ_bitbanded = record
  SERQ                   : array[0..3] of longWord;    // [0:3] Set enable request
  RESERVED0              : array[0..1] of longWord;    // [4:5] no description available
  SAER                   : longWord;                   // [6:6] Set All Enable Requests
  NOP                    : longWord;                   // [7:7] no description available
end;

TDMA_CDNE_bits = bitpacked record
  CDNE                   : TBits_4;                    // [0:3] Clear DONE Bit
  RESERVED0              : TBits_2;                    // [4:5] no description available
  CADN                   : TBits_1;                    // [6:6] Clears All DONE Bits
  NOP                    : TBits_1;                    // [7:7] no description available
end;

TDMA_CDNE_bitbanded = record
  CDNE                   : array[0..3] of longWord;    // [0:3] Clear DONE Bit
  RESERVED0              : array[0..1] of longWord;    // [4:5] no description available
  CADN                   : longWord;                   // [6:6] Clears All DONE Bits
  NOP                    : longWord;                   // [7:7] no description available
end;

TDMA_SSRT_bits = bitpacked record
  SSRT                   : TBits_4;                    // [0:3] Set START Bit
  RESERVED0              : TBits_2;                    // [4:5] no description available
  SAST                   : TBits_1;                    // [6:6] Set All START Bits (activates all channels)
  NOP                    : TBits_1;                    // [7:7] no description available
end;

TDMA_SSRT_bitbanded = record
  SSRT                   : array[0..3] of longWord;    // [0:3] Set START Bit
  RESERVED0              : array[0..1] of longWord;    // [4:5] no description available
  SAST                   : longWord;                   // [6:6] Set All START Bits (activates all channels)
  NOP                    : longWord;                   // [7:7] no description available
end;

TDMA_CERR_bits = bitpacked record
  CERR                   : TBits_4;                    // [0:3] Clear Error Indicator
  RESERVED0              : TBits_2;                    // [4:5] no description available
  CAEI                   : TBits_1;                    // [6:6] Clear All Error Indicators
  NOP                    : TBits_1;                    // [7:7] no description available
end;

TDMA_CERR_bitbanded = record
  CERR                   : array[0..3] of longWord;    // [0:3] Clear Error Indicator
  RESERVED0              : array[0..1] of longWord;    // [4:5] no description available
  CAEI                   : longWord;                   // [6:6] Clear All Error Indicators
  NOP                    : longWord;                   // [7:7] no description available
end;

TDMA_CINT_bits = bitpacked record
  CINT                   : TBits_4;                    // [0:3] Clear Interrupt Request
  RESERVED0              : TBits_2;                    // [4:5] no description available
  CAIR                   : TBits_1;                    // [6:6] Clear All Interrupt Requests
  NOP                    : TBits_1;                    // [7:7] no description available
end;

TDMA_CINT_bitbanded = record
  CINT                   : array[0..3] of longWord;    // [0:3] Clear Interrupt Request
  RESERVED0              : array[0..1] of longWord;    // [4:5] no description available
  CAIR                   : longWord;                   // [6:6] Clear All Interrupt Requests
  NOP                    : longWord;                   // [7:7] no description available
end;

TDMA_INT_bits = bitpacked record
  INT0                   : TBits_1;                    // [0:0] Interrupt Request 0
  INT1                   : TBits_1;                    // [1:1] Interrupt Request 1
  INT2                   : TBits_1;                    // [2:2] Interrupt Request 2
  INT3                   : TBits_1;                    // [3:3] Interrupt Request 3
  INT4                   : TBits_1;                    // [4:4] Interrupt Request 4
  INT5                   : TBits_1;                    // [5:5] Interrupt Request 5
  INT6                   : TBits_1;                    // [6:6] Interrupt Request 6
  INT7                   : TBits_1;                    // [7:7] Interrupt Request 7
  INT8                   : TBits_1;                    // [8:8] Interrupt Request 8
  INT9                   : TBits_1;                    // [9:9] Interrupt Request 9
  INT10                  : TBits_1;                    // [10:10] Interrupt Request 10
  INT11                  : TBits_1;                    // [11:11] Interrupt Request 11
  INT12                  : TBits_1;                    // [12:12] Interrupt Request 12
  INT13                  : TBits_1;                    // [13:13] Interrupt Request 13
  INT14                  : TBits_1;                    // [14:14] Interrupt Request 14
  INT15                  : TBits_1;                    // [15:15] Interrupt Request 15
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TDMA_INT_bitbanded = record
  INT0                   : longWord;                   // [0:0] Interrupt Request 0
  INT1                   : longWord;                   // [1:1] Interrupt Request 1
  INT2                   : longWord;                   // [2:2] Interrupt Request 2
  INT3                   : longWord;                   // [3:3] Interrupt Request 3
  INT4                   : longWord;                   // [4:4] Interrupt Request 4
  INT5                   : longWord;                   // [5:5] Interrupt Request 5
  INT6                   : longWord;                   // [6:6] Interrupt Request 6
  INT7                   : longWord;                   // [7:7] Interrupt Request 7
  INT8                   : longWord;                   // [8:8] Interrupt Request 8
  INT9                   : longWord;                   // [9:9] Interrupt Request 9
  INT10                  : longWord;                   // [10:10] Interrupt Request 10
  INT11                  : longWord;                   // [11:11] Interrupt Request 11
  INT12                  : longWord;                   // [12:12] Interrupt Request 12
  INT13                  : longWord;                   // [13:13] Interrupt Request 13
  INT14                  : longWord;                   // [14:14] Interrupt Request 14
  INT15                  : longWord;                   // [15:15] Interrupt Request 15
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TDMA_ERR_bits = bitpacked record
  ERR0                   : TBits_1;                    // [0:0] Error In Channel 0
  ERR1                   : TBits_1;                    // [1:1] Error In Channel 1
  ERR2                   : TBits_1;                    // [2:2] Error In Channel 2
  ERR3                   : TBits_1;                    // [3:3] Error In Channel 3
  ERR4                   : TBits_1;                    // [4:4] Error In Channel 4
  ERR5                   : TBits_1;                    // [5:5] Error In Channel 5
  ERR6                   : TBits_1;                    // [6:6] Error In Channel 6
  ERR7                   : TBits_1;                    // [7:7] Error In Channel 7
  ERR8                   : TBits_1;                    // [8:8] Error In Channel 8
  ERR9                   : TBits_1;                    // [9:9] Error In Channel 9
  ERR10                  : TBits_1;                    // [10:10] Error In Channel 10
  ERR11                  : TBits_1;                    // [11:11] Error In Channel 11
  ERR12                  : TBits_1;                    // [12:12] Error In Channel 12
  ERR13                  : TBits_1;                    // [13:13] Error In Channel 13
  ERR14                  : TBits_1;                    // [14:14] Error In Channel 14
  ERR15                  : TBits_1;                    // [15:15] Error In Channel 15
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TDMA_ERR_bitbanded = record
  ERR0                   : longWord;                   // [0:0] Error In Channel 0
  ERR1                   : longWord;                   // [1:1] Error In Channel 1
  ERR2                   : longWord;                   // [2:2] Error In Channel 2
  ERR3                   : longWord;                   // [3:3] Error In Channel 3
  ERR4                   : longWord;                   // [4:4] Error In Channel 4
  ERR5                   : longWord;                   // [5:5] Error In Channel 5
  ERR6                   : longWord;                   // [6:6] Error In Channel 6
  ERR7                   : longWord;                   // [7:7] Error In Channel 7
  ERR8                   : longWord;                   // [8:8] Error In Channel 8
  ERR9                   : longWord;                   // [9:9] Error In Channel 9
  ERR10                  : longWord;                   // [10:10] Error In Channel 10
  ERR11                  : longWord;                   // [11:11] Error In Channel 11
  ERR12                  : longWord;                   // [12:12] Error In Channel 12
  ERR13                  : longWord;                   // [13:13] Error In Channel 13
  ERR14                  : longWord;                   // [14:14] Error In Channel 14
  ERR15                  : longWord;                   // [15:15] Error In Channel 15
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TDMA_HRS_bits = bitpacked record
  HRS0                   : TBits_1;                    // [0:0] Hardware Request Status Channel 0
  HRS1                   : TBits_1;                    // [1:1] Hardware Request Status Channel 1
  HRS2                   : TBits_1;                    // [2:2] Hardware Request Status Channel 2
  HRS3                   : TBits_1;                    // [3:3] Hardware Request Status Channel 3
  HRS4                   : TBits_1;                    // [4:4] Hardware Request Status Channel 4
  HRS5                   : TBits_1;                    // [5:5] Hardware Request Status Channel 5
  HRS6                   : TBits_1;                    // [6:6] Hardware Request Status Channel 6
  HRS7                   : TBits_1;                    // [7:7] Hardware Request Status Channel 7
  HRS8                   : TBits_1;                    // [8:8] Hardware Request Status Channel 8
  HRS9                   : TBits_1;                    // [9:9] Hardware Request Status Channel 9
  HRS10                  : TBits_1;                    // [10:10] Hardware Request Status Channel 10
  HRS11                  : TBits_1;                    // [11:11] Hardware Request Status Channel 11
  HRS12                  : TBits_1;                    // [12:12] Hardware Request Status Channel 12
  HRS13                  : TBits_1;                    // [13:13] Hardware Request Status Channel 13
  HRS14                  : TBits_1;                    // [14:14] Hardware Request Status Channel 14
  HRS15                  : TBits_1;                    // [15:15] Hardware Request Status Channel 15
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TDMA_HRS_bitbanded = record
  HRS0                   : longWord;                   // [0:0] Hardware Request Status Channel 0
  HRS1                   : longWord;                   // [1:1] Hardware Request Status Channel 1
  HRS2                   : longWord;                   // [2:2] Hardware Request Status Channel 2
  HRS3                   : longWord;                   // [3:3] Hardware Request Status Channel 3
  HRS4                   : longWord;                   // [4:4] Hardware Request Status Channel 4
  HRS5                   : longWord;                   // [5:5] Hardware Request Status Channel 5
  HRS6                   : longWord;                   // [6:6] Hardware Request Status Channel 6
  HRS7                   : longWord;                   // [7:7] Hardware Request Status Channel 7
  HRS8                   : longWord;                   // [8:8] Hardware Request Status Channel 8
  HRS9                   : longWord;                   // [9:9] Hardware Request Status Channel 9
  HRS10                  : longWord;                   // [10:10] Hardware Request Status Channel 10
  HRS11                  : longWord;                   // [11:11] Hardware Request Status Channel 11
  HRS12                  : longWord;                   // [12:12] Hardware Request Status Channel 12
  HRS13                  : longWord;                   // [13:13] Hardware Request Status Channel 13
  HRS14                  : longWord;                   // [14:14] Hardware Request Status Channel 14
  HRS15                  : longWord;                   // [15:15] Hardware Request Status Channel 15
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TDMA_DCHPRI_bits = bitpacked record
  CHPRI                  : TBits_4;                    // [0:3] Channel n Arbitration Priority
  RESERVED0              : TBits_2;                    // [4:5] no description available
  DPA                    : TBits_1;                    // [6:6] Disable Preempt Ability
  ECP                    : TBits_1;                    // [7:7] Enable Channel Preemption
end;

TDMA_DCHPRI_bitbanded = record
  CHPRI                  : array[0..3] of longWord;    // [0:3] Channel n Arbitration Priority
  RESERVED0              : array[0..1] of longWord;    // [4:5] no description available
  DPA                    : longWord;                   // [6:6] Disable Preempt Ability
  ECP                    : longWord;                   // [7:7] Enable Channel Preemption
end;

TDMA_TCD_SADDR_bits = bitpacked record
  SADDR                  : TBits_32;                   // [0:31] Source Address
end;

TDMA_TCD_SADDR_bitbanded = record
  SADDR                  : array[0..31] of longWord;   // [0:31] Source Address
end;

TDMA_TCD_SOFF_bits = bitpacked record
  SOFF                   : TBits_16;                   // [0:15] Source address signed offset
end;

TDMA_TCD_SOFF_bitbanded = record
  SOFF                   : array[0..15] of longWord;   // [0:15] Source address signed offset
end;

TDMA_TCD_ATTR_bits = bitpacked record
  DSIZE                  : TBits_3;                    // [0:2] Destination Data Transfer Size
  DMOD                   : TBits_5;                    // [3:7] Destination Address Modulo
  SSIZE                  : TBits_3;                    // [8:10] Source data transfer size
  SMOD                   : TBits_5;                    // [11:15] Source Address Modulo.
end;

TDMA_TCD_ATTR_bitbanded = record
  DSIZE                  : array[0..2] of longWord;    // [0:2] Destination Data Transfer Size
  DMOD                   : array[0..4] of longWord;    // [3:7] Destination Address Modulo
  SSIZE                  : array[0..2] of longWord;    // [8:10] Source data transfer size
  SMOD                   : array[0..4] of longWord;    // [11:15] Source Address Modulo.
end;

TDMA_TCD_NBYTES_MLOFFYES_bits = bitpacked record
  NBYTES                 : TBits_10;                   // [0:9] Minor Byte Transfer Count
  MLOFF                  : TBits_20;                   // [10:29] If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
  DMLOE                  : TBits_1;                    // [30:30] Destination Minor Loop Offset enable
  SMLOE                  : TBits_1;                    // [31:31] Source Minor Loop Offset Enable
end;

TDMA_TCD_NBYTES_MLOFFYES_bitbanded = record
  NBYTES                 : array[0..9] of longWord;    // [0:9] Minor Byte Transfer Count
  MLOFF                  : array[0..19] of longWord;   // [10:29] If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.
  DMLOE                  : longWord;                   // [30:30] Destination Minor Loop Offset enable
  SMLOE                  : longWord;                   // [31:31] Source Minor Loop Offset Enable
end;

TDMA_TCD_NBYTES_MLOFFNO_bits = bitpacked record
  NBYTES                 : TBits_30;                   // [0:29] Minor Byte Transfer Count
  DMLOE                  : TBits_1;                    // [30:30] Destination Minor Loop Offset enable
  SMLOE                  : TBits_1;                    // [31:31] Source Minor Loop Offset Enable
end;

TDMA_TCD_NBYTES_MLOFFNO_bitbanded = record
  NBYTES                 : array[0..29] of longWord;   // [0:29] Minor Byte Transfer Count
  DMLOE                  : longWord;                   // [30:30] Destination Minor Loop Offset enable
  SMLOE                  : longWord;                   // [31:31] Source Minor Loop Offset Enable
end;

TDMA_TCD_NBYTES_MLNO_bits = bitpacked record
  NBYTES                 : TBits_32;                   // [0:31] Minor Byte Transfer Count
end;

TDMA_TCD_NBYTES_MLNO_bitbanded = record
  NBYTES                 : array[0..31] of longWord;   // [0:31] Minor Byte Transfer Count
end;

TDMA_TCD_SLAST_bits = bitpacked record
  SLAST                  : TBits_32;                   // [0:31] Last source Address Adjustment
end;

TDMA_TCD_SLAST_bitbanded = record
  SLAST                  : array[0..31] of longWord;   // [0:31] Last source Address Adjustment
end;

TDMA_TCD_DADDR_bits = bitpacked record
  DADDR                  : TBits_32;                   // [0:31] Destination Address
end;

TDMA_TCD_DADDR_bitbanded = record
  DADDR                  : array[0..31] of longWord;   // [0:31] Destination Address
end;

TDMA_TCD_DOFF_bits = bitpacked record
  DOFF                   : TBits_16;                   // [0:15] Destination Address Signed offset
end;

TDMA_TCD_DOFF_bitbanded = record
  DOFF                   : array[0..15] of longWord;   // [0:15] Destination Address Signed offset
end;

TDMA_TCD_CITER_ELINKYES_bits = bitpacked record
  CITER                  : TBits_9;                    // [0:8] Current Major Iteration Count
  LINKCH                 : TBits_4;                    // [9:12] Link Channel Number
  RESERVED0              : TBits_2;                    // [13:14] no description available
  ELINK                  : TBits_1;                    // [15:15] Enable channel-to-channel linking on minor-loop complete
end;

TDMA_TCD_CITER_ELINKYES_bitbanded = record
  CITER                  : array[0..8] of longWord;    // [0:8] Current Major Iteration Count
  LINKCH                 : array[0..3] of longWord;    // [9:12] Link Channel Number
  RESERVED0              : array[0..1] of longWord;    // [13:14] no description available
  ELINK                  : longWord;                   // [15:15] Enable channel-to-channel linking on minor-loop complete
end;

TDMA_TCD_CITER_ELINKNO_bits = bitpacked record
  CITER                  : TBits_15;                   // [0:14] Current Major Iteration Count
  ELINK                  : TBits_1;                    // [15:15] Enable channel-to-channel linking on minor-loop complete
end;

TDMA_TCD_CITER_ELINKNO_bitbanded = record
  CITER                  : array[0..14] of longWord;   // [0:14] Current Major Iteration Count
  ELINK                  : longWord;                   // [15:15] Enable channel-to-channel linking on minor-loop complete
end;

TDMA_TCD_DLASTSGA_bits = bitpacked record
  DLASTSGA               : TBits_32;                   // [0:31] no description available
end;

TDMA_TCD_DLASTSGA_bitbanded = record
  DLASTSGA               : array[0..31] of longWord;   // [0:31] no description available
end;

TDMA_TCD_CSR_bits = bitpacked record
  START                  : TBits_1;                    // [0:0] Channel Start
  INTMAJOR               : TBits_1;                    // [1:1] Enable an interrupt when major iteration count completes
  INTHALF                : TBits_1;                    // [2:2] Enable an interrupt when major counter is half complete.
  DREQ                   : TBits_1;                    // [3:3] Disable Request
  ESG                    : TBits_1;                    // [4:4] Enable Scatter/Gather Processing
  MAJORELINK             : TBits_1;                    // [5:5] Enable channel-to-channel linking on major loop complete
  ACTIVE                 : TBits_1;                    // [6:6] Channel Active
  DONE                   : TBits_1;                    // [7:7] Channel Done
  MAJORLINKCH            : TBits_4;                    // [8:11] Link Channel Number
  RESERVED0              : TBits_2;                    // [12:13] no description available
  BWC                    : TBits_2;                    // [14:15] Bandwidth Control
end;

TDMA_TCD_CSR_bitbanded = record
  START                  : longWord;                   // [0:0] Channel Start
  INTMAJOR               : longWord;                   // [1:1] Enable an interrupt when major iteration count completes
  INTHALF                : longWord;                   // [2:2] Enable an interrupt when major counter is half complete.
  DREQ                   : longWord;                   // [3:3] Disable Request
  ESG                    : longWord;                   // [4:4] Enable Scatter/Gather Processing
  MAJORELINK             : longWord;                   // [5:5] Enable channel-to-channel linking on major loop complete
  ACTIVE                 : longWord;                   // [6:6] Channel Active
  DONE                   : longWord;                   // [7:7] Channel Done
  MAJORLINKCH            : array[0..3] of longWord;    // [8:11] Link Channel Number
  RESERVED0              : array[0..1] of longWord;    // [12:13] no description available
  BWC                    : array[0..1] of longWord;    // [14:15] Bandwidth Control
end;

TDMA_TCD_BITER_ELINKYES_bits = bitpacked record
  BITER                  : TBits_9;                    // [0:8] Starting Major Iteration Count
  LINKCH                 : TBits_4;                    // [9:12] Link Channel Number
  RESERVED0              : TBits_2;                    // [13:14] no description available
  ELINK                  : TBits_1;                    // [15:15] Enables channel-to-channel linking on minor loop complete
end;

TDMA_TCD_BITER_ELINKYES_bitbanded = record
  BITER                  : array[0..8] of longWord;    // [0:8] Starting Major Iteration Count
  LINKCH                 : array[0..3] of longWord;    // [9:12] Link Channel Number
  RESERVED0              : array[0..1] of longWord;    // [13:14] no description available
  ELINK                  : longWord;                   // [15:15] Enables channel-to-channel linking on minor loop complete
end;

TDMA_TCD_BITER_ELINKNO_bits = bitpacked record
  BITER                  : TBits_15;                   // [0:14] Starting Major Iteration Count
  ELINK                  : TBits_1;                    // [15:15] Enables channel-to-channel linking on minor loop complete
end;

TDMA_TCD_BITER_ELINKNO_bitbanded = record
  BITER                  : array[0..14] of longWord;   // [0:14] Starting Major Iteration Count
  ELINK                  : longWord;                   // [15:15] Enables channel-to-channel linking on minor loop complete
end;

TDMA_Registers = record
  case boolean of false: (
  CR                     : longWord;                   // 0x00 Control Register
  ES                     : longWord;                   // 0x04 Error Status Register
  RESERVED0              : longWord;                   // 0x08
  ERQ                    : longWord;                   // 0x0C Enable Request Register
  RESERVED1              : longWord;                   // 0x10
  EEI                    : longWord;                   // 0x14 Enable Error Interrupt Register
  CEEI                   : byte;                       // 0x18 Clear Enable Error Interrupt Register
  SEEI                   : byte;                       // 0x19 Set Enable Error Interrupt Register
  CERQ                   : byte;                       // 0x1A Clear Enable Request Register
  SERQ                   : byte;                       // 0x1B Set Enable Request Register
  CDNE                   : byte;                       // 0x1C Clear DONE Status Bit Register
  SSRT                   : byte;                       // 0x1D Set START Bit Register
  CERR                   : byte;                       // 0x1E Clear Error Register
  CINT                   : byte;                       // 0x1F Clear Interrupt Request Register
  RESERVED2              : longWord;                   // 0x20
  INT                    : longWord;                   // 0x24 Interrupt Request Register
  RESERVED3              : longWord;                   // 0x28
  ERR                    : longWord;                   // 0x2C Error Register
  RESERVED4              : longWord;                   // 0x30
  HRS                    : longWord;                   // 0x34 Hardware Request Status Register
  RESERVED5              : array[0..49] of longWord;   // 0x38
  DCHPRI3                : byte;                       // 0x100 Channel n Priority Register
  DCHPRI2                : byte;                       // 0x101 Channel n Priority Register
  DCHPRI1                : byte;                       // 0x102 Channel n Priority Register
  DCHPRI0                : byte;                       // 0x103 Channel n Priority Register
  DCHPRI7                : byte;                       // 0x104 Channel n Priority Register
  DCHPRI6                : byte;                       // 0x105 Channel n Priority Register
  DCHPRI5                : byte;                       // 0x106 Channel n Priority Register
  DCHPRI4                : byte;                       // 0x107 Channel n Priority Register
  DCHPRI11               : byte;                       // 0x108 Channel n Priority Register
  DCHPRI10               : byte;                       // 0x109 Channel n Priority Register
  DCHPRI9                : byte;                       // 0x10A Channel n Priority Register
  DCHPRI8                : byte;                       // 0x10B Channel n Priority Register
  DCHPRI15               : byte;                       // 0x10C Channel n Priority Register
  DCHPRI14               : byte;                       // 0x10D Channel n Priority Register
  DCHPRI13               : byte;                       // 0x10E Channel n Priority Register
  DCHPRI12               : byte;                       // 0x10F Channel n Priority Register
  RESERVED6              : array[0..955] of longWord;  // 0x110
  TCD0_SADDR             : longWord;                   // 0x1000 TCD Source Address
  TCD0_SOFF              : word;                       // 0x1004 TCD Signed Source Address Offset
  TCD0_ATTR              : word;                       // 0x1006 TCD Transfer Attributes
  TCD0_NBYTES_MLOFFYES   : longWord;                   // 0x1008 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  TCD0_SLAST             : longWord;                   // 0x100C TCD Last Source Address Adjustment
  TCD0_DADDR             : longWord;                   // 0x1010 TCD Destination Address
  TCD0_DOFF              : word;                       // 0x1014 TCD Signed Destination Address Offset
  TCD0_CITER_ELINKYES    : word;                       // 0x1016 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD0_DLASTSGA          : longWord;                   // 0x1018 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD0_CSR               : word;                       // 0x101C TCD Control and Status
  TCD0_BITER_ELINKNO     : word;                       // 0x101E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD1_SADDR             : longWord;                   // 0x1020 TCD Source Address
  TCD1_SOFF              : word;                       // 0x1024 TCD Signed Source Address Offset
  TCD1_ATTR              : word;                       // 0x1026 TCD Transfer Attributes
  TCD1_NBYTES_MLOFFNO    : longWord;                   // 0x1028 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
  TCD1_SLAST             : longWord;                   // 0x102C TCD Last Source Address Adjustment
  TCD1_DADDR             : longWord;                   // 0x1030 TCD Destination Address
  TCD1_DOFF              : word;                       // 0x1034 TCD Signed Destination Address Offset
  TCD1_CITER_ELINKNO     : word;                       // 0x1036 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD1_DLASTSGA          : longWord;                   // 0x1038 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD1_CSR               : word;                       // 0x103C TCD Control and Status
  TCD1_BITER_ELINKNO     : word;                       // 0x103E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD2_SADDR             : longWord;                   // 0x1040 TCD Source Address
  TCD2_SOFF              : word;                       // 0x1044 TCD Signed Source Address Offset
  TCD2_ATTR              : word;                       // 0x1046 TCD Transfer Attributes
  TCD2_NBYTES_MLNO       : longWord;                   // 0x1048 TCD Minor Byte Count (Minor Loop Disabled)
  TCD2_SLAST             : longWord;                   // 0x104C TCD Last Source Address Adjustment
  TCD2_DADDR             : longWord;                   // 0x1050 TCD Destination Address
  TCD2_DOFF              : word;                       // 0x1054 TCD Signed Destination Address Offset
  TCD2_CITER_ELINKNO     : word;                       // 0x1056 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD2_DLASTSGA          : longWord;                   // 0x1058 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD2_CSR               : word;                       // 0x105C TCD Control and Status
  TCD2_BITER_ELINKYES    : word;                       // 0x105E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD3_SADDR             : longWord;                   // 0x1060 TCD Source Address
  TCD3_SOFF              : word;                       // 0x1064 TCD Signed Source Address Offset
  TCD3_ATTR              : word;                       // 0x1066 TCD Transfer Attributes
  TCD3_NBYTES_MLOFFYES   : longWord;                   // 0x1068 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  TCD3_SLAST             : longWord;                   // 0x106C TCD Last Source Address Adjustment
  TCD3_DADDR             : longWord;                   // 0x1070 TCD Destination Address
  TCD3_DOFF              : word;                       // 0x1074 TCD Signed Destination Address Offset
  TCD3_CITER_ELINKNO     : word;                       // 0x1076 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD3_DLASTSGA          : longWord;                   // 0x1078 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD3_CSR               : word;                       // 0x107C TCD Control and Status
  TCD3_BITER_ELINKYES    : word;                       // 0x107E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD4_SADDR             : longWord;                   // 0x1080 TCD Source Address
  TCD4_SOFF              : word;                       // 0x1084 TCD Signed Source Address Offset
  TCD4_ATTR              : word;                       // 0x1086 TCD Transfer Attributes
  TCD4_NBYTES_MLNO       : longWord;                   // 0x1088 TCD Minor Byte Count (Minor Loop Disabled)
  TCD4_SLAST             : longWord;                   // 0x108C TCD Last Source Address Adjustment
  TCD4_DADDR             : longWord;                   // 0x1090 TCD Destination Address
  TCD4_DOFF              : word;                       // 0x1094 TCD Signed Destination Address Offset
  TCD4_CITER_ELINKNO     : word;                       // 0x1096 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD4_DLASTSGA          : longWord;                   // 0x1098 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD4_CSR               : word;                       // 0x109C TCD Control and Status
  TCD4_BITER_ELINKYES    : word;                       // 0x109E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD5_SADDR             : longWord;                   // 0x10A0 TCD Source Address
  TCD5_SOFF              : word;                       // 0x10A4 TCD Signed Source Address Offset
  TCD5_ATTR              : word;                       // 0x10A6 TCD Transfer Attributes
  TCD5_NBYTES_MLNO       : longWord;                   // 0x10A8 TCD Minor Byte Count (Minor Loop Disabled)
  TCD5_SLAST             : longWord;                   // 0x10AC TCD Last Source Address Adjustment
  TCD5_DADDR             : longWord;                   // 0x10B0 TCD Destination Address
  TCD5_DOFF              : word;                       // 0x10B4 TCD Signed Destination Address Offset
  TCD5_CITER_ELINKYES    : word;                       // 0x10B6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD5_DLASTSGA          : longWord;                   // 0x10B8 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD5_CSR               : word;                       // 0x10BC TCD Control and Status
  TCD5_BITER_ELINKYES    : word;                       // 0x10BE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD6_SADDR             : longWord;                   // 0x10C0 TCD Source Address
  TCD6_SOFF              : word;                       // 0x10C4 TCD Signed Source Address Offset
  TCD6_ATTR              : word;                       // 0x10C6 TCD Transfer Attributes
  TCD6_NBYTES_MLNO       : longWord;                   // 0x10C8 TCD Minor Byte Count (Minor Loop Disabled)
  TCD6_SLAST             : longWord;                   // 0x10CC TCD Last Source Address Adjustment
  TCD6_DADDR             : longWord;                   // 0x10D0 TCD Destination Address
  TCD6_DOFF              : word;                       // 0x10D4 TCD Signed Destination Address Offset
  TCD6_CITER_ELINKNO     : word;                       // 0x10D6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD6_DLASTSGA          : longWord;                   // 0x10D8 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD6_CSR               : word;                       // 0x10DC TCD Control and Status
  TCD6_BITER_ELINKNO     : word;                       // 0x10DE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD7_SADDR             : longWord;                   // 0x10E0 TCD Source Address
  TCD7_SOFF              : word;                       // 0x10E4 TCD Signed Source Address Offset
  TCD7_ATTR              : word;                       // 0x10E6 TCD Transfer Attributes
  TCD7_NBYTES_MLOFFYES   : longWord;                   // 0x10E8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  TCD7_SLAST             : longWord;                   // 0x10EC TCD Last Source Address Adjustment
  TCD7_DADDR             : longWord;                   // 0x10F0 TCD Destination Address
  TCD7_DOFF              : word;                       // 0x10F4 TCD Signed Destination Address Offset
  TCD7_CITER_ELINKNO     : word;                       // 0x10F6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD7_DLASTSGA          : longWord;                   // 0x10F8 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD7_CSR               : word;                       // 0x10FC TCD Control and Status
  TCD7_BITER_ELINKNO     : word;                       // 0x10FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD8_SADDR             : longWord;                   // 0x1100 TCD Source Address
  TCD8_SOFF              : word;                       // 0x1104 TCD Signed Source Address Offset
  TCD8_ATTR              : word;                       // 0x1106 TCD Transfer Attributes
  TCD8_NBYTES_MLOFFYES   : longWord;                   // 0x1108 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  TCD8_SLAST             : longWord;                   // 0x110C TCD Last Source Address Adjustment
  TCD8_DADDR             : longWord;                   // 0x1110 TCD Destination Address
  TCD8_DOFF              : word;                       // 0x1114 TCD Signed Destination Address Offset
  TCD8_CITER_ELINKYES    : word;                       // 0x1116 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD8_DLASTSGA          : longWord;                   // 0x1118 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD8_CSR               : word;                       // 0x111C TCD Control and Status
  TCD8_BITER_ELINKNO     : word;                       // 0x111E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD9_SADDR             : longWord;                   // 0x1120 TCD Source Address
  TCD9_SOFF              : word;                       // 0x1124 TCD Signed Source Address Offset
  TCD9_ATTR              : word;                       // 0x1126 TCD Transfer Attributes
  TCD9_NBYTES_MLOFFYES   : longWord;                   // 0x1128 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  TCD9_SLAST             : longWord;                   // 0x112C TCD Last Source Address Adjustment
  TCD9_DADDR             : longWord;                   // 0x1130 TCD Destination Address
  TCD9_DOFF              : word;                       // 0x1134 TCD Signed Destination Address Offset
  TCD9_CITER_ELINKYES    : word;                       // 0x1136 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD9_DLASTSGA          : longWord;                   // 0x1138 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD9_CSR               : word;                       // 0x113C TCD Control and Status
  TCD9_BITER_ELINKYES    : word;                       // 0x113E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD10_SADDR            : longWord;                   // 0x1140 TCD Source Address
  TCD10_SOFF             : word;                       // 0x1144 TCD Signed Source Address Offset
  TCD10_ATTR             : word;                       // 0x1146 TCD Transfer Attributes
  TCD10_NBYTES_MLNO      : longWord;                   // 0x1148 TCD Minor Byte Count (Minor Loop Disabled)
  TCD10_SLAST            : longWord;                   // 0x114C TCD Last Source Address Adjustment
  TCD10_DADDR            : longWord;                   // 0x1150 TCD Destination Address
  TCD10_DOFF             : word;                       // 0x1154 TCD Signed Destination Address Offset
  TCD10_CITER_ELINKNO    : word;                       // 0x1156 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD10_DLASTSGA         : longWord;                   // 0x1158 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD10_CSR              : word;                       // 0x115C TCD Control and Status
  TCD10_BITER_ELINKNO    : word;                       // 0x115E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD11_SADDR            : longWord;                   // 0x1160 TCD Source Address
  TCD11_SOFF             : word;                       // 0x1164 TCD Signed Source Address Offset
  TCD11_ATTR             : word;                       // 0x1166 TCD Transfer Attributes
  TCD11_NBYTES_MLOFFNO   : longWord;                   // 0x1168 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
  TCD11_SLAST            : longWord;                   // 0x116C TCD Last Source Address Adjustment
  TCD11_DADDR            : longWord;                   // 0x1170 TCD Destination Address
  TCD11_DOFF             : word;                       // 0x1174 TCD Signed Destination Address Offset
  TCD11_CITER_ELINKNO    : word;                       // 0x1176 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD11_DLASTSGA         : longWord;                   // 0x1178 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD11_CSR              : word;                       // 0x117C TCD Control and Status
  TCD11_BITER_ELINKNO    : word;                       // 0x117E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD12_SADDR            : longWord;                   // 0x1180 TCD Source Address
  TCD12_SOFF             : word;                       // 0x1184 TCD Signed Source Address Offset
  TCD12_ATTR             : word;                       // 0x1186 TCD Transfer Attributes
  TCD12_NBYTES_MLOFFYES  : longWord;                   // 0x1188 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  TCD12_SLAST            : longWord;                   // 0x118C TCD Last Source Address Adjustment
  TCD12_DADDR            : longWord;                   // 0x1190 TCD Destination Address
  TCD12_DOFF             : word;                       // 0x1194 TCD Signed Destination Address Offset
  TCD12_CITER_ELINKNO    : word;                       // 0x1196 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD12_DLASTSGA         : longWord;                   // 0x1198 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD12_CSR              : word;                       // 0x119C TCD Control and Status
  TCD12_BITER_ELINKNO    : word;                       // 0x119E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD13_SADDR            : longWord;                   // 0x11A0 TCD Source Address
  TCD13_SOFF             : word;                       // 0x11A4 TCD Signed Source Address Offset
  TCD13_ATTR             : word;                       // 0x11A6 TCD Transfer Attributes
  TCD13_NBYTES_MLOFFYES  : longWord;                   // 0x11A8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  TCD13_SLAST            : longWord;                   // 0x11AC TCD Last Source Address Adjustment
  TCD13_DADDR            : longWord;                   // 0x11B0 TCD Destination Address
  TCD13_DOFF             : word;                       // 0x11B4 TCD Signed Destination Address Offset
  TCD13_CITER_ELINKYES   : word;                       // 0x11B6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD13_DLASTSGA         : longWord;                   // 0x11B8 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD13_CSR              : word;                       // 0x11BC TCD Control and Status
  TCD13_BITER_ELINKYES   : word;                       // 0x11BE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD14_SADDR            : longWord;                   // 0x11C0 TCD Source Address
  TCD14_SOFF             : word;                       // 0x11C4 TCD Signed Source Address Offset
  TCD14_ATTR             : word;                       // 0x11C6 TCD Transfer Attributes
  TCD14_NBYTES_MLNO      : longWord;                   // 0x11C8 TCD Minor Byte Count (Minor Loop Disabled)
  TCD14_SLAST            : longWord;                   // 0x11CC TCD Last Source Address Adjustment
  TCD14_DADDR            : longWord;                   // 0x11D0 TCD Destination Address
  TCD14_DOFF             : word;                       // 0x11D4 TCD Signed Destination Address Offset
  TCD14_CITER_ELINKNO    : word;                       // 0x11D6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD14_DLASTSGA         : longWord;                   // 0x11D8 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD14_CSR              : word;                       // 0x11DC TCD Control and Status
  TCD14_BITER_ELINKNO    : word;                       // 0x11DE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD15_SADDR            : longWord;                   // 0x11E0 TCD Source Address
  TCD15_SOFF             : word;                       // 0x11E4 TCD Signed Source Address Offset
  TCD15_ATTR             : word;                       // 0x11E6 TCD Transfer Attributes
  TCD15_NBYTES_MLOFFNO   : longWord;                   // 0x11E8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
  TCD15_SLAST            : longWord;                   // 0x11EC TCD Last Source Address Adjustment
  TCD15_DADDR            : longWord;                   // 0x11F0 TCD Destination Address
  TCD15_DOFF             : word;                       // 0x11F4 TCD Signed Destination Address Offset
  TCD15_CITER_ELINKNO    : word;                       // 0x11F6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD15_DLASTSGA         : longWord;                   // 0x11F8 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD15_CSR              : word;                       // 0x11FC TCD Control and Status
  TCD15_BITER_ELINKNO    : word;                       // 0x11FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
);
true : (
CR_bits                  : TDMA_CR_bits;               // 0x04 Control Register
ES_bits                  : TDMA_ES_bits;               // 0x08 Error Status Register
RESERVED_bits0           : longWord;
ERQ_bits                 : TDMA_ERQ_bits;              // 0x10 Enable Request Register
RESERVED_bits1           : longWord;
EEI_bits                 : TDMA_EEI_bits;              // 0x18 Enable Error Interrupt Register
CEEI_bits                : TDMA_CEEI_bits;             // 0x19 Clear Enable Error Interrupt Register
SEEI_bits                : TDMA_SEEI_bits;             // 0x1A Set Enable Error Interrupt Register
CERQ_bits                : TDMA_CERQ_bits;             // 0x1B Clear Enable Request Register
SERQ_bits                : TDMA_SERQ_bits;             // 0x1C Set Enable Request Register
CDNE_bits                : TDMA_CDNE_bits;             // 0x1D Clear DONE Status Bit Register
SSRT_bits                : TDMA_SSRT_bits;             // 0x1E Set START Bit Register
CERR_bits                : TDMA_CERR_bits;             // 0x1F Clear Error Register
CINT_bits                : TDMA_CINT_bits;             // 0x20 Clear Interrupt Request Register
RESERVED_bits2           : longWord;
INT_bits                 : TDMA_INT_bits;              // 0x28 Interrupt Request Register
RESERVED_bits3           : longWord;
ERR_bits                 : TDMA_ERR_bits;              // 0x30 Error Register
RESERVED_bits4           : longWord;
HRS_bits                 : TDMA_HRS_bits;              // 0x38 Hardware Request Status Register
RESERVED_bits5           : array[0..49] of longWord;
DCHPRI3_bits             : TDMA_DCHPRI_bits;           // 0x101 Channel n Priority Register
DCHPRI2_bits             : TDMA_DCHPRI_bits;           // 0x102 Channel n Priority Register
DCHPRI1_bits             : TDMA_DCHPRI_bits;           // 0x103 Channel n Priority Register
DCHPRI0_bits             : TDMA_DCHPRI_bits;           // 0x104 Channel n Priority Register
DCHPRI7_bits             : TDMA_DCHPRI_bits;           // 0x105 Channel n Priority Register
DCHPRI6_bits             : TDMA_DCHPRI_bits;           // 0x106 Channel n Priority Register
DCHPRI5_bits             : TDMA_DCHPRI_bits;           // 0x107 Channel n Priority Register
DCHPRI4_bits             : TDMA_DCHPRI_bits;           // 0x108 Channel n Priority Register
DCHPRI11_bits            : TDMA_DCHPRI_bits;           // 0x109 Channel n Priority Register
DCHPRI10_bits            : TDMA_DCHPRI_bits;           // 0x10A Channel n Priority Register
DCHPRI9_bits             : TDMA_DCHPRI_bits;           // 0x10B Channel n Priority Register
DCHPRI8_bits             : TDMA_DCHPRI_bits;           // 0x10C Channel n Priority Register
DCHPRI15_bits            : TDMA_DCHPRI_bits;           // 0x10D Channel n Priority Register
DCHPRI14_bits            : TDMA_DCHPRI_bits;           // 0x10E Channel n Priority Register
DCHPRI13_bits            : TDMA_DCHPRI_bits;           // 0x10F Channel n Priority Register
DCHPRI12_bits            : TDMA_DCHPRI_bits;           // 0x110 Channel n Priority Register
RESERVED_bits6           : array[0..955] of longWord;
TCD0_SADDR_bits          : longWord;                   // 0x1000 TCD Source Address
TCD0_SOFF_bits           : word;                       // 0x1004 TCD Signed Source Address Offset
TCD0_ATTR_bits           : word;                       // 0x1006 TCD Transfer Attributes
TCD0_NBYTES_MLOFFYES_bits : longWord;                  // 0x1008 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
TCD0_SLAST_bits          : longWord;                   // 0x100C TCD Last Source Address Adjustment
TCD0_DADDR_bits          : longWord;                   // 0x1010 TCD Destination Address
TCD0_DOFF_bits           : word;                       // 0x1014 TCD Signed Destination Address Offset
TCD0_CITER_ELINKYES_bits : word;                       // 0x1016 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
TCD0_DLASTSGA_bits       : longWord;                   // 0x1018 TCD Last Destination Address Adjustment/Scatter Gather Address
TCD0_CSR_bits            : word;                       // 0x101C TCD Control and Status
TCD0_BITER_ELINKNO_bits  : word;                       // 0x101E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD1_SADDR_bits          : longWord;                   // 0x1020 TCD Source Address
TCD1_SOFF_bits           : word;                       // 0x1024 TCD Signed Source Address Offset
TCD1_ATTR_bits           : word;                       // 0x1026 TCD Transfer Attributes
TCD1_NBYTES_MLOFFNO_bits : longWord;                   // 0x1028 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
TCD1_SLAST_bits          : longWord;                   // 0x102C TCD Last Source Address Adjustment
TCD1_DADDR_bits          : longWord;                   // 0x1030 TCD Destination Address
TCD1_DOFF_bits           : word;                       // 0x1034 TCD Signed Destination Address Offset
TCD1_CITER_ELINKNO_bits  : word;                       // 0x1036 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD1_DLASTSGA_bits       : longWord;                   // 0x1038 TCD Last Destination Address Adjustment/Scatter Gather Address
TCD1_CSR_bits            : word;                       // 0x103C TCD Control and Status
TCD1_BITER_ELINKNO_bits  : word;                       // 0x103E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD2_SADDR_bits          : longWord;                   // 0x1040 TCD Source Address
TCD2_SOFF_bits           : word;                       // 0x1044 TCD Signed Source Address Offset
TCD2_ATTR_bits           : word;                       // 0x1046 TCD Transfer Attributes
TCD2_NBYTES_MLNO_bits    : longWord;                   // 0x1048 TCD Minor Byte Count (Minor Loop Disabled)
TCD2_SLAST_bits          : longWord;                   // 0x104C TCD Last Source Address Adjustment
TCD2_DADDR_bits          : longWord;                   // 0x1050 TCD Destination Address
TCD2_DOFF_bits           : word;                       // 0x1054 TCD Signed Destination Address Offset
TCD2_CITER_ELINKNO_bits  : word;                       // 0x1056 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD2_DLASTSGA_bits       : longWord;                   // 0x1058 TCD Last Destination Address Adjustment/Scatter Gather Address
TCD2_CSR_bits            : word;                       // 0x105C TCD Control and Status
TCD2_BITER_ELINKYES_bits : word;                       // 0x105E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
TCD3_SADDR_bits          : longWord;                   // 0x1060 TCD Source Address
TCD3_SOFF_bits           : word;                       // 0x1064 TCD Signed Source Address Offset
TCD3_ATTR_bits           : word;                       // 0x1066 TCD Transfer Attributes
TCD3_NBYTES_MLOFFYES_bits : longWord;                  // 0x1068 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
TCD3_SLAST_bits          : longWord;                   // 0x106C TCD Last Source Address Adjustment
TCD3_DADDR_bits          : longWord;                   // 0x1070 TCD Destination Address
TCD3_DOFF_bits           : word;                       // 0x1074 TCD Signed Destination Address Offset
TCD3_CITER_ELINKNO_bits  : word;                       // 0x1076 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD3_DLASTSGA_bits       : longWord;                   // 0x1078 TCD Last Destination Address Adjustment/Scatter Gather Address
TCD3_CSR_bits            : word;                       // 0x107C TCD Control and Status
TCD3_BITER_ELINKYES_bits : word;                       // 0x107E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
TCD4_SADDR_bits          : longWord;                   // 0x1080 TCD Source Address
TCD4_SOFF_bits           : word;                       // 0x1084 TCD Signed Source Address Offset
TCD4_ATTR_bits           : word;                       // 0x1086 TCD Transfer Attributes
TCD4_NBYTES_MLNO_bits    : longWord;                   // 0x1088 TCD Minor Byte Count (Minor Loop Disabled)
TCD4_SLAST_bits          : longWord;                   // 0x108C TCD Last Source Address Adjustment
TCD4_DADDR_bits          : longWord;                   // 0x1090 TCD Destination Address
TCD4_DOFF_bits           : word;                       // 0x1094 TCD Signed Destination Address Offset
TCD4_CITER_ELINKNO_bits  : word;                       // 0x1096 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD4_DLASTSGA_bits       : longWord;                   // 0x1098 TCD Last Destination Address Adjustment/Scatter Gather Address
TCD4_CSR_bits            : word;                       // 0x109C TCD Control and Status
TCD4_BITER_ELINKYES_bits : word;                       // 0x109E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
TCD5_SADDR_bits          : longWord;                   // 0x10A0 TCD Source Address
TCD5_SOFF_bits           : word;                       // 0x10A4 TCD Signed Source Address Offset
TCD5_ATTR_bits           : word;                       // 0x10A6 TCD Transfer Attributes
TCD5_NBYTES_MLNO_bits    : longWord;                   // 0x10A8 TCD Minor Byte Count (Minor Loop Disabled)
TCD5_SLAST_bits          : longWord;                   // 0x10AC TCD Last Source Address Adjustment
TCD5_DADDR_bits          : longWord;                   // 0x10B0 TCD Destination Address
TCD5_DOFF_bits           : word;                       // 0x10B4 TCD Signed Destination Address Offset
TCD5_CITER_ELINKYES_bits : word;                       // 0x10B6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
TCD5_DLASTSGA_bits       : longWord;                   // 0x10B8 TCD Last Destination Address Adjustment/Scatter Gather Address
TCD5_CSR_bits            : word;                       // 0x10BC TCD Control and Status
TCD5_BITER_ELINKYES_bits : word;                       // 0x10BE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
TCD6_SADDR_bits          : longWord;                   // 0x10C0 TCD Source Address
TCD6_SOFF_bits           : word;                       // 0x10C4 TCD Signed Source Address Offset
TCD6_ATTR_bits           : word;                       // 0x10C6 TCD Transfer Attributes
TCD6_NBYTES_MLNO_bits    : longWord;                   // 0x10C8 TCD Minor Byte Count (Minor Loop Disabled)
TCD6_SLAST_bits          : longWord;                   // 0x10CC TCD Last Source Address Adjustment
TCD6_DADDR_bits          : longWord;                   // 0x10D0 TCD Destination Address
TCD6_DOFF_bits           : word;                       // 0x10D4 TCD Signed Destination Address Offset
TCD6_CITER_ELINKNO_bits  : word;                       // 0x10D6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD6_DLASTSGA_bits       : longWord;                   // 0x10D8 TCD Last Destination Address Adjustment/Scatter Gather Address
TCD6_CSR_bits            : word;                       // 0x10DC TCD Control and Status
TCD6_BITER_ELINKNO_bits  : word;                       // 0x10DE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD7_SADDR_bits          : longWord;                   // 0x10E0 TCD Source Address
TCD7_SOFF_bits           : word;                       // 0x10E4 TCD Signed Source Address Offset
TCD7_ATTR_bits           : word;                       // 0x10E6 TCD Transfer Attributes
TCD7_NBYTES_MLOFFYES_bits : longWord;                  // 0x10E8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
TCD7_SLAST_bits          : longWord;                   // 0x10EC TCD Last Source Address Adjustment
TCD7_DADDR_bits          : longWord;                   // 0x10F0 TCD Destination Address
TCD7_DOFF_bits           : word;                       // 0x10F4 TCD Signed Destination Address Offset
TCD7_CITER_ELINKNO_bits  : word;                       // 0x10F6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD7_DLASTSGA_bits       : longWord;                   // 0x10F8 TCD Last Destination Address Adjustment/Scatter Gather Address
TCD7_CSR_bits            : word;                       // 0x10FC TCD Control and Status
TCD7_BITER_ELINKNO_bits  : word;                       // 0x10FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD8_SADDR_bits          : longWord;                   // 0x1100 TCD Source Address
TCD8_SOFF_bits           : word;                       // 0x1104 TCD Signed Source Address Offset
TCD8_ATTR_bits           : word;                       // 0x1106 TCD Transfer Attributes
TCD8_NBYTES_MLOFFYES_bits : longWord;                  // 0x1108 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
TCD8_SLAST_bits          : longWord;                   // 0x110C TCD Last Source Address Adjustment
TCD8_DADDR_bits          : longWord;                   // 0x1110 TCD Destination Address
TCD8_DOFF_bits           : word;                       // 0x1114 TCD Signed Destination Address Offset
TCD8_CITER_ELINKYES_bits : word;                       // 0x1116 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
TCD8_DLASTSGA_bits       : longWord;                   // 0x1118 TCD Last Destination Address Adjustment/Scatter Gather Address
TCD8_CSR_bits            : word;                       // 0x111C TCD Control and Status
TCD8_BITER_ELINKNO_bits  : word;                       // 0x111E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD9_SADDR_bits          : longWord;                   // 0x1120 TCD Source Address
TCD9_SOFF_bits           : word;                       // 0x1124 TCD Signed Source Address Offset
TCD9_ATTR_bits           : word;                       // 0x1126 TCD Transfer Attributes
TCD9_NBYTES_MLOFFYES_bits : longWord;                  // 0x1128 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
TCD9_SLAST_bits          : longWord;                   // 0x112C TCD Last Source Address Adjustment
TCD9_DADDR_bits          : longWord;                   // 0x1130 TCD Destination Address
TCD9_DOFF_bits           : word;                       // 0x1134 TCD Signed Destination Address Offset
TCD9_CITER_ELINKYES_bits : word;                       // 0x1136 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
TCD9_DLASTSGA_bits       : longWord;                   // 0x1138 TCD Last Destination Address Adjustment/Scatter Gather Address
TCD9_CSR_bits            : word;                       // 0x113C TCD Control and Status
TCD9_BITER_ELINKYES_bits : word;                       // 0x113E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
TCD10_SADDR_bits         : longWord;                   // 0x1140 TCD Source Address
TCD10_SOFF_bits          : word;                       // 0x1144 TCD Signed Source Address Offset
TCD10_ATTR_bits          : word;                       // 0x1146 TCD Transfer Attributes
TCD10_NBYTES_MLNO_bits   : longWord;                   // 0x1148 TCD Minor Byte Count (Minor Loop Disabled)
TCD10_SLAST_bits         : longWord;                   // 0x114C TCD Last Source Address Adjustment
TCD10_DADDR_bits         : longWord;                   // 0x1150 TCD Destination Address
TCD10_DOFF_bits          : word;                       // 0x1154 TCD Signed Destination Address Offset
TCD10_CITER_ELINKNO_bits : word;                       // 0x1156 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD10_DLASTSGA_bits      : longWord;                   // 0x1158 TCD Last Destination Address Adjustment/Scatter Gather Address
TCD10_CSR_bits           : word;                       // 0x115C TCD Control and Status
TCD10_BITER_ELINKNO_bits : word;                       // 0x115E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD11_SADDR_bits         : longWord;                   // 0x1160 TCD Source Address
TCD11_SOFF_bits          : word;                       // 0x1164 TCD Signed Source Address Offset
TCD11_ATTR_bits          : word;                       // 0x1166 TCD Transfer Attributes
TCD11_NBYTES_MLOFFNO_bits : longWord;                  // 0x1168 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
TCD11_SLAST_bits         : longWord;                   // 0x116C TCD Last Source Address Adjustment
TCD11_DADDR_bits         : longWord;                   // 0x1170 TCD Destination Address
TCD11_DOFF_bits          : word;                       // 0x1174 TCD Signed Destination Address Offset
TCD11_CITER_ELINKNO_bits : word;                       // 0x1176 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD11_DLASTSGA_bits      : longWord;                   // 0x1178 TCD Last Destination Address Adjustment/Scatter Gather Address
TCD11_CSR_bits           : word;                       // 0x117C TCD Control and Status
TCD11_BITER_ELINKNO_bits : word;                       // 0x117E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD12_SADDR_bits         : longWord;                   // 0x1180 TCD Source Address
TCD12_SOFF_bits          : word;                       // 0x1184 TCD Signed Source Address Offset
TCD12_ATTR_bits          : word;                       // 0x1186 TCD Transfer Attributes
TCD12_NBYTES_MLOFFYES_bits : longWord;                 // 0x1188 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
TCD12_SLAST_bits         : longWord;                   // 0x118C TCD Last Source Address Adjustment
TCD12_DADDR_bits         : longWord;                   // 0x1190 TCD Destination Address
TCD12_DOFF_bits          : word;                       // 0x1194 TCD Signed Destination Address Offset
TCD12_CITER_ELINKNO_bits : word;                       // 0x1196 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD12_DLASTSGA_bits      : longWord;                   // 0x1198 TCD Last Destination Address Adjustment/Scatter Gather Address
TCD12_CSR_bits           : word;                       // 0x119C TCD Control and Status
TCD12_BITER_ELINKNO_bits : word;                       // 0x119E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD13_SADDR_bits         : longWord;                   // 0x11A0 TCD Source Address
TCD13_SOFF_bits          : word;                       // 0x11A4 TCD Signed Source Address Offset
TCD13_ATTR_bits          : word;                       // 0x11A6 TCD Transfer Attributes
TCD13_NBYTES_MLOFFYES_bits : longWord;                 // 0x11A8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
TCD13_SLAST_bits         : longWord;                   // 0x11AC TCD Last Source Address Adjustment
TCD13_DADDR_bits         : longWord;                   // 0x11B0 TCD Destination Address
TCD13_DOFF_bits          : word;                       // 0x11B4 TCD Signed Destination Address Offset
TCD13_CITER_ELINKYES_bits : word;                      // 0x11B6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
TCD13_DLASTSGA_bits      : longWord;                   // 0x11B8 TCD Last Destination Address Adjustment/Scatter Gather Address
TCD13_CSR_bits           : word;                       // 0x11BC TCD Control and Status
TCD13_BITER_ELINKYES_bits : word;                      // 0x11BE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
TCD14_SADDR_bits         : longWord;                   // 0x11C0 TCD Source Address
TCD14_SOFF_bits          : word;                       // 0x11C4 TCD Signed Source Address Offset
TCD14_ATTR_bits          : word;                       // 0x11C6 TCD Transfer Attributes
TCD14_NBYTES_MLNO_bits   : longWord;                   // 0x11C8 TCD Minor Byte Count (Minor Loop Disabled)
TCD14_SLAST_bits         : longWord;                   // 0x11CC TCD Last Source Address Adjustment
TCD14_DADDR_bits         : longWord;                   // 0x11D0 TCD Destination Address
TCD14_DOFF_bits          : word;                       // 0x11D4 TCD Signed Destination Address Offset
TCD14_CITER_ELINKNO_bits : word;                       // 0x11D6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD14_DLASTSGA_bits      : longWord;                   // 0x11D8 TCD Last Destination Address Adjustment/Scatter Gather Address
TCD14_CSR_bits           : word;                       // 0x11DC TCD Control and Status
TCD14_BITER_ELINKNO_bits : word;                       // 0x11DE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD15_SADDR_bits         : longWord;                   // 0x11E0 TCD Source Address
TCD15_SOFF_bits          : word;                       // 0x11E4 TCD Signed Source Address Offset
TCD15_ATTR_bits          : word;                       // 0x11E6 TCD Transfer Attributes
TCD15_NBYTES_MLOFFNO_bits : longWord;                  // 0x11E8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
TCD15_SLAST_bits         : longWord;                   // 0x11EC TCD Last Source Address Adjustment
TCD15_DADDR_bits         : longWord;                   // 0x11F0 TCD Destination Address
TCD15_DOFF_bits          : word;                       // 0x11F4 TCD Signed Destination Address Offset
TCD15_CITER_ELINKNO_bits : word;                       // 0x11F6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
TCD15_DLASTSGA_bits      : longWord;                   // 0x11F8 TCD Last Destination Address Adjustment/Scatter Gather Address
TCD15_CSR_bits           : word;                       // 0x11FC TCD Control and Status
TCD15_BITER_ELINKNO_bits : word;                       // 0x11FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
);
end;

TDMARegisters_bitbanded = record
  CR                     : TDMA_CR_bitbanded;          // 0x04 Control Register
  ES                     : TDMA_ES_bitbanded;          // 0x08 Error Status Register
  RESERVED0              : array[0..3] of array[0..7] of longWord;
  ERQ                    : TDMA_ERQ_bitbanded;         // 0x10 Enable Request Register
  RESERVED1              : array[0..3] of array[0..7] of longWord;
  EEI                    : TDMA_EEI_bitbanded;         // 0x18 Enable Error Interrupt Register
  CEEI                   : TDMA_CEEI_bitbanded;        // 0x19 Clear Enable Error Interrupt Register
  SEEI                   : TDMA_SEEI_bitbanded;        // 0x1A Set Enable Error Interrupt Register
  CERQ                   : TDMA_CERQ_bitbanded;        // 0x1B Clear Enable Request Register
  SERQ                   : TDMA_SERQ_bitbanded;        // 0x1C Set Enable Request Register
  CDNE                   : TDMA_CDNE_bitbanded;        // 0x1D Clear DONE Status Bit Register
  SSRT                   : TDMA_SSRT_bitbanded;        // 0x1E Set START Bit Register
  CERR                   : TDMA_CERR_bitbanded;        // 0x1F Clear Error Register
  CINT                   : TDMA_CINT_bitbanded;        // 0x20 Clear Interrupt Request Register
  RESERVED2              : array[0..3] of array[0..7] of longWord;
  INT                    : TDMA_INT_bitbanded;         // 0x28 Interrupt Request Register
  RESERVED3              : array[0..3] of array[0..7] of longWord;
  ERR                    : TDMA_ERR_bitbanded;         // 0x30 Error Register
  RESERVED4              : array[0..3] of array[0..7] of longWord;
  HRS                    : TDMA_HRS_bitbanded;         // 0x38 Hardware Request Status Register
  RESERVED5              : array[0..199] of array[0..7] of longWord;
  DCHPRI3                : TDMA_DCHPRI_bitbanded;      // 0x101 Channel n Priority Register
  DCHPRI2                : TDMA_DCHPRI_bitbanded;      // 0x102 Channel n Priority Register
  DCHPRI1                : TDMA_DCHPRI_bitbanded;      // 0x103 Channel n Priority Register
  DCHPRI0                : TDMA_DCHPRI_bitbanded;      // 0x104 Channel n Priority Register
  DCHPRI7                : TDMA_DCHPRI_bitbanded;      // 0x105 Channel n Priority Register
  DCHPRI6                : TDMA_DCHPRI_bitbanded;      // 0x106 Channel n Priority Register
  DCHPRI5                : TDMA_DCHPRI_bitbanded;      // 0x107 Channel n Priority Register
  DCHPRI4                : TDMA_DCHPRI_bitbanded;      // 0x108 Channel n Priority Register
  DCHPRI11               : TDMA_DCHPRI_bitbanded;      // 0x109 Channel n Priority Register
  DCHPRI10               : TDMA_DCHPRI_bitbanded;      // 0x10A Channel n Priority Register
  DCHPRI9                : TDMA_DCHPRI_bitbanded;      // 0x10B Channel n Priority Register
  DCHPRI8                : TDMA_DCHPRI_bitbanded;      // 0x10C Channel n Priority Register
  DCHPRI15               : TDMA_DCHPRI_bitbanded;      // 0x10D Channel n Priority Register
  DCHPRI14               : TDMA_DCHPRI_bitbanded;      // 0x10E Channel n Priority Register
  DCHPRI13               : TDMA_DCHPRI_bitbanded;      // 0x10F Channel n Priority Register
  DCHPRI12               : TDMA_DCHPRI_bitbanded;      // 0x110 Channel n Priority Register
  RESERVED6              : array[0..3823] of array[0..7] of longWord;
  TCD0_SADDR_bitbanded   : longWord;                   // 0x1000 TCD Source Address
  TCD0_SOFF_bitbanded    : word;                       // 0x1004 TCD Signed Source Address Offset
  TCD0_ATTR_bitbanded    : word;                       // 0x1006 TCD Transfer Attributes
  TCD0_NBYTES_MLOFFYES_bitbanded : longWord;           // 0x1008 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  TCD0_SLAST_bitbanded   : longWord;                   // 0x100C TCD Last Source Address Adjustment
  TCD0_DADDR_bitbanded   : longWord;                   // 0x1010 TCD Destination Address
  TCD0_DOFF_bitbanded    : word;                       // 0x1014 TCD Signed Destination Address Offset
  TCD0_CITER_ELINKYES_bitbanded : word;                // 0x1016 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD0_DLASTSGA_bitbanded : longWord;                  // 0x1018 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD0_CSR_bitbanded     : word;                       // 0x101C TCD Control and Status
  TCD0_BITER_ELINKNO_bitbanded : word;                 // 0x101E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD1_SADDR_bitbanded   : longWord;                   // 0x1020 TCD Source Address
  TCD1_SOFF_bitbanded    : word;                       // 0x1024 TCD Signed Source Address Offset
  TCD1_ATTR_bitbanded    : word;                       // 0x1026 TCD Transfer Attributes
  TCD1_NBYTES_MLOFFNO_bitbanded : longWord;            // 0x1028 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
  TCD1_SLAST_bitbanded   : longWord;                   // 0x102C TCD Last Source Address Adjustment
  TCD1_DADDR_bitbanded   : longWord;                   // 0x1030 TCD Destination Address
  TCD1_DOFF_bitbanded    : word;                       // 0x1034 TCD Signed Destination Address Offset
  TCD1_CITER_ELINKNO_bitbanded : word;                 // 0x1036 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD1_DLASTSGA_bitbanded : longWord;                  // 0x1038 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD1_CSR_bitbanded     : word;                       // 0x103C TCD Control and Status
  TCD1_BITER_ELINKNO_bitbanded : word;                 // 0x103E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD2_SADDR_bitbanded   : longWord;                   // 0x1040 TCD Source Address
  TCD2_SOFF_bitbanded    : word;                       // 0x1044 TCD Signed Source Address Offset
  TCD2_ATTR_bitbanded    : word;                       // 0x1046 TCD Transfer Attributes
  TCD2_NBYTES_MLNO_bitbanded : longWord;               // 0x1048 TCD Minor Byte Count (Minor Loop Disabled)
  TCD2_SLAST_bitbanded   : longWord;                   // 0x104C TCD Last Source Address Adjustment
  TCD2_DADDR_bitbanded   : longWord;                   // 0x1050 TCD Destination Address
  TCD2_DOFF_bitbanded    : word;                       // 0x1054 TCD Signed Destination Address Offset
  TCD2_CITER_ELINKNO_bitbanded : word;                 // 0x1056 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD2_DLASTSGA_bitbanded : longWord;                  // 0x1058 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD2_CSR_bitbanded     : word;                       // 0x105C TCD Control and Status
  TCD2_BITER_ELINKYES_bitbanded : word;                // 0x105E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD3_SADDR_bitbanded   : longWord;                   // 0x1060 TCD Source Address
  TCD3_SOFF_bitbanded    : word;                       // 0x1064 TCD Signed Source Address Offset
  TCD3_ATTR_bitbanded    : word;                       // 0x1066 TCD Transfer Attributes
  TCD3_NBYTES_MLOFFYES_bitbanded : longWord;           // 0x1068 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  TCD3_SLAST_bitbanded   : longWord;                   // 0x106C TCD Last Source Address Adjustment
  TCD3_DADDR_bitbanded   : longWord;                   // 0x1070 TCD Destination Address
  TCD3_DOFF_bitbanded    : word;                       // 0x1074 TCD Signed Destination Address Offset
  TCD3_CITER_ELINKNO_bitbanded : word;                 // 0x1076 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD3_DLASTSGA_bitbanded : longWord;                  // 0x1078 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD3_CSR_bitbanded     : word;                       // 0x107C TCD Control and Status
  TCD3_BITER_ELINKYES_bitbanded : word;                // 0x107E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD4_SADDR_bitbanded   : longWord;                   // 0x1080 TCD Source Address
  TCD4_SOFF_bitbanded    : word;                       // 0x1084 TCD Signed Source Address Offset
  TCD4_ATTR_bitbanded    : word;                       // 0x1086 TCD Transfer Attributes
  TCD4_NBYTES_MLNO_bitbanded : longWord;               // 0x1088 TCD Minor Byte Count (Minor Loop Disabled)
  TCD4_SLAST_bitbanded   : longWord;                   // 0x108C TCD Last Source Address Adjustment
  TCD4_DADDR_bitbanded   : longWord;                   // 0x1090 TCD Destination Address
  TCD4_DOFF_bitbanded    : word;                       // 0x1094 TCD Signed Destination Address Offset
  TCD4_CITER_ELINKNO_bitbanded : word;                 // 0x1096 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD4_DLASTSGA_bitbanded : longWord;                  // 0x1098 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD4_CSR_bitbanded     : word;                       // 0x109C TCD Control and Status
  TCD4_BITER_ELINKYES_bitbanded : word;                // 0x109E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD5_SADDR_bitbanded   : longWord;                   // 0x10A0 TCD Source Address
  TCD5_SOFF_bitbanded    : word;                       // 0x10A4 TCD Signed Source Address Offset
  TCD5_ATTR_bitbanded    : word;                       // 0x10A6 TCD Transfer Attributes
  TCD5_NBYTES_MLNO_bitbanded : longWord;               // 0x10A8 TCD Minor Byte Count (Minor Loop Disabled)
  TCD5_SLAST_bitbanded   : longWord;                   // 0x10AC TCD Last Source Address Adjustment
  TCD5_DADDR_bitbanded   : longWord;                   // 0x10B0 TCD Destination Address
  TCD5_DOFF_bitbanded    : word;                       // 0x10B4 TCD Signed Destination Address Offset
  TCD5_CITER_ELINKYES_bitbanded : word;                // 0x10B6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD5_DLASTSGA_bitbanded : longWord;                  // 0x10B8 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD5_CSR_bitbanded     : word;                       // 0x10BC TCD Control and Status
  TCD5_BITER_ELINKYES_bitbanded : word;                // 0x10BE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD6_SADDR_bitbanded   : longWord;                   // 0x10C0 TCD Source Address
  TCD6_SOFF_bitbanded    : word;                       // 0x10C4 TCD Signed Source Address Offset
  TCD6_ATTR_bitbanded    : word;                       // 0x10C6 TCD Transfer Attributes
  TCD6_NBYTES_MLNO_bitbanded : longWord;               // 0x10C8 TCD Minor Byte Count (Minor Loop Disabled)
  TCD6_SLAST_bitbanded   : longWord;                   // 0x10CC TCD Last Source Address Adjustment
  TCD6_DADDR_bitbanded   : longWord;                   // 0x10D0 TCD Destination Address
  TCD6_DOFF_bitbanded    : word;                       // 0x10D4 TCD Signed Destination Address Offset
  TCD6_CITER_ELINKNO_bitbanded : word;                 // 0x10D6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD6_DLASTSGA_bitbanded : longWord;                  // 0x10D8 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD6_CSR_bitbanded     : word;                       // 0x10DC TCD Control and Status
  TCD6_BITER_ELINKNO_bitbanded : word;                 // 0x10DE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD7_SADDR_bitbanded   : longWord;                   // 0x10E0 TCD Source Address
  TCD7_SOFF_bitbanded    : word;                       // 0x10E4 TCD Signed Source Address Offset
  TCD7_ATTR_bitbanded    : word;                       // 0x10E6 TCD Transfer Attributes
  TCD7_NBYTES_MLOFFYES_bitbanded : longWord;           // 0x10E8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  TCD7_SLAST_bitbanded   : longWord;                   // 0x10EC TCD Last Source Address Adjustment
  TCD7_DADDR_bitbanded   : longWord;                   // 0x10F0 TCD Destination Address
  TCD7_DOFF_bitbanded    : word;                       // 0x10F4 TCD Signed Destination Address Offset
  TCD7_CITER_ELINKNO_bitbanded : word;                 // 0x10F6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD7_DLASTSGA_bitbanded : longWord;                  // 0x10F8 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD7_CSR_bitbanded     : word;                       // 0x10FC TCD Control and Status
  TCD7_BITER_ELINKNO_bitbanded : word;                 // 0x10FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD8_SADDR_bitbanded   : longWord;                   // 0x1100 TCD Source Address
  TCD8_SOFF_bitbanded    : word;                       // 0x1104 TCD Signed Source Address Offset
  TCD8_ATTR_bitbanded    : word;                       // 0x1106 TCD Transfer Attributes
  TCD8_NBYTES_MLOFFYES_bitbanded : longWord;           // 0x1108 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  TCD8_SLAST_bitbanded   : longWord;                   // 0x110C TCD Last Source Address Adjustment
  TCD8_DADDR_bitbanded   : longWord;                   // 0x1110 TCD Destination Address
  TCD8_DOFF_bitbanded    : word;                       // 0x1114 TCD Signed Destination Address Offset
  TCD8_CITER_ELINKYES_bitbanded : word;                // 0x1116 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD8_DLASTSGA_bitbanded : longWord;                  // 0x1118 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD8_CSR_bitbanded     : word;                       // 0x111C TCD Control and Status
  TCD8_BITER_ELINKNO_bitbanded : word;                 // 0x111E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD9_SADDR_bitbanded   : longWord;                   // 0x1120 TCD Source Address
  TCD9_SOFF_bitbanded    : word;                       // 0x1124 TCD Signed Source Address Offset
  TCD9_ATTR_bitbanded    : word;                       // 0x1126 TCD Transfer Attributes
  TCD9_NBYTES_MLOFFYES_bitbanded : longWord;           // 0x1128 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  TCD9_SLAST_bitbanded   : longWord;                   // 0x112C TCD Last Source Address Adjustment
  TCD9_DADDR_bitbanded   : longWord;                   // 0x1130 TCD Destination Address
  TCD9_DOFF_bitbanded    : word;                       // 0x1134 TCD Signed Destination Address Offset
  TCD9_CITER_ELINKYES_bitbanded : word;                // 0x1136 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD9_DLASTSGA_bitbanded : longWord;                  // 0x1138 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD9_CSR_bitbanded     : word;                       // 0x113C TCD Control and Status
  TCD9_BITER_ELINKYES_bitbanded : word;                // 0x113E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD10_SADDR_bitbanded  : longWord;                   // 0x1140 TCD Source Address
  TCD10_SOFF_bitbanded   : word;                       // 0x1144 TCD Signed Source Address Offset
  TCD10_ATTR_bitbanded   : word;                       // 0x1146 TCD Transfer Attributes
  TCD10_NBYTES_MLNO_bitbanded : longWord;              // 0x1148 TCD Minor Byte Count (Minor Loop Disabled)
  TCD10_SLAST_bitbanded  : longWord;                   // 0x114C TCD Last Source Address Adjustment
  TCD10_DADDR_bitbanded  : longWord;                   // 0x1150 TCD Destination Address
  TCD10_DOFF_bitbanded   : word;                       // 0x1154 TCD Signed Destination Address Offset
  TCD10_CITER_ELINKNO_bitbanded : word;                // 0x1156 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD10_DLASTSGA_bitbanded : longWord;                 // 0x1158 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD10_CSR_bitbanded    : word;                       // 0x115C TCD Control and Status
  TCD10_BITER_ELINKNO_bitbanded : word;                // 0x115E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD11_SADDR_bitbanded  : longWord;                   // 0x1160 TCD Source Address
  TCD11_SOFF_bitbanded   : word;                       // 0x1164 TCD Signed Source Address Offset
  TCD11_ATTR_bitbanded   : word;                       // 0x1166 TCD Transfer Attributes
  TCD11_NBYTES_MLOFFNO_bitbanded : longWord;           // 0x1168 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
  TCD11_SLAST_bitbanded  : longWord;                   // 0x116C TCD Last Source Address Adjustment
  TCD11_DADDR_bitbanded  : longWord;                   // 0x1170 TCD Destination Address
  TCD11_DOFF_bitbanded   : word;                       // 0x1174 TCD Signed Destination Address Offset
  TCD11_CITER_ELINKNO_bitbanded : word;                // 0x1176 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD11_DLASTSGA_bitbanded : longWord;                 // 0x1178 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD11_CSR_bitbanded    : word;                       // 0x117C TCD Control and Status
  TCD11_BITER_ELINKNO_bitbanded : word;                // 0x117E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD12_SADDR_bitbanded  : longWord;                   // 0x1180 TCD Source Address
  TCD12_SOFF_bitbanded   : word;                       // 0x1184 TCD Signed Source Address Offset
  TCD12_ATTR_bitbanded   : word;                       // 0x1186 TCD Transfer Attributes
  TCD12_NBYTES_MLOFFYES_bitbanded : longWord;          // 0x1188 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  TCD12_SLAST_bitbanded  : longWord;                   // 0x118C TCD Last Source Address Adjustment
  TCD12_DADDR_bitbanded  : longWord;                   // 0x1190 TCD Destination Address
  TCD12_DOFF_bitbanded   : word;                       // 0x1194 TCD Signed Destination Address Offset
  TCD12_CITER_ELINKNO_bitbanded : word;                // 0x1196 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD12_DLASTSGA_bitbanded : longWord;                 // 0x1198 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD12_CSR_bitbanded    : word;                       // 0x119C TCD Control and Status
  TCD12_BITER_ELINKNO_bitbanded : word;                // 0x119E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD13_SADDR_bitbanded  : longWord;                   // 0x11A0 TCD Source Address
  TCD13_SOFF_bitbanded   : word;                       // 0x11A4 TCD Signed Source Address Offset
  TCD13_ATTR_bitbanded   : word;                       // 0x11A6 TCD Transfer Attributes
  TCD13_NBYTES_MLOFFYES_bitbanded : longWord;          // 0x11A8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
  TCD13_SLAST_bitbanded  : longWord;                   // 0x11AC TCD Last Source Address Adjustment
  TCD13_DADDR_bitbanded  : longWord;                   // 0x11B0 TCD Destination Address
  TCD13_DOFF_bitbanded   : word;                       // 0x11B4 TCD Signed Destination Address Offset
  TCD13_CITER_ELINKYES_bitbanded : word;               // 0x11B6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD13_DLASTSGA_bitbanded : longWord;                 // 0x11B8 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD13_CSR_bitbanded    : word;                       // 0x11BC TCD Control and Status
  TCD13_BITER_ELINKYES_bitbanded : word;               // 0x11BE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
  TCD14_SADDR_bitbanded  : longWord;                   // 0x11C0 TCD Source Address
  TCD14_SOFF_bitbanded   : word;                       // 0x11C4 TCD Signed Source Address Offset
  TCD14_ATTR_bitbanded   : word;                       // 0x11C6 TCD Transfer Attributes
  TCD14_NBYTES_MLNO_bitbanded : longWord;              // 0x11C8 TCD Minor Byte Count (Minor Loop Disabled)
  TCD14_SLAST_bitbanded  : longWord;                   // 0x11CC TCD Last Source Address Adjustment
  TCD14_DADDR_bitbanded  : longWord;                   // 0x11D0 TCD Destination Address
  TCD14_DOFF_bitbanded   : word;                       // 0x11D4 TCD Signed Destination Address Offset
  TCD14_CITER_ELINKNO_bitbanded : word;                // 0x11D6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD14_DLASTSGA_bitbanded : longWord;                 // 0x11D8 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD14_CSR_bitbanded    : word;                       // 0x11DC TCD Control and Status
  TCD14_BITER_ELINKNO_bitbanded : word;                // 0x11DE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD15_SADDR_bitbanded  : longWord;                   // 0x11E0 TCD Source Address
  TCD15_SOFF_bitbanded   : word;                       // 0x11E4 TCD Signed Source Address Offset
  TCD15_ATTR_bitbanded   : word;                       // 0x11E6 TCD Transfer Attributes
  TCD15_NBYTES_MLOFFNO_bitbanded : longWord;           // 0x11E8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
  TCD15_SLAST_bitbanded  : longWord;                   // 0x11EC TCD Last Source Address Adjustment
  TCD15_DADDR_bitbanded  : longWord;                   // 0x11F0 TCD Destination Address
  TCD15_DOFF_bitbanded   : word;                       // 0x11F4 TCD Signed Destination Address Offset
  TCD15_CITER_ELINKNO_bitbanded : word;                // 0x11F6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
  TCD15_DLASTSGA_bitbanded : longWord;                 // 0x11F8 TCD Last Destination Address Adjustment/Scatter Gather Address
  TCD15_CSR_bitbanded    : word;                       // 0x11FC TCD Control and Status
  TCD15_BITER_ELINKNO_bitbanded : word;                // 0x11FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
end;

// DMA channel multiplexor
TDMAMUX_CHCFG_bits = bitpacked record
  SOURCE                 : TBits_6;                    // [0:5] DMA Channel Source (slot)
  TRIG                   : TBits_1;                    // [6:6] DMA Channel Trigger Enable
  ENBL                   : TBits_1;                    // [7:7] DMA Channel Enable
end;

TDMAMUX_CHCFG_bitbanded = record
  SOURCE                 : array[0..5] of longWord;    // [0:5] DMA Channel Source (slot)
  TRIG                   : longWord;                   // [6:6] DMA Channel Trigger Enable
  ENBL                   : longWord;                   // [7:7] DMA Channel Enable
end;

TDMAMUX_Registers = record
  case boolean of false: (
  CHCFG0                 : byte;                       // 0x00 Channel Configuration Register
  CHCFG1                 : byte;                       // 0x01 Channel Configuration Register
  CHCFG2                 : byte;                       // 0x02 Channel Configuration Register
  CHCFG3                 : byte;                       // 0x03 Channel Configuration Register
  CHCFG4                 : byte;                       // 0x04 Channel Configuration Register
  CHCFG5                 : byte;                       // 0x05 Channel Configuration Register
  CHCFG6                 : byte;                       // 0x06 Channel Configuration Register
  CHCFG7                 : byte;                       // 0x07 Channel Configuration Register
  CHCFG8                 : byte;                       // 0x08 Channel Configuration Register
  CHCFG9                 : byte;                       // 0x09 Channel Configuration Register
  CHCFG10                : byte;                       // 0x0A Channel Configuration Register
  CHCFG11                : byte;                       // 0x0B Channel Configuration Register
  CHCFG12                : byte;                       // 0x0C Channel Configuration Register
  CHCFG13                : byte;                       // 0x0D Channel Configuration Register
  CHCFG14                : byte;                       // 0x0E Channel Configuration Register
  CHCFG15                : byte;                       // 0x0F Channel Configuration Register
);
true : (
CHCFG0_bits              : TDMAMUX_CHCFG_bits;         // 0x01 Channel Configuration Register
CHCFG1_bits              : TDMAMUX_CHCFG_bits;         // 0x02 Channel Configuration Register
CHCFG2_bits              : TDMAMUX_CHCFG_bits;         // 0x03 Channel Configuration Register
CHCFG3_bits              : TDMAMUX_CHCFG_bits;         // 0x04 Channel Configuration Register
CHCFG4_bits              : TDMAMUX_CHCFG_bits;         // 0x05 Channel Configuration Register
CHCFG5_bits              : TDMAMUX_CHCFG_bits;         // 0x06 Channel Configuration Register
CHCFG6_bits              : TDMAMUX_CHCFG_bits;         // 0x07 Channel Configuration Register
CHCFG7_bits              : TDMAMUX_CHCFG_bits;         // 0x08 Channel Configuration Register
CHCFG8_bits              : TDMAMUX_CHCFG_bits;         // 0x09 Channel Configuration Register
CHCFG9_bits              : TDMAMUX_CHCFG_bits;         // 0x0A Channel Configuration Register
CHCFG10_bits             : TDMAMUX_CHCFG_bits;         // 0x0B Channel Configuration Register
CHCFG11_bits             : TDMAMUX_CHCFG_bits;         // 0x0C Channel Configuration Register
CHCFG12_bits             : TDMAMUX_CHCFG_bits;         // 0x0D Channel Configuration Register
CHCFG13_bits             : TDMAMUX_CHCFG_bits;         // 0x0E Channel Configuration Register
CHCFG14_bits             : TDMAMUX_CHCFG_bits;         // 0x0F Channel Configuration Register
CHCFG15_bits             : TDMAMUX_CHCFG_bits;         // 0x10 Channel Configuration Register
);
end;

TDMAMUXRegisters_bitbanded = record
  CHCFG0                 : TDMAMUX_CHCFG_bitbanded;    // 0x01 Channel Configuration Register
  CHCFG1                 : TDMAMUX_CHCFG_bitbanded;    // 0x02 Channel Configuration Register
  CHCFG2                 : TDMAMUX_CHCFG_bitbanded;    // 0x03 Channel Configuration Register
  CHCFG3                 : TDMAMUX_CHCFG_bitbanded;    // 0x04 Channel Configuration Register
  CHCFG4                 : TDMAMUX_CHCFG_bitbanded;    // 0x05 Channel Configuration Register
  CHCFG5                 : TDMAMUX_CHCFG_bitbanded;    // 0x06 Channel Configuration Register
  CHCFG6                 : TDMAMUX_CHCFG_bitbanded;    // 0x07 Channel Configuration Register
  CHCFG7                 : TDMAMUX_CHCFG_bitbanded;    // 0x08 Channel Configuration Register
  CHCFG8                 : TDMAMUX_CHCFG_bitbanded;    // 0x09 Channel Configuration Register
  CHCFG9                 : TDMAMUX_CHCFG_bitbanded;    // 0x0A Channel Configuration Register
  CHCFG10                : TDMAMUX_CHCFG_bitbanded;    // 0x0B Channel Configuration Register
  CHCFG11                : TDMAMUX_CHCFG_bitbanded;    // 0x0C Channel Configuration Register
  CHCFG12                : TDMAMUX_CHCFG_bitbanded;    // 0x0D Channel Configuration Register
  CHCFG13                : TDMAMUX_CHCFG_bitbanded;    // 0x0E Channel Configuration Register
  CHCFG14                : TDMAMUX_CHCFG_bitbanded;    // 0x0F Channel Configuration Register
  CHCFG15                : TDMAMUX_CHCFG_bitbanded;    // 0x10 Channel Configuration Register
end;

// External Watchdog Monitor
TEWM_CTRL_bits = bitpacked record
  EWMEN                  : TBits_1;                    // [0:0] EWM enable.
  ASSIN                  : TBits_1;                    // [1:1] EWM_in's Assertion State Select.
  INEN                   : TBits_1;                    // [2:2] Input Enable.
  INTEN                  : TBits_1;                    // [3:3] Interrupt Enable.
  RESERVED0              : TBits_4;                    // [4:7] no description available
end;

TEWM_CTRL_bitbanded = record
  EWMEN                  : longWord;                   // [0:0] EWM enable.
  ASSIN                  : longWord;                   // [1:1] EWM_in's Assertion State Select.
  INEN                   : longWord;                   // [2:2] Input Enable.
  INTEN                  : longWord;                   // [3:3] Interrupt Enable.
  RESERVED0              : array[0..3] of longWord;    // [4:7] no description available
end;

TEWM_SERV_bits = bitpacked record
  SERVICE                : TBits_8;                    // [0:7] no description available
end;

TEWM_SERV_bitbanded = record
  SERVICE                : array[0..7] of longWord;    // [0:7] no description available
end;

TEWM_CMPL_bits = bitpacked record
  COMPAREL               : TBits_8;                    // [0:7] no description available
end;

TEWM_CMPL_bitbanded = record
  COMPAREL               : array[0..7] of longWord;    // [0:7] no description available
end;

TEWM_CMPH_bits = bitpacked record
  COMPAREH               : TBits_8;                    // [0:7] no description available
end;

TEWM_CMPH_bitbanded = record
  COMPAREH               : array[0..7] of longWord;    // [0:7] no description available
end;

TEWM_Registers = record
  case boolean of false: (
  CTRL                   : byte;                       // 0x00 Control Register
  SERV                   : byte;                       // 0x01 Service Register
  CMPL                   : byte;                       // 0x02 Compare Low Register
  CMPH                   : byte;                       // 0x03 Compare High Register
);
true : (
CTRL_bits                : TEWM_CTRL_bits;             // 0x01 Control Register
SERV_bits                : TEWM_SERV_bits;             // 0x02 Service Register
CMPL_bits                : TEWM_CMPL_bits;             // 0x03 Compare Low Register
CMPH_bits                : TEWM_CMPH_bits;             // 0x04 Compare High Register
);
end;

TEWMRegisters_bitbanded = record
  CTRL                   : TEWM_CTRL_bitbanded;        // 0x01 Control Register
  SERV                   : TEWM_SERV_bitbanded;        // 0x02 Service Register
  CMPL                   : TEWM_CMPL_bitbanded;        // 0x03 Compare Low Register
  CMPH                   : TEWM_CMPH_bitbanded;        // 0x04 Compare High Register
end;

// FlexBus external bus interface
TFB_CSAR_bits = bitpacked record
  RESERVED0              : TBits_16;                   // [0:15] no description available
  BA                     : TBits_16;                   // [16:31] Base address
end;

TFB_CSAR_bitbanded = record
  RESERVED0              : array[0..15] of longWord;   // [0:15] no description available
  BA                     : array[0..15] of longWord;   // [16:31] Base address
end;

TFB_CSMR_bits = bitpacked record
  V                      : TBits_1;                    // [0:0] Valid
  RESERVED0              : TBits_7;                    // [1:7] no description available
  WP                     : TBits_1;                    // [8:8] Write protect
  RESERVED1              : TBits_7;                    // [9:15] no description available
  BAM                    : TBits_16;                   // [16:31] Base address mask
end;

TFB_CSMR_bitbanded = record
  V                      : longWord;                   // [0:0] Valid
  RESERVED0              : array[0..6] of longWord;    // [1:7] no description available
  WP                     : longWord;                   // [8:8] Write protect
  RESERVED1              : array[0..6] of longWord;    // [9:15] no description available
  BAM                    : array[0..15] of longWord;   // [16:31] Base address mask
end;

TFB_CSCR_bits = bitpacked record
  RESERVED0              : TBits_3;                    // [0:2] no description available
  BSTW                   : TBits_1;                    // [3:3] Burst-write enable
  BSTR                   : TBits_1;                    // [4:4] Burst-read enable
  BEM                    : TBits_1;                    // [5:5] Byte-enable mode
  PS                     : TBits_2;                    // [6:7] Port size
  AA                     : TBits_1;                    // [8:8] Auto-acknowledge enable
  BLS                    : TBits_1;                    // [9:9] Byte-lane shift
  WS                     : TBits_6;                    // [10:15] Wait states
  WRAH                   : TBits_2;                    // [16:17] Write address hold or deselect
  RDAH                   : TBits_2;                    // [18:19] Read address hold or deselect
  ASET                   : TBits_2;                    // [20:21] Address setup
  EXTS                   : TBits_1;                    // [22:22] no description available
  SWSEN                  : TBits_1;                    // [23:23] Secondary wait state enable
  RESERVED1              : TBits_2;                    // [24:25] no description available
  SWS                    : TBits_6;                    // [26:31] Secondary wait states
end;

TFB_CSCR_bitbanded = record
  RESERVED0              : array[0..2] of longWord;    // [0:2] no description available
  BSTW                   : longWord;                   // [3:3] Burst-write enable
  BSTR                   : longWord;                   // [4:4] Burst-read enable
  BEM                    : longWord;                   // [5:5] Byte-enable mode
  PS                     : array[0..1] of longWord;    // [6:7] Port size
  AA                     : longWord;                   // [8:8] Auto-acknowledge enable
  BLS                    : longWord;                   // [9:9] Byte-lane shift
  WS                     : array[0..5] of longWord;    // [10:15] Wait states
  WRAH                   : array[0..1] of longWord;    // [16:17] Write address hold or deselect
  RDAH                   : array[0..1] of longWord;    // [18:19] Read address hold or deselect
  ASET                   : array[0..1] of longWord;    // [20:21] Address setup
  EXTS                   : longWord;                   // [22:22] no description available
  SWSEN                  : longWord;                   // [23:23] Secondary wait state enable
  RESERVED1              : array[0..1] of longWord;    // [24:25] no description available
  SWS                    : array[0..5] of longWord;    // [26:31] Secondary wait states
end;

TFB_CSPMCR_bits = bitpacked record
  RESERVED0              : TBits_12;                   // [0:11] no description available
  GROUP5                 : TBits_4;                    // [12:15] FlexBus signal group 5 multiplex control
  GROUP4                 : TBits_4;                    // [16:19] FlexBus signal group 4 multiplex control
  GROUP3                 : TBits_4;                    // [20:23] FlexBus signal group 3 multiplex control
  GROUP2                 : TBits_4;                    // [24:27] FlexBus signal group 2 multiplex control
  GROUP1                 : TBits_4;                    // [28:31] FlexBus signal group 1 multiplex control
end;

TFB_CSPMCR_bitbanded = record
  RESERVED0              : array[0..11] of longWord;   // [0:11] no description available
  GROUP5                 : array[0..3] of longWord;    // [12:15] FlexBus signal group 5 multiplex control
  GROUP4                 : array[0..3] of longWord;    // [16:19] FlexBus signal group 4 multiplex control
  GROUP3                 : array[0..3] of longWord;    // [20:23] FlexBus signal group 3 multiplex control
  GROUP2                 : array[0..3] of longWord;    // [24:27] FlexBus signal group 2 multiplex control
  GROUP1                 : array[0..3] of longWord;    // [28:31] FlexBus signal group 1 multiplex control
end;

TFB_Registers = record
  case boolean of false: (
  CSAR0                  : longWord;                   // 0x00 Chip select address register
  CSMR0                  : longWord;                   // 0x04 Chip select mask register
  CSCR0                  : longWord;                   // 0x08 Chip select control register
  CSAR1                  : longWord;                   // 0x0C Chip select address register
  CSMR1                  : longWord;                   // 0x10 Chip select mask register
  CSCR1                  : longWord;                   // 0x14 Chip select control register
  CSAR2                  : longWord;                   // 0x18 Chip select address register
  CSMR2                  : longWord;                   // 0x1C Chip select mask register
  CSCR2                  : longWord;                   // 0x20 Chip select control register
  CSAR3                  : longWord;                   // 0x24 Chip select address register
  CSMR3                  : longWord;                   // 0x28 Chip select mask register
  CSCR3                  : longWord;                   // 0x2C Chip select control register
  CSAR4                  : longWord;                   // 0x30 Chip select address register
  CSMR4                  : longWord;                   // 0x34 Chip select mask register
  CSCR4                  : longWord;                   // 0x38 Chip select control register
  CSAR5                  : longWord;                   // 0x3C Chip select address register
  CSMR5                  : longWord;                   // 0x40 Chip select mask register
  CSCR5                  : longWord;                   // 0x44 Chip select control register
  RESERVED0              : array[0..5] of longWord;    // 0x48
  CSPMCR                 : longWord;                   // 0x60 Chip select port multiplexing control register
);
true : (
CSAR0_bits               : TFB_CSAR_bits;              // 0x04 Chip select address register
CSMR0_bits               : TFB_CSMR_bits;              // 0x08 Chip select mask register
CSCR0_bits               : TFB_CSCR_bits;              // 0x0C Chip select control register
CSAR1_bits               : TFB_CSAR_bits;              // 0x10 Chip select address register
CSMR1_bits               : TFB_CSMR_bits;              // 0x14 Chip select mask register
CSCR1_bits               : TFB_CSCR_bits;              // 0x18 Chip select control register
CSAR2_bits               : TFB_CSAR_bits;              // 0x1C Chip select address register
CSMR2_bits               : TFB_CSMR_bits;              // 0x20 Chip select mask register
CSCR2_bits               : TFB_CSCR_bits;              // 0x24 Chip select control register
CSAR3_bits               : TFB_CSAR_bits;              // 0x28 Chip select address register
CSMR3_bits               : TFB_CSMR_bits;              // 0x2C Chip select mask register
CSCR3_bits               : TFB_CSCR_bits;              // 0x30 Chip select control register
CSAR4_bits               : TFB_CSAR_bits;              // 0x34 Chip select address register
CSMR4_bits               : TFB_CSMR_bits;              // 0x38 Chip select mask register
CSCR4_bits               : TFB_CSCR_bits;              // 0x3C Chip select control register
CSAR5_bits               : TFB_CSAR_bits;              // 0x40 Chip select address register
CSMR5_bits               : TFB_CSMR_bits;              // 0x44 Chip select mask register
CSCR5_bits               : TFB_CSCR_bits;              // 0x48 Chip select control register
RESERVED_bits0           : array[0..5] of longWord;
CSPMCR_bits              : TFB_CSPMCR_bits;            // 0x64 Chip select port multiplexing control register
);
end;

TFBRegisters_bitbanded = record
  CSAR0                  : TFB_CSAR_bitbanded;         // 0x04 Chip select address register
  CSMR0                  : TFB_CSMR_bitbanded;         // 0x08 Chip select mask register
  CSCR0                  : TFB_CSCR_bitbanded;         // 0x0C Chip select control register
  CSAR1                  : TFB_CSAR_bitbanded;         // 0x10 Chip select address register
  CSMR1                  : TFB_CSMR_bitbanded;         // 0x14 Chip select mask register
  CSCR1                  : TFB_CSCR_bitbanded;         // 0x18 Chip select control register
  CSAR2                  : TFB_CSAR_bitbanded;         // 0x1C Chip select address register
  CSMR2                  : TFB_CSMR_bitbanded;         // 0x20 Chip select mask register
  CSCR2                  : TFB_CSCR_bitbanded;         // 0x24 Chip select control register
  CSAR3                  : TFB_CSAR_bitbanded;         // 0x28 Chip select address register
  CSMR3                  : TFB_CSMR_bitbanded;         // 0x2C Chip select mask register
  CSCR3                  : TFB_CSCR_bitbanded;         // 0x30 Chip select control register
  CSAR4                  : TFB_CSAR_bitbanded;         // 0x34 Chip select address register
  CSMR4                  : TFB_CSMR_bitbanded;         // 0x38 Chip select mask register
  CSCR4                  : TFB_CSCR_bitbanded;         // 0x3C Chip select control register
  CSAR5                  : TFB_CSAR_bitbanded;         // 0x40 Chip select address register
  CSMR5                  : TFB_CSMR_bitbanded;         // 0x44 Chip select mask register
  CSCR5                  : TFB_CSCR_bitbanded;         // 0x48 Chip select control register
  RESERVED0              : array[0..23] of array[0..7] of longWord;
  CSPMCR                 : TFB_CSPMCR_bitbanded;       // 0x64 Chip select port multiplexing control register
end;

// Flash Memory Controller
TFMC_PFAPR_bits = bitpacked record
  M0AP                   : TBits_2;                    // [0:1] Master 0 Access Protection
  M1AP                   : TBits_2;                    // [2:3] Master 1 Access Protection
  M2AP                   : TBits_2;                    // [4:5] Master 2 Access Protection
  M3AP                   : TBits_2;                    // [6:7] Master 3 Access Protection
  M4AP                   : TBits_2;                    // [8:9] Master 4 Access Protection
  M5AP                   : TBits_2;                    // [10:11] Master 5 Access Protection
  M6AP                   : TBits_2;                    // [12:13] Master 6 Access Protection
  M7AP                   : TBits_2;                    // [14:15] Master 7 Access Protection
  M0PFD                  : TBits_1;                    // [16:16] Master 0 Prefetch Disable
  M1PFD                  : TBits_1;                    // [17:17] Master 1 Prefetch Disable
  M2PFD                  : TBits_1;                    // [18:18] Master 2 Prefetch Disable
  M3PFD                  : TBits_1;                    // [19:19] Master 3 Prefetch Disable
  M4PFD                  : TBits_1;                    // [20:20] Master 4 Prefetch Disable
  M5PFD                  : TBits_1;                    // [21:21] Master 5 Prefetch Disable
  M6PFD                  : TBits_1;                    // [22:22] Master 6 Prefetch Disable
  M7PFD                  : TBits_1;                    // [23:23] Master 7 Prefetch Disable
  RESERVED0              : TBits_8;                    // [24:31] no description available
end;

TFMC_PFAPR_bitbanded = record
  M0AP                   : array[0..1] of longWord;    // [0:1] Master 0 Access Protection
  M1AP                   : array[0..1] of longWord;    // [2:3] Master 1 Access Protection
  M2AP                   : array[0..1] of longWord;    // [4:5] Master 2 Access Protection
  M3AP                   : array[0..1] of longWord;    // [6:7] Master 3 Access Protection
  M4AP                   : array[0..1] of longWord;    // [8:9] Master 4 Access Protection
  M5AP                   : array[0..1] of longWord;    // [10:11] Master 5 Access Protection
  M6AP                   : array[0..1] of longWord;    // [12:13] Master 6 Access Protection
  M7AP                   : array[0..1] of longWord;    // [14:15] Master 7 Access Protection
  M0PFD                  : longWord;                   // [16:16] Master 0 Prefetch Disable
  M1PFD                  : longWord;                   // [17:17] Master 1 Prefetch Disable
  M2PFD                  : longWord;                   // [18:18] Master 2 Prefetch Disable
  M3PFD                  : longWord;                   // [19:19] Master 3 Prefetch Disable
  M4PFD                  : longWord;                   // [20:20] Master 4 Prefetch Disable
  M5PFD                  : longWord;                   // [21:21] Master 5 Prefetch Disable
  M6PFD                  : longWord;                   // [22:22] Master 6 Prefetch Disable
  M7PFD                  : longWord;                   // [23:23] Master 7 Prefetch Disable
  RESERVED0              : array[0..7] of longWord;    // [24:31] no description available
end;

TFMC_PFB0CR_bits = bitpacked record
  B0SEBE                 : TBits_1;                    // [0:0] Bank 0 Single Entry Buffer Enable
  B0IPE                  : TBits_1;                    // [1:1] Bank 0 Instruction Prefetch Enable
  B0DPE                  : TBits_1;                    // [2:2] Bank 0 Data Prefetch Enable
  B0ICE                  : TBits_1;                    // [3:3] Bank 0 Instruction Cache Enable
  B0DCE                  : TBits_1;                    // [4:4] Bank 0 Data Cache Enable
  CRC                    : TBits_3;                    // [5:7] Cache Replacement Control
  RESERVED0              : TBits_8;                    // [8:15] no description available
  RESERVED1              : TBits_1;                    // [16:16] no description available
  B0MW                   : TBits_2;                    // [17:18] Bank 0 Memory Width
  S_B_INV                : TBits_1;                    // [19:19] Invalidate Prefetch Speculation Buffer
  CINV_WAY               : TBits_4;                    // [20:23] Cache Invalidate Way x
  CLCK_WAY               : TBits_4;                    // [24:27] Cache Lock Way x
  B0RWSC                 : TBits_4;                    // [28:31] Bank 0 Read Wait State Control
end;

TFMC_PFB0CR_bitbanded = record
  B0SEBE                 : longWord;                   // [0:0] Bank 0 Single Entry Buffer Enable
  B0IPE                  : longWord;                   // [1:1] Bank 0 Instruction Prefetch Enable
  B0DPE                  : longWord;                   // [2:2] Bank 0 Data Prefetch Enable
  B0ICE                  : longWord;                   // [3:3] Bank 0 Instruction Cache Enable
  B0DCE                  : longWord;                   // [4:4] Bank 0 Data Cache Enable
  CRC                    : array[0..2] of longWord;    // [5:7] Cache Replacement Control
  RESERVED0              : array[0..7] of longWord;    // [8:15] no description available
  RESERVED1              : longWord;                   // [16:16] no description available
  B0MW                   : array[0..1] of longWord;    // [17:18] Bank 0 Memory Width
  S_B_INV                : longWord;                   // [19:19] Invalidate Prefetch Speculation Buffer
  CINV_WAY               : array[0..3] of longWord;    // [20:23] Cache Invalidate Way x
  CLCK_WAY               : array[0..3] of longWord;    // [24:27] Cache Lock Way x
  B0RWSC                 : array[0..3] of longWord;    // [28:31] Bank 0 Read Wait State Control
end;

TFMC_PFB1CR_bits = bitpacked record
  B1SEBE                 : TBits_1;                    // [0:0] Bank 1 Single Entry Buffer Enable
  B1IPE                  : TBits_1;                    // [1:1] Bank 1 Instruction Prefetch Enable
  B1DPE                  : TBits_1;                    // [2:2] Bank 1 Data Prefetch Enable
  B1ICE                  : TBits_1;                    // [3:3] Bank 1 Instruction Cache Enable
  B1DCE                  : TBits_1;                    // [4:4] Bank 1 Data Cache Enable
  RESERVED0              : TBits_3;                    // [5:7] no description available
  RESERVED1              : TBits_8;                    // [8:15] no description available
  RESERVED2              : TBits_1;                    // [16:16] no description available
  B1MW                   : TBits_2;                    // [17:18] Bank 1 Memory Width
  RESERVED3              : TBits_9;                    // [19:27] no description available
  B1RWSC                 : TBits_4;                    // [28:31] Bank 1 Read Wait State Control
end;

TFMC_PFB1CR_bitbanded = record
  B1SEBE                 : longWord;                   // [0:0] Bank 1 Single Entry Buffer Enable
  B1IPE                  : longWord;                   // [1:1] Bank 1 Instruction Prefetch Enable
  B1DPE                  : longWord;                   // [2:2] Bank 1 Data Prefetch Enable
  B1ICE                  : longWord;                   // [3:3] Bank 1 Instruction Cache Enable
  B1DCE                  : longWord;                   // [4:4] Bank 1 Data Cache Enable
  RESERVED0              : array[0..2] of longWord;    // [5:7] no description available
  RESERVED1              : array[0..7] of longWord;    // [8:15] no description available
  RESERVED2              : longWord;                   // [16:16] no description available
  B1MW                   : array[0..1] of longWord;    // [17:18] Bank 1 Memory Width
  RESERVED3              : array[0..8] of longWord;    // [19:27] no description available
  B1RWSC                 : array[0..3] of longWord;    // [28:31] Bank 1 Read Wait State Control
end;

TFMC_TAGVDW0S_bits = bitpacked record
  valid                  : TBits_1;                    // [0:0] 1-bit valid for cache entry
  RESERVED0              : TBits_5;                    // [1:5] no description available
  tag                    : TBits_13;                   // [6:18] 13-bit tag for cache entry
  RESERVED1              : TBits_13;                   // [19:31] no description available
end;

TFMC_TAGVDW0S_bitbanded = record
  valid                  : longWord;                   // [0:0] 1-bit valid for cache entry
  RESERVED0              : array[0..4] of longWord;    // [1:5] no description available
  tag                    : array[0..12] of longWord;   // [6:18] 13-bit tag for cache entry
  RESERVED1              : array[0..12] of longWord;   // [19:31] no description available
end;

TFMC_TAGVDW1S_bits = bitpacked record
  valid                  : TBits_1;                    // [0:0] 1-bit valid for cache entry
  RESERVED0              : TBits_5;                    // [1:5] no description available
  tag                    : TBits_13;                   // [6:18] 13-bit tag for cache entry
  RESERVED1              : TBits_13;                   // [19:31] no description available
end;

TFMC_TAGVDW1S_bitbanded = record
  valid                  : longWord;                   // [0:0] 1-bit valid for cache entry
  RESERVED0              : array[0..4] of longWord;    // [1:5] no description available
  tag                    : array[0..12] of longWord;   // [6:18] 13-bit tag for cache entry
  RESERVED1              : array[0..12] of longWord;   // [19:31] no description available
end;

TFMC_TAGVDW2S_bits = bitpacked record
  valid                  : TBits_1;                    // [0:0] 1-bit valid for cache entry
  RESERVED0              : TBits_5;                    // [1:5] no description available
  tag                    : TBits_13;                   // [6:18] 13-bit tag for cache entry
  RESERVED1              : TBits_13;                   // [19:31] no description available
end;

TFMC_TAGVDW2S_bitbanded = record
  valid                  : longWord;                   // [0:0] 1-bit valid for cache entry
  RESERVED0              : array[0..4] of longWord;    // [1:5] no description available
  tag                    : array[0..12] of longWord;   // [6:18] 13-bit tag for cache entry
  RESERVED1              : array[0..12] of longWord;   // [19:31] no description available
end;

TFMC_TAGVDW3S_bits = bitpacked record
  valid                  : TBits_1;                    // [0:0] 1-bit valid for cache entry
  RESERVED0              : TBits_5;                    // [1:5] no description available
  tag                    : TBits_13;                   // [6:18] 13-bit tag for cache entry
  RESERVED1              : TBits_13;                   // [19:31] no description available
end;

TFMC_TAGVDW3S_bitbanded = record
  valid                  : longWord;                   // [0:0] 1-bit valid for cache entry
  RESERVED0              : array[0..4] of longWord;    // [1:5] no description available
  tag                    : array[0..12] of longWord;   // [6:18] 13-bit tag for cache entry
  RESERVED1              : array[0..12] of longWord;   // [19:31] no description available
end;

TFMC_DATAW0SU_bits = bitpacked record
  data                   : TBits_32;                   // [0:31] Bits [63:32] of data entry
end;

TFMC_DATAW0SU_bitbanded = record
  data                   : array[0..31] of longWord;   // [0:31] Bits [63:32] of data entry
end;

TFMC_DATAW0SL_bits = bitpacked record
  data                   : TBits_32;                   // [0:31] Bits [31:0] of data entry
end;

TFMC_DATAW0SL_bitbanded = record
  data                   : array[0..31] of longWord;   // [0:31] Bits [31:0] of data entry
end;

TFMC_DATAW1SU_bits = bitpacked record
  data                   : TBits_32;                   // [0:31] Bits [63:32] of data entry
end;

TFMC_DATAW1SU_bitbanded = record
  data                   : array[0..31] of longWord;   // [0:31] Bits [63:32] of data entry
end;

TFMC_DATAW1SL_bits = bitpacked record
  data                   : TBits_32;                   // [0:31] Bits [31:0] of data entry
end;

TFMC_DATAW1SL_bitbanded = record
  data                   : array[0..31] of longWord;   // [0:31] Bits [31:0] of data entry
end;

TFMC_DATAW2SU_bits = bitpacked record
  data                   : TBits_32;                   // [0:31] Bits [63:32] of data entry
end;

TFMC_DATAW2SU_bitbanded = record
  data                   : array[0..31] of longWord;   // [0:31] Bits [63:32] of data entry
end;

TFMC_DATAW2SL_bits = bitpacked record
  data                   : TBits_32;                   // [0:31] Bits [31:0] of data entry
end;

TFMC_DATAW2SL_bitbanded = record
  data                   : array[0..31] of longWord;   // [0:31] Bits [31:0] of data entry
end;

TFMC_DATAW3SU_bits = bitpacked record
  data                   : TBits_32;                   // [0:31] Bits [63:32] of data entry
end;

TFMC_DATAW3SU_bitbanded = record
  data                   : array[0..31] of longWord;   // [0:31] Bits [63:32] of data entry
end;

TFMC_DATAW3SL_bits = bitpacked record
  data                   : TBits_32;                   // [0:31] Bits [31:0] of data entry
end;

TFMC_DATAW3SL_bitbanded = record
  data                   : array[0..31] of longWord;   // [0:31] Bits [31:0] of data entry
end;

TFMC_Registers = record
  case boolean of false: (
  PFAPR                  : longWord;                   // 0x00 Flash Access Protection Register
  PFB0CR                 : longWord;                   // 0x04 Flash Bank 0 Control Register
  PFB1CR                 : longWord;                   // 0x08 Flash Bank 1 Control Register
  RESERVED0              : array[0..60] of longWord;   // 0x0C
  TAGVDW0S0              : longWord;                   // 0x100 Cache Tag Storage
  TAGVDW0S1              : longWord;                   // 0x104 Cache Tag Storage
  TAGVDW0S2              : longWord;                   // 0x108 Cache Tag Storage
  TAGVDW0S3              : longWord;                   // 0x10C Cache Tag Storage
  TAGVDW0S4              : longWord;                   // 0x110 Cache Tag Storage
  TAGVDW0S5              : longWord;                   // 0x114 Cache Tag Storage
  TAGVDW0S6              : longWord;                   // 0x118 Cache Tag Storage
  TAGVDW0S7              : longWord;                   // 0x11C Cache Tag Storage
  TAGVDW1S0              : longWord;                   // 0x120 Cache Tag Storage
  TAGVDW1S1              : longWord;                   // 0x124 Cache Tag Storage
  TAGVDW1S2              : longWord;                   // 0x128 Cache Tag Storage
  TAGVDW1S3              : longWord;                   // 0x12C Cache Tag Storage
  TAGVDW1S4              : longWord;                   // 0x130 Cache Tag Storage
  TAGVDW1S5              : longWord;                   // 0x134 Cache Tag Storage
  TAGVDW1S6              : longWord;                   // 0x138 Cache Tag Storage
  TAGVDW1S7              : longWord;                   // 0x13C Cache Tag Storage
  TAGVDW2S0              : longWord;                   // 0x140 Cache Tag Storage
  TAGVDW2S1              : longWord;                   // 0x144 Cache Tag Storage
  TAGVDW2S2              : longWord;                   // 0x148 Cache Tag Storage
  TAGVDW2S3              : longWord;                   // 0x14C Cache Tag Storage
  TAGVDW2S4              : longWord;                   // 0x150 Cache Tag Storage
  TAGVDW2S5              : longWord;                   // 0x154 Cache Tag Storage
  TAGVDW2S6              : longWord;                   // 0x158 Cache Tag Storage
  TAGVDW2S7              : longWord;                   // 0x15C Cache Tag Storage
  TAGVDW3S0              : longWord;                   // 0x160 Cache Tag Storage
  TAGVDW3S1              : longWord;                   // 0x164 Cache Tag Storage
  TAGVDW3S2              : longWord;                   // 0x168 Cache Tag Storage
  TAGVDW3S3              : longWord;                   // 0x16C Cache Tag Storage
  TAGVDW3S4              : longWord;                   // 0x170 Cache Tag Storage
  TAGVDW3S5              : longWord;                   // 0x174 Cache Tag Storage
  TAGVDW3S6              : longWord;                   // 0x178 Cache Tag Storage
  TAGVDW3S7              : longWord;                   // 0x17C Cache Tag Storage
  RESERVED1              : array[0..31] of longWord;   // 0x180
  DATAW0S0U              : longWord;                   // 0x200 Cache Data Storage (upper word)
  DATAW0S0L              : longWord;                   // 0x204 Cache Data Storage (lower word)
  DATAW0S1U              : longWord;                   // 0x208 Cache Data Storage (upper word)
  DATAW0S1L              : longWord;                   // 0x20C Cache Data Storage (lower word)
  DATAW0S2U              : longWord;                   // 0x210 Cache Data Storage (upper word)
  DATAW0S2L              : longWord;                   // 0x214 Cache Data Storage (lower word)
  DATAW0S3U              : longWord;                   // 0x218 Cache Data Storage (upper word)
  DATAW0S3L              : longWord;                   // 0x21C Cache Data Storage (lower word)
  DATAW0S4U              : longWord;                   // 0x220 Cache Data Storage (upper word)
  DATAW0S4L              : longWord;                   // 0x224 Cache Data Storage (lower word)
  DATAW0S5U              : longWord;                   // 0x228 Cache Data Storage (upper word)
  DATAW0S5L              : longWord;                   // 0x22C Cache Data Storage (lower word)
  DATAW0S6U              : longWord;                   // 0x230 Cache Data Storage (upper word)
  DATAW0S6L              : longWord;                   // 0x234 Cache Data Storage (lower word)
  DATAW0S7U              : longWord;                   // 0x238 Cache Data Storage (upper word)
  DATAW0S7L              : longWord;                   // 0x23C Cache Data Storage (lower word)
  DATAW1S0U              : longWord;                   // 0x240 Cache Data Storage (upper word)
  DATAW1S0L              : longWord;                   // 0x244 Cache Data Storage (lower word)
  DATAW1S1U              : longWord;                   // 0x248 Cache Data Storage (upper word)
  DATAW1S1L              : longWord;                   // 0x24C Cache Data Storage (lower word)
  DATAW1S2U              : longWord;                   // 0x250 Cache Data Storage (upper word)
  DATAW1S2L              : longWord;                   // 0x254 Cache Data Storage (lower word)
  DATAW1S3U              : longWord;                   // 0x258 Cache Data Storage (upper word)
  DATAW1S3L              : longWord;                   // 0x25C Cache Data Storage (lower word)
  DATAW1S4U              : longWord;                   // 0x260 Cache Data Storage (upper word)
  DATAW1S4L              : longWord;                   // 0x264 Cache Data Storage (lower word)
  DATAW1S5U              : longWord;                   // 0x268 Cache Data Storage (upper word)
  DATAW1S5L              : longWord;                   // 0x26C Cache Data Storage (lower word)
  DATAW1S6U              : longWord;                   // 0x270 Cache Data Storage (upper word)
  DATAW1S6L              : longWord;                   // 0x274 Cache Data Storage (lower word)
  DATAW1S7U              : longWord;                   // 0x278 Cache Data Storage (upper word)
  DATAW1S7L              : longWord;                   // 0x27C Cache Data Storage (lower word)
  DATAW2S0U              : longWord;                   // 0x280 Cache Data Storage (upper word)
  DATAW2S0L              : longWord;                   // 0x284 Cache Data Storage (lower word)
  DATAW2S1U              : longWord;                   // 0x288 Cache Data Storage (upper word)
  DATAW2S1L              : longWord;                   // 0x28C Cache Data Storage (lower word)
  DATAW2S2U              : longWord;                   // 0x290 Cache Data Storage (upper word)
  DATAW2S2L              : longWord;                   // 0x294 Cache Data Storage (lower word)
  DATAW2S3U              : longWord;                   // 0x298 Cache Data Storage (upper word)
  DATAW2S3L              : longWord;                   // 0x29C Cache Data Storage (lower word)
  DATAW2S4U              : longWord;                   // 0x2A0 Cache Data Storage (upper word)
  DATAW2S4L              : longWord;                   // 0x2A4 Cache Data Storage (lower word)
  DATAW2S5U              : longWord;                   // 0x2A8 Cache Data Storage (upper word)
  DATAW2S5L              : longWord;                   // 0x2AC Cache Data Storage (lower word)
  DATAW2S6U              : longWord;                   // 0x2B0 Cache Data Storage (upper word)
  DATAW2S6L              : longWord;                   // 0x2B4 Cache Data Storage (lower word)
  DATAW2S7U              : longWord;                   // 0x2B8 Cache Data Storage (upper word)
  DATAW2S7L              : longWord;                   // 0x2BC Cache Data Storage (lower word)
  DATAW3S0U              : longWord;                   // 0x2C0 Cache Data Storage (upper word)
  DATAW3S0L              : longWord;                   // 0x2C4 Cache Data Storage (lower word)
  DATAW3S1U              : longWord;                   // 0x2C8 Cache Data Storage (upper word)
  DATAW3S1L              : longWord;                   // 0x2CC Cache Data Storage (lower word)
  DATAW3S2U              : longWord;                   // 0x2D0 Cache Data Storage (upper word)
  DATAW3S2L              : longWord;                   // 0x2D4 Cache Data Storage (lower word)
  DATAW3S3U              : longWord;                   // 0x2D8 Cache Data Storage (upper word)
  DATAW3S3L              : longWord;                   // 0x2DC Cache Data Storage (lower word)
  DATAW3S4U              : longWord;                   // 0x2E0 Cache Data Storage (upper word)
  DATAW3S4L              : longWord;                   // 0x2E4 Cache Data Storage (lower word)
  DATAW3S5U              : longWord;                   // 0x2E8 Cache Data Storage (upper word)
  DATAW3S5L              : longWord;                   // 0x2EC Cache Data Storage (lower word)
  DATAW3S6U              : longWord;                   // 0x2F0 Cache Data Storage (upper word)
  DATAW3S6L              : longWord;                   // 0x2F4 Cache Data Storage (lower word)
  DATAW3S7U              : longWord;                   // 0x2F8 Cache Data Storage (upper word)
  DATAW3S7L              : longWord;                   // 0x2FC Cache Data Storage (lower word)
);
true : (
PFAPR_bits               : TFMC_PFAPR_bits;            // 0x04 Flash Access Protection Register
PFB0CR_bits              : TFMC_PFB0CR_bits;           // 0x08 Flash Bank 0 Control Register
PFB1CR_bits              : TFMC_PFB1CR_bits;           // 0x0C Flash Bank 1 Control Register
RESERVED_bits0           : array[0..60] of longWord;
TAGVDW0S0_bits           : TFMC_TAGVDW0S_bits;         // 0x104 Cache Tag Storage
TAGVDW0S1_bits           : TFMC_TAGVDW0S_bits;         // 0x108 Cache Tag Storage
TAGVDW0S2_bits           : TFMC_TAGVDW0S_bits;         // 0x10C Cache Tag Storage
TAGVDW0S3_bits           : TFMC_TAGVDW0S_bits;         // 0x110 Cache Tag Storage
TAGVDW0S4_bits           : TFMC_TAGVDW0S_bits;         // 0x114 Cache Tag Storage
TAGVDW0S5_bits           : TFMC_TAGVDW0S_bits;         // 0x118 Cache Tag Storage
TAGVDW0S6_bits           : TFMC_TAGVDW0S_bits;         // 0x11C Cache Tag Storage
TAGVDW0S7_bits           : TFMC_TAGVDW0S_bits;         // 0x120 Cache Tag Storage
TAGVDW1S0_bits           : TFMC_TAGVDW1S_bits;         // 0x124 Cache Tag Storage
TAGVDW1S1_bits           : TFMC_TAGVDW1S_bits;         // 0x128 Cache Tag Storage
TAGVDW1S2_bits           : TFMC_TAGVDW1S_bits;         // 0x12C Cache Tag Storage
TAGVDW1S3_bits           : TFMC_TAGVDW1S_bits;         // 0x130 Cache Tag Storage
TAGVDW1S4_bits           : TFMC_TAGVDW1S_bits;         // 0x134 Cache Tag Storage
TAGVDW1S5_bits           : TFMC_TAGVDW1S_bits;         // 0x138 Cache Tag Storage
TAGVDW1S6_bits           : TFMC_TAGVDW1S_bits;         // 0x13C Cache Tag Storage
TAGVDW1S7_bits           : TFMC_TAGVDW1S_bits;         // 0x140 Cache Tag Storage
TAGVDW2S0_bits           : TFMC_TAGVDW2S_bits;         // 0x144 Cache Tag Storage
TAGVDW2S1_bits           : TFMC_TAGVDW2S_bits;         // 0x148 Cache Tag Storage
TAGVDW2S2_bits           : TFMC_TAGVDW2S_bits;         // 0x14C Cache Tag Storage
TAGVDW2S3_bits           : TFMC_TAGVDW2S_bits;         // 0x150 Cache Tag Storage
TAGVDW2S4_bits           : TFMC_TAGVDW2S_bits;         // 0x154 Cache Tag Storage
TAGVDW2S5_bits           : TFMC_TAGVDW2S_bits;         // 0x158 Cache Tag Storage
TAGVDW2S6_bits           : TFMC_TAGVDW2S_bits;         // 0x15C Cache Tag Storage
TAGVDW2S7_bits           : TFMC_TAGVDW2S_bits;         // 0x160 Cache Tag Storage
TAGVDW3S0_bits           : TFMC_TAGVDW3S_bits;         // 0x164 Cache Tag Storage
TAGVDW3S1_bits           : TFMC_TAGVDW3S_bits;         // 0x168 Cache Tag Storage
TAGVDW3S2_bits           : TFMC_TAGVDW3S_bits;         // 0x16C Cache Tag Storage
TAGVDW3S3_bits           : TFMC_TAGVDW3S_bits;         // 0x170 Cache Tag Storage
TAGVDW3S4_bits           : TFMC_TAGVDW3S_bits;         // 0x174 Cache Tag Storage
TAGVDW3S5_bits           : TFMC_TAGVDW3S_bits;         // 0x178 Cache Tag Storage
TAGVDW3S6_bits           : TFMC_TAGVDW3S_bits;         // 0x17C Cache Tag Storage
TAGVDW3S7_bits           : TFMC_TAGVDW3S_bits;         // 0x180 Cache Tag Storage
RESERVED_bits1           : array[0..31] of longWord;
DATAW0S0U_bits           : longWord;                   // 0x200 Cache Data Storage (upper word)
DATAW0S0L_bits           : longWord;                   // 0x204 Cache Data Storage (lower word)
DATAW0S1U_bits           : longWord;                   // 0x208 Cache Data Storage (upper word)
DATAW0S1L_bits           : longWord;                   // 0x20C Cache Data Storage (lower word)
DATAW0S2U_bits           : longWord;                   // 0x210 Cache Data Storage (upper word)
DATAW0S2L_bits           : longWord;                   // 0x214 Cache Data Storage (lower word)
DATAW0S3U_bits           : longWord;                   // 0x218 Cache Data Storage (upper word)
DATAW0S3L_bits           : longWord;                   // 0x21C Cache Data Storage (lower word)
DATAW0S4U_bits           : longWord;                   // 0x220 Cache Data Storage (upper word)
DATAW0S4L_bits           : longWord;                   // 0x224 Cache Data Storage (lower word)
DATAW0S5U_bits           : longWord;                   // 0x228 Cache Data Storage (upper word)
DATAW0S5L_bits           : longWord;                   // 0x22C Cache Data Storage (lower word)
DATAW0S6U_bits           : longWord;                   // 0x230 Cache Data Storage (upper word)
DATAW0S6L_bits           : longWord;                   // 0x234 Cache Data Storage (lower word)
DATAW0S7U_bits           : longWord;                   // 0x238 Cache Data Storage (upper word)
DATAW0S7L_bits           : longWord;                   // 0x23C Cache Data Storage (lower word)
DATAW1S0U_bits           : longWord;                   // 0x240 Cache Data Storage (upper word)
DATAW1S0L_bits           : longWord;                   // 0x244 Cache Data Storage (lower word)
DATAW1S1U_bits           : longWord;                   // 0x248 Cache Data Storage (upper word)
DATAW1S1L_bits           : longWord;                   // 0x24C Cache Data Storage (lower word)
DATAW1S2U_bits           : longWord;                   // 0x250 Cache Data Storage (upper word)
DATAW1S2L_bits           : longWord;                   // 0x254 Cache Data Storage (lower word)
DATAW1S3U_bits           : longWord;                   // 0x258 Cache Data Storage (upper word)
DATAW1S3L_bits           : longWord;                   // 0x25C Cache Data Storage (lower word)
DATAW1S4U_bits           : longWord;                   // 0x260 Cache Data Storage (upper word)
DATAW1S4L_bits           : longWord;                   // 0x264 Cache Data Storage (lower word)
DATAW1S5U_bits           : longWord;                   // 0x268 Cache Data Storage (upper word)
DATAW1S5L_bits           : longWord;                   // 0x26C Cache Data Storage (lower word)
DATAW1S6U_bits           : longWord;                   // 0x270 Cache Data Storage (upper word)
DATAW1S6L_bits           : longWord;                   // 0x274 Cache Data Storage (lower word)
DATAW1S7U_bits           : longWord;                   // 0x278 Cache Data Storage (upper word)
DATAW1S7L_bits           : longWord;                   // 0x27C Cache Data Storage (lower word)
DATAW2S0U_bits           : longWord;                   // 0x280 Cache Data Storage (upper word)
DATAW2S0L_bits           : longWord;                   // 0x284 Cache Data Storage (lower word)
DATAW2S1U_bits           : longWord;                   // 0x288 Cache Data Storage (upper word)
DATAW2S1L_bits           : longWord;                   // 0x28C Cache Data Storage (lower word)
DATAW2S2U_bits           : longWord;                   // 0x290 Cache Data Storage (upper word)
DATAW2S2L_bits           : longWord;                   // 0x294 Cache Data Storage (lower word)
DATAW2S3U_bits           : longWord;                   // 0x298 Cache Data Storage (upper word)
DATAW2S3L_bits           : longWord;                   // 0x29C Cache Data Storage (lower word)
DATAW2S4U_bits           : longWord;                   // 0x2A0 Cache Data Storage (upper word)
DATAW2S4L_bits           : longWord;                   // 0x2A4 Cache Data Storage (lower word)
DATAW2S5U_bits           : longWord;                   // 0x2A8 Cache Data Storage (upper word)
DATAW2S5L_bits           : longWord;                   // 0x2AC Cache Data Storage (lower word)
DATAW2S6U_bits           : longWord;                   // 0x2B0 Cache Data Storage (upper word)
DATAW2S6L_bits           : longWord;                   // 0x2B4 Cache Data Storage (lower word)
DATAW2S7U_bits           : longWord;                   // 0x2B8 Cache Data Storage (upper word)
DATAW2S7L_bits           : longWord;                   // 0x2BC Cache Data Storage (lower word)
DATAW3S0U_bits           : longWord;                   // 0x2C0 Cache Data Storage (upper word)
DATAW3S0L_bits           : longWord;                   // 0x2C4 Cache Data Storage (lower word)
DATAW3S1U_bits           : longWord;                   // 0x2C8 Cache Data Storage (upper word)
DATAW3S1L_bits           : longWord;                   // 0x2CC Cache Data Storage (lower word)
DATAW3S2U_bits           : longWord;                   // 0x2D0 Cache Data Storage (upper word)
DATAW3S2L_bits           : longWord;                   // 0x2D4 Cache Data Storage (lower word)
DATAW3S3U_bits           : longWord;                   // 0x2D8 Cache Data Storage (upper word)
DATAW3S3L_bits           : longWord;                   // 0x2DC Cache Data Storage (lower word)
DATAW3S4U_bits           : longWord;                   // 0x2E0 Cache Data Storage (upper word)
DATAW3S4L_bits           : longWord;                   // 0x2E4 Cache Data Storage (lower word)
DATAW3S5U_bits           : longWord;                   // 0x2E8 Cache Data Storage (upper word)
DATAW3S5L_bits           : longWord;                   // 0x2EC Cache Data Storage (lower word)
DATAW3S6U_bits           : longWord;                   // 0x2F0 Cache Data Storage (upper word)
DATAW3S6L_bits           : longWord;                   // 0x2F4 Cache Data Storage (lower word)
DATAW3S7U_bits           : longWord;                   // 0x2F8 Cache Data Storage (upper word)
DATAW3S7L_bits           : longWord;                   // 0x2FC Cache Data Storage (lower word)
);
end;

TFMCRegisters_bitbanded = record
  PFAPR                  : TFMC_PFAPR_bitbanded;       // 0x04 Flash Access Protection Register
  PFB0CR                 : TFMC_PFB0CR_bitbanded;      // 0x08 Flash Bank 0 Control Register
  PFB1CR                 : TFMC_PFB1CR_bitbanded;      // 0x0C Flash Bank 1 Control Register
  RESERVED0              : array[0..243] of array[0..7] of longWord;
  TAGVDW0S0              : TFMC_TAGVDW0S_bitbanded;    // 0x104 Cache Tag Storage
  TAGVDW0S1              : TFMC_TAGVDW0S_bitbanded;    // 0x108 Cache Tag Storage
  TAGVDW0S2              : TFMC_TAGVDW0S_bitbanded;    // 0x10C Cache Tag Storage
  TAGVDW0S3              : TFMC_TAGVDW0S_bitbanded;    // 0x110 Cache Tag Storage
  TAGVDW0S4              : TFMC_TAGVDW0S_bitbanded;    // 0x114 Cache Tag Storage
  TAGVDW0S5              : TFMC_TAGVDW0S_bitbanded;    // 0x118 Cache Tag Storage
  TAGVDW0S6              : TFMC_TAGVDW0S_bitbanded;    // 0x11C Cache Tag Storage
  TAGVDW0S7              : TFMC_TAGVDW0S_bitbanded;    // 0x120 Cache Tag Storage
  TAGVDW1S0              : TFMC_TAGVDW1S_bitbanded;    // 0x124 Cache Tag Storage
  TAGVDW1S1              : TFMC_TAGVDW1S_bitbanded;    // 0x128 Cache Tag Storage
  TAGVDW1S2              : TFMC_TAGVDW1S_bitbanded;    // 0x12C Cache Tag Storage
  TAGVDW1S3              : TFMC_TAGVDW1S_bitbanded;    // 0x130 Cache Tag Storage
  TAGVDW1S4              : TFMC_TAGVDW1S_bitbanded;    // 0x134 Cache Tag Storage
  TAGVDW1S5              : TFMC_TAGVDW1S_bitbanded;    // 0x138 Cache Tag Storage
  TAGVDW1S6              : TFMC_TAGVDW1S_bitbanded;    // 0x13C Cache Tag Storage
  TAGVDW1S7              : TFMC_TAGVDW1S_bitbanded;    // 0x140 Cache Tag Storage
  TAGVDW2S0              : TFMC_TAGVDW2S_bitbanded;    // 0x144 Cache Tag Storage
  TAGVDW2S1              : TFMC_TAGVDW2S_bitbanded;    // 0x148 Cache Tag Storage
  TAGVDW2S2              : TFMC_TAGVDW2S_bitbanded;    // 0x14C Cache Tag Storage
  TAGVDW2S3              : TFMC_TAGVDW2S_bitbanded;    // 0x150 Cache Tag Storage
  TAGVDW2S4              : TFMC_TAGVDW2S_bitbanded;    // 0x154 Cache Tag Storage
  TAGVDW2S5              : TFMC_TAGVDW2S_bitbanded;    // 0x158 Cache Tag Storage
  TAGVDW2S6              : TFMC_TAGVDW2S_bitbanded;    // 0x15C Cache Tag Storage
  TAGVDW2S7              : TFMC_TAGVDW2S_bitbanded;    // 0x160 Cache Tag Storage
  TAGVDW3S0              : TFMC_TAGVDW3S_bitbanded;    // 0x164 Cache Tag Storage
  TAGVDW3S1              : TFMC_TAGVDW3S_bitbanded;    // 0x168 Cache Tag Storage
  TAGVDW3S2              : TFMC_TAGVDW3S_bitbanded;    // 0x16C Cache Tag Storage
  TAGVDW3S3              : TFMC_TAGVDW3S_bitbanded;    // 0x170 Cache Tag Storage
  TAGVDW3S4              : TFMC_TAGVDW3S_bitbanded;    // 0x174 Cache Tag Storage
  TAGVDW3S5              : TFMC_TAGVDW3S_bitbanded;    // 0x178 Cache Tag Storage
  TAGVDW3S6              : TFMC_TAGVDW3S_bitbanded;    // 0x17C Cache Tag Storage
  TAGVDW3S7              : TFMC_TAGVDW3S_bitbanded;    // 0x180 Cache Tag Storage
  RESERVED1              : array[0..127] of array[0..7] of longWord;
  DATAW0S0U_bitbanded    : longWord;                   // 0x200 Cache Data Storage (upper word)
  DATAW0S0L_bitbanded    : longWord;                   // 0x204 Cache Data Storage (lower word)
  DATAW0S1U_bitbanded    : longWord;                   // 0x208 Cache Data Storage (upper word)
  DATAW0S1L_bitbanded    : longWord;                   // 0x20C Cache Data Storage (lower word)
  DATAW0S2U_bitbanded    : longWord;                   // 0x210 Cache Data Storage (upper word)
  DATAW0S2L_bitbanded    : longWord;                   // 0x214 Cache Data Storage (lower word)
  DATAW0S3U_bitbanded    : longWord;                   // 0x218 Cache Data Storage (upper word)
  DATAW0S3L_bitbanded    : longWord;                   // 0x21C Cache Data Storage (lower word)
  DATAW0S4U_bitbanded    : longWord;                   // 0x220 Cache Data Storage (upper word)
  DATAW0S4L_bitbanded    : longWord;                   // 0x224 Cache Data Storage (lower word)
  DATAW0S5U_bitbanded    : longWord;                   // 0x228 Cache Data Storage (upper word)
  DATAW0S5L_bitbanded    : longWord;                   // 0x22C Cache Data Storage (lower word)
  DATAW0S6U_bitbanded    : longWord;                   // 0x230 Cache Data Storage (upper word)
  DATAW0S6L_bitbanded    : longWord;                   // 0x234 Cache Data Storage (lower word)
  DATAW0S7U_bitbanded    : longWord;                   // 0x238 Cache Data Storage (upper word)
  DATAW0S7L_bitbanded    : longWord;                   // 0x23C Cache Data Storage (lower word)
  DATAW1S0U_bitbanded    : longWord;                   // 0x240 Cache Data Storage (upper word)
  DATAW1S0L_bitbanded    : longWord;                   // 0x244 Cache Data Storage (lower word)
  DATAW1S1U_bitbanded    : longWord;                   // 0x248 Cache Data Storage (upper word)
  DATAW1S1L_bitbanded    : longWord;                   // 0x24C Cache Data Storage (lower word)
  DATAW1S2U_bitbanded    : longWord;                   // 0x250 Cache Data Storage (upper word)
  DATAW1S2L_bitbanded    : longWord;                   // 0x254 Cache Data Storage (lower word)
  DATAW1S3U_bitbanded    : longWord;                   // 0x258 Cache Data Storage (upper word)
  DATAW1S3L_bitbanded    : longWord;                   // 0x25C Cache Data Storage (lower word)
  DATAW1S4U_bitbanded    : longWord;                   // 0x260 Cache Data Storage (upper word)
  DATAW1S4L_bitbanded    : longWord;                   // 0x264 Cache Data Storage (lower word)
  DATAW1S5U_bitbanded    : longWord;                   // 0x268 Cache Data Storage (upper word)
  DATAW1S5L_bitbanded    : longWord;                   // 0x26C Cache Data Storage (lower word)
  DATAW1S6U_bitbanded    : longWord;                   // 0x270 Cache Data Storage (upper word)
  DATAW1S6L_bitbanded    : longWord;                   // 0x274 Cache Data Storage (lower word)
  DATAW1S7U_bitbanded    : longWord;                   // 0x278 Cache Data Storage (upper word)
  DATAW1S7L_bitbanded    : longWord;                   // 0x27C Cache Data Storage (lower word)
  DATAW2S0U_bitbanded    : longWord;                   // 0x280 Cache Data Storage (upper word)
  DATAW2S0L_bitbanded    : longWord;                   // 0x284 Cache Data Storage (lower word)
  DATAW2S1U_bitbanded    : longWord;                   // 0x288 Cache Data Storage (upper word)
  DATAW2S1L_bitbanded    : longWord;                   // 0x28C Cache Data Storage (lower word)
  DATAW2S2U_bitbanded    : longWord;                   // 0x290 Cache Data Storage (upper word)
  DATAW2S2L_bitbanded    : longWord;                   // 0x294 Cache Data Storage (lower word)
  DATAW2S3U_bitbanded    : longWord;                   // 0x298 Cache Data Storage (upper word)
  DATAW2S3L_bitbanded    : longWord;                   // 0x29C Cache Data Storage (lower word)
  DATAW2S4U_bitbanded    : longWord;                   // 0x2A0 Cache Data Storage (upper word)
  DATAW2S4L_bitbanded    : longWord;                   // 0x2A4 Cache Data Storage (lower word)
  DATAW2S5U_bitbanded    : longWord;                   // 0x2A8 Cache Data Storage (upper word)
  DATAW2S5L_bitbanded    : longWord;                   // 0x2AC Cache Data Storage (lower word)
  DATAW2S6U_bitbanded    : longWord;                   // 0x2B0 Cache Data Storage (upper word)
  DATAW2S6L_bitbanded    : longWord;                   // 0x2B4 Cache Data Storage (lower word)
  DATAW2S7U_bitbanded    : longWord;                   // 0x2B8 Cache Data Storage (upper word)
  DATAW2S7L_bitbanded    : longWord;                   // 0x2BC Cache Data Storage (lower word)
  DATAW3S0U_bitbanded    : longWord;                   // 0x2C0 Cache Data Storage (upper word)
  DATAW3S0L_bitbanded    : longWord;                   // 0x2C4 Cache Data Storage (lower word)
  DATAW3S1U_bitbanded    : longWord;                   // 0x2C8 Cache Data Storage (upper word)
  DATAW3S1L_bitbanded    : longWord;                   // 0x2CC Cache Data Storage (lower word)
  DATAW3S2U_bitbanded    : longWord;                   // 0x2D0 Cache Data Storage (upper word)
  DATAW3S2L_bitbanded    : longWord;                   // 0x2D4 Cache Data Storage (lower word)
  DATAW3S3U_bitbanded    : longWord;                   // 0x2D8 Cache Data Storage (upper word)
  DATAW3S3L_bitbanded    : longWord;                   // 0x2DC Cache Data Storage (lower word)
  DATAW3S4U_bitbanded    : longWord;                   // 0x2E0 Cache Data Storage (upper word)
  DATAW3S4L_bitbanded    : longWord;                   // 0x2E4 Cache Data Storage (lower word)
  DATAW3S5U_bitbanded    : longWord;                   // 0x2E8 Cache Data Storage (upper word)
  DATAW3S5L_bitbanded    : longWord;                   // 0x2EC Cache Data Storage (lower word)
  DATAW3S6U_bitbanded    : longWord;                   // 0x2F0 Cache Data Storage (upper word)
  DATAW3S6L_bitbanded    : longWord;                   // 0x2F4 Cache Data Storage (lower word)
  DATAW3S7U_bitbanded    : longWord;                   // 0x2F8 Cache Data Storage (upper word)
  DATAW3S7L_bitbanded    : longWord;                   // 0x2FC Cache Data Storage (lower word)
end;

// Flash Memory Interface
TFTFL_FSTAT_bits = bitpacked record
  MGSTAT0                : TBits_1;                    // [0:0] Memory Controller Command Completion Status Flag
  RESERVED0              : TBits_3;                    // [1:3] no description available
  FPVIOL                 : TBits_1;                    // [4:4] Flash Protection Violation Flag
  ACCERR                 : TBits_1;                    // [5:5] Flash Access Error Flag
  RDCOLERR               : TBits_1;                    // [6:6] FTFL Read Collision Error Flag
  CCIF                   : TBits_1;                    // [7:7] Command Complete Interrupt Flag
end;

TFTFL_FSTAT_bitbanded = record
  MGSTAT0                : longWord;                   // [0:0] Memory Controller Command Completion Status Flag
  RESERVED0              : array[0..2] of longWord;    // [1:3] no description available
  FPVIOL                 : longWord;                   // [4:4] Flash Protection Violation Flag
  ACCERR                 : longWord;                   // [5:5] Flash Access Error Flag
  RDCOLERR               : longWord;                   // [6:6] FTFL Read Collision Error Flag
  CCIF                   : longWord;                   // [7:7] Command Complete Interrupt Flag
end;

TFTFL_FCNFG_bits = bitpacked record
  EEERDY                 : TBits_1;                    // [0:0] no description available
  RAMRDY                 : TBits_1;                    // [1:1] RAM Ready
  PFLSH                  : TBits_1;                    // [2:2] FTFL configuration
  SWAP                   : TBits_1;                    // [3:3] Swap
  ERSSUSP                : TBits_1;                    // [4:4] Erase Suspend
  ERSAREQ                : TBits_1;                    // [5:5] Erase All Request
  RDCOLLIE               : TBits_1;                    // [6:6] Read Collision Error Interrupt Enable
  CCIE                   : TBits_1;                    // [7:7] Command Complete Interrupt Enable
end;

TFTFL_FCNFG_bitbanded = record
  EEERDY                 : longWord;                   // [0:0] no description available
  RAMRDY                 : longWord;                   // [1:1] RAM Ready
  PFLSH                  : longWord;                   // [2:2] FTFL configuration
  SWAP                   : longWord;                   // [3:3] Swap
  ERSSUSP                : longWord;                   // [4:4] Erase Suspend
  ERSAREQ                : longWord;                   // [5:5] Erase All Request
  RDCOLLIE               : longWord;                   // [6:6] Read Collision Error Interrupt Enable
  CCIE                   : longWord;                   // [7:7] Command Complete Interrupt Enable
end;

TFTFL_FSEC_bits = bitpacked record
  SEC                    : TBits_2;                    // [0:1] Flash Security
  FSLACC                 : TBits_2;                    // [2:3] Freescale Failure Analysis Access Code
  MEEN                   : TBits_2;                    // [4:5] Mass Erase Enable Bits
  KEYEN                  : TBits_2;                    // [6:7] Backdoor Key Security Enable
end;

TFTFL_FSEC_bitbanded = record
  SEC                    : array[0..1] of longWord;    // [0:1] Flash Security
  FSLACC                 : array[0..1] of longWord;    // [2:3] Freescale Failure Analysis Access Code
  MEEN                   : array[0..1] of longWord;    // [4:5] Mass Erase Enable Bits
  KEYEN                  : array[0..1] of longWord;    // [6:7] Backdoor Key Security Enable
end;

TFTFL_FOPT_bits = bitpacked record
  OPT                    : TBits_8;                    // [0:7] Nonvolatile Option
end;

TFTFL_FOPT_bitbanded = record
  OPT                    : array[0..7] of longWord;    // [0:7] Nonvolatile Option
end;

TFTFL_FCCOB_bits = bitpacked record
  CCOBn                  : TBits_8;                    // [0:7] no description available
end;

TFTFL_FCCOB_bitbanded = record
  CCOBn                  : array[0..7] of longWord;    // [0:7] no description available
end;

TFTFL_FPROT_bits = bitpacked record
  PROT                   : TBits_8;                    // [0:7] Program Flash Region Protect
end;

TFTFL_FPROT_bitbanded = record
  PROT                   : array[0..7] of longWord;    // [0:7] Program Flash Region Protect
end;

TFTFL_FEPROT_bits = bitpacked record
  EPROT                  : TBits_8;                    // [0:7] EEPROM Region Protect
end;

TFTFL_FEPROT_bitbanded = record
  EPROT                  : array[0..7] of longWord;    // [0:7] EEPROM Region Protect
end;

TFTFL_FDPROT_bits = bitpacked record
  DPROT                  : TBits_8;                    // [0:7] Data Flash Region Protect
end;

TFTFL_FDPROT_bitbanded = record
  DPROT                  : array[0..7] of longWord;    // [0:7] Data Flash Region Protect
end;

TFTFL_Registers = record
  case boolean of false: (
  FSTAT                  : byte;                       // 0x00 Flash Status Register
  FCNFG                  : byte;                       // 0x01 Flash Configuration Register
  FSEC                   : byte;                       // 0x02 Flash Security Register
  FOPT                   : byte;                       // 0x03 Flash Option Register
  FCCOB3                 : byte;                       // 0x04 Flash Common Command Object Registers
  FCCOB2                 : byte;                       // 0x05 Flash Common Command Object Registers
  FCCOB1                 : byte;                       // 0x06 Flash Common Command Object Registers
  FCCOB0                 : byte;                       // 0x07 Flash Common Command Object Registers
  FCCOB7                 : byte;                       // 0x08 Flash Common Command Object Registers
  FCCOB6                 : byte;                       // 0x09 Flash Common Command Object Registers
  FCCOB5                 : byte;                       // 0x0A Flash Common Command Object Registers
  FCCOB4                 : byte;                       // 0x0B Flash Common Command Object Registers
  FCCOBB                 : byte;                       // 0x0C Flash Common Command Object Registers
  FCCOBA                 : byte;                       // 0x0D Flash Common Command Object Registers
  FCCOB9                 : byte;                       // 0x0E Flash Common Command Object Registers
  FCCOB8                 : byte;                       // 0x0F Flash Common Command Object Registers
  FPROT3                 : byte;                       // 0x10 Program Flash Protection Registers
  FPROT2                 : byte;                       // 0x11 Program Flash Protection Registers
  FPROT1                 : byte;                       // 0x12 Program Flash Protection Registers
  FPROT0                 : byte;                       // 0x13 Program Flash Protection Registers
  RESERVED0              : word;                       // 0x14
  FEPROT                 : byte;                       // 0x16 EEPROM Protection Register
  FDPROT                 : byte;                       // 0x17 Data Flash Protection Register
);
true : (
FSTAT_bits               : TFTFL_FSTAT_bits;           // 0x01 Flash Status Register
FCNFG_bits               : TFTFL_FCNFG_bits;           // 0x02 Flash Configuration Register
FSEC_bits                : TFTFL_FSEC_bits;            // 0x03 Flash Security Register
FOPT_bits                : TFTFL_FOPT_bits;            // 0x04 Flash Option Register
FCCOB3_bits              : TFTFL_FCCOB_bits;           // 0x05 Flash Common Command Object Registers
FCCOB2_bits              : TFTFL_FCCOB_bits;           // 0x06 Flash Common Command Object Registers
FCCOB1_bits              : TFTFL_FCCOB_bits;           // 0x07 Flash Common Command Object Registers
FCCOB0_bits              : TFTFL_FCCOB_bits;           // 0x08 Flash Common Command Object Registers
FCCOB7_bits              : TFTFL_FCCOB_bits;           // 0x09 Flash Common Command Object Registers
FCCOB6_bits              : TFTFL_FCCOB_bits;           // 0x0A Flash Common Command Object Registers
FCCOB5_bits              : TFTFL_FCCOB_bits;           // 0x0B Flash Common Command Object Registers
FCCOB4_bits              : TFTFL_FCCOB_bits;           // 0x0C Flash Common Command Object Registers
FCCOBB_bits              : byte;                       // 0x0C Flash Common Command Object Registers
FCCOBA_bits              : byte;                       // 0x0D Flash Common Command Object Registers
FCCOB9_bits              : TFTFL_FCCOB_bits;           // 0x0F Flash Common Command Object Registers
FCCOB8_bits              : TFTFL_FCCOB_bits;           // 0x10 Flash Common Command Object Registers
FPROT3_bits              : TFTFL_FPROT_bits;           // 0x11 Program Flash Protection Registers
FPROT2_bits              : TFTFL_FPROT_bits;           // 0x12 Program Flash Protection Registers
FPROT1_bits              : TFTFL_FPROT_bits;           // 0x13 Program Flash Protection Registers
FPROT0_bits              : TFTFL_FPROT_bits;           // 0x14 Program Flash Protection Registers
RESERVED_bits0           : word;
FEPROT_bits              : TFTFL_FEPROT_bits;          // 0x17 EEPROM Protection Register
FDPROT_bits              : TFTFL_FDPROT_bits;          // 0x18 Data Flash Protection Register
);
end;

TFTFLRegisters_bitbanded = record
  FSTAT                  : TFTFL_FSTAT_bitbanded;      // 0x01 Flash Status Register
  FCNFG                  : TFTFL_FCNFG_bitbanded;      // 0x02 Flash Configuration Register
  FSEC                   : TFTFL_FSEC_bitbanded;       // 0x03 Flash Security Register
  FOPT                   : TFTFL_FOPT_bitbanded;       // 0x04 Flash Option Register
  FCCOB3                 : TFTFL_FCCOB_bitbanded;      // 0x05 Flash Common Command Object Registers
  FCCOB2                 : TFTFL_FCCOB_bitbanded;      // 0x06 Flash Common Command Object Registers
  FCCOB1                 : TFTFL_FCCOB_bitbanded;      // 0x07 Flash Common Command Object Registers
  FCCOB0                 : TFTFL_FCCOB_bitbanded;      // 0x08 Flash Common Command Object Registers
  FCCOB7                 : TFTFL_FCCOB_bitbanded;      // 0x09 Flash Common Command Object Registers
  FCCOB6                 : TFTFL_FCCOB_bitbanded;      // 0x0A Flash Common Command Object Registers
  FCCOB5                 : TFTFL_FCCOB_bitbanded;      // 0x0B Flash Common Command Object Registers
  FCCOB4                 : TFTFL_FCCOB_bitbanded;      // 0x0C Flash Common Command Object Registers
  FCCOBB_bitbanded       : byte;                       // 0x0C Flash Common Command Object Registers
  FCCOBA_bitbanded       : byte;                       // 0x0D Flash Common Command Object Registers
  FCCOB9                 : TFTFL_FCCOB_bitbanded;      // 0x0F Flash Common Command Object Registers
  FCCOB8                 : TFTFL_FCCOB_bitbanded;      // 0x10 Flash Common Command Object Registers
  FPROT3                 : TFTFL_FPROT_bitbanded;      // 0x11 Program Flash Protection Registers
  FPROT2                 : TFTFL_FPROT_bitbanded;      // 0x12 Program Flash Protection Registers
  FPROT1                 : TFTFL_FPROT_bitbanded;      // 0x13 Program Flash Protection Registers
  FPROT0                 : TFTFL_FPROT_bitbanded;      // 0x14 Program Flash Protection Registers
  RESERVED0              : array[0..1] of array[0..7] of longWord;
  FEPROT                 : TFTFL_FEPROT_bitbanded;     // 0x17 EEPROM Protection Register
  FDPROT                 : TFTFL_FDPROT_bitbanded;     // 0x18 Data Flash Protection Register
end;

// Flash Memory Interface
TFTFL_FlashConfig_BACKKEY3_bits = bitpacked record
  KEY                    : TBits_8;                    // [0:7] Backdoor Comparison Key.
end;

TFTFL_FlashConfig_BACKKEY3_bitbanded = record
  KEY                    : array[0..7] of longWord;    // [0:7] Backdoor Comparison Key.
end;

TFTFL_FlashConfig_BACKKEY2_bits = bitpacked record
  KEY                    : TBits_8;                    // [0:7] Backdoor Comparison Key.
end;

TFTFL_FlashConfig_BACKKEY2_bitbanded = record
  KEY                    : array[0..7] of longWord;    // [0:7] Backdoor Comparison Key.
end;

TFTFL_FlashConfig_BACKKEY1_bits = bitpacked record
  KEY                    : TBits_8;                    // [0:7] Backdoor Comparison Key.
end;

TFTFL_FlashConfig_BACKKEY1_bitbanded = record
  KEY                    : array[0..7] of longWord;    // [0:7] Backdoor Comparison Key.
end;

TFTFL_FlashConfig_BACKKEY0_bits = bitpacked record
  KEY                    : TBits_8;                    // [0:7] Backdoor Comparison Key.
end;

TFTFL_FlashConfig_BACKKEY0_bitbanded = record
  KEY                    : array[0..7] of longWord;    // [0:7] Backdoor Comparison Key.
end;

TFTFL_FlashConfig_BACKKEY7_bits = bitpacked record
  KEY                    : TBits_8;                    // [0:7] Backdoor Comparison Key.
end;

TFTFL_FlashConfig_BACKKEY7_bitbanded = record
  KEY                    : array[0..7] of longWord;    // [0:7] Backdoor Comparison Key.
end;

TFTFL_FlashConfig_BACKKEY6_bits = bitpacked record
  KEY                    : TBits_8;                    // [0:7] Backdoor Comparison Key.
end;

TFTFL_FlashConfig_BACKKEY6_bitbanded = record
  KEY                    : array[0..7] of longWord;    // [0:7] Backdoor Comparison Key.
end;

TFTFL_FlashConfig_BACKKEY5_bits = bitpacked record
  KEY                    : TBits_8;                    // [0:7] Backdoor Comparison Key.
end;

TFTFL_FlashConfig_BACKKEY5_bitbanded = record
  KEY                    : array[0..7] of longWord;    // [0:7] Backdoor Comparison Key.
end;

TFTFL_FlashConfig_BACKKEY4_bits = bitpacked record
  KEY                    : TBits_8;                    // [0:7] Backdoor Comparison Key.
end;

TFTFL_FlashConfig_BACKKEY4_bitbanded = record
  KEY                    : array[0..7] of longWord;    // [0:7] Backdoor Comparison Key.
end;

TFTFL_FlashConfig_FPROT3_bits = bitpacked record
  PROT                   : TBits_8;                    // [0:7] P-Flash Region Protect
end;

TFTFL_FlashConfig_FPROT3_bitbanded = record
  PROT                   : array[0..7] of longWord;    // [0:7] P-Flash Region Protect
end;

TFTFL_FlashConfig_FPROT2_bits = bitpacked record
  PROT                   : TBits_8;                    // [0:7] P-Flash Region Protect
end;

TFTFL_FlashConfig_FPROT2_bitbanded = record
  PROT                   : array[0..7] of longWord;    // [0:7] P-Flash Region Protect
end;

TFTFL_FlashConfig_FPROT1_bits = bitpacked record
  PROT                   : TBits_8;                    // [0:7] P-Flash Region Protect
end;

TFTFL_FlashConfig_FPROT1_bitbanded = record
  PROT                   : array[0..7] of longWord;    // [0:7] P-Flash Region Protect
end;

TFTFL_FlashConfig_FPROT0_bits = bitpacked record
  PROT                   : TBits_8;                    // [0:7] P-Flash Region Protect
end;

TFTFL_FlashConfig_FPROT0_bitbanded = record
  PROT                   : array[0..7] of longWord;    // [0:7] P-Flash Region Protect
end;

TFTFL_FlashConfig_FSEC_bits = bitpacked record
  SEC                    : TBits_2;                    // [0:1] Flash Security
  FSLACC                 : TBits_2;                    // [2:3] Freescale Failure Analysis Access Code
  MEEN                   : TBits_2;                    // [4:5] no description available
  KEYEN                  : TBits_2;                    // [6:7] Backdoor Key Security Enable
end;

TFTFL_FlashConfig_FSEC_bitbanded = record
  SEC                    : array[0..1] of longWord;    // [0:1] Flash Security
  FSLACC                 : array[0..1] of longWord;    // [2:3] Freescale Failure Analysis Access Code
  MEEN                   : array[0..1] of longWord;    // [4:5] no description available
  KEYEN                  : array[0..1] of longWord;    // [6:7] Backdoor Key Security Enable
end;

TFTFL_FlashConfig_FOPT_bits = bitpacked record
  LPBOOT                 : TBits_1;                    // [0:0] no description available
  EZPORT_DIS             : TBits_1;                    // [1:1] no description available
  RESERVED0              : TBits_1;                    // [2:2] no description available
  RESERVED1              : TBits_1;                    // [3:3] no description available
  RESERVED2              : TBits_1;                    // [4:4] no description available
  RESERVED3              : TBits_1;                    // [5:5] no description available
  RESERVED4              : TBits_1;                    // [6:6] no description available
  RESERVED5              : TBits_1;                    // [7:7] no description available
end;

TFTFL_FlashConfig_FOPT_bitbanded = record
  LPBOOT                 : longWord;                   // [0:0] no description available
  EZPORT_DIS             : longWord;                   // [1:1] no description available
  RESERVED0              : longWord;                   // [2:2] no description available
  RESERVED1              : longWord;                   // [3:3] no description available
  RESERVED2              : longWord;                   // [4:4] no description available
  RESERVED3              : longWord;                   // [5:5] no description available
  RESERVED4              : longWord;                   // [6:6] no description available
  RESERVED5              : longWord;                   // [7:7] no description available
end;

TFTFL_FlashConfig_FEPROT_bits = bitpacked record
  EPROT                  : TBits_8;                    // [0:7] no description available
end;

TFTFL_FlashConfig_FEPROT_bitbanded = record
  EPROT                  : array[0..7] of longWord;    // [0:7] no description available
end;

TFTFL_FlashConfig_FDPROT_bits = bitpacked record
  DPROT                  : TBits_8;                    // [0:7] D-Flash Region Protect
end;

TFTFL_FlashConfig_FDPROT_bitbanded = record
  DPROT                  : array[0..7] of longWord;    // [0:7] D-Flash Region Protect
end;

TFTFL_FlashConfig_Registers = record
  case boolean of false: (
  BACKKEY3               : byte;                       // 0x00 Backdoor Comparison Key 3.
  BACKKEY2               : byte;                       // 0x01 Backdoor Comparison Key 2.
  BACKKEY1               : byte;                       // 0x02 Backdoor Comparison Key 1.
  BACKKEY0               : byte;                       // 0x03 Backdoor Comparison Key 0.
  BACKKEY7               : byte;                       // 0x04 Backdoor Comparison Key 7.
  BACKKEY6               : byte;                       // 0x05 Backdoor Comparison Key 6.
  BACKKEY5               : byte;                       // 0x06 Backdoor Comparison Key 5.
  BACKKEY4               : byte;                       // 0x07 Backdoor Comparison Key 4.
  FPROT3                 : byte;                       // 0x08 Non-volatile P-Flash Protection 1 - Low Register
  FPROT2                 : byte;                       // 0x09 Non-volatile P-Flash Protection 1 - High Register
  FPROT1                 : byte;                       // 0x0A Non-volatile P-Flash Protection 0 - Low Register
  FPROT0                 : byte;                       // 0x0B Non-volatile P-Flash Protection 0 - High Register
  FSEC                   : byte;                       // 0x0C Non-volatile Flash Security Register
  FOPT                   : byte;                       // 0x0D Non-volatile Flash Option Register
  FEPROT                 : byte;                       // 0x0E Non-volatile EERAM Protection Register
  FDPROT                 : byte;                       // 0x0F Non-volatile D-Flash Protection Register
);
true : (
BACKKEY3_bits            : TFTFL_FlashConfig_BACKKEY3_bits;// 0x01 Backdoor Comparison Key 3.
BACKKEY2_bits            : TFTFL_FlashConfig_BACKKEY2_bits;// 0x02 Backdoor Comparison Key 2.
BACKKEY1_bits            : TFTFL_FlashConfig_BACKKEY1_bits;// 0x03 Backdoor Comparison Key 1.
BACKKEY0_bits            : TFTFL_FlashConfig_BACKKEY0_bits;// 0x04 Backdoor Comparison Key 0.
BACKKEY7_bits            : TFTFL_FlashConfig_BACKKEY7_bits;// 0x05 Backdoor Comparison Key 7.
BACKKEY6_bits            : TFTFL_FlashConfig_BACKKEY6_bits;// 0x06 Backdoor Comparison Key 6.
BACKKEY5_bits            : TFTFL_FlashConfig_BACKKEY5_bits;// 0x07 Backdoor Comparison Key 5.
BACKKEY4_bits            : TFTFL_FlashConfig_BACKKEY4_bits;// 0x08 Backdoor Comparison Key 4.
FPROT3_bits              : TFTFL_FlashConfig_FPROT3_bits;// 0x09 Non-volatile P-Flash Protection 1 - Low Register
FPROT2_bits              : TFTFL_FlashConfig_FPROT2_bits;// 0x0A Non-volatile P-Flash Protection 1 - High Register
FPROT1_bits              : TFTFL_FlashConfig_FPROT1_bits;// 0x0B Non-volatile P-Flash Protection 0 - Low Register
FPROT0_bits              : TFTFL_FlashConfig_FPROT0_bits;// 0x0C Non-volatile P-Flash Protection 0 - High Register
FSEC_bits                : TFTFL_FlashConfig_FSEC_bits;// 0x0D Non-volatile Flash Security Register
FOPT_bits                : TFTFL_FlashConfig_FOPT_bits;// 0x0E Non-volatile Flash Option Register
FEPROT_bits              : TFTFL_FlashConfig_FEPROT_bits;// 0x0F Non-volatile EERAM Protection Register
FDPROT_bits              : TFTFL_FlashConfig_FDPROT_bits;// 0x10 Non-volatile D-Flash Protection Register
);
end;

TFTFL_FlashConfigRegisters_bitbanded = record
  BACKKEY3               : TFTFL_FlashConfig_BACKKEY3_bitbanded;// 0x01 Backdoor Comparison Key 3.
  BACKKEY2               : TFTFL_FlashConfig_BACKKEY2_bitbanded;// 0x02 Backdoor Comparison Key 2.
  BACKKEY1               : TFTFL_FlashConfig_BACKKEY1_bitbanded;// 0x03 Backdoor Comparison Key 1.
  BACKKEY0               : TFTFL_FlashConfig_BACKKEY0_bitbanded;// 0x04 Backdoor Comparison Key 0.
  BACKKEY7               : TFTFL_FlashConfig_BACKKEY7_bitbanded;// 0x05 Backdoor Comparison Key 7.
  BACKKEY6               : TFTFL_FlashConfig_BACKKEY6_bitbanded;// 0x06 Backdoor Comparison Key 6.
  BACKKEY5               : TFTFL_FlashConfig_BACKKEY5_bitbanded;// 0x07 Backdoor Comparison Key 5.
  BACKKEY4               : TFTFL_FlashConfig_BACKKEY4_bitbanded;// 0x08 Backdoor Comparison Key 4.
  FPROT3                 : TFTFL_FlashConfig_FPROT3_bitbanded;// 0x09 Non-volatile P-Flash Protection 1 - Low Register
  FPROT2                 : TFTFL_FlashConfig_FPROT2_bitbanded;// 0x0A Non-volatile P-Flash Protection 1 - High Register
  FPROT1                 : TFTFL_FlashConfig_FPROT1_bitbanded;// 0x0B Non-volatile P-Flash Protection 0 - Low Register
  FPROT0                 : TFTFL_FlashConfig_FPROT0_bitbanded;// 0x0C Non-volatile P-Flash Protection 0 - High Register
  FSEC                   : TFTFL_FlashConfig_FSEC_bitbanded;// 0x0D Non-volatile Flash Security Register
  FOPT                   : TFTFL_FlashConfig_FOPT_bitbanded;// 0x0E Non-volatile Flash Option Register
  FEPROT                 : TFTFL_FlashConfig_FEPROT_bitbanded;// 0x0F Non-volatile EERAM Protection Register
  FDPROT                 : TFTFL_FlashConfig_FDPROT_bitbanded;// 0x10 Non-volatile D-Flash Protection Register
end;

// FlexTimer Module
TFTM0_SC_bits = bitpacked record
  PS                     : TBits_3;                    // [0:2] Prescale Factor Selection
  CLKS                   : TBits_2;                    // [3:4] Clock Source Selection
  CPWMS                  : TBits_1;                    // [5:5] Center-aligned PWM Select
  TOIE                   : TBits_1;                    // [6:6] Timer Overflow Interrupt Enable
  TOF                    : TBits_1;                    // [7:7] Timer Overflow Flag
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM0_SC_bitbanded = record
  PS                     : array[0..2] of longWord;    // [0:2] Prescale Factor Selection
  CLKS                   : array[0..1] of longWord;    // [3:4] Clock Source Selection
  CPWMS                  : longWord;                   // [5:5] Center-aligned PWM Select
  TOIE                   : longWord;                   // [6:6] Timer Overflow Interrupt Enable
  TOF                    : longWord;                   // [7:7] Timer Overflow Flag
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM0_CNT_bits = bitpacked record
  COUNT                  : TBits_16;                   // [0:15] Counter value
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM0_CNT_bitbanded = record
  COUNT                  : array[0..15] of longWord;   // [0:15] Counter value
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM0_MOD_bits = bitpacked record
  &MOD                   : TBits_16;                   // [0:15] no description available
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM0_MOD_bitbanded = record
  &MOD                   : array[0..15] of longWord;   // [0:15] no description available
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM0_CSC_bits = bitpacked record
  DMA                    : TBits_1;                    // [0:0] DMA Enable
  RESERVED0              : TBits_1;                    // [1:1] no description available
  ELSA                   : TBits_1;                    // [2:2] Edge or Level Select
  ELSB                   : TBits_1;                    // [3:3] Edge or Level Select
  MSA                    : TBits_1;                    // [4:4] Channel Mode Select
  MSB                    : TBits_1;                    // [5:5] Channel Mode Select
  CHIE                   : TBits_1;                    // [6:6] Channel Interrupt Enable
  CHF                    : TBits_1;                    // [7:7] Channel Flag
  RESERVED1              : TBits_24;                   // [8:31] no description available
end;

TFTM0_CSC_bitbanded = record
  DMA                    : longWord;                   // [0:0] DMA Enable
  RESERVED0              : longWord;                   // [1:1] no description available
  ELSA                   : longWord;                   // [2:2] Edge or Level Select
  ELSB                   : longWord;                   // [3:3] Edge or Level Select
  MSA                    : longWord;                   // [4:4] Channel Mode Select
  MSB                    : longWord;                   // [5:5] Channel Mode Select
  CHIE                   : longWord;                   // [6:6] Channel Interrupt Enable
  CHF                    : longWord;                   // [7:7] Channel Flag
  RESERVED1              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM0_CV_bits = bitpacked record
  VAL                    : TBits_16;                   // [0:15] Channel Value
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM0_CV_bitbanded = record
  VAL                    : array[0..15] of longWord;   // [0:15] Channel Value
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM0_CNTIN_bits = bitpacked record
  INIT                   : TBits_16;                   // [0:15] no description available
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM0_CNTIN_bitbanded = record
  INIT                   : array[0..15] of longWord;   // [0:15] no description available
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM0_STATUS_bits = bitpacked record
  CH0F                   : TBits_1;                    // [0:0] Channel 0 Flag
  CH1F                   : TBits_1;                    // [1:1] Channel 1 Flag
  CH2F                   : TBits_1;                    // [2:2] Channel 2 Flag
  CH3F                   : TBits_1;                    // [3:3] Channel 3 Flag
  CH4F                   : TBits_1;                    // [4:4] Channel 4 Flag
  CH5F                   : TBits_1;                    // [5:5] Channel 5 Flag
  CH6F                   : TBits_1;                    // [6:6] Channel 6 Flag
  CH7F                   : TBits_1;                    // [7:7] Channel 7 Flag
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM0_STATUS_bitbanded = record
  CH0F                   : longWord;                   // [0:0] Channel 0 Flag
  CH1F                   : longWord;                   // [1:1] Channel 1 Flag
  CH2F                   : longWord;                   // [2:2] Channel 2 Flag
  CH3F                   : longWord;                   // [3:3] Channel 3 Flag
  CH4F                   : longWord;                   // [4:4] Channel 4 Flag
  CH5F                   : longWord;                   // [5:5] Channel 5 Flag
  CH6F                   : longWord;                   // [6:6] Channel 6 Flag
  CH7F                   : longWord;                   // [7:7] Channel 7 Flag
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM0_MODE_bits = bitpacked record
  FTMEN                  : TBits_1;                    // [0:0] FTM Enable
  INIT                   : TBits_1;                    // [1:1] Initialize the Channels Output
  WPDIS                  : TBits_1;                    // [2:2] Write Protection Disable
  PWMSYNC                : TBits_1;                    // [3:3] PWM Synchronization Mode
  CAPTEST                : TBits_1;                    // [4:4] Capture Test Mode Enable
  FAULTM                 : TBits_2;                    // [5:6] Fault Control Mode
  FAULTIE                : TBits_1;                    // [7:7] Fault Interrupt Enable
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM0_MODE_bitbanded = record
  FTMEN                  : longWord;                   // [0:0] FTM Enable
  INIT                   : longWord;                   // [1:1] Initialize the Channels Output
  WPDIS                  : longWord;                   // [2:2] Write Protection Disable
  PWMSYNC                : longWord;                   // [3:3] PWM Synchronization Mode
  CAPTEST                : longWord;                   // [4:4] Capture Test Mode Enable
  FAULTM                 : array[0..1] of longWord;    // [5:6] Fault Control Mode
  FAULTIE                : longWord;                   // [7:7] Fault Interrupt Enable
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM0_SYNC_bits = bitpacked record
  CNTMIN                 : TBits_1;                    // [0:0] Minimum loading point enable
  CNTMAX                 : TBits_1;                    // [1:1] Maximum loading point enable
  REINIT                 : TBits_1;                    // [2:2] FTM Counter Reinitialization by Synchronization (FTM Counter Synchronization)
  SYNCHOM                : TBits_1;                    // [3:3] Output Mask Synchronization
  TRIG0                  : TBits_1;                    // [4:4] PWM Synchronization Hardware Trigger 0
  TRIG1                  : TBits_1;                    // [5:5] PWM Synchronization Hardware Trigger 1
  TRIG2                  : TBits_1;                    // [6:6] PWM Synchronization Hardware Trigger 2
  SWSYNC                 : TBits_1;                    // [7:7] PWM Synchronization Software Trigger
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM0_SYNC_bitbanded = record
  CNTMIN                 : longWord;                   // [0:0] Minimum loading point enable
  CNTMAX                 : longWord;                   // [1:1] Maximum loading point enable
  REINIT                 : longWord;                   // [2:2] FTM Counter Reinitialization by Synchronization (FTM Counter Synchronization)
  SYNCHOM                : longWord;                   // [3:3] Output Mask Synchronization
  TRIG0                  : longWord;                   // [4:4] PWM Synchronization Hardware Trigger 0
  TRIG1                  : longWord;                   // [5:5] PWM Synchronization Hardware Trigger 1
  TRIG2                  : longWord;                   // [6:6] PWM Synchronization Hardware Trigger 2
  SWSYNC                 : longWord;                   // [7:7] PWM Synchronization Software Trigger
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM0_OUTINIT_bits = bitpacked record
  CH0OI                  : TBits_1;                    // [0:0] Channel 0 Output Initialization Value
  CH1OI                  : TBits_1;                    // [1:1] Channel 1 Output Initialization Value
  CH2OI                  : TBits_1;                    // [2:2] Channel 2 Output Initialization Value
  CH3OI                  : TBits_1;                    // [3:3] Channel 3 Output Initialization Value
  CH4OI                  : TBits_1;                    // [4:4] Channel 4 Output Initialization Value
  CH5OI                  : TBits_1;                    // [5:5] Channel 5 Output Initialization Value
  CH6OI                  : TBits_1;                    // [6:6] Channel 6 Output Initialization Value
  CH7OI                  : TBits_1;                    // [7:7] Channel 7 Output Initialization Value
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM0_OUTINIT_bitbanded = record
  CH0OI                  : longWord;                   // [0:0] Channel 0 Output Initialization Value
  CH1OI                  : longWord;                   // [1:1] Channel 1 Output Initialization Value
  CH2OI                  : longWord;                   // [2:2] Channel 2 Output Initialization Value
  CH3OI                  : longWord;                   // [3:3] Channel 3 Output Initialization Value
  CH4OI                  : longWord;                   // [4:4] Channel 4 Output Initialization Value
  CH5OI                  : longWord;                   // [5:5] Channel 5 Output Initialization Value
  CH6OI                  : longWord;                   // [6:6] Channel 6 Output Initialization Value
  CH7OI                  : longWord;                   // [7:7] Channel 7 Output Initialization Value
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM0_OUTMASK_bits = bitpacked record
  CH0OM                  : TBits_1;                    // [0:0] Channel 0 Output Mask
  CH1OM                  : TBits_1;                    // [1:1] Channel 1 Output Mask
  CH2OM                  : TBits_1;                    // [2:2] Channel 2 Output Mask
  CH3OM                  : TBits_1;                    // [3:3] Channel 3 Output Mask
  CH4OM                  : TBits_1;                    // [4:4] Channel 4 Output Mask
  CH5OM                  : TBits_1;                    // [5:5] Channel 5 Output Mask
  CH6OM                  : TBits_1;                    // [6:6] Channel 6 Output Mask
  CH7OM                  : TBits_1;                    // [7:7] Channel 7 Output Mask
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM0_OUTMASK_bitbanded = record
  CH0OM                  : longWord;                   // [0:0] Channel 0 Output Mask
  CH1OM                  : longWord;                   // [1:1] Channel 1 Output Mask
  CH2OM                  : longWord;                   // [2:2] Channel 2 Output Mask
  CH3OM                  : longWord;                   // [3:3] Channel 3 Output Mask
  CH4OM                  : longWord;                   // [4:4] Channel 4 Output Mask
  CH5OM                  : longWord;                   // [5:5] Channel 5 Output Mask
  CH6OM                  : longWord;                   // [6:6] Channel 6 Output Mask
  CH7OM                  : longWord;                   // [7:7] Channel 7 Output Mask
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM0_COMBINE_bits = bitpacked record
  COMBINE0               : TBits_1;                    // [0:0] Combine Channels for n = 0
  COMP0                  : TBits_1;                    // [1:1] Complement of Channel (n) for n = 0
  DECAPEN0               : TBits_1;                    // [2:2] Dual Edge Capture Mode Enable for n = 0
  DECAP0                 : TBits_1;                    // [3:3] Dual Edge Capture Mode Captures for n = 0
  DTEN0                  : TBits_1;                    // [4:4] Deadtime Enable for n = 0
  SYNCEN0                : TBits_1;                    // [5:5] Synchronization Enable for n = 0
  FAULTEN0               : TBits_1;                    // [6:6] Fault Control Enable for n = 0
  RESERVED0              : TBits_1;                    // [7:7] no description available
  COMBINE1               : TBits_1;                    // [8:8] Combine Channels for n = 2
  COMP1                  : TBits_1;                    // [9:9] Complement of Channel (n) for n = 2
  DECAPEN1               : TBits_1;                    // [10:10] Dual Edge Capture Mode Enable for n = 2
  DECAP1                 : TBits_1;                    // [11:11] Dual Edge Capture Mode Captures for n = 2
  DTEN1                  : TBits_1;                    // [12:12] Deadtime Enable for n = 2
  SYNCEN1                : TBits_1;                    // [13:13] Synchronization Enable for n = 2
  FAULTEN1               : TBits_1;                    // [14:14] Fault Control Enable for n = 2
  RESERVED1              : TBits_1;                    // [15:15] no description available
  COMBINE2               : TBits_1;                    // [16:16] Combine Channels for n = 4
  COMP2                  : TBits_1;                    // [17:17] Complement of Channel (n) for n = 4
  DECAPEN2               : TBits_1;                    // [18:18] Dual Edge Capture Mode Enable for n = 4
  DECAP2                 : TBits_1;                    // [19:19] Dual Edge Capture Mode Captures for n = 4
  DTEN2                  : TBits_1;                    // [20:20] Deadtime Enable for n = 4
  SYNCEN2                : TBits_1;                    // [21:21] Synchronization Enable for n = 4
  FAULTEN2               : TBits_1;                    // [22:22] Fault Control Enable for n = 4
  RESERVED2              : TBits_1;                    // [23:23] no description available
  COMBINE3               : TBits_1;                    // [24:24] Combine Channels for n = 6
  COMP3                  : TBits_1;                    // [25:25] Complement of Channel (n) for n = 6
  DECAPEN3               : TBits_1;                    // [26:26] Dual Edge Capture Mode Enable for n = 6
  DECAP3                 : TBits_1;                    // [27:27] Dual Edge Capture Mode Captures for n = 6
  DTEN3                  : TBits_1;                    // [28:28] Deadtime Enable for n = 6
  SYNCEN3                : TBits_1;                    // [29:29] Synchronization Enable for n = 6
  FAULTEN3               : TBits_1;                    // [30:30] Fault Control Enable for n = 6
  RESERVED3              : TBits_1;                    // [31:31] no description available
end;

TFTM0_COMBINE_bitbanded = record
  COMBINE0               : longWord;                   // [0:0] Combine Channels for n = 0
  COMP0                  : longWord;                   // [1:1] Complement of Channel (n) for n = 0
  DECAPEN0               : longWord;                   // [2:2] Dual Edge Capture Mode Enable for n = 0
  DECAP0                 : longWord;                   // [3:3] Dual Edge Capture Mode Captures for n = 0
  DTEN0                  : longWord;                   // [4:4] Deadtime Enable for n = 0
  SYNCEN0                : longWord;                   // [5:5] Synchronization Enable for n = 0
  FAULTEN0               : longWord;                   // [6:6] Fault Control Enable for n = 0
  RESERVED0              : longWord;                   // [7:7] no description available
  COMBINE1               : longWord;                   // [8:8] Combine Channels for n = 2
  COMP1                  : longWord;                   // [9:9] Complement of Channel (n) for n = 2
  DECAPEN1               : longWord;                   // [10:10] Dual Edge Capture Mode Enable for n = 2
  DECAP1                 : longWord;                   // [11:11] Dual Edge Capture Mode Captures for n = 2
  DTEN1                  : longWord;                   // [12:12] Deadtime Enable for n = 2
  SYNCEN1                : longWord;                   // [13:13] Synchronization Enable for n = 2
  FAULTEN1               : longWord;                   // [14:14] Fault Control Enable for n = 2
  RESERVED1              : longWord;                   // [15:15] no description available
  COMBINE2               : longWord;                   // [16:16] Combine Channels for n = 4
  COMP2                  : longWord;                   // [17:17] Complement of Channel (n) for n = 4
  DECAPEN2               : longWord;                   // [18:18] Dual Edge Capture Mode Enable for n = 4
  DECAP2                 : longWord;                   // [19:19] Dual Edge Capture Mode Captures for n = 4
  DTEN2                  : longWord;                   // [20:20] Deadtime Enable for n = 4
  SYNCEN2                : longWord;                   // [21:21] Synchronization Enable for n = 4
  FAULTEN2               : longWord;                   // [22:22] Fault Control Enable for n = 4
  RESERVED2              : longWord;                   // [23:23] no description available
  COMBINE3               : longWord;                   // [24:24] Combine Channels for n = 6
  COMP3                  : longWord;                   // [25:25] Complement of Channel (n) for n = 6
  DECAPEN3               : longWord;                   // [26:26] Dual Edge Capture Mode Enable for n = 6
  DECAP3                 : longWord;                   // [27:27] Dual Edge Capture Mode Captures for n = 6
  DTEN3                  : longWord;                   // [28:28] Deadtime Enable for n = 6
  SYNCEN3                : longWord;                   // [29:29] Synchronization Enable for n = 6
  FAULTEN3               : longWord;                   // [30:30] Fault Control Enable for n = 6
  RESERVED3              : longWord;                   // [31:31] no description available
end;

TFTM0_DEADTIME_bits = bitpacked record
  DTVAL                  : TBits_6;                    // [0:5] Deadtime Value
  DTPS                   : TBits_2;                    // [6:7] Deadtime Prescaler Value
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM0_DEADTIME_bitbanded = record
  DTVAL                  : array[0..5] of longWord;    // [0:5] Deadtime Value
  DTPS                   : array[0..1] of longWord;    // [6:7] Deadtime Prescaler Value
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM0_EXTTRIG_bits = bitpacked record
  CH2TRIG                : TBits_1;                    // [0:0] Channel 2 Trigger Enable
  CH3TRIG                : TBits_1;                    // [1:1] Channel 3 Trigger Enable
  CH4TRIG                : TBits_1;                    // [2:2] Channel 4 Trigger Enable
  CH5TRIG                : TBits_1;                    // [3:3] Channel 5 Trigger Enable
  CH0TRIG                : TBits_1;                    // [4:4] Channel 0 Trigger Enable
  CH1TRIG                : TBits_1;                    // [5:5] Channel 1 Trigger Enable
  INITTRIGEN             : TBits_1;                    // [6:6] Initialization Trigger Enable
  TRIGF                  : TBits_1;                    // [7:7] Channel Trigger Flag
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM0_EXTTRIG_bitbanded = record
  CH2TRIG                : longWord;                   // [0:0] Channel 2 Trigger Enable
  CH3TRIG                : longWord;                   // [1:1] Channel 3 Trigger Enable
  CH4TRIG                : longWord;                   // [2:2] Channel 4 Trigger Enable
  CH5TRIG                : longWord;                   // [3:3] Channel 5 Trigger Enable
  CH0TRIG                : longWord;                   // [4:4] Channel 0 Trigger Enable
  CH1TRIG                : longWord;                   // [5:5] Channel 1 Trigger Enable
  INITTRIGEN             : longWord;                   // [6:6] Initialization Trigger Enable
  TRIGF                  : longWord;                   // [7:7] Channel Trigger Flag
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM0_POL_bits = bitpacked record
  POL0                   : TBits_1;                    // [0:0] Channel 0 Polarity
  POL1                   : TBits_1;                    // [1:1] Channel 1 Polarity
  POL2                   : TBits_1;                    // [2:2] Channel 2 Polarity
  POL3                   : TBits_1;                    // [3:3] Channel 3 Polarity
  POL4                   : TBits_1;                    // [4:4] Channel 4 Polarity
  POL5                   : TBits_1;                    // [5:5] Channel 5 Polarity
  POL6                   : TBits_1;                    // [6:6] Channel 6 Polarity
  POL7                   : TBits_1;                    // [7:7] Channel 7 Polarity
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM0_POL_bitbanded = record
  POL0                   : longWord;                   // [0:0] Channel 0 Polarity
  POL1                   : longWord;                   // [1:1] Channel 1 Polarity
  POL2                   : longWord;                   // [2:2] Channel 2 Polarity
  POL3                   : longWord;                   // [3:3] Channel 3 Polarity
  POL4                   : longWord;                   // [4:4] Channel 4 Polarity
  POL5                   : longWord;                   // [5:5] Channel 5 Polarity
  POL6                   : longWord;                   // [6:6] Channel 6 Polarity
  POL7                   : longWord;                   // [7:7] Channel 7 Polarity
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM0_FMS_bits = bitpacked record
  FAULTF0                : TBits_1;                    // [0:0] Fault Detection Flag 0
  FAULTF1                : TBits_1;                    // [1:1] Fault Detection Flag 1
  FAULTF2                : TBits_1;                    // [2:2] Fault Detection Flag 2
  FAULTF3                : TBits_1;                    // [3:3] Fault Detection Flag 3
  RESERVED0              : TBits_1;                    // [4:4] no description available
  FAULTIN                : TBits_1;                    // [5:5] Fault Inputs
  WPEN                   : TBits_1;                    // [6:6] Write Protection Enable
  FAULTF                 : TBits_1;                    // [7:7] Fault Detection Flag
  RESERVED1              : TBits_24;                   // [8:31] no description available
end;

TFTM0_FMS_bitbanded = record
  FAULTF0                : longWord;                   // [0:0] Fault Detection Flag 0
  FAULTF1                : longWord;                   // [1:1] Fault Detection Flag 1
  FAULTF2                : longWord;                   // [2:2] Fault Detection Flag 2
  FAULTF3                : longWord;                   // [3:3] Fault Detection Flag 3
  RESERVED0              : longWord;                   // [4:4] no description available
  FAULTIN                : longWord;                   // [5:5] Fault Inputs
  WPEN                   : longWord;                   // [6:6] Write Protection Enable
  FAULTF                 : longWord;                   // [7:7] Fault Detection Flag
  RESERVED1              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM0_FILTER_bits = bitpacked record
  CH0FVAL                : TBits_4;                    // [0:3] Channel 0 Input Filter
  CH1FVAL                : TBits_4;                    // [4:7] Channel 1 Input Filter
  CH2FVAL                : TBits_4;                    // [8:11] Channel 2 Input Filter
  CH3FVAL                : TBits_4;                    // [12:15] Channel 3 Input Filter
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM0_FILTER_bitbanded = record
  CH0FVAL                : array[0..3] of longWord;    // [0:3] Channel 0 Input Filter
  CH1FVAL                : array[0..3] of longWord;    // [4:7] Channel 1 Input Filter
  CH2FVAL                : array[0..3] of longWord;    // [8:11] Channel 2 Input Filter
  CH3FVAL                : array[0..3] of longWord;    // [12:15] Channel 3 Input Filter
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM0_FLTCTRL_bits = bitpacked record
  FAULT0EN               : TBits_1;                    // [0:0] Fault Input 0 Enable
  FAULT1EN               : TBits_1;                    // [1:1] Fault Input 1 Enable
  FAULT2EN               : TBits_1;                    // [2:2] Fault Input 2 Enable
  FAULT3EN               : TBits_1;                    // [3:3] Fault Input 3 Enable
  FFLTR0EN               : TBits_1;                    // [4:4] Fault Input 0 Filter Enable
  FFLTR1EN               : TBits_1;                    // [5:5] Fault Input 1 Filter Enable
  FFLTR2EN               : TBits_1;                    // [6:6] Fault Input 2 Filter Enable
  FFLTR3EN               : TBits_1;                    // [7:7] Fault Input 3 Filter Enable
  FFVAL                  : TBits_4;                    // [8:11] Fault Input Filter
  RESERVED0              : TBits_20;                   // [12:31] no description available
end;

TFTM0_FLTCTRL_bitbanded = record
  FAULT0EN               : longWord;                   // [0:0] Fault Input 0 Enable
  FAULT1EN               : longWord;                   // [1:1] Fault Input 1 Enable
  FAULT2EN               : longWord;                   // [2:2] Fault Input 2 Enable
  FAULT3EN               : longWord;                   // [3:3] Fault Input 3 Enable
  FFLTR0EN               : longWord;                   // [4:4] Fault Input 0 Filter Enable
  FFLTR1EN               : longWord;                   // [5:5] Fault Input 1 Filter Enable
  FFLTR2EN               : longWord;                   // [6:6] Fault Input 2 Filter Enable
  FFLTR3EN               : longWord;                   // [7:7] Fault Input 3 Filter Enable
  FFVAL                  : array[0..3] of longWord;    // [8:11] Fault Input Filter
  RESERVED0              : array[0..19] of longWord;   // [12:31] no description available
end;

TFTM0_QDCTRL_bits = bitpacked record
  QUADEN                 : TBits_1;                    // [0:0] Quadrature Decoder Mode Enable
  TOFDIR                 : TBits_1;                    // [1:1] Timer Overflow Direction in Quadrature Decoder Mode
  QUADIR                 : TBits_1;                    // [2:2] FTM Counter Direction in Quadrature Decoder Mode
  QUADMODE               : TBits_1;                    // [3:3] Quadrature Decoder Mode
  PHBPOL                 : TBits_1;                    // [4:4] Phase B Input Polarity
  PHAPOL                 : TBits_1;                    // [5:5] Phase A Input Polarity
  PHBFLTREN              : TBits_1;                    // [6:6] Phase B Input Filter Enable
  PHAFLTREN              : TBits_1;                    // [7:7] Phase A Input Filter Enable
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM0_QDCTRL_bitbanded = record
  QUADEN                 : longWord;                   // [0:0] Quadrature Decoder Mode Enable
  TOFDIR                 : longWord;                   // [1:1] Timer Overflow Direction in Quadrature Decoder Mode
  QUADIR                 : longWord;                   // [2:2] FTM Counter Direction in Quadrature Decoder Mode
  QUADMODE               : longWord;                   // [3:3] Quadrature Decoder Mode
  PHBPOL                 : longWord;                   // [4:4] Phase B Input Polarity
  PHAPOL                 : longWord;                   // [5:5] Phase A Input Polarity
  PHBFLTREN              : longWord;                   // [6:6] Phase B Input Filter Enable
  PHAFLTREN              : longWord;                   // [7:7] Phase A Input Filter Enable
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM0_CONF_bits = bitpacked record
  NUMTOF                 : TBits_5;                    // [0:4] TOF Frequency
  RESERVED0              : TBits_1;                    // [5:5] no description available
  BDMMODE                : TBits_2;                    // [6:7] BDM Mode
  RESERVED1              : TBits_1;                    // [8:8] no description available
  GTBEEN                 : TBits_1;                    // [9:9] Global time base enable
  GTBEOUT                : TBits_1;                    // [10:10] Global time base output
  RESERVED2              : TBits_21;                   // [11:31] no description available
end;

TFTM0_CONF_bitbanded = record
  NUMTOF                 : array[0..4] of longWord;    // [0:4] TOF Frequency
  RESERVED0              : longWord;                   // [5:5] no description available
  BDMMODE                : array[0..1] of longWord;    // [6:7] BDM Mode
  RESERVED1              : longWord;                   // [8:8] no description available
  GTBEEN                 : longWord;                   // [9:9] Global time base enable
  GTBEOUT                : longWord;                   // [10:10] Global time base output
  RESERVED2              : array[0..20] of longWord;   // [11:31] no description available
end;

TFTM0_FLTPOL_bits = bitpacked record
  FLT0POL                : TBits_1;                    // [0:0] Fault Input 0 Polarity
  FLT1POL                : TBits_1;                    // [1:1] Fault Input 1 Polarity
  FLT2POL                : TBits_1;                    // [2:2] Fault Input 2 Polarity
  FLT3POL                : TBits_1;                    // [3:3] Fault Input 3 Polarity
  RESERVED0              : TBits_28;                   // [4:31] no description available
end;

TFTM0_FLTPOL_bitbanded = record
  FLT0POL                : longWord;                   // [0:0] Fault Input 0 Polarity
  FLT1POL                : longWord;                   // [1:1] Fault Input 1 Polarity
  FLT2POL                : longWord;                   // [2:2] Fault Input 2 Polarity
  FLT3POL                : longWord;                   // [3:3] Fault Input 3 Polarity
  RESERVED0              : array[0..27] of longWord;   // [4:31] no description available
end;

TFTM0_SYNCONF_bits = bitpacked record
  HWTRIGMODE             : TBits_1;                    // [0:0] Hardware Trigger Mode
  RESERVED0              : TBits_1;                    // [1:1] no description available
  CNTINC                 : TBits_1;                    // [2:2] CNTIN register synchronization
  RESERVED1              : TBits_1;                    // [3:3] no description available
  INVC                   : TBits_1;                    // [4:4] INVCTRL register synchronization
  SWOC                   : TBits_1;                    // [5:5] SWOCTRL register synchronization
  RESERVED2              : TBits_1;                    // [6:6] no description available
  SYNCMODE               : TBits_1;                    // [7:7] Synchronization Mode
  SWRSTCNT               : TBits_1;                    // [8:8] no description available
  SWWRBUF                : TBits_1;                    // [9:9] no description available
  SWOM                   : TBits_1;                    // [10:10] no description available
  SWINVC                 : TBits_1;                    // [11:11] no description available
  SWSOC                  : TBits_1;                    // [12:12] no description available
  RESERVED3              : TBits_3;                    // [13:15] no description available
  HWRSTCNT               : TBits_1;                    // [16:16] no description available
  HWWRBUF                : TBits_1;                    // [17:17] no description available
  HWOM                   : TBits_1;                    // [18:18] no description available
  HWINVC                 : TBits_1;                    // [19:19] no description available
  HWSOC                  : TBits_1;                    // [20:20] no description available
  RESERVED4              : TBits_11;                   // [21:31] no description available
end;

TFTM0_SYNCONF_bitbanded = record
  HWTRIGMODE             : longWord;                   // [0:0] Hardware Trigger Mode
  RESERVED0              : longWord;                   // [1:1] no description available
  CNTINC                 : longWord;                   // [2:2] CNTIN register synchronization
  RESERVED1              : longWord;                   // [3:3] no description available
  INVC                   : longWord;                   // [4:4] INVCTRL register synchronization
  SWOC                   : longWord;                   // [5:5] SWOCTRL register synchronization
  RESERVED2              : longWord;                   // [6:6] no description available
  SYNCMODE               : longWord;                   // [7:7] Synchronization Mode
  SWRSTCNT               : longWord;                   // [8:8] no description available
  SWWRBUF                : longWord;                   // [9:9] no description available
  SWOM                   : longWord;                   // [10:10] no description available
  SWINVC                 : longWord;                   // [11:11] no description available
  SWSOC                  : longWord;                   // [12:12] no description available
  RESERVED3              : array[0..2] of longWord;    // [13:15] no description available
  HWRSTCNT               : longWord;                   // [16:16] no description available
  HWWRBUF                : longWord;                   // [17:17] no description available
  HWOM                   : longWord;                   // [18:18] no description available
  HWINVC                 : longWord;                   // [19:19] no description available
  HWSOC                  : longWord;                   // [20:20] no description available
  RESERVED4              : array[0..10] of longWord;   // [21:31] no description available
end;

TFTM0_INVCTRL_bits = bitpacked record
  INV0EN                 : TBits_1;                    // [0:0] Pair Channels 0 Inverting Enable
  INV1EN                 : TBits_1;                    // [1:1] Pair Channels 1 Inverting Enable
  INV2EN                 : TBits_1;                    // [2:2] Pair Channels 2 Inverting Enable
  INV3EN                 : TBits_1;                    // [3:3] Pair Channels 3 Inverting Enable
  RESERVED0              : TBits_28;                   // [4:31] no description available
end;

TFTM0_INVCTRL_bitbanded = record
  INV0EN                 : longWord;                   // [0:0] Pair Channels 0 Inverting Enable
  INV1EN                 : longWord;                   // [1:1] Pair Channels 1 Inverting Enable
  INV2EN                 : longWord;                   // [2:2] Pair Channels 2 Inverting Enable
  INV3EN                 : longWord;                   // [3:3] Pair Channels 3 Inverting Enable
  RESERVED0              : array[0..27] of longWord;   // [4:31] no description available
end;

TFTM0_SWOCTRL_bits = bitpacked record
  CH0OC                  : TBits_1;                    // [0:0] Channel 0 Software Output Control Enable
  CH1OC                  : TBits_1;                    // [1:1] Channel 1 Software Output Control Enable
  CH2OC                  : TBits_1;                    // [2:2] Channel 2 Software Output Control Enable
  CH3OC                  : TBits_1;                    // [3:3] Channel 3 Software Output Control Enable
  CH4OC                  : TBits_1;                    // [4:4] Channel 4 Software Output Control Enable
  CH5OC                  : TBits_1;                    // [5:5] Channel 5 Software Output Control Enable
  CH6OC                  : TBits_1;                    // [6:6] Channel 6 Software Output Control Enable
  CH7OC                  : TBits_1;                    // [7:7] Channel 7 Software Output Control Enable
  CH0OCV                 : TBits_1;                    // [8:8] Channel 0 Software Output Control Value
  CH1OCV                 : TBits_1;                    // [9:9] Channel 1 Software Output Control Value
  CH2OCV                 : TBits_1;                    // [10:10] Channel 2 Software Output Control Value
  CH3OCV                 : TBits_1;                    // [11:11] Channel 3 Software Output Control Value
  CH4OCV                 : TBits_1;                    // [12:12] Channel 4 Software Output Control Value
  CH5OCV                 : TBits_1;                    // [13:13] Channel 5 Software Output Control Value
  CH6OCV                 : TBits_1;                    // [14:14] Channel 6 Software Output Control Value
  CH7OCV                 : TBits_1;                    // [15:15] Channel 7 Software Output Control Value
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM0_SWOCTRL_bitbanded = record
  CH0OC                  : longWord;                   // [0:0] Channel 0 Software Output Control Enable
  CH1OC                  : longWord;                   // [1:1] Channel 1 Software Output Control Enable
  CH2OC                  : longWord;                   // [2:2] Channel 2 Software Output Control Enable
  CH3OC                  : longWord;                   // [3:3] Channel 3 Software Output Control Enable
  CH4OC                  : longWord;                   // [4:4] Channel 4 Software Output Control Enable
  CH5OC                  : longWord;                   // [5:5] Channel 5 Software Output Control Enable
  CH6OC                  : longWord;                   // [6:6] Channel 6 Software Output Control Enable
  CH7OC                  : longWord;                   // [7:7] Channel 7 Software Output Control Enable
  CH0OCV                 : longWord;                   // [8:8] Channel 0 Software Output Control Value
  CH1OCV                 : longWord;                   // [9:9] Channel 1 Software Output Control Value
  CH2OCV                 : longWord;                   // [10:10] Channel 2 Software Output Control Value
  CH3OCV                 : longWord;                   // [11:11] Channel 3 Software Output Control Value
  CH4OCV                 : longWord;                   // [12:12] Channel 4 Software Output Control Value
  CH5OCV                 : longWord;                   // [13:13] Channel 5 Software Output Control Value
  CH6OCV                 : longWord;                   // [14:14] Channel 6 Software Output Control Value
  CH7OCV                 : longWord;                   // [15:15] Channel 7 Software Output Control Value
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM0_PWMLOAD_bits = bitpacked record
  CH0SEL                 : TBits_1;                    // [0:0] Channel 0 Select
  CH1SEL                 : TBits_1;                    // [1:1] Channel 1 Select
  CH2SEL                 : TBits_1;                    // [2:2] Channel 2 Select
  CH3SEL                 : TBits_1;                    // [3:3] Channel 3 Select
  CH4SEL                 : TBits_1;                    // [4:4] Channel 4 Select
  CH5SEL                 : TBits_1;                    // [5:5] Channel 5 Select
  CH6SEL                 : TBits_1;                    // [6:6] Channel 6 Select
  CH7SEL                 : TBits_1;                    // [7:7] Channel 7 Select
  RESERVED0              : TBits_1;                    // [8:8] no description available
  LDOK                   : TBits_1;                    // [9:9] Load Enable
  RESERVED1              : TBits_22;                   // [10:31] no description available
end;

TFTM0_PWMLOAD_bitbanded = record
  CH0SEL                 : longWord;                   // [0:0] Channel 0 Select
  CH1SEL                 : longWord;                   // [1:1] Channel 1 Select
  CH2SEL                 : longWord;                   // [2:2] Channel 2 Select
  CH3SEL                 : longWord;                   // [3:3] Channel 3 Select
  CH4SEL                 : longWord;                   // [4:4] Channel 4 Select
  CH5SEL                 : longWord;                   // [5:5] Channel 5 Select
  CH6SEL                 : longWord;                   // [6:6] Channel 6 Select
  CH7SEL                 : longWord;                   // [7:7] Channel 7 Select
  RESERVED0              : longWord;                   // [8:8] no description available
  LDOK                   : longWord;                   // [9:9] Load Enable
  RESERVED1              : array[0..21] of longWord;   // [10:31] no description available
end;

TFTM0_Registers = record
  case boolean of false: (
  SC                     : longWord;                   // 0x00 Status and Control
  CNT                    : longWord;                   // 0x04 Counter
  &MOD                   : longWord;                   // 0x08 Modulo
  C0SC                   : longWord;                   // 0x0C Channel (n) Status and Control
  C0V                    : longWord;                   // 0x10 Channel (n) Value
  C1SC                   : longWord;                   // 0x14 Channel (n) Status and Control
  C1V                    : longWord;                   // 0x18 Channel (n) Value
  C2SC                   : longWord;                   // 0x1C Channel (n) Status and Control
  C2V                    : longWord;                   // 0x20 Channel (n) Value
  C3SC                   : longWord;                   // 0x24 Channel (n) Status and Control
  C3V                    : longWord;                   // 0x28 Channel (n) Value
  C4SC                   : longWord;                   // 0x2C Channel (n) Status and Control
  C4V                    : longWord;                   // 0x30 Channel (n) Value
  C5SC                   : longWord;                   // 0x34 Channel (n) Status and Control
  C5V                    : longWord;                   // 0x38 Channel (n) Value
  C6SC                   : longWord;                   // 0x3C Channel (n) Status and Control
  C6V                    : longWord;                   // 0x40 Channel (n) Value
  C7SC                   : longWord;                   // 0x44 Channel (n) Status and Control
  C7V                    : longWord;                   // 0x48 Channel (n) Value
  CNTIN                  : longWord;                   // 0x4C Counter Initial Value
  STATUS                 : longWord;                   // 0x50 Capture and Compare Status
  MODE                   : longWord;                   // 0x54 Features Mode Selection
  SYNC                   : longWord;                   // 0x58 Synchronization
  OUTINIT                : longWord;                   // 0x5C Initial State for Channels Output
  OUTMASK                : longWord;                   // 0x60 Output Mask
  COMBINE                : longWord;                   // 0x64 Function for Linked Channels
  DEADTIME               : longWord;                   // 0x68 Deadtime Insertion Control
  EXTTRIG                : longWord;                   // 0x6C FTM External Trigger
  POL                    : longWord;                   // 0x70 Channels Polarity
  FMS                    : longWord;                   // 0x74 Fault Mode Status
  FILTER                 : longWord;                   // 0x78 Input Capture Filter Control
  FLTCTRL                : longWord;                   // 0x7C Fault Control
  QDCTRL                 : longWord;                   // 0x80 Quadrature Decoder Control and Status
  CONF                   : longWord;                   // 0x84 Configuration
  FLTPOL                 : longWord;                   // 0x88 FTM Fault Input Polarity
  SYNCONF                : longWord;                   // 0x8C Synchronization Configuration
  INVCTRL                : longWord;                   // 0x90 FTM Inverting Control
  SWOCTRL                : longWord;                   // 0x94 FTM Software Output Control
  PWMLOAD                : longWord;                   // 0x98 FTM PWM Load
);
true : (
SC_bits                  : TFTM0_SC_bits;              // 0x04 Status and Control
CNT_bits                 : TFTM0_CNT_bits;             // 0x08 Counter
MOD_bits                 : TFTM0_MOD_bits;             // 0x0C Modulo
C0SC_bits                : longWord;                   // 0x0C Channel (n) Status and Control
C0V_bits                 : longWord;                   // 0x10 Channel (n) Value
C1SC_bits                : longWord;                   // 0x14 Channel (n) Status and Control
C1V_bits                 : longWord;                   // 0x18 Channel (n) Value
C2SC_bits                : longWord;                   // 0x1C Channel (n) Status and Control
C2V_bits                 : longWord;                   // 0x20 Channel (n) Value
C3SC_bits                : longWord;                   // 0x24 Channel (n) Status and Control
C3V_bits                 : longWord;                   // 0x28 Channel (n) Value
C4SC_bits                : longWord;                   // 0x2C Channel (n) Status and Control
C4V_bits                 : longWord;                   // 0x30 Channel (n) Value
C5SC_bits                : longWord;                   // 0x34 Channel (n) Status and Control
C5V_bits                 : longWord;                   // 0x38 Channel (n) Value
C6SC_bits                : longWord;                   // 0x3C Channel (n) Status and Control
C6V_bits                 : longWord;                   // 0x40 Channel (n) Value
C7SC_bits                : longWord;                   // 0x44 Channel (n) Status and Control
C7V_bits                 : longWord;                   // 0x48 Channel (n) Value
CNTIN_bits               : TFTM0_CNTIN_bits;           // 0x50 Counter Initial Value
STATUS_bits              : TFTM0_STATUS_bits;          // 0x54 Capture and Compare Status
MODE_bits                : TFTM0_MODE_bits;            // 0x58 Features Mode Selection
SYNC_bits                : TFTM0_SYNC_bits;            // 0x5C Synchronization
OUTINIT_bits             : TFTM0_OUTINIT_bits;         // 0x60 Initial State for Channels Output
OUTMASK_bits             : TFTM0_OUTMASK_bits;         // 0x64 Output Mask
COMBINE_bits             : TFTM0_COMBINE_bits;         // 0x68 Function for Linked Channels
DEADTIME_bits            : TFTM0_DEADTIME_bits;        // 0x6C Deadtime Insertion Control
EXTTRIG_bits             : TFTM0_EXTTRIG_bits;         // 0x70 FTM External Trigger
POL_bits                 : TFTM0_POL_bits;             // 0x74 Channels Polarity
FMS_bits                 : TFTM0_FMS_bits;             // 0x78 Fault Mode Status
FILTER_bits              : TFTM0_FILTER_bits;          // 0x7C Input Capture Filter Control
FLTCTRL_bits             : TFTM0_FLTCTRL_bits;         // 0x80 Fault Control
QDCTRL_bits              : TFTM0_QDCTRL_bits;          // 0x84 Quadrature Decoder Control and Status
CONF_bits                : TFTM0_CONF_bits;            // 0x88 Configuration
FLTPOL_bits              : TFTM0_FLTPOL_bits;          // 0x8C FTM Fault Input Polarity
SYNCONF_bits             : TFTM0_SYNCONF_bits;         // 0x90 Synchronization Configuration
INVCTRL_bits             : TFTM0_INVCTRL_bits;         // 0x94 FTM Inverting Control
SWOCTRL_bits             : TFTM0_SWOCTRL_bits;         // 0x98 FTM Software Output Control
PWMLOAD_bits             : TFTM0_PWMLOAD_bits;         // 0x9C FTM PWM Load
);
end;

TFTM0Registers_bitbanded = record
  SC                     : TFTM0_SC_bitbanded;         // 0x04 Status and Control
  CNT                    : TFTM0_CNT_bitbanded;        // 0x08 Counter
  &MOD                   : TFTM0_MOD_bitbanded;        // 0x0C Modulo
  C0SC_bitbanded         : longWord;                   // 0x0C Channel (n) Status and Control
  C0V_bitbanded          : longWord;                   // 0x10 Channel (n) Value
  C1SC_bitbanded         : longWord;                   // 0x14 Channel (n) Status and Control
  C1V_bitbanded          : longWord;                   // 0x18 Channel (n) Value
  C2SC_bitbanded         : longWord;                   // 0x1C Channel (n) Status and Control
  C2V_bitbanded          : longWord;                   // 0x20 Channel (n) Value
  C3SC_bitbanded         : longWord;                   // 0x24 Channel (n) Status and Control
  C3V_bitbanded          : longWord;                   // 0x28 Channel (n) Value
  C4SC_bitbanded         : longWord;                   // 0x2C Channel (n) Status and Control
  C4V_bitbanded          : longWord;                   // 0x30 Channel (n) Value
  C5SC_bitbanded         : longWord;                   // 0x34 Channel (n) Status and Control
  C5V_bitbanded          : longWord;                   // 0x38 Channel (n) Value
  C6SC_bitbanded         : longWord;                   // 0x3C Channel (n) Status and Control
  C6V_bitbanded          : longWord;                   // 0x40 Channel (n) Value
  C7SC_bitbanded         : longWord;                   // 0x44 Channel (n) Status and Control
  C7V_bitbanded          : longWord;                   // 0x48 Channel (n) Value
  CNTIN                  : TFTM0_CNTIN_bitbanded;      // 0x50 Counter Initial Value
  STATUS                 : TFTM0_STATUS_bitbanded;     // 0x54 Capture and Compare Status
  MODE                   : TFTM0_MODE_bitbanded;       // 0x58 Features Mode Selection
  SYNC                   : TFTM0_SYNC_bitbanded;       // 0x5C Synchronization
  OUTINIT                : TFTM0_OUTINIT_bitbanded;    // 0x60 Initial State for Channels Output
  OUTMASK                : TFTM0_OUTMASK_bitbanded;    // 0x64 Output Mask
  COMBINE                : TFTM0_COMBINE_bitbanded;    // 0x68 Function for Linked Channels
  DEADTIME               : TFTM0_DEADTIME_bitbanded;   // 0x6C Deadtime Insertion Control
  EXTTRIG                : TFTM0_EXTTRIG_bitbanded;    // 0x70 FTM External Trigger
  POL                    : TFTM0_POL_bitbanded;        // 0x74 Channels Polarity
  FMS                    : TFTM0_FMS_bitbanded;        // 0x78 Fault Mode Status
  FILTER                 : TFTM0_FILTER_bitbanded;     // 0x7C Input Capture Filter Control
  FLTCTRL                : TFTM0_FLTCTRL_bitbanded;    // 0x80 Fault Control
  QDCTRL                 : TFTM0_QDCTRL_bitbanded;     // 0x84 Quadrature Decoder Control and Status
  CONF                   : TFTM0_CONF_bitbanded;       // 0x88 Configuration
  FLTPOL                 : TFTM0_FLTPOL_bitbanded;     // 0x8C FTM Fault Input Polarity
  SYNCONF                : TFTM0_SYNCONF_bitbanded;    // 0x90 Synchronization Configuration
  INVCTRL                : TFTM0_INVCTRL_bitbanded;    // 0x94 FTM Inverting Control
  SWOCTRL                : TFTM0_SWOCTRL_bitbanded;    // 0x98 FTM Software Output Control
  PWMLOAD                : TFTM0_PWMLOAD_bitbanded;    // 0x9C FTM PWM Load
end;

// FlexTimer Module
TFTM1_SC_bits = bitpacked record
  PS                     : TBits_3;                    // [0:2] Prescale Factor Selection
  CLKS                   : TBits_2;                    // [3:4] Clock Source Selection
  CPWMS                  : TBits_1;                    // [5:5] Center-aligned PWM Select
  TOIE                   : TBits_1;                    // [6:6] Timer Overflow Interrupt Enable
  TOF                    : TBits_1;                    // [7:7] Timer Overflow Flag
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM1_SC_bitbanded = record
  PS                     : array[0..2] of longWord;    // [0:2] Prescale Factor Selection
  CLKS                   : array[0..1] of longWord;    // [3:4] Clock Source Selection
  CPWMS                  : longWord;                   // [5:5] Center-aligned PWM Select
  TOIE                   : longWord;                   // [6:6] Timer Overflow Interrupt Enable
  TOF                    : longWord;                   // [7:7] Timer Overflow Flag
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM1_CNT_bits = bitpacked record
  COUNT                  : TBits_16;                   // [0:15] Counter value
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM1_CNT_bitbanded = record
  COUNT                  : array[0..15] of longWord;   // [0:15] Counter value
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM1_MOD_bits = bitpacked record
  &MOD                   : TBits_16;                   // [0:15] no description available
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM1_MOD_bitbanded = record
  &MOD                   : array[0..15] of longWord;   // [0:15] no description available
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM1_CSC_bits = bitpacked record
  DMA                    : TBits_1;                    // [0:0] DMA Enable
  RESERVED0              : TBits_1;                    // [1:1] no description available
  ELSA                   : TBits_1;                    // [2:2] Edge or Level Select
  ELSB                   : TBits_1;                    // [3:3] Edge or Level Select
  MSA                    : TBits_1;                    // [4:4] Channel Mode Select
  MSB                    : TBits_1;                    // [5:5] Channel Mode Select
  CHIE                   : TBits_1;                    // [6:6] Channel Interrupt Enable
  CHF                    : TBits_1;                    // [7:7] Channel Flag
  RESERVED1              : TBits_24;                   // [8:31] no description available
end;

TFTM1_CSC_bitbanded = record
  DMA                    : longWord;                   // [0:0] DMA Enable
  RESERVED0              : longWord;                   // [1:1] no description available
  ELSA                   : longWord;                   // [2:2] Edge or Level Select
  ELSB                   : longWord;                   // [3:3] Edge or Level Select
  MSA                    : longWord;                   // [4:4] Channel Mode Select
  MSB                    : longWord;                   // [5:5] Channel Mode Select
  CHIE                   : longWord;                   // [6:6] Channel Interrupt Enable
  CHF                    : longWord;                   // [7:7] Channel Flag
  RESERVED1              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM1_CV_bits = bitpacked record
  VAL                    : TBits_16;                   // [0:15] Channel Value
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM1_CV_bitbanded = record
  VAL                    : array[0..15] of longWord;   // [0:15] Channel Value
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM1_CNTIN_bits = bitpacked record
  INIT                   : TBits_16;                   // [0:15] no description available
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM1_CNTIN_bitbanded = record
  INIT                   : array[0..15] of longWord;   // [0:15] no description available
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM1_STATUS_bits = bitpacked record
  CH0F                   : TBits_1;                    // [0:0] Channel 0 Flag
  CH1F                   : TBits_1;                    // [1:1] Channel 1 Flag
  CH2F                   : TBits_1;                    // [2:2] Channel 2 Flag
  CH3F                   : TBits_1;                    // [3:3] Channel 3 Flag
  CH4F                   : TBits_1;                    // [4:4] Channel 4 Flag
  CH5F                   : TBits_1;                    // [5:5] Channel 5 Flag
  CH6F                   : TBits_1;                    // [6:6] Channel 6 Flag
  CH7F                   : TBits_1;                    // [7:7] Channel 7 Flag
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM1_STATUS_bitbanded = record
  CH0F                   : longWord;                   // [0:0] Channel 0 Flag
  CH1F                   : longWord;                   // [1:1] Channel 1 Flag
  CH2F                   : longWord;                   // [2:2] Channel 2 Flag
  CH3F                   : longWord;                   // [3:3] Channel 3 Flag
  CH4F                   : longWord;                   // [4:4] Channel 4 Flag
  CH5F                   : longWord;                   // [5:5] Channel 5 Flag
  CH6F                   : longWord;                   // [6:6] Channel 6 Flag
  CH7F                   : longWord;                   // [7:7] Channel 7 Flag
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM1_MODE_bits = bitpacked record
  FTMEN                  : TBits_1;                    // [0:0] FTM Enable
  INIT                   : TBits_1;                    // [1:1] Initialize the Channels Output
  WPDIS                  : TBits_1;                    // [2:2] Write Protection Disable
  PWMSYNC                : TBits_1;                    // [3:3] PWM Synchronization Mode
  CAPTEST                : TBits_1;                    // [4:4] Capture Test Mode Enable
  FAULTM                 : TBits_2;                    // [5:6] Fault Control Mode
  FAULTIE                : TBits_1;                    // [7:7] Fault Interrupt Enable
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM1_MODE_bitbanded = record
  FTMEN                  : longWord;                   // [0:0] FTM Enable
  INIT                   : longWord;                   // [1:1] Initialize the Channels Output
  WPDIS                  : longWord;                   // [2:2] Write Protection Disable
  PWMSYNC                : longWord;                   // [3:3] PWM Synchronization Mode
  CAPTEST                : longWord;                   // [4:4] Capture Test Mode Enable
  FAULTM                 : array[0..1] of longWord;    // [5:6] Fault Control Mode
  FAULTIE                : longWord;                   // [7:7] Fault Interrupt Enable
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM1_SYNC_bits = bitpacked record
  CNTMIN                 : TBits_1;                    // [0:0] Minimum loading point enable
  CNTMAX                 : TBits_1;                    // [1:1] Maximum loading point enable
  REINIT                 : TBits_1;                    // [2:2] FTM Counter Reinitialization by Synchronization (FTM Counter Synchronization)
  SYNCHOM                : TBits_1;                    // [3:3] Output Mask Synchronization
  TRIG0                  : TBits_1;                    // [4:4] PWM Synchronization Hardware Trigger 0
  TRIG1                  : TBits_1;                    // [5:5] PWM Synchronization Hardware Trigger 1
  TRIG2                  : TBits_1;                    // [6:6] PWM Synchronization Hardware Trigger 2
  SWSYNC                 : TBits_1;                    // [7:7] PWM Synchronization Software Trigger
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM1_SYNC_bitbanded = record
  CNTMIN                 : longWord;                   // [0:0] Minimum loading point enable
  CNTMAX                 : longWord;                   // [1:1] Maximum loading point enable
  REINIT                 : longWord;                   // [2:2] FTM Counter Reinitialization by Synchronization (FTM Counter Synchronization)
  SYNCHOM                : longWord;                   // [3:3] Output Mask Synchronization
  TRIG0                  : longWord;                   // [4:4] PWM Synchronization Hardware Trigger 0
  TRIG1                  : longWord;                   // [5:5] PWM Synchronization Hardware Trigger 1
  TRIG2                  : longWord;                   // [6:6] PWM Synchronization Hardware Trigger 2
  SWSYNC                 : longWord;                   // [7:7] PWM Synchronization Software Trigger
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM1_OUTINIT_bits = bitpacked record
  CH0OI                  : TBits_1;                    // [0:0] Channel 0 Output Initialization Value
  CH1OI                  : TBits_1;                    // [1:1] Channel 1 Output Initialization Value
  CH2OI                  : TBits_1;                    // [2:2] Channel 2 Output Initialization Value
  CH3OI                  : TBits_1;                    // [3:3] Channel 3 Output Initialization Value
  CH4OI                  : TBits_1;                    // [4:4] Channel 4 Output Initialization Value
  CH5OI                  : TBits_1;                    // [5:5] Channel 5 Output Initialization Value
  CH6OI                  : TBits_1;                    // [6:6] Channel 6 Output Initialization Value
  CH7OI                  : TBits_1;                    // [7:7] Channel 7 Output Initialization Value
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM1_OUTINIT_bitbanded = record
  CH0OI                  : longWord;                   // [0:0] Channel 0 Output Initialization Value
  CH1OI                  : longWord;                   // [1:1] Channel 1 Output Initialization Value
  CH2OI                  : longWord;                   // [2:2] Channel 2 Output Initialization Value
  CH3OI                  : longWord;                   // [3:3] Channel 3 Output Initialization Value
  CH4OI                  : longWord;                   // [4:4] Channel 4 Output Initialization Value
  CH5OI                  : longWord;                   // [5:5] Channel 5 Output Initialization Value
  CH6OI                  : longWord;                   // [6:6] Channel 6 Output Initialization Value
  CH7OI                  : longWord;                   // [7:7] Channel 7 Output Initialization Value
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM1_OUTMASK_bits = bitpacked record
  CH0OM                  : TBits_1;                    // [0:0] Channel 0 Output Mask
  CH1OM                  : TBits_1;                    // [1:1] Channel 1 Output Mask
  CH2OM                  : TBits_1;                    // [2:2] Channel 2 Output Mask
  CH3OM                  : TBits_1;                    // [3:3] Channel 3 Output Mask
  CH4OM                  : TBits_1;                    // [4:4] Channel 4 Output Mask
  CH5OM                  : TBits_1;                    // [5:5] Channel 5 Output Mask
  CH6OM                  : TBits_1;                    // [6:6] Channel 6 Output Mask
  CH7OM                  : TBits_1;                    // [7:7] Channel 7 Output Mask
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM1_OUTMASK_bitbanded = record
  CH0OM                  : longWord;                   // [0:0] Channel 0 Output Mask
  CH1OM                  : longWord;                   // [1:1] Channel 1 Output Mask
  CH2OM                  : longWord;                   // [2:2] Channel 2 Output Mask
  CH3OM                  : longWord;                   // [3:3] Channel 3 Output Mask
  CH4OM                  : longWord;                   // [4:4] Channel 4 Output Mask
  CH5OM                  : longWord;                   // [5:5] Channel 5 Output Mask
  CH6OM                  : longWord;                   // [6:6] Channel 6 Output Mask
  CH7OM                  : longWord;                   // [7:7] Channel 7 Output Mask
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM1_COMBINE_bits = bitpacked record
  COMBINE0               : TBits_1;                    // [0:0] Combine Channels for n = 0
  COMP0                  : TBits_1;                    // [1:1] Complement of Channel (n) for n = 0
  DECAPEN0               : TBits_1;                    // [2:2] Dual Edge Capture Mode Enable for n = 0
  DECAP0                 : TBits_1;                    // [3:3] Dual Edge Capture Mode Captures for n = 0
  DTEN0                  : TBits_1;                    // [4:4] Deadtime Enable for n = 0
  SYNCEN0                : TBits_1;                    // [5:5] Synchronization Enable for n = 0
  FAULTEN0               : TBits_1;                    // [6:6] Fault Control Enable for n = 0
  RESERVED0              : TBits_1;                    // [7:7] no description available
  COMBINE1               : TBits_1;                    // [8:8] Combine Channels for n = 2
  COMP1                  : TBits_1;                    // [9:9] Complement of Channel (n) for n = 2
  DECAPEN1               : TBits_1;                    // [10:10] Dual Edge Capture Mode Enable for n = 2
  DECAP1                 : TBits_1;                    // [11:11] Dual Edge Capture Mode Captures for n = 2
  DTEN1                  : TBits_1;                    // [12:12] Deadtime Enable for n = 2
  SYNCEN1                : TBits_1;                    // [13:13] Synchronization Enable for n = 2
  FAULTEN1               : TBits_1;                    // [14:14] Fault Control Enable for n = 2
  RESERVED1              : TBits_1;                    // [15:15] no description available
  COMBINE2               : TBits_1;                    // [16:16] Combine Channels for n = 4
  COMP2                  : TBits_1;                    // [17:17] Complement of Channel (n) for n = 4
  DECAPEN2               : TBits_1;                    // [18:18] Dual Edge Capture Mode Enable for n = 4
  DECAP2                 : TBits_1;                    // [19:19] Dual Edge Capture Mode Captures for n = 4
  DTEN2                  : TBits_1;                    // [20:20] Deadtime Enable for n = 4
  SYNCEN2                : TBits_1;                    // [21:21] Synchronization Enable for n = 4
  FAULTEN2               : TBits_1;                    // [22:22] Fault Control Enable for n = 4
  RESERVED2              : TBits_1;                    // [23:23] no description available
  COMBINE3               : TBits_1;                    // [24:24] Combine Channels for n = 6
  COMP3                  : TBits_1;                    // [25:25] Complement of Channel (n) for n = 6
  DECAPEN3               : TBits_1;                    // [26:26] Dual Edge Capture Mode Enable for n = 6
  DECAP3                 : TBits_1;                    // [27:27] Dual Edge Capture Mode Captures for n = 6
  DTEN3                  : TBits_1;                    // [28:28] Deadtime Enable for n = 6
  SYNCEN3                : TBits_1;                    // [29:29] Synchronization Enable for n = 6
  FAULTEN3               : TBits_1;                    // [30:30] Fault Control Enable for n = 6
  RESERVED3              : TBits_1;                    // [31:31] no description available
end;

TFTM1_COMBINE_bitbanded = record
  COMBINE0               : longWord;                   // [0:0] Combine Channels for n = 0
  COMP0                  : longWord;                   // [1:1] Complement of Channel (n) for n = 0
  DECAPEN0               : longWord;                   // [2:2] Dual Edge Capture Mode Enable for n = 0
  DECAP0                 : longWord;                   // [3:3] Dual Edge Capture Mode Captures for n = 0
  DTEN0                  : longWord;                   // [4:4] Deadtime Enable for n = 0
  SYNCEN0                : longWord;                   // [5:5] Synchronization Enable for n = 0
  FAULTEN0               : longWord;                   // [6:6] Fault Control Enable for n = 0
  RESERVED0              : longWord;                   // [7:7] no description available
  COMBINE1               : longWord;                   // [8:8] Combine Channels for n = 2
  COMP1                  : longWord;                   // [9:9] Complement of Channel (n) for n = 2
  DECAPEN1               : longWord;                   // [10:10] Dual Edge Capture Mode Enable for n = 2
  DECAP1                 : longWord;                   // [11:11] Dual Edge Capture Mode Captures for n = 2
  DTEN1                  : longWord;                   // [12:12] Deadtime Enable for n = 2
  SYNCEN1                : longWord;                   // [13:13] Synchronization Enable for n = 2
  FAULTEN1               : longWord;                   // [14:14] Fault Control Enable for n = 2
  RESERVED1              : longWord;                   // [15:15] no description available
  COMBINE2               : longWord;                   // [16:16] Combine Channels for n = 4
  COMP2                  : longWord;                   // [17:17] Complement of Channel (n) for n = 4
  DECAPEN2               : longWord;                   // [18:18] Dual Edge Capture Mode Enable for n = 4
  DECAP2                 : longWord;                   // [19:19] Dual Edge Capture Mode Captures for n = 4
  DTEN2                  : longWord;                   // [20:20] Deadtime Enable for n = 4
  SYNCEN2                : longWord;                   // [21:21] Synchronization Enable for n = 4
  FAULTEN2               : longWord;                   // [22:22] Fault Control Enable for n = 4
  RESERVED2              : longWord;                   // [23:23] no description available
  COMBINE3               : longWord;                   // [24:24] Combine Channels for n = 6
  COMP3                  : longWord;                   // [25:25] Complement of Channel (n) for n = 6
  DECAPEN3               : longWord;                   // [26:26] Dual Edge Capture Mode Enable for n = 6
  DECAP3                 : longWord;                   // [27:27] Dual Edge Capture Mode Captures for n = 6
  DTEN3                  : longWord;                   // [28:28] Deadtime Enable for n = 6
  SYNCEN3                : longWord;                   // [29:29] Synchronization Enable for n = 6
  FAULTEN3               : longWord;                   // [30:30] Fault Control Enable for n = 6
  RESERVED3              : longWord;                   // [31:31] no description available
end;

TFTM1_DEADTIME_bits = bitpacked record
  DTVAL                  : TBits_6;                    // [0:5] Deadtime Value
  DTPS                   : TBits_2;                    // [6:7] Deadtime Prescaler Value
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM1_DEADTIME_bitbanded = record
  DTVAL                  : array[0..5] of longWord;    // [0:5] Deadtime Value
  DTPS                   : array[0..1] of longWord;    // [6:7] Deadtime Prescaler Value
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM1_EXTTRIG_bits = bitpacked record
  CH2TRIG                : TBits_1;                    // [0:0] Channel 2 Trigger Enable
  CH3TRIG                : TBits_1;                    // [1:1] Channel 3 Trigger Enable
  CH4TRIG                : TBits_1;                    // [2:2] Channel 4 Trigger Enable
  CH5TRIG                : TBits_1;                    // [3:3] Channel 5 Trigger Enable
  CH0TRIG                : TBits_1;                    // [4:4] Channel 0 Trigger Enable
  CH1TRIG                : TBits_1;                    // [5:5] Channel 1 Trigger Enable
  INITTRIGEN             : TBits_1;                    // [6:6] Initialization Trigger Enable
  TRIGF                  : TBits_1;                    // [7:7] Channel Trigger Flag
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM1_EXTTRIG_bitbanded = record
  CH2TRIG                : longWord;                   // [0:0] Channel 2 Trigger Enable
  CH3TRIG                : longWord;                   // [1:1] Channel 3 Trigger Enable
  CH4TRIG                : longWord;                   // [2:2] Channel 4 Trigger Enable
  CH5TRIG                : longWord;                   // [3:3] Channel 5 Trigger Enable
  CH0TRIG                : longWord;                   // [4:4] Channel 0 Trigger Enable
  CH1TRIG                : longWord;                   // [5:5] Channel 1 Trigger Enable
  INITTRIGEN             : longWord;                   // [6:6] Initialization Trigger Enable
  TRIGF                  : longWord;                   // [7:7] Channel Trigger Flag
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM1_POL_bits = bitpacked record
  POL0                   : TBits_1;                    // [0:0] Channel 0 Polarity
  POL1                   : TBits_1;                    // [1:1] Channel 1 Polarity
  POL2                   : TBits_1;                    // [2:2] Channel 2 Polarity
  POL3                   : TBits_1;                    // [3:3] Channel 3 Polarity
  POL4                   : TBits_1;                    // [4:4] Channel 4 Polarity
  POL5                   : TBits_1;                    // [5:5] Channel 5 Polarity
  POL6                   : TBits_1;                    // [6:6] Channel 6 Polarity
  POL7                   : TBits_1;                    // [7:7] Channel 7 Polarity
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM1_POL_bitbanded = record
  POL0                   : longWord;                   // [0:0] Channel 0 Polarity
  POL1                   : longWord;                   // [1:1] Channel 1 Polarity
  POL2                   : longWord;                   // [2:2] Channel 2 Polarity
  POL3                   : longWord;                   // [3:3] Channel 3 Polarity
  POL4                   : longWord;                   // [4:4] Channel 4 Polarity
  POL5                   : longWord;                   // [5:5] Channel 5 Polarity
  POL6                   : longWord;                   // [6:6] Channel 6 Polarity
  POL7                   : longWord;                   // [7:7] Channel 7 Polarity
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM1_FMS_bits = bitpacked record
  FAULTF0                : TBits_1;                    // [0:0] Fault Detection Flag 0
  FAULTF1                : TBits_1;                    // [1:1] Fault Detection Flag 1
  FAULTF2                : TBits_1;                    // [2:2] Fault Detection Flag 2
  FAULTF3                : TBits_1;                    // [3:3] Fault Detection Flag 3
  RESERVED0              : TBits_1;                    // [4:4] no description available
  FAULTIN                : TBits_1;                    // [5:5] Fault Inputs
  WPEN                   : TBits_1;                    // [6:6] Write Protection Enable
  FAULTF                 : TBits_1;                    // [7:7] Fault Detection Flag
  RESERVED1              : TBits_24;                   // [8:31] no description available
end;

TFTM1_FMS_bitbanded = record
  FAULTF0                : longWord;                   // [0:0] Fault Detection Flag 0
  FAULTF1                : longWord;                   // [1:1] Fault Detection Flag 1
  FAULTF2                : longWord;                   // [2:2] Fault Detection Flag 2
  FAULTF3                : longWord;                   // [3:3] Fault Detection Flag 3
  RESERVED0              : longWord;                   // [4:4] no description available
  FAULTIN                : longWord;                   // [5:5] Fault Inputs
  WPEN                   : longWord;                   // [6:6] Write Protection Enable
  FAULTF                 : longWord;                   // [7:7] Fault Detection Flag
  RESERVED1              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM1_FILTER_bits = bitpacked record
  CH0FVAL                : TBits_4;                    // [0:3] Channel 0 Input Filter
  CH1FVAL                : TBits_4;                    // [4:7] Channel 1 Input Filter
  CH2FVAL                : TBits_4;                    // [8:11] Channel 2 Input Filter
  CH3FVAL                : TBits_4;                    // [12:15] Channel 3 Input Filter
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM1_FILTER_bitbanded = record
  CH0FVAL                : array[0..3] of longWord;    // [0:3] Channel 0 Input Filter
  CH1FVAL                : array[0..3] of longWord;    // [4:7] Channel 1 Input Filter
  CH2FVAL                : array[0..3] of longWord;    // [8:11] Channel 2 Input Filter
  CH3FVAL                : array[0..3] of longWord;    // [12:15] Channel 3 Input Filter
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM1_FLTCTRL_bits = bitpacked record
  FAULT0EN               : TBits_1;                    // [0:0] Fault Input 0 Enable
  FAULT1EN               : TBits_1;                    // [1:1] Fault Input 1 Enable
  FAULT2EN               : TBits_1;                    // [2:2] Fault Input 2 Enable
  FAULT3EN               : TBits_1;                    // [3:3] Fault Input 3 Enable
  FFLTR0EN               : TBits_1;                    // [4:4] Fault Input 0 Filter Enable
  FFLTR1EN               : TBits_1;                    // [5:5] Fault Input 1 Filter Enable
  FFLTR2EN               : TBits_1;                    // [6:6] Fault Input 2 Filter Enable
  FFLTR3EN               : TBits_1;                    // [7:7] Fault Input 3 Filter Enable
  FFVAL                  : TBits_4;                    // [8:11] Fault Input Filter
  RESERVED0              : TBits_20;                   // [12:31] no description available
end;

TFTM1_FLTCTRL_bitbanded = record
  FAULT0EN               : longWord;                   // [0:0] Fault Input 0 Enable
  FAULT1EN               : longWord;                   // [1:1] Fault Input 1 Enable
  FAULT2EN               : longWord;                   // [2:2] Fault Input 2 Enable
  FAULT3EN               : longWord;                   // [3:3] Fault Input 3 Enable
  FFLTR0EN               : longWord;                   // [4:4] Fault Input 0 Filter Enable
  FFLTR1EN               : longWord;                   // [5:5] Fault Input 1 Filter Enable
  FFLTR2EN               : longWord;                   // [6:6] Fault Input 2 Filter Enable
  FFLTR3EN               : longWord;                   // [7:7] Fault Input 3 Filter Enable
  FFVAL                  : array[0..3] of longWord;    // [8:11] Fault Input Filter
  RESERVED0              : array[0..19] of longWord;   // [12:31] no description available
end;

TFTM1_QDCTRL_bits = bitpacked record
  QUADEN                 : TBits_1;                    // [0:0] Quadrature Decoder Mode Enable
  TOFDIR                 : TBits_1;                    // [1:1] Timer Overflow Direction in Quadrature Decoder Mode
  QUADIR                 : TBits_1;                    // [2:2] FTM Counter Direction in Quadrature Decoder Mode
  QUADMODE               : TBits_1;                    // [3:3] Quadrature Decoder Mode
  PHBPOL                 : TBits_1;                    // [4:4] Phase B Input Polarity
  PHAPOL                 : TBits_1;                    // [5:5] Phase A Input Polarity
  PHBFLTREN              : TBits_1;                    // [6:6] Phase B Input Filter Enable
  PHAFLTREN              : TBits_1;                    // [7:7] Phase A Input Filter Enable
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM1_QDCTRL_bitbanded = record
  QUADEN                 : longWord;                   // [0:0] Quadrature Decoder Mode Enable
  TOFDIR                 : longWord;                   // [1:1] Timer Overflow Direction in Quadrature Decoder Mode
  QUADIR                 : longWord;                   // [2:2] FTM Counter Direction in Quadrature Decoder Mode
  QUADMODE               : longWord;                   // [3:3] Quadrature Decoder Mode
  PHBPOL                 : longWord;                   // [4:4] Phase B Input Polarity
  PHAPOL                 : longWord;                   // [5:5] Phase A Input Polarity
  PHBFLTREN              : longWord;                   // [6:6] Phase B Input Filter Enable
  PHAFLTREN              : longWord;                   // [7:7] Phase A Input Filter Enable
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM1_CONF_bits = bitpacked record
  NUMTOF                 : TBits_5;                    // [0:4] TOF Frequency
  RESERVED0              : TBits_1;                    // [5:5] no description available
  BDMMODE                : TBits_2;                    // [6:7] BDM Mode
  RESERVED1              : TBits_1;                    // [8:8] no description available
  GTBEEN                 : TBits_1;                    // [9:9] Global time base enable
  GTBEOUT                : TBits_1;                    // [10:10] Global time base output
  RESERVED2              : TBits_21;                   // [11:31] no description available
end;

TFTM1_CONF_bitbanded = record
  NUMTOF                 : array[0..4] of longWord;    // [0:4] TOF Frequency
  RESERVED0              : longWord;                   // [5:5] no description available
  BDMMODE                : array[0..1] of longWord;    // [6:7] BDM Mode
  RESERVED1              : longWord;                   // [8:8] no description available
  GTBEEN                 : longWord;                   // [9:9] Global time base enable
  GTBEOUT                : longWord;                   // [10:10] Global time base output
  RESERVED2              : array[0..20] of longWord;   // [11:31] no description available
end;

TFTM1_FLTPOL_bits = bitpacked record
  FLT0POL                : TBits_1;                    // [0:0] Fault Input 0 Polarity
  FLT1POL                : TBits_1;                    // [1:1] Fault Input 1 Polarity
  FLT2POL                : TBits_1;                    // [2:2] Fault Input 2 Polarity
  FLT3POL                : TBits_1;                    // [3:3] Fault Input 3 Polarity
  RESERVED0              : TBits_28;                   // [4:31] no description available
end;

TFTM1_FLTPOL_bitbanded = record
  FLT0POL                : longWord;                   // [0:0] Fault Input 0 Polarity
  FLT1POL                : longWord;                   // [1:1] Fault Input 1 Polarity
  FLT2POL                : longWord;                   // [2:2] Fault Input 2 Polarity
  FLT3POL                : longWord;                   // [3:3] Fault Input 3 Polarity
  RESERVED0              : array[0..27] of longWord;   // [4:31] no description available
end;

TFTM1_SYNCONF_bits = bitpacked record
  HWTRIGMODE             : TBits_1;                    // [0:0] Hardware Trigger Mode
  RESERVED0              : TBits_1;                    // [1:1] no description available
  CNTINC                 : TBits_1;                    // [2:2] CNTIN register synchronization
  RESERVED1              : TBits_1;                    // [3:3] no description available
  INVC                   : TBits_1;                    // [4:4] INVCTRL register synchronization
  SWOC                   : TBits_1;                    // [5:5] SWOCTRL register synchronization
  RESERVED2              : TBits_1;                    // [6:6] no description available
  SYNCMODE               : TBits_1;                    // [7:7] Synchronization Mode
  SWRSTCNT               : TBits_1;                    // [8:8] no description available
  SWWRBUF                : TBits_1;                    // [9:9] no description available
  SWOM                   : TBits_1;                    // [10:10] no description available
  SWINVC                 : TBits_1;                    // [11:11] no description available
  SWSOC                  : TBits_1;                    // [12:12] no description available
  RESERVED3              : TBits_3;                    // [13:15] no description available
  HWRSTCNT               : TBits_1;                    // [16:16] no description available
  HWWRBUF                : TBits_1;                    // [17:17] no description available
  HWOM                   : TBits_1;                    // [18:18] no description available
  HWINVC                 : TBits_1;                    // [19:19] no description available
  HWSOC                  : TBits_1;                    // [20:20] no description available
  RESERVED4              : TBits_11;                   // [21:31] no description available
end;

TFTM1_SYNCONF_bitbanded = record
  HWTRIGMODE             : longWord;                   // [0:0] Hardware Trigger Mode
  RESERVED0              : longWord;                   // [1:1] no description available
  CNTINC                 : longWord;                   // [2:2] CNTIN register synchronization
  RESERVED1              : longWord;                   // [3:3] no description available
  INVC                   : longWord;                   // [4:4] INVCTRL register synchronization
  SWOC                   : longWord;                   // [5:5] SWOCTRL register synchronization
  RESERVED2              : longWord;                   // [6:6] no description available
  SYNCMODE               : longWord;                   // [7:7] Synchronization Mode
  SWRSTCNT               : longWord;                   // [8:8] no description available
  SWWRBUF                : longWord;                   // [9:9] no description available
  SWOM                   : longWord;                   // [10:10] no description available
  SWINVC                 : longWord;                   // [11:11] no description available
  SWSOC                  : longWord;                   // [12:12] no description available
  RESERVED3              : array[0..2] of longWord;    // [13:15] no description available
  HWRSTCNT               : longWord;                   // [16:16] no description available
  HWWRBUF                : longWord;                   // [17:17] no description available
  HWOM                   : longWord;                   // [18:18] no description available
  HWINVC                 : longWord;                   // [19:19] no description available
  HWSOC                  : longWord;                   // [20:20] no description available
  RESERVED4              : array[0..10] of longWord;   // [21:31] no description available
end;

TFTM1_INVCTRL_bits = bitpacked record
  INV0EN                 : TBits_1;                    // [0:0] Pair Channels 0 Inverting Enable
  INV1EN                 : TBits_1;                    // [1:1] Pair Channels 1 Inverting Enable
  INV2EN                 : TBits_1;                    // [2:2] Pair Channels 2 Inverting Enable
  INV3EN                 : TBits_1;                    // [3:3] Pair Channels 3 Inverting Enable
  RESERVED0              : TBits_28;                   // [4:31] no description available
end;

TFTM1_INVCTRL_bitbanded = record
  INV0EN                 : longWord;                   // [0:0] Pair Channels 0 Inverting Enable
  INV1EN                 : longWord;                   // [1:1] Pair Channels 1 Inverting Enable
  INV2EN                 : longWord;                   // [2:2] Pair Channels 2 Inverting Enable
  INV3EN                 : longWord;                   // [3:3] Pair Channels 3 Inverting Enable
  RESERVED0              : array[0..27] of longWord;   // [4:31] no description available
end;

TFTM1_SWOCTRL_bits = bitpacked record
  CH0OC                  : TBits_1;                    // [0:0] Channel 0 Software Output Control Enable
  CH1OC                  : TBits_1;                    // [1:1] Channel 1 Software Output Control Enable
  CH2OC                  : TBits_1;                    // [2:2] Channel 2 Software Output Control Enable
  CH3OC                  : TBits_1;                    // [3:3] Channel 3 Software Output Control Enable
  CH4OC                  : TBits_1;                    // [4:4] Channel 4 Software Output Control Enable
  CH5OC                  : TBits_1;                    // [5:5] Channel 5 Software Output Control Enable
  CH6OC                  : TBits_1;                    // [6:6] Channel 6 Software Output Control Enable
  CH7OC                  : TBits_1;                    // [7:7] Channel 7 Software Output Control Enable
  CH0OCV                 : TBits_1;                    // [8:8] Channel 0 Software Output Control Value
  CH1OCV                 : TBits_1;                    // [9:9] Channel 1 Software Output Control Value
  CH2OCV                 : TBits_1;                    // [10:10] Channel 2 Software Output Control Value
  CH3OCV                 : TBits_1;                    // [11:11] Channel 3 Software Output Control Value
  CH4OCV                 : TBits_1;                    // [12:12] Channel 4 Software Output Control Value
  CH5OCV                 : TBits_1;                    // [13:13] Channel 5 Software Output Control Value
  CH6OCV                 : TBits_1;                    // [14:14] Channel 6 Software Output Control Value
  CH7OCV                 : TBits_1;                    // [15:15] Channel 7 Software Output Control Value
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM1_SWOCTRL_bitbanded = record
  CH0OC                  : longWord;                   // [0:0] Channel 0 Software Output Control Enable
  CH1OC                  : longWord;                   // [1:1] Channel 1 Software Output Control Enable
  CH2OC                  : longWord;                   // [2:2] Channel 2 Software Output Control Enable
  CH3OC                  : longWord;                   // [3:3] Channel 3 Software Output Control Enable
  CH4OC                  : longWord;                   // [4:4] Channel 4 Software Output Control Enable
  CH5OC                  : longWord;                   // [5:5] Channel 5 Software Output Control Enable
  CH6OC                  : longWord;                   // [6:6] Channel 6 Software Output Control Enable
  CH7OC                  : longWord;                   // [7:7] Channel 7 Software Output Control Enable
  CH0OCV                 : longWord;                   // [8:8] Channel 0 Software Output Control Value
  CH1OCV                 : longWord;                   // [9:9] Channel 1 Software Output Control Value
  CH2OCV                 : longWord;                   // [10:10] Channel 2 Software Output Control Value
  CH3OCV                 : longWord;                   // [11:11] Channel 3 Software Output Control Value
  CH4OCV                 : longWord;                   // [12:12] Channel 4 Software Output Control Value
  CH5OCV                 : longWord;                   // [13:13] Channel 5 Software Output Control Value
  CH6OCV                 : longWord;                   // [14:14] Channel 6 Software Output Control Value
  CH7OCV                 : longWord;                   // [15:15] Channel 7 Software Output Control Value
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM1_PWMLOAD_bits = bitpacked record
  CH0SEL                 : TBits_1;                    // [0:0] Channel 0 Select
  CH1SEL                 : TBits_1;                    // [1:1] Channel 1 Select
  CH2SEL                 : TBits_1;                    // [2:2] Channel 2 Select
  CH3SEL                 : TBits_1;                    // [3:3] Channel 3 Select
  CH4SEL                 : TBits_1;                    // [4:4] Channel 4 Select
  CH5SEL                 : TBits_1;                    // [5:5] Channel 5 Select
  CH6SEL                 : TBits_1;                    // [6:6] Channel 6 Select
  CH7SEL                 : TBits_1;                    // [7:7] Channel 7 Select
  RESERVED0              : TBits_1;                    // [8:8] no description available
  LDOK                   : TBits_1;                    // [9:9] Load Enable
  RESERVED1              : TBits_22;                   // [10:31] no description available
end;

TFTM1_PWMLOAD_bitbanded = record
  CH0SEL                 : longWord;                   // [0:0] Channel 0 Select
  CH1SEL                 : longWord;                   // [1:1] Channel 1 Select
  CH2SEL                 : longWord;                   // [2:2] Channel 2 Select
  CH3SEL                 : longWord;                   // [3:3] Channel 3 Select
  CH4SEL                 : longWord;                   // [4:4] Channel 4 Select
  CH5SEL                 : longWord;                   // [5:5] Channel 5 Select
  CH6SEL                 : longWord;                   // [6:6] Channel 6 Select
  CH7SEL                 : longWord;                   // [7:7] Channel 7 Select
  RESERVED0              : longWord;                   // [8:8] no description available
  LDOK                   : longWord;                   // [9:9] Load Enable
  RESERVED1              : array[0..21] of longWord;   // [10:31] no description available
end;

TFTM1_Registers = record
  case boolean of false: (
  SC                     : longWord;                   // 0x00 Status and Control
  CNT                    : longWord;                   // 0x04 Counter
  &MOD                   : longWord;                   // 0x08 Modulo
  C0SC                   : longWord;                   // 0x0C Channel (n) Status and Control
  C0V                    : longWord;                   // 0x10 Channel (n) Value
  C1SC                   : longWord;                   // 0x14 Channel (n) Status and Control
  C1V                    : longWord;                   // 0x18 Channel (n) Value
  RESERVED0              : array[0..11] of longWord;   // 0x1C
  CNTIN                  : longWord;                   // 0x4C Counter Initial Value
  STATUS                 : longWord;                   // 0x50 Capture and Compare Status
  MODE                   : longWord;                   // 0x54 Features Mode Selection
  SYNC                   : longWord;                   // 0x58 Synchronization
  OUTINIT                : longWord;                   // 0x5C Initial State for Channels Output
  OUTMASK                : longWord;                   // 0x60 Output Mask
  COMBINE                : longWord;                   // 0x64 Function for Linked Channels
  DEADTIME               : longWord;                   // 0x68 Deadtime Insertion Control
  EXTTRIG                : longWord;                   // 0x6C FTM External Trigger
  POL                    : longWord;                   // 0x70 Channels Polarity
  FMS                    : longWord;                   // 0x74 Fault Mode Status
  FILTER                 : longWord;                   // 0x78 Input Capture Filter Control
  FLTCTRL                : longWord;                   // 0x7C Fault Control
  QDCTRL                 : longWord;                   // 0x80 Quadrature Decoder Control and Status
  CONF                   : longWord;                   // 0x84 Configuration
  FLTPOL                 : longWord;                   // 0x88 FTM Fault Input Polarity
  SYNCONF                : longWord;                   // 0x8C Synchronization Configuration
  INVCTRL                : longWord;                   // 0x90 FTM Inverting Control
  SWOCTRL                : longWord;                   // 0x94 FTM Software Output Control
  PWMLOAD                : longWord;                   // 0x98 FTM PWM Load
);
true : (
SC_bits                  : TFTM1_SC_bits;              // 0x04 Status and Control
CNT_bits                 : TFTM1_CNT_bits;             // 0x08 Counter
MOD_bits                 : TFTM1_MOD_bits;             // 0x0C Modulo
C0SC_bits                : longWord;                   // 0x0C Channel (n) Status and Control
C0V_bits                 : longWord;                   // 0x10 Channel (n) Value
C1SC_bits                : longWord;                   // 0x14 Channel (n) Status and Control
C1V_bits                 : longWord;                   // 0x18 Channel (n) Value
RESERVED_bits0           : array[0..11] of longWord;
CNTIN_bits               : TFTM1_CNTIN_bits;           // 0x50 Counter Initial Value
STATUS_bits              : TFTM1_STATUS_bits;          // 0x54 Capture and Compare Status
MODE_bits                : TFTM1_MODE_bits;            // 0x58 Features Mode Selection
SYNC_bits                : TFTM1_SYNC_bits;            // 0x5C Synchronization
OUTINIT_bits             : TFTM1_OUTINIT_bits;         // 0x60 Initial State for Channels Output
OUTMASK_bits             : TFTM1_OUTMASK_bits;         // 0x64 Output Mask
COMBINE_bits             : TFTM1_COMBINE_bits;         // 0x68 Function for Linked Channels
DEADTIME_bits            : TFTM1_DEADTIME_bits;        // 0x6C Deadtime Insertion Control
EXTTRIG_bits             : TFTM1_EXTTRIG_bits;         // 0x70 FTM External Trigger
POL_bits                 : TFTM1_POL_bits;             // 0x74 Channels Polarity
FMS_bits                 : TFTM1_FMS_bits;             // 0x78 Fault Mode Status
FILTER_bits              : TFTM1_FILTER_bits;          // 0x7C Input Capture Filter Control
FLTCTRL_bits             : TFTM1_FLTCTRL_bits;         // 0x80 Fault Control
QDCTRL_bits              : TFTM1_QDCTRL_bits;          // 0x84 Quadrature Decoder Control and Status
CONF_bits                : TFTM1_CONF_bits;            // 0x88 Configuration
FLTPOL_bits              : TFTM1_FLTPOL_bits;          // 0x8C FTM Fault Input Polarity
SYNCONF_bits             : TFTM1_SYNCONF_bits;         // 0x90 Synchronization Configuration
INVCTRL_bits             : TFTM1_INVCTRL_bits;         // 0x94 FTM Inverting Control
SWOCTRL_bits             : TFTM1_SWOCTRL_bits;         // 0x98 FTM Software Output Control
PWMLOAD_bits             : TFTM1_PWMLOAD_bits;         // 0x9C FTM PWM Load
);
end;

TFTM1Registers_bitbanded = record
  SC                     : TFTM1_SC_bitbanded;         // 0x04 Status and Control
  CNT                    : TFTM1_CNT_bitbanded;        // 0x08 Counter
  &MOD                   : TFTM1_MOD_bitbanded;        // 0x0C Modulo
  C0SC_bitbanded         : longWord;                   // 0x0C Channel (n) Status and Control
  C0V_bitbanded          : longWord;                   // 0x10 Channel (n) Value
  C1SC_bitbanded         : longWord;                   // 0x14 Channel (n) Status and Control
  C1V_bitbanded          : longWord;                   // 0x18 Channel (n) Value
  RESERVED0              : array[0..47] of array[0..7] of longWord;
  CNTIN                  : TFTM1_CNTIN_bitbanded;      // 0x50 Counter Initial Value
  STATUS                 : TFTM1_STATUS_bitbanded;     // 0x54 Capture and Compare Status
  MODE                   : TFTM1_MODE_bitbanded;       // 0x58 Features Mode Selection
  SYNC                   : TFTM1_SYNC_bitbanded;       // 0x5C Synchronization
  OUTINIT                : TFTM1_OUTINIT_bitbanded;    // 0x60 Initial State for Channels Output
  OUTMASK                : TFTM1_OUTMASK_bitbanded;    // 0x64 Output Mask
  COMBINE                : TFTM1_COMBINE_bitbanded;    // 0x68 Function for Linked Channels
  DEADTIME               : TFTM1_DEADTIME_bitbanded;   // 0x6C Deadtime Insertion Control
  EXTTRIG                : TFTM1_EXTTRIG_bitbanded;    // 0x70 FTM External Trigger
  POL                    : TFTM1_POL_bitbanded;        // 0x74 Channels Polarity
  FMS                    : TFTM1_FMS_bitbanded;        // 0x78 Fault Mode Status
  FILTER                 : TFTM1_FILTER_bitbanded;     // 0x7C Input Capture Filter Control
  FLTCTRL                : TFTM1_FLTCTRL_bitbanded;    // 0x80 Fault Control
  QDCTRL                 : TFTM1_QDCTRL_bitbanded;     // 0x84 Quadrature Decoder Control and Status
  CONF                   : TFTM1_CONF_bitbanded;       // 0x88 Configuration
  FLTPOL                 : TFTM1_FLTPOL_bitbanded;     // 0x8C FTM Fault Input Polarity
  SYNCONF                : TFTM1_SYNCONF_bitbanded;    // 0x90 Synchronization Configuration
  INVCTRL                : TFTM1_INVCTRL_bitbanded;    // 0x94 FTM Inverting Control
  SWOCTRL                : TFTM1_SWOCTRL_bitbanded;    // 0x98 FTM Software Output Control
  PWMLOAD                : TFTM1_PWMLOAD_bitbanded;    // 0x9C FTM PWM Load
end;

// FlexTimer Module
TFTM2_SC_bits = bitpacked record
  PS                     : TBits_3;                    // [0:2] Prescale Factor Selection
  CLKS                   : TBits_2;                    // [3:4] Clock Source Selection
  CPWMS                  : TBits_1;                    // [5:5] Center-aligned PWM Select
  TOIE                   : TBits_1;                    // [6:6] Timer Overflow Interrupt Enable
  TOF                    : TBits_1;                    // [7:7] Timer Overflow Flag
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM2_SC_bitbanded = record
  PS                     : array[0..2] of longWord;    // [0:2] Prescale Factor Selection
  CLKS                   : array[0..1] of longWord;    // [3:4] Clock Source Selection
  CPWMS                  : longWord;                   // [5:5] Center-aligned PWM Select
  TOIE                   : longWord;                   // [6:6] Timer Overflow Interrupt Enable
  TOF                    : longWord;                   // [7:7] Timer Overflow Flag
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM2_CNT_bits = bitpacked record
  COUNT                  : TBits_16;                   // [0:15] Counter value
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM2_CNT_bitbanded = record
  COUNT                  : array[0..15] of longWord;   // [0:15] Counter value
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM2_MOD_bits = bitpacked record
  &MOD                   : TBits_16;                   // [0:15] no description available
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM2_MOD_bitbanded = record
  &MOD                   : array[0..15] of longWord;   // [0:15] no description available
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM2_CSC_bits = bitpacked record
  DMA                    : TBits_1;                    // [0:0] DMA Enable
  RESERVED0              : TBits_1;                    // [1:1] no description available
  ELSA                   : TBits_1;                    // [2:2] Edge or Level Select
  ELSB                   : TBits_1;                    // [3:3] Edge or Level Select
  MSA                    : TBits_1;                    // [4:4] Channel Mode Select
  MSB                    : TBits_1;                    // [5:5] Channel Mode Select
  CHIE                   : TBits_1;                    // [6:6] Channel Interrupt Enable
  CHF                    : TBits_1;                    // [7:7] Channel Flag
  RESERVED1              : TBits_24;                   // [8:31] no description available
end;

TFTM2_CSC_bitbanded = record
  DMA                    : longWord;                   // [0:0] DMA Enable
  RESERVED0              : longWord;                   // [1:1] no description available
  ELSA                   : longWord;                   // [2:2] Edge or Level Select
  ELSB                   : longWord;                   // [3:3] Edge or Level Select
  MSA                    : longWord;                   // [4:4] Channel Mode Select
  MSB                    : longWord;                   // [5:5] Channel Mode Select
  CHIE                   : longWord;                   // [6:6] Channel Interrupt Enable
  CHF                    : longWord;                   // [7:7] Channel Flag
  RESERVED1              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM2_CV_bits = bitpacked record
  VAL                    : TBits_16;                   // [0:15] Channel Value
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM2_CV_bitbanded = record
  VAL                    : array[0..15] of longWord;   // [0:15] Channel Value
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM2_CNTIN_bits = bitpacked record
  INIT                   : TBits_16;                   // [0:15] no description available
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM2_CNTIN_bitbanded = record
  INIT                   : array[0..15] of longWord;   // [0:15] no description available
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM2_STATUS_bits = bitpacked record
  CH0F                   : TBits_1;                    // [0:0] Channel 0 Flag
  CH1F                   : TBits_1;                    // [1:1] Channel 1 Flag
  CH2F                   : TBits_1;                    // [2:2] Channel 2 Flag
  CH3F                   : TBits_1;                    // [3:3] Channel 3 Flag
  CH4F                   : TBits_1;                    // [4:4] Channel 4 Flag
  CH5F                   : TBits_1;                    // [5:5] Channel 5 Flag
  CH6F                   : TBits_1;                    // [6:6] Channel 6 Flag
  CH7F                   : TBits_1;                    // [7:7] Channel 7 Flag
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM2_STATUS_bitbanded = record
  CH0F                   : longWord;                   // [0:0] Channel 0 Flag
  CH1F                   : longWord;                   // [1:1] Channel 1 Flag
  CH2F                   : longWord;                   // [2:2] Channel 2 Flag
  CH3F                   : longWord;                   // [3:3] Channel 3 Flag
  CH4F                   : longWord;                   // [4:4] Channel 4 Flag
  CH5F                   : longWord;                   // [5:5] Channel 5 Flag
  CH6F                   : longWord;                   // [6:6] Channel 6 Flag
  CH7F                   : longWord;                   // [7:7] Channel 7 Flag
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM2_MODE_bits = bitpacked record
  FTMEN                  : TBits_1;                    // [0:0] FTM Enable
  INIT                   : TBits_1;                    // [1:1] Initialize the Channels Output
  WPDIS                  : TBits_1;                    // [2:2] Write Protection Disable
  PWMSYNC                : TBits_1;                    // [3:3] PWM Synchronization Mode
  CAPTEST                : TBits_1;                    // [4:4] Capture Test Mode Enable
  FAULTM                 : TBits_2;                    // [5:6] Fault Control Mode
  FAULTIE                : TBits_1;                    // [7:7] Fault Interrupt Enable
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM2_MODE_bitbanded = record
  FTMEN                  : longWord;                   // [0:0] FTM Enable
  INIT                   : longWord;                   // [1:1] Initialize the Channels Output
  WPDIS                  : longWord;                   // [2:2] Write Protection Disable
  PWMSYNC                : longWord;                   // [3:3] PWM Synchronization Mode
  CAPTEST                : longWord;                   // [4:4] Capture Test Mode Enable
  FAULTM                 : array[0..1] of longWord;    // [5:6] Fault Control Mode
  FAULTIE                : longWord;                   // [7:7] Fault Interrupt Enable
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM2_SYNC_bits = bitpacked record
  CNTMIN                 : TBits_1;                    // [0:0] Minimum loading point enable
  CNTMAX                 : TBits_1;                    // [1:1] Maximum loading point enable
  REINIT                 : TBits_1;                    // [2:2] FTM Counter Reinitialization by Synchronization (FTM Counter Synchronization)
  SYNCHOM                : TBits_1;                    // [3:3] Output Mask Synchronization
  TRIG0                  : TBits_1;                    // [4:4] PWM Synchronization Hardware Trigger 0
  TRIG1                  : TBits_1;                    // [5:5] PWM Synchronization Hardware Trigger 1
  TRIG2                  : TBits_1;                    // [6:6] PWM Synchronization Hardware Trigger 2
  SWSYNC                 : TBits_1;                    // [7:7] PWM Synchronization Software Trigger
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM2_SYNC_bitbanded = record
  CNTMIN                 : longWord;                   // [0:0] Minimum loading point enable
  CNTMAX                 : longWord;                   // [1:1] Maximum loading point enable
  REINIT                 : longWord;                   // [2:2] FTM Counter Reinitialization by Synchronization (FTM Counter Synchronization)
  SYNCHOM                : longWord;                   // [3:3] Output Mask Synchronization
  TRIG0                  : longWord;                   // [4:4] PWM Synchronization Hardware Trigger 0
  TRIG1                  : longWord;                   // [5:5] PWM Synchronization Hardware Trigger 1
  TRIG2                  : longWord;                   // [6:6] PWM Synchronization Hardware Trigger 2
  SWSYNC                 : longWord;                   // [7:7] PWM Synchronization Software Trigger
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM2_OUTINIT_bits = bitpacked record
  CH0OI                  : TBits_1;                    // [0:0] Channel 0 Output Initialization Value
  CH1OI                  : TBits_1;                    // [1:1] Channel 1 Output Initialization Value
  CH2OI                  : TBits_1;                    // [2:2] Channel 2 Output Initialization Value
  CH3OI                  : TBits_1;                    // [3:3] Channel 3 Output Initialization Value
  CH4OI                  : TBits_1;                    // [4:4] Channel 4 Output Initialization Value
  CH5OI                  : TBits_1;                    // [5:5] Channel 5 Output Initialization Value
  CH6OI                  : TBits_1;                    // [6:6] Channel 6 Output Initialization Value
  CH7OI                  : TBits_1;                    // [7:7] Channel 7 Output Initialization Value
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM2_OUTINIT_bitbanded = record
  CH0OI                  : longWord;                   // [0:0] Channel 0 Output Initialization Value
  CH1OI                  : longWord;                   // [1:1] Channel 1 Output Initialization Value
  CH2OI                  : longWord;                   // [2:2] Channel 2 Output Initialization Value
  CH3OI                  : longWord;                   // [3:3] Channel 3 Output Initialization Value
  CH4OI                  : longWord;                   // [4:4] Channel 4 Output Initialization Value
  CH5OI                  : longWord;                   // [5:5] Channel 5 Output Initialization Value
  CH6OI                  : longWord;                   // [6:6] Channel 6 Output Initialization Value
  CH7OI                  : longWord;                   // [7:7] Channel 7 Output Initialization Value
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM2_OUTMASK_bits = bitpacked record
  CH0OM                  : TBits_1;                    // [0:0] Channel 0 Output Mask
  CH1OM                  : TBits_1;                    // [1:1] Channel 1 Output Mask
  CH2OM                  : TBits_1;                    // [2:2] Channel 2 Output Mask
  CH3OM                  : TBits_1;                    // [3:3] Channel 3 Output Mask
  CH4OM                  : TBits_1;                    // [4:4] Channel 4 Output Mask
  CH5OM                  : TBits_1;                    // [5:5] Channel 5 Output Mask
  CH6OM                  : TBits_1;                    // [6:6] Channel 6 Output Mask
  CH7OM                  : TBits_1;                    // [7:7] Channel 7 Output Mask
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM2_OUTMASK_bitbanded = record
  CH0OM                  : longWord;                   // [0:0] Channel 0 Output Mask
  CH1OM                  : longWord;                   // [1:1] Channel 1 Output Mask
  CH2OM                  : longWord;                   // [2:2] Channel 2 Output Mask
  CH3OM                  : longWord;                   // [3:3] Channel 3 Output Mask
  CH4OM                  : longWord;                   // [4:4] Channel 4 Output Mask
  CH5OM                  : longWord;                   // [5:5] Channel 5 Output Mask
  CH6OM                  : longWord;                   // [6:6] Channel 6 Output Mask
  CH7OM                  : longWord;                   // [7:7] Channel 7 Output Mask
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM2_COMBINE_bits = bitpacked record
  COMBINE0               : TBits_1;                    // [0:0] Combine Channels for n = 0
  COMP0                  : TBits_1;                    // [1:1] Complement of Channel (n) for n = 0
  DECAPEN0               : TBits_1;                    // [2:2] Dual Edge Capture Mode Enable for n = 0
  DECAP0                 : TBits_1;                    // [3:3] Dual Edge Capture Mode Captures for n = 0
  DTEN0                  : TBits_1;                    // [4:4] Deadtime Enable for n = 0
  SYNCEN0                : TBits_1;                    // [5:5] Synchronization Enable for n = 0
  FAULTEN0               : TBits_1;                    // [6:6] Fault Control Enable for n = 0
  RESERVED0              : TBits_1;                    // [7:7] no description available
  COMBINE1               : TBits_1;                    // [8:8] Combine Channels for n = 2
  COMP1                  : TBits_1;                    // [9:9] Complement of Channel (n) for n = 2
  DECAPEN1               : TBits_1;                    // [10:10] Dual Edge Capture Mode Enable for n = 2
  DECAP1                 : TBits_1;                    // [11:11] Dual Edge Capture Mode Captures for n = 2
  DTEN1                  : TBits_1;                    // [12:12] Deadtime Enable for n = 2
  SYNCEN1                : TBits_1;                    // [13:13] Synchronization Enable for n = 2
  FAULTEN1               : TBits_1;                    // [14:14] Fault Control Enable for n = 2
  RESERVED1              : TBits_1;                    // [15:15] no description available
  COMBINE2               : TBits_1;                    // [16:16] Combine Channels for n = 4
  COMP2                  : TBits_1;                    // [17:17] Complement of Channel (n) for n = 4
  DECAPEN2               : TBits_1;                    // [18:18] Dual Edge Capture Mode Enable for n = 4
  DECAP2                 : TBits_1;                    // [19:19] Dual Edge Capture Mode Captures for n = 4
  DTEN2                  : TBits_1;                    // [20:20] Deadtime Enable for n = 4
  SYNCEN2                : TBits_1;                    // [21:21] Synchronization Enable for n = 4
  FAULTEN2               : TBits_1;                    // [22:22] Fault Control Enable for n = 4
  RESERVED2              : TBits_1;                    // [23:23] no description available
  COMBINE3               : TBits_1;                    // [24:24] Combine Channels for n = 6
  COMP3                  : TBits_1;                    // [25:25] Complement of Channel (n) for n = 6
  DECAPEN3               : TBits_1;                    // [26:26] Dual Edge Capture Mode Enable for n = 6
  DECAP3                 : TBits_1;                    // [27:27] Dual Edge Capture Mode Captures for n = 6
  DTEN3                  : TBits_1;                    // [28:28] Deadtime Enable for n = 6
  SYNCEN3                : TBits_1;                    // [29:29] Synchronization Enable for n = 6
  FAULTEN3               : TBits_1;                    // [30:30] Fault Control Enable for n = 6
  RESERVED3              : TBits_1;                    // [31:31] no description available
end;

TFTM2_COMBINE_bitbanded = record
  COMBINE0               : longWord;                   // [0:0] Combine Channels for n = 0
  COMP0                  : longWord;                   // [1:1] Complement of Channel (n) for n = 0
  DECAPEN0               : longWord;                   // [2:2] Dual Edge Capture Mode Enable for n = 0
  DECAP0                 : longWord;                   // [3:3] Dual Edge Capture Mode Captures for n = 0
  DTEN0                  : longWord;                   // [4:4] Deadtime Enable for n = 0
  SYNCEN0                : longWord;                   // [5:5] Synchronization Enable for n = 0
  FAULTEN0               : longWord;                   // [6:6] Fault Control Enable for n = 0
  RESERVED0              : longWord;                   // [7:7] no description available
  COMBINE1               : longWord;                   // [8:8] Combine Channels for n = 2
  COMP1                  : longWord;                   // [9:9] Complement of Channel (n) for n = 2
  DECAPEN1               : longWord;                   // [10:10] Dual Edge Capture Mode Enable for n = 2
  DECAP1                 : longWord;                   // [11:11] Dual Edge Capture Mode Captures for n = 2
  DTEN1                  : longWord;                   // [12:12] Deadtime Enable for n = 2
  SYNCEN1                : longWord;                   // [13:13] Synchronization Enable for n = 2
  FAULTEN1               : longWord;                   // [14:14] Fault Control Enable for n = 2
  RESERVED1              : longWord;                   // [15:15] no description available
  COMBINE2               : longWord;                   // [16:16] Combine Channels for n = 4
  COMP2                  : longWord;                   // [17:17] Complement of Channel (n) for n = 4
  DECAPEN2               : longWord;                   // [18:18] Dual Edge Capture Mode Enable for n = 4
  DECAP2                 : longWord;                   // [19:19] Dual Edge Capture Mode Captures for n = 4
  DTEN2                  : longWord;                   // [20:20] Deadtime Enable for n = 4
  SYNCEN2                : longWord;                   // [21:21] Synchronization Enable for n = 4
  FAULTEN2               : longWord;                   // [22:22] Fault Control Enable for n = 4
  RESERVED2              : longWord;                   // [23:23] no description available
  COMBINE3               : longWord;                   // [24:24] Combine Channels for n = 6
  COMP3                  : longWord;                   // [25:25] Complement of Channel (n) for n = 6
  DECAPEN3               : longWord;                   // [26:26] Dual Edge Capture Mode Enable for n = 6
  DECAP3                 : longWord;                   // [27:27] Dual Edge Capture Mode Captures for n = 6
  DTEN3                  : longWord;                   // [28:28] Deadtime Enable for n = 6
  SYNCEN3                : longWord;                   // [29:29] Synchronization Enable for n = 6
  FAULTEN3               : longWord;                   // [30:30] Fault Control Enable for n = 6
  RESERVED3              : longWord;                   // [31:31] no description available
end;

TFTM2_DEADTIME_bits = bitpacked record
  DTVAL                  : TBits_6;                    // [0:5] Deadtime Value
  DTPS                   : TBits_2;                    // [6:7] Deadtime Prescaler Value
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM2_DEADTIME_bitbanded = record
  DTVAL                  : array[0..5] of longWord;    // [0:5] Deadtime Value
  DTPS                   : array[0..1] of longWord;    // [6:7] Deadtime Prescaler Value
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM2_EXTTRIG_bits = bitpacked record
  CH2TRIG                : TBits_1;                    // [0:0] Channel 2 Trigger Enable
  CH3TRIG                : TBits_1;                    // [1:1] Channel 3 Trigger Enable
  CH4TRIG                : TBits_1;                    // [2:2] Channel 4 Trigger Enable
  CH5TRIG                : TBits_1;                    // [3:3] Channel 5 Trigger Enable
  CH0TRIG                : TBits_1;                    // [4:4] Channel 0 Trigger Enable
  CH1TRIG                : TBits_1;                    // [5:5] Channel 1 Trigger Enable
  INITTRIGEN             : TBits_1;                    // [6:6] Initialization Trigger Enable
  TRIGF                  : TBits_1;                    // [7:7] Channel Trigger Flag
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM2_EXTTRIG_bitbanded = record
  CH2TRIG                : longWord;                   // [0:0] Channel 2 Trigger Enable
  CH3TRIG                : longWord;                   // [1:1] Channel 3 Trigger Enable
  CH4TRIG                : longWord;                   // [2:2] Channel 4 Trigger Enable
  CH5TRIG                : longWord;                   // [3:3] Channel 5 Trigger Enable
  CH0TRIG                : longWord;                   // [4:4] Channel 0 Trigger Enable
  CH1TRIG                : longWord;                   // [5:5] Channel 1 Trigger Enable
  INITTRIGEN             : longWord;                   // [6:6] Initialization Trigger Enable
  TRIGF                  : longWord;                   // [7:7] Channel Trigger Flag
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM2_POL_bits = bitpacked record
  POL0                   : TBits_1;                    // [0:0] Channel 0 Polarity
  POL1                   : TBits_1;                    // [1:1] Channel 1 Polarity
  POL2                   : TBits_1;                    // [2:2] Channel 2 Polarity
  POL3                   : TBits_1;                    // [3:3] Channel 3 Polarity
  POL4                   : TBits_1;                    // [4:4] Channel 4 Polarity
  POL5                   : TBits_1;                    // [5:5] Channel 5 Polarity
  POL6                   : TBits_1;                    // [6:6] Channel 6 Polarity
  POL7                   : TBits_1;                    // [7:7] Channel 7 Polarity
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM2_POL_bitbanded = record
  POL0                   : longWord;                   // [0:0] Channel 0 Polarity
  POL1                   : longWord;                   // [1:1] Channel 1 Polarity
  POL2                   : longWord;                   // [2:2] Channel 2 Polarity
  POL3                   : longWord;                   // [3:3] Channel 3 Polarity
  POL4                   : longWord;                   // [4:4] Channel 4 Polarity
  POL5                   : longWord;                   // [5:5] Channel 5 Polarity
  POL6                   : longWord;                   // [6:6] Channel 6 Polarity
  POL7                   : longWord;                   // [7:7] Channel 7 Polarity
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM2_FMS_bits = bitpacked record
  FAULTF0                : TBits_1;                    // [0:0] Fault Detection Flag 0
  FAULTF1                : TBits_1;                    // [1:1] Fault Detection Flag 1
  FAULTF2                : TBits_1;                    // [2:2] Fault Detection Flag 2
  FAULTF3                : TBits_1;                    // [3:3] Fault Detection Flag 3
  RESERVED0              : TBits_1;                    // [4:4] no description available
  FAULTIN                : TBits_1;                    // [5:5] Fault Inputs
  WPEN                   : TBits_1;                    // [6:6] Write Protection Enable
  FAULTF                 : TBits_1;                    // [7:7] Fault Detection Flag
  RESERVED1              : TBits_24;                   // [8:31] no description available
end;

TFTM2_FMS_bitbanded = record
  FAULTF0                : longWord;                   // [0:0] Fault Detection Flag 0
  FAULTF1                : longWord;                   // [1:1] Fault Detection Flag 1
  FAULTF2                : longWord;                   // [2:2] Fault Detection Flag 2
  FAULTF3                : longWord;                   // [3:3] Fault Detection Flag 3
  RESERVED0              : longWord;                   // [4:4] no description available
  FAULTIN                : longWord;                   // [5:5] Fault Inputs
  WPEN                   : longWord;                   // [6:6] Write Protection Enable
  FAULTF                 : longWord;                   // [7:7] Fault Detection Flag
  RESERVED1              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM2_FILTER_bits = bitpacked record
  CH0FVAL                : TBits_4;                    // [0:3] Channel 0 Input Filter
  CH1FVAL                : TBits_4;                    // [4:7] Channel 1 Input Filter
  CH2FVAL                : TBits_4;                    // [8:11] Channel 2 Input Filter
  CH3FVAL                : TBits_4;                    // [12:15] Channel 3 Input Filter
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM2_FILTER_bitbanded = record
  CH0FVAL                : array[0..3] of longWord;    // [0:3] Channel 0 Input Filter
  CH1FVAL                : array[0..3] of longWord;    // [4:7] Channel 1 Input Filter
  CH2FVAL                : array[0..3] of longWord;    // [8:11] Channel 2 Input Filter
  CH3FVAL                : array[0..3] of longWord;    // [12:15] Channel 3 Input Filter
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM2_FLTCTRL_bits = bitpacked record
  FAULT0EN               : TBits_1;                    // [0:0] Fault Input 0 Enable
  FAULT1EN               : TBits_1;                    // [1:1] Fault Input 1 Enable
  FAULT2EN               : TBits_1;                    // [2:2] Fault Input 2 Enable
  FAULT3EN               : TBits_1;                    // [3:3] Fault Input 3 Enable
  FFLTR0EN               : TBits_1;                    // [4:4] Fault Input 0 Filter Enable
  FFLTR1EN               : TBits_1;                    // [5:5] Fault Input 1 Filter Enable
  FFLTR2EN               : TBits_1;                    // [6:6] Fault Input 2 Filter Enable
  FFLTR3EN               : TBits_1;                    // [7:7] Fault Input 3 Filter Enable
  FFVAL                  : TBits_4;                    // [8:11] Fault Input Filter
  RESERVED0              : TBits_20;                   // [12:31] no description available
end;

TFTM2_FLTCTRL_bitbanded = record
  FAULT0EN               : longWord;                   // [0:0] Fault Input 0 Enable
  FAULT1EN               : longWord;                   // [1:1] Fault Input 1 Enable
  FAULT2EN               : longWord;                   // [2:2] Fault Input 2 Enable
  FAULT3EN               : longWord;                   // [3:3] Fault Input 3 Enable
  FFLTR0EN               : longWord;                   // [4:4] Fault Input 0 Filter Enable
  FFLTR1EN               : longWord;                   // [5:5] Fault Input 1 Filter Enable
  FFLTR2EN               : longWord;                   // [6:6] Fault Input 2 Filter Enable
  FFLTR3EN               : longWord;                   // [7:7] Fault Input 3 Filter Enable
  FFVAL                  : array[0..3] of longWord;    // [8:11] Fault Input Filter
  RESERVED0              : array[0..19] of longWord;   // [12:31] no description available
end;

TFTM2_QDCTRL_bits = bitpacked record
  QUADEN                 : TBits_1;                    // [0:0] Quadrature Decoder Mode Enable
  TOFDIR                 : TBits_1;                    // [1:1] Timer Overflow Direction in Quadrature Decoder Mode
  QUADIR                 : TBits_1;                    // [2:2] FTM Counter Direction in Quadrature Decoder Mode
  QUADMODE               : TBits_1;                    // [3:3] Quadrature Decoder Mode
  PHBPOL                 : TBits_1;                    // [4:4] Phase B Input Polarity
  PHAPOL                 : TBits_1;                    // [5:5] Phase A Input Polarity
  PHBFLTREN              : TBits_1;                    // [6:6] Phase B Input Filter Enable
  PHAFLTREN              : TBits_1;                    // [7:7] Phase A Input Filter Enable
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TFTM2_QDCTRL_bitbanded = record
  QUADEN                 : longWord;                   // [0:0] Quadrature Decoder Mode Enable
  TOFDIR                 : longWord;                   // [1:1] Timer Overflow Direction in Quadrature Decoder Mode
  QUADIR                 : longWord;                   // [2:2] FTM Counter Direction in Quadrature Decoder Mode
  QUADMODE               : longWord;                   // [3:3] Quadrature Decoder Mode
  PHBPOL                 : longWord;                   // [4:4] Phase B Input Polarity
  PHAPOL                 : longWord;                   // [5:5] Phase A Input Polarity
  PHBFLTREN              : longWord;                   // [6:6] Phase B Input Filter Enable
  PHAFLTREN              : longWord;                   // [7:7] Phase A Input Filter Enable
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TFTM2_CONF_bits = bitpacked record
  NUMTOF                 : TBits_5;                    // [0:4] TOF Frequency
  RESERVED0              : TBits_1;                    // [5:5] no description available
  BDMMODE                : TBits_2;                    // [6:7] BDM Mode
  RESERVED1              : TBits_1;                    // [8:8] no description available
  GTBEEN                 : TBits_1;                    // [9:9] Global time base enable
  GTBEOUT                : TBits_1;                    // [10:10] Global time base output
  RESERVED2              : TBits_21;                   // [11:31] no description available
end;

TFTM2_CONF_bitbanded = record
  NUMTOF                 : array[0..4] of longWord;    // [0:4] TOF Frequency
  RESERVED0              : longWord;                   // [5:5] no description available
  BDMMODE                : array[0..1] of longWord;    // [6:7] BDM Mode
  RESERVED1              : longWord;                   // [8:8] no description available
  GTBEEN                 : longWord;                   // [9:9] Global time base enable
  GTBEOUT                : longWord;                   // [10:10] Global time base output
  RESERVED2              : array[0..20] of longWord;   // [11:31] no description available
end;

TFTM2_FLTPOL_bits = bitpacked record
  FLT0POL                : TBits_1;                    // [0:0] Fault Input 0 Polarity
  FLT1POL                : TBits_1;                    // [1:1] Fault Input 1 Polarity
  FLT2POL                : TBits_1;                    // [2:2] Fault Input 2 Polarity
  FLT3POL                : TBits_1;                    // [3:3] Fault Input 3 Polarity
  RESERVED0              : TBits_28;                   // [4:31] no description available
end;

TFTM2_FLTPOL_bitbanded = record
  FLT0POL                : longWord;                   // [0:0] Fault Input 0 Polarity
  FLT1POL                : longWord;                   // [1:1] Fault Input 1 Polarity
  FLT2POL                : longWord;                   // [2:2] Fault Input 2 Polarity
  FLT3POL                : longWord;                   // [3:3] Fault Input 3 Polarity
  RESERVED0              : array[0..27] of longWord;   // [4:31] no description available
end;

TFTM2_SYNCONF_bits = bitpacked record
  HWTRIGMODE             : TBits_1;                    // [0:0] Hardware Trigger Mode
  RESERVED0              : TBits_1;                    // [1:1] no description available
  CNTINC                 : TBits_1;                    // [2:2] CNTIN register synchronization
  RESERVED1              : TBits_1;                    // [3:3] no description available
  INVC                   : TBits_1;                    // [4:4] INVCTRL register synchronization
  SWOC                   : TBits_1;                    // [5:5] SWOCTRL register synchronization
  RESERVED2              : TBits_1;                    // [6:6] no description available
  SYNCMODE               : TBits_1;                    // [7:7] Synchronization Mode
  SWRSTCNT               : TBits_1;                    // [8:8] no description available
  SWWRBUF                : TBits_1;                    // [9:9] no description available
  SWOM                   : TBits_1;                    // [10:10] no description available
  SWINVC                 : TBits_1;                    // [11:11] no description available
  SWSOC                  : TBits_1;                    // [12:12] no description available
  RESERVED3              : TBits_3;                    // [13:15] no description available
  HWRSTCNT               : TBits_1;                    // [16:16] no description available
  HWWRBUF                : TBits_1;                    // [17:17] no description available
  HWOM                   : TBits_1;                    // [18:18] no description available
  HWINVC                 : TBits_1;                    // [19:19] no description available
  HWSOC                  : TBits_1;                    // [20:20] no description available
  RESERVED4              : TBits_11;                   // [21:31] no description available
end;

TFTM2_SYNCONF_bitbanded = record
  HWTRIGMODE             : longWord;                   // [0:0] Hardware Trigger Mode
  RESERVED0              : longWord;                   // [1:1] no description available
  CNTINC                 : longWord;                   // [2:2] CNTIN register synchronization
  RESERVED1              : longWord;                   // [3:3] no description available
  INVC                   : longWord;                   // [4:4] INVCTRL register synchronization
  SWOC                   : longWord;                   // [5:5] SWOCTRL register synchronization
  RESERVED2              : longWord;                   // [6:6] no description available
  SYNCMODE               : longWord;                   // [7:7] Synchronization Mode
  SWRSTCNT               : longWord;                   // [8:8] no description available
  SWWRBUF                : longWord;                   // [9:9] no description available
  SWOM                   : longWord;                   // [10:10] no description available
  SWINVC                 : longWord;                   // [11:11] no description available
  SWSOC                  : longWord;                   // [12:12] no description available
  RESERVED3              : array[0..2] of longWord;    // [13:15] no description available
  HWRSTCNT               : longWord;                   // [16:16] no description available
  HWWRBUF                : longWord;                   // [17:17] no description available
  HWOM                   : longWord;                   // [18:18] no description available
  HWINVC                 : longWord;                   // [19:19] no description available
  HWSOC                  : longWord;                   // [20:20] no description available
  RESERVED4              : array[0..10] of longWord;   // [21:31] no description available
end;

TFTM2_INVCTRL_bits = bitpacked record
  INV0EN                 : TBits_1;                    // [0:0] Pair Channels 0 Inverting Enable
  INV1EN                 : TBits_1;                    // [1:1] Pair Channels 1 Inverting Enable
  INV2EN                 : TBits_1;                    // [2:2] Pair Channels 2 Inverting Enable
  INV3EN                 : TBits_1;                    // [3:3] Pair Channels 3 Inverting Enable
  RESERVED0              : TBits_28;                   // [4:31] no description available
end;

TFTM2_INVCTRL_bitbanded = record
  INV0EN                 : longWord;                   // [0:0] Pair Channels 0 Inverting Enable
  INV1EN                 : longWord;                   // [1:1] Pair Channels 1 Inverting Enable
  INV2EN                 : longWord;                   // [2:2] Pair Channels 2 Inverting Enable
  INV3EN                 : longWord;                   // [3:3] Pair Channels 3 Inverting Enable
  RESERVED0              : array[0..27] of longWord;   // [4:31] no description available
end;

TFTM2_SWOCTRL_bits = bitpacked record
  CH0OC                  : TBits_1;                    // [0:0] Channel 0 Software Output Control Enable
  CH1OC                  : TBits_1;                    // [1:1] Channel 1 Software Output Control Enable
  CH2OC                  : TBits_1;                    // [2:2] Channel 2 Software Output Control Enable
  CH3OC                  : TBits_1;                    // [3:3] Channel 3 Software Output Control Enable
  CH4OC                  : TBits_1;                    // [4:4] Channel 4 Software Output Control Enable
  CH5OC                  : TBits_1;                    // [5:5] Channel 5 Software Output Control Enable
  CH6OC                  : TBits_1;                    // [6:6] Channel 6 Software Output Control Enable
  CH7OC                  : TBits_1;                    // [7:7] Channel 7 Software Output Control Enable
  CH0OCV                 : TBits_1;                    // [8:8] Channel 0 Software Output Control Value
  CH1OCV                 : TBits_1;                    // [9:9] Channel 1 Software Output Control Value
  CH2OCV                 : TBits_1;                    // [10:10] Channel 2 Software Output Control Value
  CH3OCV                 : TBits_1;                    // [11:11] Channel 3 Software Output Control Value
  CH4OCV                 : TBits_1;                    // [12:12] Channel 4 Software Output Control Value
  CH5OCV                 : TBits_1;                    // [13:13] Channel 5 Software Output Control Value
  CH6OCV                 : TBits_1;                    // [14:14] Channel 6 Software Output Control Value
  CH7OCV                 : TBits_1;                    // [15:15] Channel 7 Software Output Control Value
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TFTM2_SWOCTRL_bitbanded = record
  CH0OC                  : longWord;                   // [0:0] Channel 0 Software Output Control Enable
  CH1OC                  : longWord;                   // [1:1] Channel 1 Software Output Control Enable
  CH2OC                  : longWord;                   // [2:2] Channel 2 Software Output Control Enable
  CH3OC                  : longWord;                   // [3:3] Channel 3 Software Output Control Enable
  CH4OC                  : longWord;                   // [4:4] Channel 4 Software Output Control Enable
  CH5OC                  : longWord;                   // [5:5] Channel 5 Software Output Control Enable
  CH6OC                  : longWord;                   // [6:6] Channel 6 Software Output Control Enable
  CH7OC                  : longWord;                   // [7:7] Channel 7 Software Output Control Enable
  CH0OCV                 : longWord;                   // [8:8] Channel 0 Software Output Control Value
  CH1OCV                 : longWord;                   // [9:9] Channel 1 Software Output Control Value
  CH2OCV                 : longWord;                   // [10:10] Channel 2 Software Output Control Value
  CH3OCV                 : longWord;                   // [11:11] Channel 3 Software Output Control Value
  CH4OCV                 : longWord;                   // [12:12] Channel 4 Software Output Control Value
  CH5OCV                 : longWord;                   // [13:13] Channel 5 Software Output Control Value
  CH6OCV                 : longWord;                   // [14:14] Channel 6 Software Output Control Value
  CH7OCV                 : longWord;                   // [15:15] Channel 7 Software Output Control Value
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TFTM2_PWMLOAD_bits = bitpacked record
  CH0SEL                 : TBits_1;                    // [0:0] Channel 0 Select
  CH1SEL                 : TBits_1;                    // [1:1] Channel 1 Select
  CH2SEL                 : TBits_1;                    // [2:2] Channel 2 Select
  CH3SEL                 : TBits_1;                    // [3:3] Channel 3 Select
  CH4SEL                 : TBits_1;                    // [4:4] Channel 4 Select
  CH5SEL                 : TBits_1;                    // [5:5] Channel 5 Select
  CH6SEL                 : TBits_1;                    // [6:6] Channel 6 Select
  CH7SEL                 : TBits_1;                    // [7:7] Channel 7 Select
  RESERVED0              : TBits_1;                    // [8:8] no description available
  LDOK                   : TBits_1;                    // [9:9] Load Enable
  RESERVED1              : TBits_22;                   // [10:31] no description available
end;

TFTM2_PWMLOAD_bitbanded = record
  CH0SEL                 : longWord;                   // [0:0] Channel 0 Select
  CH1SEL                 : longWord;                   // [1:1] Channel 1 Select
  CH2SEL                 : longWord;                   // [2:2] Channel 2 Select
  CH3SEL                 : longWord;                   // [3:3] Channel 3 Select
  CH4SEL                 : longWord;                   // [4:4] Channel 4 Select
  CH5SEL                 : longWord;                   // [5:5] Channel 5 Select
  CH6SEL                 : longWord;                   // [6:6] Channel 6 Select
  CH7SEL                 : longWord;                   // [7:7] Channel 7 Select
  RESERVED0              : longWord;                   // [8:8] no description available
  LDOK                   : longWord;                   // [9:9] Load Enable
  RESERVED1              : array[0..21] of longWord;   // [10:31] no description available
end;

TFTM2_Registers = record
  case boolean of false: (
  SC                     : longWord;                   // 0x00 Status and Control
  CNT                    : longWord;                   // 0x04 Counter
  &MOD                   : longWord;                   // 0x08 Modulo
  C0SC                   : longWord;                   // 0x0C Channel (n) Status and Control
  C0V                    : longWord;                   // 0x10 Channel (n) Value
  C1SC                   : longWord;                   // 0x14 Channel (n) Status and Control
  C1V                    : longWord;                   // 0x18 Channel (n) Value
  RESERVED0              : array[0..11] of longWord;   // 0x1C
  CNTIN                  : longWord;                   // 0x4C Counter Initial Value
  STATUS                 : longWord;                   // 0x50 Capture and Compare Status
  MODE                   : longWord;                   // 0x54 Features Mode Selection
  SYNC                   : longWord;                   // 0x58 Synchronization
  OUTINIT                : longWord;                   // 0x5C Initial State for Channels Output
  OUTMASK                : longWord;                   // 0x60 Output Mask
  COMBINE                : longWord;                   // 0x64 Function for Linked Channels
  DEADTIME               : longWord;                   // 0x68 Deadtime Insertion Control
  EXTTRIG                : longWord;                   // 0x6C FTM External Trigger
  POL                    : longWord;                   // 0x70 Channels Polarity
  FMS                    : longWord;                   // 0x74 Fault Mode Status
  FILTER                 : longWord;                   // 0x78 Input Capture Filter Control
  FLTCTRL                : longWord;                   // 0x7C Fault Control
  QDCTRL                 : longWord;                   // 0x80 Quadrature Decoder Control and Status
  CONF                   : longWord;                   // 0x84 Configuration
  FLTPOL                 : longWord;                   // 0x88 FTM Fault Input Polarity
  SYNCONF                : longWord;                   // 0x8C Synchronization Configuration
  INVCTRL                : longWord;                   // 0x90 FTM Inverting Control
  SWOCTRL                : longWord;                   // 0x94 FTM Software Output Control
  PWMLOAD                : longWord;                   // 0x98 FTM PWM Load
);
true : (
SC_bits                  : TFTM2_SC_bits;              // 0x04 Status and Control
CNT_bits                 : TFTM2_CNT_bits;             // 0x08 Counter
MOD_bits                 : TFTM2_MOD_bits;             // 0x0C Modulo
C0SC_bits                : longWord;                   // 0x0C Channel (n) Status and Control
C0V_bits                 : longWord;                   // 0x10 Channel (n) Value
C1SC_bits                : longWord;                   // 0x14 Channel (n) Status and Control
C1V_bits                 : longWord;                   // 0x18 Channel (n) Value
RESERVED_bits0           : array[0..11] of longWord;
CNTIN_bits               : TFTM2_CNTIN_bits;           // 0x50 Counter Initial Value
STATUS_bits              : TFTM2_STATUS_bits;          // 0x54 Capture and Compare Status
MODE_bits                : TFTM2_MODE_bits;            // 0x58 Features Mode Selection
SYNC_bits                : TFTM2_SYNC_bits;            // 0x5C Synchronization
OUTINIT_bits             : TFTM2_OUTINIT_bits;         // 0x60 Initial State for Channels Output
OUTMASK_bits             : TFTM2_OUTMASK_bits;         // 0x64 Output Mask
COMBINE_bits             : TFTM2_COMBINE_bits;         // 0x68 Function for Linked Channels
DEADTIME_bits            : TFTM2_DEADTIME_bits;        // 0x6C Deadtime Insertion Control
EXTTRIG_bits             : TFTM2_EXTTRIG_bits;         // 0x70 FTM External Trigger
POL_bits                 : TFTM2_POL_bits;             // 0x74 Channels Polarity
FMS_bits                 : TFTM2_FMS_bits;             // 0x78 Fault Mode Status
FILTER_bits              : TFTM2_FILTER_bits;          // 0x7C Input Capture Filter Control
FLTCTRL_bits             : TFTM2_FLTCTRL_bits;         // 0x80 Fault Control
QDCTRL_bits              : TFTM2_QDCTRL_bits;          // 0x84 Quadrature Decoder Control and Status
CONF_bits                : TFTM2_CONF_bits;            // 0x88 Configuration
FLTPOL_bits              : TFTM2_FLTPOL_bits;          // 0x8C FTM Fault Input Polarity
SYNCONF_bits             : TFTM2_SYNCONF_bits;         // 0x90 Synchronization Configuration
INVCTRL_bits             : TFTM2_INVCTRL_bits;         // 0x94 FTM Inverting Control
SWOCTRL_bits             : TFTM2_SWOCTRL_bits;         // 0x98 FTM Software Output Control
PWMLOAD_bits             : TFTM2_PWMLOAD_bits;         // 0x9C FTM PWM Load
);
end;

TFTM2Registers_bitbanded = record
  SC                     : TFTM2_SC_bitbanded;         // 0x04 Status and Control
  CNT                    : TFTM2_CNT_bitbanded;        // 0x08 Counter
  &MOD                   : TFTM2_MOD_bitbanded;        // 0x0C Modulo
  C0SC_bitbanded         : longWord;                   // 0x0C Channel (n) Status and Control
  C0V_bitbanded          : longWord;                   // 0x10 Channel (n) Value
  C1SC_bitbanded         : longWord;                   // 0x14 Channel (n) Status and Control
  C1V_bitbanded          : longWord;                   // 0x18 Channel (n) Value
  RESERVED0              : array[0..47] of array[0..7] of longWord;
  CNTIN                  : TFTM2_CNTIN_bitbanded;      // 0x50 Counter Initial Value
  STATUS                 : TFTM2_STATUS_bitbanded;     // 0x54 Capture and Compare Status
  MODE                   : TFTM2_MODE_bitbanded;       // 0x58 Features Mode Selection
  SYNC                   : TFTM2_SYNC_bitbanded;       // 0x5C Synchronization
  OUTINIT                : TFTM2_OUTINIT_bitbanded;    // 0x60 Initial State for Channels Output
  OUTMASK                : TFTM2_OUTMASK_bitbanded;    // 0x64 Output Mask
  COMBINE                : TFTM2_COMBINE_bitbanded;    // 0x68 Function for Linked Channels
  DEADTIME               : TFTM2_DEADTIME_bitbanded;   // 0x6C Deadtime Insertion Control
  EXTTRIG                : TFTM2_EXTTRIG_bitbanded;    // 0x70 FTM External Trigger
  POL                    : TFTM2_POL_bitbanded;        // 0x74 Channels Polarity
  FMS                    : TFTM2_FMS_bitbanded;        // 0x78 Fault Mode Status
  FILTER                 : TFTM2_FILTER_bitbanded;     // 0x7C Input Capture Filter Control
  FLTCTRL                : TFTM2_FLTCTRL_bitbanded;    // 0x80 Fault Control
  QDCTRL                 : TFTM2_QDCTRL_bitbanded;     // 0x84 Quadrature Decoder Control and Status
  CONF                   : TFTM2_CONF_bitbanded;       // 0x88 Configuration
  FLTPOL                 : TFTM2_FLTPOL_bitbanded;     // 0x8C FTM Fault Input Polarity
  SYNCONF                : TFTM2_SYNCONF_bitbanded;    // 0x90 Synchronization Configuration
  INVCTRL                : TFTM2_INVCTRL_bitbanded;    // 0x94 FTM Inverting Control
  SWOCTRL                : TFTM2_SWOCTRL_bitbanded;    // 0x98 FTM Software Output Control
  PWMLOAD                : TFTM2_PWMLOAD_bitbanded;    // 0x9C FTM PWM Load
end;

// General Purpose Input/Output
TPTA_PDOR_bits = bitpacked record
  PDO                    : TBits_32;                   // [0:31] Port Data Output
end;

TPTA_PDOR_bitbanded = record
  PDO                    : array[0..31] of longWord;   // [0:31] Port Data Output
end;

TPTA_PSOR_bits = bitpacked record
  PTSO                   : TBits_32;                   // [0:31] Port Set Output
end;

TPTA_PSOR_bitbanded = record
  PTSO                   : array[0..31] of longWord;   // [0:31] Port Set Output
end;

TPTA_PCOR_bits = bitpacked record
  PTCO                   : TBits_32;                   // [0:31] Port Clear Output
end;

TPTA_PCOR_bitbanded = record
  PTCO                   : array[0..31] of longWord;   // [0:31] Port Clear Output
end;

TPTA_PTOR_bits = bitpacked record
  PTTO                   : TBits_32;                   // [0:31] Port Toggle Output
end;

TPTA_PTOR_bitbanded = record
  PTTO                   : array[0..31] of longWord;   // [0:31] Port Toggle Output
end;

TPTA_PDIR_bits = bitpacked record
  PDI                    : TBits_32;                   // [0:31] Port Data Input
end;

TPTA_PDIR_bitbanded = record
  PDI                    : array[0..31] of longWord;   // [0:31] Port Data Input
end;

TPTA_PDDR_bits = bitpacked record
  PDD                    : TBits_32;                   // [0:31] Port data direction
end;

TPTA_PDDR_bitbanded = record
  PDD                    : array[0..31] of longWord;   // [0:31] Port data direction
end;

TPTA_Registers = record
  case boolean of false: (
  PDOR                   : longWord;                   // 0x00 Port Data Output Register
  PSOR                   : longWord;                   // 0x04 Port Set Output Register
  PCOR                   : longWord;                   // 0x08 Port Clear Output Register
  PTOR                   : longWord;                   // 0x0C Port Toggle Output Register
  PDIR                   : longWord;                   // 0x10 Port Data Input Register
  PDDR                   : longWord;                   // 0x14 Port Data Direction Register
);
true : (
PDOR_bits                : TPTA_PDOR_bits;             // 0x04 Port Data Output Register
PSOR_bits                : TPTA_PSOR_bits;             // 0x08 Port Set Output Register
PCOR_bits                : TPTA_PCOR_bits;             // 0x0C Port Clear Output Register
PTOR_bits                : TPTA_PTOR_bits;             // 0x10 Port Toggle Output Register
PDIR_bits                : TPTA_PDIR_bits;             // 0x14 Port Data Input Register
PDDR_bits                : TPTA_PDDR_bits;             // 0x18 Port Data Direction Register
);
end;

TPTARegisters_bitbanded = record
  PDOR                   : TPTA_PDOR_bitbanded;        // 0x04 Port Data Output Register
  PSOR                   : TPTA_PSOR_bitbanded;        // 0x08 Port Set Output Register
  PCOR                   : TPTA_PCOR_bitbanded;        // 0x0C Port Clear Output Register
  PTOR                   : TPTA_PTOR_bitbanded;        // 0x10 Port Toggle Output Register
  PDIR                   : TPTA_PDIR_bitbanded;        // 0x14 Port Data Input Register
  PDDR                   : TPTA_PDDR_bitbanded;        // 0x18 Port Data Direction Register
end;

// General Purpose Input/Output
TPTB_PDOR_bits = bitpacked record
  PDO                    : TBits_32;                   // [0:31] Port Data Output
end;

TPTB_PDOR_bitbanded = record
  PDO                    : array[0..31] of longWord;   // [0:31] Port Data Output
end;

TPTB_PSOR_bits = bitpacked record
  PTSO                   : TBits_32;                   // [0:31] Port Set Output
end;

TPTB_PSOR_bitbanded = record
  PTSO                   : array[0..31] of longWord;   // [0:31] Port Set Output
end;

TPTB_PCOR_bits = bitpacked record
  PTCO                   : TBits_32;                   // [0:31] Port Clear Output
end;

TPTB_PCOR_bitbanded = record
  PTCO                   : array[0..31] of longWord;   // [0:31] Port Clear Output
end;

TPTB_PTOR_bits = bitpacked record
  PTTO                   : TBits_32;                   // [0:31] Port Toggle Output
end;

TPTB_PTOR_bitbanded = record
  PTTO                   : array[0..31] of longWord;   // [0:31] Port Toggle Output
end;

TPTB_PDIR_bits = bitpacked record
  PDI                    : TBits_32;                   // [0:31] Port Data Input
end;

TPTB_PDIR_bitbanded = record
  PDI                    : array[0..31] of longWord;   // [0:31] Port Data Input
end;

TPTB_PDDR_bits = bitpacked record
  PDD                    : TBits_32;                   // [0:31] Port data direction
end;

TPTB_PDDR_bitbanded = record
  PDD                    : array[0..31] of longWord;   // [0:31] Port data direction
end;

TPTB_Registers = record
  case boolean of false: (
  PDOR                   : longWord;                   // 0x00 Port Data Output Register
  PSOR                   : longWord;                   // 0x04 Port Set Output Register
  PCOR                   : longWord;                   // 0x08 Port Clear Output Register
  PTOR                   : longWord;                   // 0x0C Port Toggle Output Register
  PDIR                   : longWord;                   // 0x10 Port Data Input Register
  PDDR                   : longWord;                   // 0x14 Port Data Direction Register
);
true : (
PDOR_bits                : TPTB_PDOR_bits;             // 0x04 Port Data Output Register
PSOR_bits                : TPTB_PSOR_bits;             // 0x08 Port Set Output Register
PCOR_bits                : TPTB_PCOR_bits;             // 0x0C Port Clear Output Register
PTOR_bits                : TPTB_PTOR_bits;             // 0x10 Port Toggle Output Register
PDIR_bits                : TPTB_PDIR_bits;             // 0x14 Port Data Input Register
PDDR_bits                : TPTB_PDDR_bits;             // 0x18 Port Data Direction Register
);
end;

TPTBRegisters_bitbanded = record
  PDOR                   : TPTB_PDOR_bitbanded;        // 0x04 Port Data Output Register
  PSOR                   : TPTB_PSOR_bitbanded;        // 0x08 Port Set Output Register
  PCOR                   : TPTB_PCOR_bitbanded;        // 0x0C Port Clear Output Register
  PTOR                   : TPTB_PTOR_bitbanded;        // 0x10 Port Toggle Output Register
  PDIR                   : TPTB_PDIR_bitbanded;        // 0x14 Port Data Input Register
  PDDR                   : TPTB_PDDR_bitbanded;        // 0x18 Port Data Direction Register
end;

// General Purpose Input/Output
TPTC_PDOR_bits = bitpacked record
  PDO                    : TBits_32;                   // [0:31] Port Data Output
end;

TPTC_PDOR_bitbanded = record
  PDO                    : array[0..31] of longWord;   // [0:31] Port Data Output
end;

TPTC_PSOR_bits = bitpacked record
  PTSO                   : TBits_32;                   // [0:31] Port Set Output
end;

TPTC_PSOR_bitbanded = record
  PTSO                   : array[0..31] of longWord;   // [0:31] Port Set Output
end;

TPTC_PCOR_bits = bitpacked record
  PTCO                   : TBits_32;                   // [0:31] Port Clear Output
end;

TPTC_PCOR_bitbanded = record
  PTCO                   : array[0..31] of longWord;   // [0:31] Port Clear Output
end;

TPTC_PTOR_bits = bitpacked record
  PTTO                   : TBits_32;                   // [0:31] Port Toggle Output
end;

TPTC_PTOR_bitbanded = record
  PTTO                   : array[0..31] of longWord;   // [0:31] Port Toggle Output
end;

TPTC_PDIR_bits = bitpacked record
  PDI                    : TBits_32;                   // [0:31] Port Data Input
end;

TPTC_PDIR_bitbanded = record
  PDI                    : array[0..31] of longWord;   // [0:31] Port Data Input
end;

TPTC_PDDR_bits = bitpacked record
  PDD                    : TBits_32;                   // [0:31] Port data direction
end;

TPTC_PDDR_bitbanded = record
  PDD                    : array[0..31] of longWord;   // [0:31] Port data direction
end;

TPTC_Registers = record
  case boolean of false: (
  PDOR                   : longWord;                   // 0x00 Port Data Output Register
  PSOR                   : longWord;                   // 0x04 Port Set Output Register
  PCOR                   : longWord;                   // 0x08 Port Clear Output Register
  PTOR                   : longWord;                   // 0x0C Port Toggle Output Register
  PDIR                   : longWord;                   // 0x10 Port Data Input Register
  PDDR                   : longWord;                   // 0x14 Port Data Direction Register
);
true : (
PDOR_bits                : TPTC_PDOR_bits;             // 0x04 Port Data Output Register
PSOR_bits                : TPTC_PSOR_bits;             // 0x08 Port Set Output Register
PCOR_bits                : TPTC_PCOR_bits;             // 0x0C Port Clear Output Register
PTOR_bits                : TPTC_PTOR_bits;             // 0x10 Port Toggle Output Register
PDIR_bits                : TPTC_PDIR_bits;             // 0x14 Port Data Input Register
PDDR_bits                : TPTC_PDDR_bits;             // 0x18 Port Data Direction Register
);
end;

TPTCRegisters_bitbanded = record
  PDOR                   : TPTC_PDOR_bitbanded;        // 0x04 Port Data Output Register
  PSOR                   : TPTC_PSOR_bitbanded;        // 0x08 Port Set Output Register
  PCOR                   : TPTC_PCOR_bitbanded;        // 0x0C Port Clear Output Register
  PTOR                   : TPTC_PTOR_bitbanded;        // 0x10 Port Toggle Output Register
  PDIR                   : TPTC_PDIR_bitbanded;        // 0x14 Port Data Input Register
  PDDR                   : TPTC_PDDR_bitbanded;        // 0x18 Port Data Direction Register
end;

// General Purpose Input/Output
TPTD_PDOR_bits = bitpacked record
  PDO                    : TBits_32;                   // [0:31] Port Data Output
end;

TPTD_PDOR_bitbanded = record
  PDO                    : array[0..31] of longWord;   // [0:31] Port Data Output
end;

TPTD_PSOR_bits = bitpacked record
  PTSO                   : TBits_32;                   // [0:31] Port Set Output
end;

TPTD_PSOR_bitbanded = record
  PTSO                   : array[0..31] of longWord;   // [0:31] Port Set Output
end;

TPTD_PCOR_bits = bitpacked record
  PTCO                   : TBits_32;                   // [0:31] Port Clear Output
end;

TPTD_PCOR_bitbanded = record
  PTCO                   : array[0..31] of longWord;   // [0:31] Port Clear Output
end;

TPTD_PTOR_bits = bitpacked record
  PTTO                   : TBits_32;                   // [0:31] Port Toggle Output
end;

TPTD_PTOR_bitbanded = record
  PTTO                   : array[0..31] of longWord;   // [0:31] Port Toggle Output
end;

TPTD_PDIR_bits = bitpacked record
  PDI                    : TBits_32;                   // [0:31] Port Data Input
end;

TPTD_PDIR_bitbanded = record
  PDI                    : array[0..31] of longWord;   // [0:31] Port Data Input
end;

TPTD_PDDR_bits = bitpacked record
  PDD                    : TBits_32;                   // [0:31] Port data direction
end;

TPTD_PDDR_bitbanded = record
  PDD                    : array[0..31] of longWord;   // [0:31] Port data direction
end;

TPTD_Registers = record
  case boolean of false: (
  PDOR                   : longWord;                   // 0x00 Port Data Output Register
  PSOR                   : longWord;                   // 0x04 Port Set Output Register
  PCOR                   : longWord;                   // 0x08 Port Clear Output Register
  PTOR                   : longWord;                   // 0x0C Port Toggle Output Register
  PDIR                   : longWord;                   // 0x10 Port Data Input Register
  PDDR                   : longWord;                   // 0x14 Port Data Direction Register
);
true : (
PDOR_bits                : TPTD_PDOR_bits;             // 0x04 Port Data Output Register
PSOR_bits                : TPTD_PSOR_bits;             // 0x08 Port Set Output Register
PCOR_bits                : TPTD_PCOR_bits;             // 0x0C Port Clear Output Register
PTOR_bits                : TPTD_PTOR_bits;             // 0x10 Port Toggle Output Register
PDIR_bits                : TPTD_PDIR_bits;             // 0x14 Port Data Input Register
PDDR_bits                : TPTD_PDDR_bits;             // 0x18 Port Data Direction Register
);
end;

TPTDRegisters_bitbanded = record
  PDOR                   : TPTD_PDOR_bitbanded;        // 0x04 Port Data Output Register
  PSOR                   : TPTD_PSOR_bitbanded;        // 0x08 Port Set Output Register
  PCOR                   : TPTD_PCOR_bitbanded;        // 0x0C Port Clear Output Register
  PTOR                   : TPTD_PTOR_bitbanded;        // 0x10 Port Toggle Output Register
  PDIR                   : TPTD_PDIR_bitbanded;        // 0x14 Port Data Input Register
  PDDR                   : TPTD_PDDR_bitbanded;        // 0x18 Port Data Direction Register
end;

// General Purpose Input/Output
TPTE_PDOR_bits = bitpacked record
  PDO                    : TBits_32;                   // [0:31] Port Data Output
end;

TPTE_PDOR_bitbanded = record
  PDO                    : array[0..31] of longWord;   // [0:31] Port Data Output
end;

TPTE_PSOR_bits = bitpacked record
  PTSO                   : TBits_32;                   // [0:31] Port Set Output
end;

TPTE_PSOR_bitbanded = record
  PTSO                   : array[0..31] of longWord;   // [0:31] Port Set Output
end;

TPTE_PCOR_bits = bitpacked record
  PTCO                   : TBits_32;                   // [0:31] Port Clear Output
end;

TPTE_PCOR_bitbanded = record
  PTCO                   : array[0..31] of longWord;   // [0:31] Port Clear Output
end;

TPTE_PTOR_bits = bitpacked record
  PTTO                   : TBits_32;                   // [0:31] Port Toggle Output
end;

TPTE_PTOR_bitbanded = record
  PTTO                   : array[0..31] of longWord;   // [0:31] Port Toggle Output
end;

TPTE_PDIR_bits = bitpacked record
  PDI                    : TBits_32;                   // [0:31] Port Data Input
end;

TPTE_PDIR_bitbanded = record
  PDI                    : array[0..31] of longWord;   // [0:31] Port Data Input
end;

TPTE_PDDR_bits = bitpacked record
  PDD                    : TBits_32;                   // [0:31] Port data direction
end;

TPTE_PDDR_bitbanded = record
  PDD                    : array[0..31] of longWord;   // [0:31] Port data direction
end;

TPTE_Registers = record
  case boolean of false: (
  PDOR                   : longWord;                   // 0x00 Port Data Output Register
  PSOR                   : longWord;                   // 0x04 Port Set Output Register
  PCOR                   : longWord;                   // 0x08 Port Clear Output Register
  PTOR                   : longWord;                   // 0x0C Port Toggle Output Register
  PDIR                   : longWord;                   // 0x10 Port Data Input Register
  PDDR                   : longWord;                   // 0x14 Port Data Direction Register
);
true : (
PDOR_bits                : TPTE_PDOR_bits;             // 0x04 Port Data Output Register
PSOR_bits                : TPTE_PSOR_bits;             // 0x08 Port Set Output Register
PCOR_bits                : TPTE_PCOR_bits;             // 0x0C Port Clear Output Register
PTOR_bits                : TPTE_PTOR_bits;             // 0x10 Port Toggle Output Register
PDIR_bits                : TPTE_PDIR_bits;             // 0x14 Port Data Input Register
PDDR_bits                : TPTE_PDDR_bits;             // 0x18 Port Data Direction Register
);
end;

TPTERegisters_bitbanded = record
  PDOR                   : TPTE_PDOR_bitbanded;        // 0x04 Port Data Output Register
  PSOR                   : TPTE_PSOR_bitbanded;        // 0x08 Port Set Output Register
  PCOR                   : TPTE_PCOR_bitbanded;        // 0x0C Port Clear Output Register
  PTOR                   : TPTE_PTOR_bitbanded;        // 0x10 Port Toggle Output Register
  PDIR                   : TPTE_PDIR_bitbanded;        // 0x14 Port Data Input Register
  PDDR                   : TPTE_PDDR_bitbanded;        // 0x18 Port Data Direction Register
end;

// Inter-Integrated Circuit
TI2C0_A1_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] no description available
  AD                     : TBits_7;                    // [1:7] Address
end;

TI2C0_A1_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] no description available
  AD                     : array[0..6] of longWord;    // [1:7] Address
end;

TI2C0_F_bits = bitpacked record
  ICR                    : TBits_6;                    // [0:5] Clock rate
  MULT                   : TBits_2;                    // [6:7] no description available
end;

TI2C0_F_bitbanded = record
  ICR                    : array[0..5] of longWord;    // [0:5] Clock rate
  MULT                   : array[0..1] of longWord;    // [6:7] no description available
end;

TI2C0_C1_bits = bitpacked record
  DMAEN                  : TBits_1;                    // [0:0] DMA enable
  WUEN                   : TBits_1;                    // [1:1] Wakeup enable
  RSTA                   : TBits_1;                    // [2:2] Repeat START
  TXAK                   : TBits_1;                    // [3:3] Transmit acknowledge enable
  TX                     : TBits_1;                    // [4:4] Transmit mode select
  MST                    : TBits_1;                    // [5:5] Master mode select
  IICIE                  : TBits_1;                    // [6:6] I2C interrupt enable
  IICEN                  : TBits_1;                    // [7:7] I2C enable
end;

TI2C0_C1_bitbanded = record
  DMAEN                  : longWord;                   // [0:0] DMA enable
  WUEN                   : longWord;                   // [1:1] Wakeup enable
  RSTA                   : longWord;                   // [2:2] Repeat START
  TXAK                   : longWord;                   // [3:3] Transmit acknowledge enable
  TX                     : longWord;                   // [4:4] Transmit mode select
  MST                    : longWord;                   // [5:5] Master mode select
  IICIE                  : longWord;                   // [6:6] I2C interrupt enable
  IICEN                  : longWord;                   // [7:7] I2C enable
end;

TI2C0_S_bits = bitpacked record
  RXAK                   : TBits_1;                    // [0:0] Receive acknowledge
  IICIF                  : TBits_1;                    // [1:1] Interrupt flag
  SRW                    : TBits_1;                    // [2:2] Slave read/write
  RAM                    : TBits_1;                    // [3:3] Range address match
  ARBL                   : TBits_1;                    // [4:4] Arbitration lost
  BUSY                   : TBits_1;                    // [5:5] Bus busy
  IAAS                   : TBits_1;                    // [6:6] Addressed as a slave
  TCF                    : TBits_1;                    // [7:7] Transfer complete flag
end;

TI2C0_S_bitbanded = record
  RXAK                   : longWord;                   // [0:0] Receive acknowledge
  IICIF                  : longWord;                   // [1:1] Interrupt flag
  SRW                    : longWord;                   // [2:2] Slave read/write
  RAM                    : longWord;                   // [3:3] Range address match
  ARBL                   : longWord;                   // [4:4] Arbitration lost
  BUSY                   : longWord;                   // [5:5] Bus busy
  IAAS                   : longWord;                   // [6:6] Addressed as a slave
  TCF                    : longWord;                   // [7:7] Transfer complete flag
end;

TI2C0_D_bits = bitpacked record
  DATA                   : TBits_8;                    // [0:7] Data
end;

TI2C0_D_bitbanded = record
  DATA                   : array[0..7] of longWord;    // [0:7] Data
end;

TI2C0_C2_bits = bitpacked record
  AD                     : TBits_3;                    // [0:2] Slave address
  RMEN                   : TBits_1;                    // [3:3] Range address matching enable
  SBRC                   : TBits_1;                    // [4:4] Slave baud rate control
  HDRS                   : TBits_1;                    // [5:5] High drive select
  ADEXT                  : TBits_1;                    // [6:6] Address extension
  GCAEN                  : TBits_1;                    // [7:7] General call address enable
end;

TI2C0_C2_bitbanded = record
  AD                     : array[0..2] of longWord;    // [0:2] Slave address
  RMEN                   : longWord;                   // [3:3] Range address matching enable
  SBRC                   : longWord;                   // [4:4] Slave baud rate control
  HDRS                   : longWord;                   // [5:5] High drive select
  ADEXT                  : longWord;                   // [6:6] Address extension
  GCAEN                  : longWord;                   // [7:7] General call address enable
end;

TI2C0_FLT_bits = bitpacked record
  FLT                    : TBits_5;                    // [0:4] I2C programmable filter factor
  RESERVED0              : TBits_2;                    // [5:6] no description available
  RESERVED1              : TBits_1;                    // [7:7] no description available
end;

TI2C0_FLT_bitbanded = record
  FLT                    : array[0..4] of longWord;    // [0:4] I2C programmable filter factor
  RESERVED0              : array[0..1] of longWord;    // [5:6] no description available
  RESERVED1              : longWord;                   // [7:7] no description available
end;

TI2C0_RA_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] no description available
  RAD                    : TBits_7;                    // [1:7] Range slave address
end;

TI2C0_RA_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] no description available
  RAD                    : array[0..6] of longWord;    // [1:7] Range slave address
end;

TI2C0_SMB_bits = bitpacked record
  SHTF2IE                : TBits_1;                    // [0:0] SHTF2 interrupt enable
  SHTF2                  : TBits_1;                    // [1:1] SCL high timeout flag 2
  SHTF1                  : TBits_1;                    // [2:2] SCL high timeout flag 1
  SLTF                   : TBits_1;                    // [3:3] SCL low timeout flag
  TCKSEL                 : TBits_1;                    // [4:4] Timeout counter clock select
  SIICAEN                : TBits_1;                    // [5:5] Second I2C address enable
  ALERTEN                : TBits_1;                    // [6:6] SMBus alert response address enable
  FACK                   : TBits_1;                    // [7:7] Fast NACK/ACK enable
end;

TI2C0_SMB_bitbanded = record
  SHTF2IE                : longWord;                   // [0:0] SHTF2 interrupt enable
  SHTF2                  : longWord;                   // [1:1] SCL high timeout flag 2
  SHTF1                  : longWord;                   // [2:2] SCL high timeout flag 1
  SLTF                   : longWord;                   // [3:3] SCL low timeout flag
  TCKSEL                 : longWord;                   // [4:4] Timeout counter clock select
  SIICAEN                : longWord;                   // [5:5] Second I2C address enable
  ALERTEN                : longWord;                   // [6:6] SMBus alert response address enable
  FACK                   : longWord;                   // [7:7] Fast NACK/ACK enable
end;

TI2C0_A2_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] no description available
  SAD                    : TBits_7;                    // [1:7] SMBus address
end;

TI2C0_A2_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] no description available
  SAD                    : array[0..6] of longWord;    // [1:7] SMBus address
end;

TI2C0_SLTH_bits = bitpacked record
  SSLT                   : TBits_8;                    // [0:7] no description available
end;

TI2C0_SLTH_bitbanded = record
  SSLT                   : array[0..7] of longWord;    // [0:7] no description available
end;

TI2C0_SLTL_bits = bitpacked record
  SSLT                   : TBits_8;                    // [0:7] no description available
end;

TI2C0_SLTL_bitbanded = record
  SSLT                   : array[0..7] of longWord;    // [0:7] no description available
end;

TI2C0_Registers = record
  case boolean of false: (
  A1                     : byte;                       // 0x00 I2C Address Register 1
  F                      : byte;                       // 0x01 I2C Frequency Divider register
  C1                     : byte;                       // 0x02 I2C Control Register 1
  S                      : byte;                       // 0x03 I2C Status Register
  D                      : byte;                       // 0x04 I2C Data I/O register
  C2                     : byte;                       // 0x05 I2C Control Register 2
  FLT                    : byte;                       // 0x06 I2C Programmable Input Glitch Filter register
  RA                     : byte;                       // 0x07 I2C Range Address register
  SMB                    : byte;                       // 0x08 I2C SMBus Control and Status register
  A2                     : byte;                       // 0x09 I2C Address Register 2
  SLTH                   : byte;                       // 0x0A I2C SCL Low Timeout Register High
  SLTL                   : byte;                       // 0x0B I2C SCL Low Timeout Register Low
);
true : (
A1_bits                  : TI2C0_A1_bits;              // 0x01 I2C Address Register 1
F_bits                   : TI2C0_F_bits;               // 0x02 I2C Frequency Divider register
C1_bits                  : TI2C0_C1_bits;              // 0x03 I2C Control Register 1
S_bits                   : TI2C0_S_bits;               // 0x04 I2C Status Register
D_bits                   : TI2C0_D_bits;               // 0x05 I2C Data I/O register
C2_bits                  : TI2C0_C2_bits;              // 0x06 I2C Control Register 2
FLT_bits                 : TI2C0_FLT_bits;             // 0x07 I2C Programmable Input Glitch Filter register
RA_bits                  : TI2C0_RA_bits;              // 0x08 I2C Range Address register
SMB_bits                 : TI2C0_SMB_bits;             // 0x09 I2C SMBus Control and Status register
A2_bits                  : TI2C0_A2_bits;              // 0x0A I2C Address Register 2
SLTH_bits                : TI2C0_SLTH_bits;            // 0x0B I2C SCL Low Timeout Register High
SLTL_bits                : TI2C0_SLTL_bits;            // 0x0C I2C SCL Low Timeout Register Low
);
end;

TI2C0Registers_bitbanded = record
  A1                     : TI2C0_A1_bitbanded;         // 0x01 I2C Address Register 1
  F                      : TI2C0_F_bitbanded;          // 0x02 I2C Frequency Divider register
  C1                     : TI2C0_C1_bitbanded;         // 0x03 I2C Control Register 1
  S                      : TI2C0_S_bitbanded;          // 0x04 I2C Status Register
  D                      : TI2C0_D_bitbanded;          // 0x05 I2C Data I/O register
  C2                     : TI2C0_C2_bitbanded;         // 0x06 I2C Control Register 2
  FLT                    : TI2C0_FLT_bitbanded;        // 0x07 I2C Programmable Input Glitch Filter register
  RA                     : TI2C0_RA_bitbanded;         // 0x08 I2C Range Address register
  SMB                    : TI2C0_SMB_bitbanded;        // 0x09 I2C SMBus Control and Status register
  A2                     : TI2C0_A2_bitbanded;         // 0x0A I2C Address Register 2
  SLTH                   : TI2C0_SLTH_bitbanded;       // 0x0B I2C SCL Low Timeout Register High
  SLTL                   : TI2C0_SLTL_bitbanded;       // 0x0C I2C SCL Low Timeout Register Low
end;

// Inter-Integrated Circuit
TI2C1_A1_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] no description available
  AD                     : TBits_7;                    // [1:7] Address
end;

TI2C1_A1_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] no description available
  AD                     : array[0..6] of longWord;    // [1:7] Address
end;

TI2C1_F_bits = bitpacked record
  ICR                    : TBits_6;                    // [0:5] Clock rate
  MULT                   : TBits_2;                    // [6:7] no description available
end;

TI2C1_F_bitbanded = record
  ICR                    : array[0..5] of longWord;    // [0:5] Clock rate
  MULT                   : array[0..1] of longWord;    // [6:7] no description available
end;

TI2C1_C1_bits = bitpacked record
  DMAEN                  : TBits_1;                    // [0:0] DMA enable
  WUEN                   : TBits_1;                    // [1:1] Wakeup enable
  RSTA                   : TBits_1;                    // [2:2] Repeat START
  TXAK                   : TBits_1;                    // [3:3] Transmit acknowledge enable
  TX                     : TBits_1;                    // [4:4] Transmit mode select
  MST                    : TBits_1;                    // [5:5] Master mode select
  IICIE                  : TBits_1;                    // [6:6] I2C interrupt enable
  IICEN                  : TBits_1;                    // [7:7] I2C enable
end;

TI2C1_C1_bitbanded = record
  DMAEN                  : longWord;                   // [0:0] DMA enable
  WUEN                   : longWord;                   // [1:1] Wakeup enable
  RSTA                   : longWord;                   // [2:2] Repeat START
  TXAK                   : longWord;                   // [3:3] Transmit acknowledge enable
  TX                     : longWord;                   // [4:4] Transmit mode select
  MST                    : longWord;                   // [5:5] Master mode select
  IICIE                  : longWord;                   // [6:6] I2C interrupt enable
  IICEN                  : longWord;                   // [7:7] I2C enable
end;

TI2C1_S_bits = bitpacked record
  RXAK                   : TBits_1;                    // [0:0] Receive acknowledge
  IICIF                  : TBits_1;                    // [1:1] Interrupt flag
  SRW                    : TBits_1;                    // [2:2] Slave read/write
  RAM                    : TBits_1;                    // [3:3] Range address match
  ARBL                   : TBits_1;                    // [4:4] Arbitration lost
  BUSY                   : TBits_1;                    // [5:5] Bus busy
  IAAS                   : TBits_1;                    // [6:6] Addressed as a slave
  TCF                    : TBits_1;                    // [7:7] Transfer complete flag
end;

TI2C1_S_bitbanded = record
  RXAK                   : longWord;                   // [0:0] Receive acknowledge
  IICIF                  : longWord;                   // [1:1] Interrupt flag
  SRW                    : longWord;                   // [2:2] Slave read/write
  RAM                    : longWord;                   // [3:3] Range address match
  ARBL                   : longWord;                   // [4:4] Arbitration lost
  BUSY                   : longWord;                   // [5:5] Bus busy
  IAAS                   : longWord;                   // [6:6] Addressed as a slave
  TCF                    : longWord;                   // [7:7] Transfer complete flag
end;

TI2C1_D_bits = bitpacked record
  DATA                   : TBits_8;                    // [0:7] Data
end;

TI2C1_D_bitbanded = record
  DATA                   : array[0..7] of longWord;    // [0:7] Data
end;

TI2C1_C2_bits = bitpacked record
  AD                     : TBits_3;                    // [0:2] Slave address
  RMEN                   : TBits_1;                    // [3:3] Range address matching enable
  SBRC                   : TBits_1;                    // [4:4] Slave baud rate control
  HDRS                   : TBits_1;                    // [5:5] High drive select
  ADEXT                  : TBits_1;                    // [6:6] Address extension
  GCAEN                  : TBits_1;                    // [7:7] General call address enable
end;

TI2C1_C2_bitbanded = record
  AD                     : array[0..2] of longWord;    // [0:2] Slave address
  RMEN                   : longWord;                   // [3:3] Range address matching enable
  SBRC                   : longWord;                   // [4:4] Slave baud rate control
  HDRS                   : longWord;                   // [5:5] High drive select
  ADEXT                  : longWord;                   // [6:6] Address extension
  GCAEN                  : longWord;                   // [7:7] General call address enable
end;

TI2C1_FLT_bits = bitpacked record
  FLT                    : TBits_5;                    // [0:4] I2C programmable filter factor
  RESERVED0              : TBits_2;                    // [5:6] no description available
  RESERVED1              : TBits_1;                    // [7:7] no description available
end;

TI2C1_FLT_bitbanded = record
  FLT                    : array[0..4] of longWord;    // [0:4] I2C programmable filter factor
  RESERVED0              : array[0..1] of longWord;    // [5:6] no description available
  RESERVED1              : longWord;                   // [7:7] no description available
end;

TI2C1_RA_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] no description available
  RAD                    : TBits_7;                    // [1:7] Range slave address
end;

TI2C1_RA_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] no description available
  RAD                    : array[0..6] of longWord;    // [1:7] Range slave address
end;

TI2C1_SMB_bits = bitpacked record
  SHTF2IE                : TBits_1;                    // [0:0] SHTF2 interrupt enable
  SHTF2                  : TBits_1;                    // [1:1] SCL high timeout flag 2
  SHTF1                  : TBits_1;                    // [2:2] SCL high timeout flag 1
  SLTF                   : TBits_1;                    // [3:3] SCL low timeout flag
  TCKSEL                 : TBits_1;                    // [4:4] Timeout counter clock select
  SIICAEN                : TBits_1;                    // [5:5] Second I2C address enable
  ALERTEN                : TBits_1;                    // [6:6] SMBus alert response address enable
  FACK                   : TBits_1;                    // [7:7] Fast NACK/ACK enable
end;

TI2C1_SMB_bitbanded = record
  SHTF2IE                : longWord;                   // [0:0] SHTF2 interrupt enable
  SHTF2                  : longWord;                   // [1:1] SCL high timeout flag 2
  SHTF1                  : longWord;                   // [2:2] SCL high timeout flag 1
  SLTF                   : longWord;                   // [3:3] SCL low timeout flag
  TCKSEL                 : longWord;                   // [4:4] Timeout counter clock select
  SIICAEN                : longWord;                   // [5:5] Second I2C address enable
  ALERTEN                : longWord;                   // [6:6] SMBus alert response address enable
  FACK                   : longWord;                   // [7:7] Fast NACK/ACK enable
end;

TI2C1_A2_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] no description available
  SAD                    : TBits_7;                    // [1:7] SMBus address
end;

TI2C1_A2_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] no description available
  SAD                    : array[0..6] of longWord;    // [1:7] SMBus address
end;

TI2C1_SLTH_bits = bitpacked record
  SSLT                   : TBits_8;                    // [0:7] no description available
end;

TI2C1_SLTH_bitbanded = record
  SSLT                   : array[0..7] of longWord;    // [0:7] no description available
end;

TI2C1_SLTL_bits = bitpacked record
  SSLT                   : TBits_8;                    // [0:7] no description available
end;

TI2C1_SLTL_bitbanded = record
  SSLT                   : array[0..7] of longWord;    // [0:7] no description available
end;

TI2C1_Registers = record
  case boolean of false: (
  A1                     : byte;                       // 0x00 I2C Address Register 1
  F                      : byte;                       // 0x01 I2C Frequency Divider register
  C1                     : byte;                       // 0x02 I2C Control Register 1
  S                      : byte;                       // 0x03 I2C Status Register
  D                      : byte;                       // 0x04 I2C Data I/O register
  C2                     : byte;                       // 0x05 I2C Control Register 2
  FLT                    : byte;                       // 0x06 I2C Programmable Input Glitch Filter register
  RA                     : byte;                       // 0x07 I2C Range Address register
  SMB                    : byte;                       // 0x08 I2C SMBus Control and Status register
  A2                     : byte;                       // 0x09 I2C Address Register 2
  SLTH                   : byte;                       // 0x0A I2C SCL Low Timeout Register High
  SLTL                   : byte;                       // 0x0B I2C SCL Low Timeout Register Low
);
true : (
A1_bits                  : TI2C1_A1_bits;              // 0x01 I2C Address Register 1
F_bits                   : TI2C1_F_bits;               // 0x02 I2C Frequency Divider register
C1_bits                  : TI2C1_C1_bits;              // 0x03 I2C Control Register 1
S_bits                   : TI2C1_S_bits;               // 0x04 I2C Status Register
D_bits                   : TI2C1_D_bits;               // 0x05 I2C Data I/O register
C2_bits                  : TI2C1_C2_bits;              // 0x06 I2C Control Register 2
FLT_bits                 : TI2C1_FLT_bits;             // 0x07 I2C Programmable Input Glitch Filter register
RA_bits                  : TI2C1_RA_bits;              // 0x08 I2C Range Address register
SMB_bits                 : TI2C1_SMB_bits;             // 0x09 I2C SMBus Control and Status register
A2_bits                  : TI2C1_A2_bits;              // 0x0A I2C Address Register 2
SLTH_bits                : TI2C1_SLTH_bits;            // 0x0B I2C SCL Low Timeout Register High
SLTL_bits                : TI2C1_SLTL_bits;            // 0x0C I2C SCL Low Timeout Register Low
);
end;

TI2C1Registers_bitbanded = record
  A1                     : TI2C1_A1_bitbanded;         // 0x01 I2C Address Register 1
  F                      : TI2C1_F_bitbanded;          // 0x02 I2C Frequency Divider register
  C1                     : TI2C1_C1_bitbanded;         // 0x03 I2C Control Register 1
  S                      : TI2C1_S_bitbanded;          // 0x04 I2C Status Register
  D                      : TI2C1_D_bitbanded;          // 0x05 I2C Data I/O register
  C2                     : TI2C1_C2_bitbanded;         // 0x06 I2C Control Register 2
  FLT                    : TI2C1_FLT_bitbanded;        // 0x07 I2C Programmable Input Glitch Filter register
  RA                     : TI2C1_RA_bitbanded;         // 0x08 I2C Range Address register
  SMB                    : TI2C1_SMB_bitbanded;        // 0x09 I2C SMBus Control and Status register
  A2                     : TI2C1_A2_bitbanded;         // 0x0A I2C Address Register 2
  SLTH                   : TI2C1_SLTH_bitbanded;       // 0x0B I2C SCL Low Timeout Register High
  SLTL                   : TI2C1_SLTL_bitbanded;       // 0x0C I2C SCL Low Timeout Register Low
end;

// Inter-IC Sound / Synchronous Audio Interface
TI2S0_TCSR_bits = bitpacked record
  FRDE                   : TBits_1;                    // [0:0] FIFO request DMA enable
  FWDE                   : TBits_1;                    // [1:1] FIFO warning DMA enable
  RESERVED0              : TBits_3;                    // [2:4] no description available
  RESERVED1              : TBits_3;                    // [5:7] no description available
  FRIE                   : TBits_1;                    // [8:8] FIFO request interrupt enable
  FWIE                   : TBits_1;                    // [9:9] FIFO warning interrupt enable
  FEIE                   : TBits_1;                    // [10:10] FIFO error interrupt enable
  SEIE                   : TBits_1;                    // [11:11] Sync error interrupt enable
  WSIE                   : TBits_1;                    // [12:12] Word start interrupt enable
  RESERVED2              : TBits_3;                    // [13:15] no description available
  FRF                    : TBits_1;                    // [16:16] FIFO request flag
  FWF                    : TBits_1;                    // [17:17] FIFO warning flag
  FEF                    : TBits_1;                    // [18:18] FIFO error flag
  SEF                    : TBits_1;                    // [19:19] Sync error flag
  WSF                    : TBits_1;                    // [20:20] Word start flag
  RESERVED3              : TBits_3;                    // [21:23] no description available
  SR                     : TBits_1;                    // [24:24] Software reset
  FR                     : TBits_1;                    // [25:25] FIFO reset
  RESERVED4              : TBits_2;                    // [26:27] no description available
  BCE                    : TBits_1;                    // [28:28] Bit Clock Enable
  DBGE                   : TBits_1;                    // [29:29] Debug enable
  STOPE                  : TBits_1;                    // [30:30] Stop enable
  TE                     : TBits_1;                    // [31:31] Transmitter enable
end;

TI2S0_TCSR_bitbanded = record
  FRDE                   : longWord;                   // [0:0] FIFO request DMA enable
  FWDE                   : longWord;                   // [1:1] FIFO warning DMA enable
  RESERVED0              : array[0..2] of longWord;    // [2:4] no description available
  RESERVED1              : array[0..2] of longWord;    // [5:7] no description available
  FRIE                   : longWord;                   // [8:8] FIFO request interrupt enable
  FWIE                   : longWord;                   // [9:9] FIFO warning interrupt enable
  FEIE                   : longWord;                   // [10:10] FIFO error interrupt enable
  SEIE                   : longWord;                   // [11:11] Sync error interrupt enable
  WSIE                   : longWord;                   // [12:12] Word start interrupt enable
  RESERVED2              : array[0..2] of longWord;    // [13:15] no description available
  FRF                    : longWord;                   // [16:16] FIFO request flag
  FWF                    : longWord;                   // [17:17] FIFO warning flag
  FEF                    : longWord;                   // [18:18] FIFO error flag
  SEF                    : longWord;                   // [19:19] Sync error flag
  WSF                    : longWord;                   // [20:20] Word start flag
  RESERVED3              : array[0..2] of longWord;    // [21:23] no description available
  SR                     : longWord;                   // [24:24] Software reset
  FR                     : longWord;                   // [25:25] FIFO reset
  RESERVED4              : array[0..1] of longWord;    // [26:27] no description available
  BCE                    : longWord;                   // [28:28] Bit Clock Enable
  DBGE                   : longWord;                   // [29:29] Debug enable
  STOPE                  : longWord;                   // [30:30] Stop enable
  TE                     : longWord;                   // [31:31] Transmitter enable
end;

TI2S0_TCR1_bits = bitpacked record
  TFW                    : TBits_3;                    // [0:2] Transmit FIFO watermark
  RESERVED0              : TBits_29;                   // [3:31] no description available
end;

TI2S0_TCR1_bitbanded = record
  TFW                    : array[0..2] of longWord;    // [0:2] Transmit FIFO watermark
  RESERVED0              : array[0..28] of longWord;   // [3:31] no description available
end;

TI2S0_TCR2_bits = bitpacked record
  &DIV                   : TBits_8;                    // [0:7] Bit clock divide
  RESERVED0              : TBits_16;                   // [8:23] no description available
  BCD                    : TBits_1;                    // [24:24] Bit clock direction
  BCP                    : TBits_1;                    // [25:25] Bit clock polarity
  MSEL                   : TBits_2;                    // [26:27] MCLK Select
  BCI                    : TBits_1;                    // [28:28] Bit Clock Input
  BCS                    : TBits_1;                    // [29:29] Bit Clock Swap
  SYNC                   : TBits_2;                    // [30:31] Synchronous Mode
end;

TI2S0_TCR2_bitbanded = record
  &DIV                   : array[0..7] of longWord;    // [0:7] Bit clock divide
  RESERVED0              : array[0..15] of longWord;   // [8:23] no description available
  BCD                    : longWord;                   // [24:24] Bit clock direction
  BCP                    : longWord;                   // [25:25] Bit clock polarity
  MSEL                   : array[0..1] of longWord;    // [26:27] MCLK Select
  BCI                    : longWord;                   // [28:28] Bit Clock Input
  BCS                    : longWord;                   // [29:29] Bit Clock Swap
  SYNC                   : array[0..1] of longWord;    // [30:31] Synchronous Mode
end;

TI2S0_TCR3_bits = bitpacked record
  WDFL                   : TBits_5;                    // [0:4] Word flag configuration
  RESERVED0              : TBits_11;                   // [5:15] no description available
  TCE                    : TBits_2;                    // [16:17] Transmit channel enable
  RESERVED1              : TBits_14;                   // [18:31] no description available
end;

TI2S0_TCR3_bitbanded = record
  WDFL                   : array[0..4] of longWord;    // [0:4] Word flag configuration
  RESERVED0              : array[0..10] of longWord;   // [5:15] no description available
  TCE                    : array[0..1] of longWord;    // [16:17] Transmit channel enable
  RESERVED1              : array[0..13] of longWord;   // [18:31] no description available
end;

TI2S0_TCR4_bits = bitpacked record
  FSD                    : TBits_1;                    // [0:0] Frame sync direction
  FSP                    : TBits_1;                    // [1:1] Frame sync polarity
  RESERVED0              : TBits_1;                    // [2:2] no description available
  FSE                    : TBits_1;                    // [3:3] Frame sync early
  MF                     : TBits_1;                    // [4:4] MSB first
  RESERVED1              : TBits_3;                    // [5:7] no description available
  SYWD                   : TBits_5;                    // [8:12] Sync width
  RESERVED2              : TBits_3;                    // [13:15] no description available
  FRSZ                   : TBits_5;                    // [16:20] Frame size
  RESERVED3              : TBits_11;                   // [21:31] no description available
end;

TI2S0_TCR4_bitbanded = record
  FSD                    : longWord;                   // [0:0] Frame sync direction
  FSP                    : longWord;                   // [1:1] Frame sync polarity
  RESERVED0              : longWord;                   // [2:2] no description available
  FSE                    : longWord;                   // [3:3] Frame sync early
  MF                     : longWord;                   // [4:4] MSB first
  RESERVED1              : array[0..2] of longWord;    // [5:7] no description available
  SYWD                   : array[0..4] of longWord;    // [8:12] Sync width
  RESERVED2              : array[0..2] of longWord;    // [13:15] no description available
  FRSZ                   : array[0..4] of longWord;    // [16:20] Frame size
  RESERVED3              : array[0..10] of longWord;   // [21:31] no description available
end;

TI2S0_TCR5_bits = bitpacked record
  RESERVED0              : TBits_8;                    // [0:7] no description available
  FBT                    : TBits_5;                    // [8:12] First bit shifted
  RESERVED1              : TBits_3;                    // [13:15] no description available
  W0W                    : TBits_5;                    // [16:20] Word 0 width
  RESERVED2              : TBits_3;                    // [21:23] no description available
  WNW                    : TBits_5;                    // [24:28] Word N width
  RESERVED3              : TBits_3;                    // [29:31] no description available
end;

TI2S0_TCR5_bitbanded = record
  RESERVED0              : array[0..7] of longWord;    // [0:7] no description available
  FBT                    : array[0..4] of longWord;    // [8:12] First bit shifted
  RESERVED1              : array[0..2] of longWord;    // [13:15] no description available
  W0W                    : array[0..4] of longWord;    // [16:20] Word 0 width
  RESERVED2              : array[0..2] of longWord;    // [21:23] no description available
  WNW                    : array[0..4] of longWord;    // [24:28] Word N width
  RESERVED3              : array[0..2] of longWord;    // [29:31] no description available
end;

TI2S0_TDR_bits = bitpacked record
  TDR                    : TBits_32;                   // [0:31] Transmit data register
end;

TI2S0_TDR_bitbanded = record
  TDR                    : array[0..31] of longWord;   // [0:31] Transmit data register
end;

TI2S0_TFR_bits = bitpacked record
  RFP                    : TBits_4;                    // [0:3] Read FIFO pointer
  RESERVED0              : TBits_12;                   // [4:15] no description available
  WFP                    : TBits_4;                    // [16:19] Write FIFO pointer
  RESERVED1              : TBits_12;                   // [20:31] no description available
end;

TI2S0_TFR_bitbanded = record
  RFP                    : array[0..3] of longWord;    // [0:3] Read FIFO pointer
  RESERVED0              : array[0..11] of longWord;   // [4:15] no description available
  WFP                    : array[0..3] of longWord;    // [16:19] Write FIFO pointer
  RESERVED1              : array[0..11] of longWord;   // [20:31] no description available
end;

TI2S0_TMR_bits = bitpacked record
  TWM                    : TBits_32;                   // [0:31] Transmit word mask
end;

TI2S0_TMR_bitbanded = record
  TWM                    : array[0..31] of longWord;   // [0:31] Transmit word mask
end;

TI2S0_RCSR_bits = bitpacked record
  FRDE                   : TBits_1;                    // [0:0] FIFO request DMA enable
  FWDE                   : TBits_1;                    // [1:1] FIFO warning DMA enable
  RESERVED0              : TBits_3;                    // [2:4] no description available
  RESERVED1              : TBits_3;                    // [5:7] no description available
  FRIE                   : TBits_1;                    // [8:8] FIFO request interrupt enable
  FWIE                   : TBits_1;                    // [9:9] FIFO warning interrupt enable
  FEIE                   : TBits_1;                    // [10:10] FIFO error interrupt enable
  SEIE                   : TBits_1;                    // [11:11] Sync error interrupt enable
  WSIE                   : TBits_1;                    // [12:12] Word start interrupt enable
  RESERVED2              : TBits_3;                    // [13:15] no description available
  FRF                    : TBits_1;                    // [16:16] FIFO request flag
  FWF                    : TBits_1;                    // [17:17] FIFO warning flag
  FEF                    : TBits_1;                    // [18:18] FIFO error flag
  SEF                    : TBits_1;                    // [19:19] Sync error flag
  WSF                    : TBits_1;                    // [20:20] Word start flag
  RESERVED3              : TBits_3;                    // [21:23] no description available
  SR                     : TBits_1;                    // [24:24] Software reset
  FR                     : TBits_1;                    // [25:25] FIFO reset
  RESERVED4              : TBits_2;                    // [26:27] no description available
  BCE                    : TBits_1;                    // [28:28] Bit Clock enable
  DBGE                   : TBits_1;                    // [29:29] Debug enable
  STOPE                  : TBits_1;                    // [30:30] Stop enable
  RE                     : TBits_1;                    // [31:31] Receiver enable
end;

TI2S0_RCSR_bitbanded = record
  FRDE                   : longWord;                   // [0:0] FIFO request DMA enable
  FWDE                   : longWord;                   // [1:1] FIFO warning DMA enable
  RESERVED0              : array[0..2] of longWord;    // [2:4] no description available
  RESERVED1              : array[0..2] of longWord;    // [5:7] no description available
  FRIE                   : longWord;                   // [8:8] FIFO request interrupt enable
  FWIE                   : longWord;                   // [9:9] FIFO warning interrupt enable
  FEIE                   : longWord;                   // [10:10] FIFO error interrupt enable
  SEIE                   : longWord;                   // [11:11] Sync error interrupt enable
  WSIE                   : longWord;                   // [12:12] Word start interrupt enable
  RESERVED2              : array[0..2] of longWord;    // [13:15] no description available
  FRF                    : longWord;                   // [16:16] FIFO request flag
  FWF                    : longWord;                   // [17:17] FIFO warning flag
  FEF                    : longWord;                   // [18:18] FIFO error flag
  SEF                    : longWord;                   // [19:19] Sync error flag
  WSF                    : longWord;                   // [20:20] Word start flag
  RESERVED3              : array[0..2] of longWord;    // [21:23] no description available
  SR                     : longWord;                   // [24:24] Software reset
  FR                     : longWord;                   // [25:25] FIFO reset
  RESERVED4              : array[0..1] of longWord;    // [26:27] no description available
  BCE                    : longWord;                   // [28:28] Bit Clock enable
  DBGE                   : longWord;                   // [29:29] Debug enable
  STOPE                  : longWord;                   // [30:30] Stop enable
  RE                     : longWord;                   // [31:31] Receiver enable
end;

TI2S0_RCR1_bits = bitpacked record
  RFW                    : TBits_3;                    // [0:2] Receive FIFO watermark
  RESERVED0              : TBits_29;                   // [3:31] no description available
end;

TI2S0_RCR1_bitbanded = record
  RFW                    : array[0..2] of longWord;    // [0:2] Receive FIFO watermark
  RESERVED0              : array[0..28] of longWord;   // [3:31] no description available
end;

TI2S0_RCR2_bits = bitpacked record
  &DIV                   : TBits_8;                    // [0:7] Bit clock divide
  RESERVED0              : TBits_16;                   // [8:23] no description available
  BCD                    : TBits_1;                    // [24:24] Bit clock direction
  BCP                    : TBits_1;                    // [25:25] Bit clock polarity
  MSEL                   : TBits_2;                    // [26:27] MCLK Select
  BCI                    : TBits_1;                    // [28:28] Bit Clock Input
  BCS                    : TBits_1;                    // [29:29] Bit Clock Swap
  SYNC                   : TBits_2;                    // [30:31] Synchronous Mode
end;

TI2S0_RCR2_bitbanded = record
  &DIV                   : array[0..7] of longWord;    // [0:7] Bit clock divide
  RESERVED0              : array[0..15] of longWord;   // [8:23] no description available
  BCD                    : longWord;                   // [24:24] Bit clock direction
  BCP                    : longWord;                   // [25:25] Bit clock polarity
  MSEL                   : array[0..1] of longWord;    // [26:27] MCLK Select
  BCI                    : longWord;                   // [28:28] Bit Clock Input
  BCS                    : longWord;                   // [29:29] Bit Clock Swap
  SYNC                   : array[0..1] of longWord;    // [30:31] Synchronous Mode
end;

TI2S0_RCR3_bits = bitpacked record
  WDFL                   : TBits_5;                    // [0:4] Word flag configuration
  RESERVED0              : TBits_11;                   // [5:15] no description available
  RCE                    : TBits_2;                    // [16:17] Receive channel enable
  RESERVED1              : TBits_14;                   // [18:31] no description available
end;

TI2S0_RCR3_bitbanded = record
  WDFL                   : array[0..4] of longWord;    // [0:4] Word flag configuration
  RESERVED0              : array[0..10] of longWord;   // [5:15] no description available
  RCE                    : array[0..1] of longWord;    // [16:17] Receive channel enable
  RESERVED1              : array[0..13] of longWord;   // [18:31] no description available
end;

TI2S0_RCR4_bits = bitpacked record
  FSD                    : TBits_1;                    // [0:0] Frame sync direction
  FSP                    : TBits_1;                    // [1:1] Frame sync polarity
  RESERVED0              : TBits_1;                    // [2:2] no description available
  FSE                    : TBits_1;                    // [3:3] Frame sync early
  MF                     : TBits_1;                    // [4:4] MSB first
  RESERVED1              : TBits_3;                    // [5:7] no description available
  SYWD                   : TBits_5;                    // [8:12] Sync width
  RESERVED2              : TBits_3;                    // [13:15] no description available
  FRSZ                   : TBits_5;                    // [16:20] Frame size
  RESERVED3              : TBits_11;                   // [21:31] no description available
end;

TI2S0_RCR4_bitbanded = record
  FSD                    : longWord;                   // [0:0] Frame sync direction
  FSP                    : longWord;                   // [1:1] Frame sync polarity
  RESERVED0              : longWord;                   // [2:2] no description available
  FSE                    : longWord;                   // [3:3] Frame sync early
  MF                     : longWord;                   // [4:4] MSB first
  RESERVED1              : array[0..2] of longWord;    // [5:7] no description available
  SYWD                   : array[0..4] of longWord;    // [8:12] Sync width
  RESERVED2              : array[0..2] of longWord;    // [13:15] no description available
  FRSZ                   : array[0..4] of longWord;    // [16:20] Frame size
  RESERVED3              : array[0..10] of longWord;   // [21:31] no description available
end;

TI2S0_RCR5_bits = bitpacked record
  RESERVED0              : TBits_8;                    // [0:7] no description available
  FBT                    : TBits_5;                    // [8:12] First bit shifted
  RESERVED1              : TBits_3;                    // [13:15] no description available
  W0W                    : TBits_5;                    // [16:20] Word 0 width
  RESERVED2              : TBits_3;                    // [21:23] no description available
  WNW                    : TBits_5;                    // [24:28] Word N width
  RESERVED3              : TBits_3;                    // [29:31] no description available
end;

TI2S0_RCR5_bitbanded = record
  RESERVED0              : array[0..7] of longWord;    // [0:7] no description available
  FBT                    : array[0..4] of longWord;    // [8:12] First bit shifted
  RESERVED1              : array[0..2] of longWord;    // [13:15] no description available
  W0W                    : array[0..4] of longWord;    // [16:20] Word 0 width
  RESERVED2              : array[0..2] of longWord;    // [21:23] no description available
  WNW                    : array[0..4] of longWord;    // [24:28] Word N width
  RESERVED3              : array[0..2] of longWord;    // [29:31] no description available
end;

TI2S0_RDR_bits = bitpacked record
  RDR                    : TBits_32;                   // [0:31] Receive data register
end;

TI2S0_RDR_bitbanded = record
  RDR                    : array[0..31] of longWord;   // [0:31] Receive data register
end;

TI2S0_RFR_bits = bitpacked record
  RFP                    : TBits_4;                    // [0:3] Read FIFO pointer
  RESERVED0              : TBits_12;                   // [4:15] no description available
  WFP                    : TBits_4;                    // [16:19] Write FIFO pointer
  RESERVED1              : TBits_12;                   // [20:31] no description available
end;

TI2S0_RFR_bitbanded = record
  RFP                    : array[0..3] of longWord;    // [0:3] Read FIFO pointer
  RESERVED0              : array[0..11] of longWord;   // [4:15] no description available
  WFP                    : array[0..3] of longWord;    // [16:19] Write FIFO pointer
  RESERVED1              : array[0..11] of longWord;   // [20:31] no description available
end;

TI2S0_RMR_bits = bitpacked record
  RWM                    : TBits_32;                   // [0:31] Receive word mask
end;

TI2S0_RMR_bitbanded = record
  RWM                    : array[0..31] of longWord;   // [0:31] Receive word mask
end;

TI2S0_MCR_bits = bitpacked record
  RESERVED0              : TBits_24;                   // [0:23] no description available
  MICS                   : TBits_2;                    // [24:25] MCLK Input Clock Select
  RESERVED1              : TBits_4;                    // [26:29] no description available
  MOE                    : TBits_1;                    // [30:30] MCLK Output Enable
  DUF                    : TBits_1;                    // [31:31] Divider Update Flag
end;

TI2S0_MCR_bitbanded = record
  RESERVED0              : array[0..23] of longWord;   // [0:23] no description available
  MICS                   : array[0..1] of longWord;    // [24:25] MCLK Input Clock Select
  RESERVED1              : array[0..3] of longWord;    // [26:29] no description available
  MOE                    : longWord;                   // [30:30] MCLK Output Enable
  DUF                    : longWord;                   // [31:31] Divider Update Flag
end;

TI2S0_MDR_bits = bitpacked record
  DIVIDE                 : TBits_12;                   // [0:11] MCLK Divide
  FRACT                  : TBits_8;                    // [12:19] MCLK Fraction
  RESERVED0              : TBits_12;                   // [20:31] no description available
end;

TI2S0_MDR_bitbanded = record
  DIVIDE                 : array[0..11] of longWord;   // [0:11] MCLK Divide
  FRACT                  : array[0..7] of longWord;    // [12:19] MCLK Fraction
  RESERVED0              : array[0..11] of longWord;   // [20:31] no description available
end;

TI2S0_Registers = record
  case boolean of false: (
  TCSR                   : longWord;                   // 0x00 SAI Transmit Control Register
  TCR1                   : longWord;                   // 0x04 SAI Transmit Configuration 1 Register
  TCR2                   : longWord;                   // 0x08 SAI Transmit Configuration 2 Register
  TCR3                   : longWord;                   // 0x0C SAI Transmit Configuration 3 Register
  TCR4                   : longWord;                   // 0x10 SAI Transmit Configuration 4 Register
  TCR5                   : longWord;                   // 0x14 SAI Transmit Configuration 5 Register
  RESERVED0              : array[0..1] of longWord;    // 0x18
  TDR0                   : longWord;                   // 0x20 SAI Transmit Data Register
  TDR1                   : longWord;                   // 0x24 SAI Transmit Data Register
  RESERVED1              : array[0..5] of longWord;    // 0x28
  TFR0                   : longWord;                   // 0x40 SAI Transmit FIFO Register
  TFR1                   : longWord;                   // 0x44 SAI Transmit FIFO Register
  RESERVED2              : array[0..5] of longWord;    // 0x48
  TMR                    : longWord;                   // 0x60 SAI Transmit Mask Register
  RESERVED3              : array[0..6] of longWord;    // 0x64
  RCSR                   : longWord;                   // 0x80 SAI Receive Control Register
  RCR1                   : longWord;                   // 0x84 SAI Receive Configuration 1 Register
  RCR2                   : longWord;                   // 0x88 SAI Receive Configuration 2 Register
  RCR3                   : longWord;                   // 0x8C SAI Receive Configuration 3 Register
  RCR4                   : longWord;                   // 0x90 SAI Receive Configuration 4 Register
  RCR5                   : longWord;                   // 0x94 SAI Receive Configuration 5 Register
  RESERVED4              : array[0..1] of longWord;    // 0x98
  RDR0                   : longWord;                   // 0xA0 SAI Receive Data Register
  RDR1                   : longWord;                   // 0xA4 SAI Receive Data Register
  RESERVED5              : array[0..5] of longWord;    // 0xA8
  RFR0                   : longWord;                   // 0xC0 SAI Receive FIFO Register
  RFR1                   : longWord;                   // 0xC4 SAI Receive FIFO Register
  RESERVED6              : array[0..5] of longWord;    // 0xC8
  RMR                    : longWord;                   // 0xE0 SAI Receive Mask Register
  RESERVED7              : array[0..6] of longWord;    // 0xE4
  MCR                    : longWord;                   // 0x100 SAI MCLK Control Register
  MDR                    : longWord;                   // 0x104 MCLK Divide Register
);
true : (
TCSR_bits                : TI2S0_TCSR_bits;            // 0x04 SAI Transmit Control Register
TCR1_bits                : TI2S0_TCR1_bits;            // 0x08 SAI Transmit Configuration 1 Register
TCR2_bits                : TI2S0_TCR2_bits;            // 0x0C SAI Transmit Configuration 2 Register
TCR3_bits                : TI2S0_TCR3_bits;            // 0x10 SAI Transmit Configuration 3 Register
TCR4_bits                : TI2S0_TCR4_bits;            // 0x14 SAI Transmit Configuration 4 Register
TCR5_bits                : TI2S0_TCR5_bits;            // 0x18 SAI Transmit Configuration 5 Register
RESERVED_bits0           : array[0..1] of longWord;
TDR0_bits                : TI2S0_TDR_bits;             // 0x24 SAI Transmit Data Register
TDR1_bits                : TI2S0_TDR_bits;             // 0x28 SAI Transmit Data Register
RESERVED_bits1           : array[0..5] of longWord;
TFR0_bits                : TI2S0_TFR_bits;             // 0x44 SAI Transmit FIFO Register
TFR1_bits                : TI2S0_TFR_bits;             // 0x48 SAI Transmit FIFO Register
RESERVED_bits2           : array[0..5] of longWord;
TMR_bits                 : TI2S0_TMR_bits;             // 0x64 SAI Transmit Mask Register
RESERVED_bits3           : array[0..6] of longWord;
RCSR_bits                : TI2S0_RCSR_bits;            // 0x84 SAI Receive Control Register
RCR1_bits                : TI2S0_RCR1_bits;            // 0x88 SAI Receive Configuration 1 Register
RCR2_bits                : TI2S0_RCR2_bits;            // 0x8C SAI Receive Configuration 2 Register
RCR3_bits                : TI2S0_RCR3_bits;            // 0x90 SAI Receive Configuration 3 Register
RCR4_bits                : TI2S0_RCR4_bits;            // 0x94 SAI Receive Configuration 4 Register
RCR5_bits                : TI2S0_RCR5_bits;            // 0x98 SAI Receive Configuration 5 Register
RESERVED_bits4           : array[0..1] of longWord;
RDR0_bits                : TI2S0_RDR_bits;             // 0xA4 SAI Receive Data Register
RDR1_bits                : TI2S0_RDR_bits;             // 0xA8 SAI Receive Data Register
RESERVED_bits5           : array[0..5] of longWord;
RFR0_bits                : TI2S0_RFR_bits;             // 0xC4 SAI Receive FIFO Register
RFR1_bits                : TI2S0_RFR_bits;             // 0xC8 SAI Receive FIFO Register
RESERVED_bits6           : array[0..5] of longWord;
RMR_bits                 : TI2S0_RMR_bits;             // 0xE4 SAI Receive Mask Register
RESERVED_bits7           : array[0..6] of longWord;
MCR_bits                 : TI2S0_MCR_bits;             // 0x104 SAI MCLK Control Register
MDR_bits                 : TI2S0_MDR_bits;             // 0x108 MCLK Divide Register
);
end;

TI2S0Registers_bitbanded = record
  TCSR                   : TI2S0_TCSR_bitbanded;       // 0x04 SAI Transmit Control Register
  TCR1                   : TI2S0_TCR1_bitbanded;       // 0x08 SAI Transmit Configuration 1 Register
  TCR2                   : TI2S0_TCR2_bitbanded;       // 0x0C SAI Transmit Configuration 2 Register
  TCR3                   : TI2S0_TCR3_bitbanded;       // 0x10 SAI Transmit Configuration 3 Register
  TCR4                   : TI2S0_TCR4_bitbanded;       // 0x14 SAI Transmit Configuration 4 Register
  TCR5                   : TI2S0_TCR5_bitbanded;       // 0x18 SAI Transmit Configuration 5 Register
  RESERVED0              : array[0..7] of array[0..7] of longWord;
  TDR0                   : TI2S0_TDR_bitbanded;        // 0x24 SAI Transmit Data Register
  TDR1                   : TI2S0_TDR_bitbanded;        // 0x28 SAI Transmit Data Register
  RESERVED1              : array[0..23] of array[0..7] of longWord;
  TFR0                   : TI2S0_TFR_bitbanded;        // 0x44 SAI Transmit FIFO Register
  TFR1                   : TI2S0_TFR_bitbanded;        // 0x48 SAI Transmit FIFO Register
  RESERVED2              : array[0..23] of array[0..7] of longWord;
  TMR                    : TI2S0_TMR_bitbanded;        // 0x64 SAI Transmit Mask Register
  RESERVED3              : array[0..27] of array[0..7] of longWord;
  RCSR                   : TI2S0_RCSR_bitbanded;       // 0x84 SAI Receive Control Register
  RCR1                   : TI2S0_RCR1_bitbanded;       // 0x88 SAI Receive Configuration 1 Register
  RCR2                   : TI2S0_RCR2_bitbanded;       // 0x8C SAI Receive Configuration 2 Register
  RCR3                   : TI2S0_RCR3_bitbanded;       // 0x90 SAI Receive Configuration 3 Register
  RCR4                   : TI2S0_RCR4_bitbanded;       // 0x94 SAI Receive Configuration 4 Register
  RCR5                   : TI2S0_RCR5_bitbanded;       // 0x98 SAI Receive Configuration 5 Register
  RESERVED4              : array[0..7] of array[0..7] of longWord;
  RDR0                   : TI2S0_RDR_bitbanded;        // 0xA4 SAI Receive Data Register
  RDR1                   : TI2S0_RDR_bitbanded;        // 0xA8 SAI Receive Data Register
  RESERVED5              : array[0..23] of array[0..7] of longWord;
  RFR0                   : TI2S0_RFR_bitbanded;        // 0xC4 SAI Receive FIFO Register
  RFR1                   : TI2S0_RFR_bitbanded;        // 0xC8 SAI Receive FIFO Register
  RESERVED6              : array[0..23] of array[0..7] of longWord;
  RMR                    : TI2S0_RMR_bitbanded;        // 0xE4 SAI Receive Mask Register
  RESERVED7              : array[0..27] of array[0..7] of longWord;
  MCR                    : TI2S0_MCR_bitbanded;        // 0x104 SAI MCLK Control Register
  MDR                    : TI2S0_MDR_bitbanded;        // 0x108 MCLK Divide Register
end;

// Low leakage wakeup unit
TLLWU_PE1_bits = bitpacked record
  WUPE0                  : TBits_2;                    // [0:1] Wakeup Pin Enable for LLWU_P0
  WUPE1                  : TBits_2;                    // [2:3] Wakeup Pin Enable for LLWU_P1
  WUPE2                  : TBits_2;                    // [4:5] Wakeup Pin Enable for LLWU_P2
  WUPE3                  : TBits_2;                    // [6:7] Wakeup Pin Enable for LLWU_P3
end;

TLLWU_PE1_bitbanded = record
  WUPE0                  : array[0..1] of longWord;    // [0:1] Wakeup Pin Enable for LLWU_P0
  WUPE1                  : array[0..1] of longWord;    // [2:3] Wakeup Pin Enable for LLWU_P1
  WUPE2                  : array[0..1] of longWord;    // [4:5] Wakeup Pin Enable for LLWU_P2
  WUPE3                  : array[0..1] of longWord;    // [6:7] Wakeup Pin Enable for LLWU_P3
end;

TLLWU_PE2_bits = bitpacked record
  WUPE4                  : TBits_2;                    // [0:1] Wakeup Pin Enable for LLWU_P4
  WUPE5                  : TBits_2;                    // [2:3] Wakeup Pin Enable for LLWU_P5
  WUPE6                  : TBits_2;                    // [4:5] Wakeup Pin Enable for LLWU_P6
  WUPE7                  : TBits_2;                    // [6:7] Wakeup Pin Enable for LLWU_P7
end;

TLLWU_PE2_bitbanded = record
  WUPE4                  : array[0..1] of longWord;    // [0:1] Wakeup Pin Enable for LLWU_P4
  WUPE5                  : array[0..1] of longWord;    // [2:3] Wakeup Pin Enable for LLWU_P5
  WUPE6                  : array[0..1] of longWord;    // [4:5] Wakeup Pin Enable for LLWU_P6
  WUPE7                  : array[0..1] of longWord;    // [6:7] Wakeup Pin Enable for LLWU_P7
end;

TLLWU_PE3_bits = bitpacked record
  WUPE8                  : TBits_2;                    // [0:1] Wakeup Pin Enable for LLWU_P8
  WUPE9                  : TBits_2;                    // [2:3] Wakeup Pin Enable for LLWU_P9
  WUPE10                 : TBits_2;                    // [4:5] Wakeup Pin Enable for LLWU_P10
  WUPE11                 : TBits_2;                    // [6:7] Wakeup Pin Enable for LLWU_P11
end;

TLLWU_PE3_bitbanded = record
  WUPE8                  : array[0..1] of longWord;    // [0:1] Wakeup Pin Enable for LLWU_P8
  WUPE9                  : array[0..1] of longWord;    // [2:3] Wakeup Pin Enable for LLWU_P9
  WUPE10                 : array[0..1] of longWord;    // [4:5] Wakeup Pin Enable for LLWU_P10
  WUPE11                 : array[0..1] of longWord;    // [6:7] Wakeup Pin Enable for LLWU_P11
end;

TLLWU_PE4_bits = bitpacked record
  WUPE12                 : TBits_2;                    // [0:1] Wakeup Pin Enable for LLWU_P12
  WUPE13                 : TBits_2;                    // [2:3] Wakeup Pin Enable for LLWU_P13
  WUPE14                 : TBits_2;                    // [4:5] Wakeup Pin Enable for LLWU_P14
  WUPE15                 : TBits_2;                    // [6:7] Wakeup Pin Enable for LLWU_P15
end;

TLLWU_PE4_bitbanded = record
  WUPE12                 : array[0..1] of longWord;    // [0:1] Wakeup Pin Enable for LLWU_P12
  WUPE13                 : array[0..1] of longWord;    // [2:3] Wakeup Pin Enable for LLWU_P13
  WUPE14                 : array[0..1] of longWord;    // [4:5] Wakeup Pin Enable for LLWU_P14
  WUPE15                 : array[0..1] of longWord;    // [6:7] Wakeup Pin Enable for LLWU_P15
end;

TLLWU_ME_bits = bitpacked record
  WUME0                  : TBits_1;                    // [0:0] Wakeup Module Enable for Module 0
  WUME1                  : TBits_1;                    // [1:1] Wakeup Module Enable for Module 1
  WUME2                  : TBits_1;                    // [2:2] Wakeup Module Enable for Module 2
  WUME3                  : TBits_1;                    // [3:3] Wakeup Module Enable for Module 3
  WUME4                  : TBits_1;                    // [4:4] Wakeup Module Enable for Module 4
  WUME5                  : TBits_1;                    // [5:5] Wakeup Module Enable for Module 5
  WUME6                  : TBits_1;                    // [6:6] Wakeup Module Enable for Module 6
  WUME7                  : TBits_1;                    // [7:7] Wakeup Module Enable for Module 7
end;

TLLWU_ME_bitbanded = record
  WUME0                  : longWord;                   // [0:0] Wakeup Module Enable for Module 0
  WUME1                  : longWord;                   // [1:1] Wakeup Module Enable for Module 1
  WUME2                  : longWord;                   // [2:2] Wakeup Module Enable for Module 2
  WUME3                  : longWord;                   // [3:3] Wakeup Module Enable for Module 3
  WUME4                  : longWord;                   // [4:4] Wakeup Module Enable for Module 4
  WUME5                  : longWord;                   // [5:5] Wakeup Module Enable for Module 5
  WUME6                  : longWord;                   // [6:6] Wakeup Module Enable for Module 6
  WUME7                  : longWord;                   // [7:7] Wakeup Module Enable for Module 7
end;

TLLWU_F1_bits = bitpacked record
  WUF0                   : TBits_1;                    // [0:0] Wakeup Flag for LLWU_P0
  WUF1                   : TBits_1;                    // [1:1] Wakeup Flag for LLWU_P1
  WUF2                   : TBits_1;                    // [2:2] Wakeup Flag for LLWU_P2
  WUF3                   : TBits_1;                    // [3:3] Wakeup Flag for LLWU_P3
  WUF4                   : TBits_1;                    // [4:4] Wakeup Flag for LLWU_P4
  WUF5                   : TBits_1;                    // [5:5] Wakeup Flag for LLWU_P5
  WUF6                   : TBits_1;                    // [6:6] Wakeup Flag for LLWU_P6
  WUF7                   : TBits_1;                    // [7:7] Wakeup Flag for LLWU_P7
end;

TLLWU_F1_bitbanded = record
  WUF0                   : longWord;                   // [0:0] Wakeup Flag for LLWU_P0
  WUF1                   : longWord;                   // [1:1] Wakeup Flag for LLWU_P1
  WUF2                   : longWord;                   // [2:2] Wakeup Flag for LLWU_P2
  WUF3                   : longWord;                   // [3:3] Wakeup Flag for LLWU_P3
  WUF4                   : longWord;                   // [4:4] Wakeup Flag for LLWU_P4
  WUF5                   : longWord;                   // [5:5] Wakeup Flag for LLWU_P5
  WUF6                   : longWord;                   // [6:6] Wakeup Flag for LLWU_P6
  WUF7                   : longWord;                   // [7:7] Wakeup Flag for LLWU_P7
end;

TLLWU_F2_bits = bitpacked record
  WUF8                   : TBits_1;                    // [0:0] Wakeup Flag for LLWU_P8
  WUF9                   : TBits_1;                    // [1:1] Wakeup Flag for LLWU_P9
  WUF10                  : TBits_1;                    // [2:2] Wakeup Flag for LLWU_P10
  WUF11                  : TBits_1;                    // [3:3] Wakeup Flag for LLWU_P11
  WUF12                  : TBits_1;                    // [4:4] Wakeup Flag for LLWU_P12
  WUF13                  : TBits_1;                    // [5:5] Wakeup Flag for LLWU_P13
  WUF14                  : TBits_1;                    // [6:6] Wakeup Flag for LLWU_P14
  WUF15                  : TBits_1;                    // [7:7] Wakeup Flag for LLWU_P15
end;

TLLWU_F2_bitbanded = record
  WUF8                   : longWord;                   // [0:0] Wakeup Flag for LLWU_P8
  WUF9                   : longWord;                   // [1:1] Wakeup Flag for LLWU_P9
  WUF10                  : longWord;                   // [2:2] Wakeup Flag for LLWU_P10
  WUF11                  : longWord;                   // [3:3] Wakeup Flag for LLWU_P11
  WUF12                  : longWord;                   // [4:4] Wakeup Flag for LLWU_P12
  WUF13                  : longWord;                   // [5:5] Wakeup Flag for LLWU_P13
  WUF14                  : longWord;                   // [6:6] Wakeup Flag for LLWU_P14
  WUF15                  : longWord;                   // [7:7] Wakeup Flag for LLWU_P15
end;

TLLWU_F3_bits = bitpacked record
  MWUF0                  : TBits_1;                    // [0:0] Wakeup flag for module 0
  MWUF1                  : TBits_1;                    // [1:1] Wakeup flag for module 1
  MWUF2                  : TBits_1;                    // [2:2] Wakeup flag for module 2
  MWUF3                  : TBits_1;                    // [3:3] Wakeup flag for module 3
  MWUF4                  : TBits_1;                    // [4:4] Wakeup flag for module 4
  MWUF5                  : TBits_1;                    // [5:5] Wakeup flag for module 5
  MWUF6                  : TBits_1;                    // [6:6] Wakeup flag for module 6
  MWUF7                  : TBits_1;                    // [7:7] Wakeup flag for module 7
end;

TLLWU_F3_bitbanded = record
  MWUF0                  : longWord;                   // [0:0] Wakeup flag for module 0
  MWUF1                  : longWord;                   // [1:1] Wakeup flag for module 1
  MWUF2                  : longWord;                   // [2:2] Wakeup flag for module 2
  MWUF3                  : longWord;                   // [3:3] Wakeup flag for module 3
  MWUF4                  : longWord;                   // [4:4] Wakeup flag for module 4
  MWUF5                  : longWord;                   // [5:5] Wakeup flag for module 5
  MWUF6                  : longWord;                   // [6:6] Wakeup flag for module 6
  MWUF7                  : longWord;                   // [7:7] Wakeup flag for module 7
end;

TLLWU_FILT1_bits = bitpacked record
  FILTSEL                : TBits_4;                    // [0:3] Filter pin select
  RESERVED0              : TBits_1;                    // [4:4] no description available
  FILTE                  : TBits_2;                    // [5:6] Digital Filter on External Pin
  FILTF                  : TBits_1;                    // [7:7] Filter Detect Flag
end;

TLLWU_FILT1_bitbanded = record
  FILTSEL                : array[0..3] of longWord;    // [0:3] Filter pin select
  RESERVED0              : longWord;                   // [4:4] no description available
  FILTE                  : array[0..1] of longWord;    // [5:6] Digital Filter on External Pin
  FILTF                  : longWord;                   // [7:7] Filter Detect Flag
end;

TLLWU_FILT2_bits = bitpacked record
  FILTSEL                : TBits_4;                    // [0:3] Filter pin select
  RESERVED0              : TBits_1;                    // [4:4] no description available
  FILTE                  : TBits_2;                    // [5:6] Digital Filter on External Pin
  FILTF                  : TBits_1;                    // [7:7] Filter Detect Flag
end;

TLLWU_FILT2_bitbanded = record
  FILTSEL                : array[0..3] of longWord;    // [0:3] Filter pin select
  RESERVED0              : longWord;                   // [4:4] no description available
  FILTE                  : array[0..1] of longWord;    // [5:6] Digital Filter on External Pin
  FILTF                  : longWord;                   // [7:7] Filter Detect Flag
end;

TLLWU_RST_bits = bitpacked record
  RSTFILT                : TBits_1;                    // [0:0] Digital Filter on RESET Pin
  LLRSTE                 : TBits_1;                    // [1:1] Low Leakage mode RESET enable
  RESERVED0              : TBits_6;                    // [2:7] no description available
end;

TLLWU_RST_bitbanded = record
  RSTFILT                : longWord;                   // [0:0] Digital Filter on RESET Pin
  LLRSTE                 : longWord;                   // [1:1] Low Leakage mode RESET enable
  RESERVED0              : array[0..5] of longWord;    // [2:7] no description available
end;

TLLWU_Registers = record
  case boolean of false: (
  PE1                    : byte;                       // 0x00 LLWU Pin Enable 1 Register
  PE2                    : byte;                       // 0x01 LLWU Pin Enable 2 Register
  PE3                    : byte;                       // 0x02 LLWU Pin Enable 3 Register
  PE4                    : byte;                       // 0x03 LLWU Pin Enable 4 Register
  ME                     : byte;                       // 0x04 LLWU Module Enable Register
  F1                     : byte;                       // 0x05 LLWU Flag 1 Register
  F2                     : byte;                       // 0x06 LLWU Flag 2 Register
  F3                     : byte;                       // 0x07 LLWU Flag 3 Register
  FILT1                  : byte;                       // 0x08 LLWU Pin Filter 1 Register
  FILT2                  : byte;                       // 0x09 LLWU Pin Filter 2 Register
  RST                    : byte;                       // 0x0A LLWU Reset Enable Register
);
true : (
PE1_bits                 : TLLWU_PE1_bits;             // 0x01 LLWU Pin Enable 1 Register
PE2_bits                 : TLLWU_PE2_bits;             // 0x02 LLWU Pin Enable 2 Register
PE3_bits                 : TLLWU_PE3_bits;             // 0x03 LLWU Pin Enable 3 Register
PE4_bits                 : TLLWU_PE4_bits;             // 0x04 LLWU Pin Enable 4 Register
ME_bits                  : TLLWU_ME_bits;              // 0x05 LLWU Module Enable Register
F1_bits                  : TLLWU_F1_bits;              // 0x06 LLWU Flag 1 Register
F2_bits                  : TLLWU_F2_bits;              // 0x07 LLWU Flag 2 Register
F3_bits                  : TLLWU_F3_bits;              // 0x08 LLWU Flag 3 Register
FILT1_bits               : TLLWU_FILT1_bits;           // 0x09 LLWU Pin Filter 1 Register
FILT2_bits               : TLLWU_FILT2_bits;           // 0x0A LLWU Pin Filter 2 Register
RST_bits                 : TLLWU_RST_bits;             // 0x0B LLWU Reset Enable Register
);
end;

TLLWURegisters_bitbanded = record
  PE1                    : TLLWU_PE1_bitbanded;        // 0x01 LLWU Pin Enable 1 Register
  PE2                    : TLLWU_PE2_bitbanded;        // 0x02 LLWU Pin Enable 2 Register
  PE3                    : TLLWU_PE3_bitbanded;        // 0x03 LLWU Pin Enable 3 Register
  PE4                    : TLLWU_PE4_bitbanded;        // 0x04 LLWU Pin Enable 4 Register
  ME                     : TLLWU_ME_bitbanded;         // 0x05 LLWU Module Enable Register
  F1                     : TLLWU_F1_bitbanded;         // 0x06 LLWU Flag 1 Register
  F2                     : TLLWU_F2_bitbanded;         // 0x07 LLWU Flag 2 Register
  F3                     : TLLWU_F3_bitbanded;         // 0x08 LLWU Flag 3 Register
  FILT1                  : TLLWU_FILT1_bitbanded;      // 0x09 LLWU Pin Filter 1 Register
  FILT2                  : TLLWU_FILT2_bitbanded;      // 0x0A LLWU Pin Filter 2 Register
  RST                    : TLLWU_RST_bitbanded;        // 0x0B LLWU Reset Enable Register
end;

// Low Power Timer
TLPTMR0_CSR_bits = bitpacked record
  TEN                    : TBits_1;                    // [0:0] Timer Enable
  TMS                    : TBits_1;                    // [1:1] Timer Mode Select
  TFC                    : TBits_1;                    // [2:2] Timer Free Running Counter
  TPP                    : TBits_1;                    // [3:3] Timer Pin Polarity
  TPS                    : TBits_2;                    // [4:5] Timer Pin Select
  TIE                    : TBits_1;                    // [6:6] Timer Interrupt Enable
  TCF                    : TBits_1;                    // [7:7] Timer Compare Flag
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TLPTMR0_CSR_bitbanded = record
  TEN                    : longWord;                   // [0:0] Timer Enable
  TMS                    : longWord;                   // [1:1] Timer Mode Select
  TFC                    : longWord;                   // [2:2] Timer Free Running Counter
  TPP                    : longWord;                   // [3:3] Timer Pin Polarity
  TPS                    : array[0..1] of longWord;    // [4:5] Timer Pin Select
  TIE                    : longWord;                   // [6:6] Timer Interrupt Enable
  TCF                    : longWord;                   // [7:7] Timer Compare Flag
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TLPTMR0_PSR_bits = bitpacked record
  PCS                    : TBits_2;                    // [0:1] Prescaler Clock Select
  PBYP                   : TBits_1;                    // [2:2] Prescaler Bypass
  PRESCALE               : TBits_4;                    // [3:6] Prescale Value
  RESERVED0              : TBits_25;                   // [7:31] no description available
end;

TLPTMR0_PSR_bitbanded = record
  PCS                    : array[0..1] of longWord;    // [0:1] Prescaler Clock Select
  PBYP                   : longWord;                   // [2:2] Prescaler Bypass
  PRESCALE               : array[0..3] of longWord;    // [3:6] Prescale Value
  RESERVED0              : array[0..24] of longWord;   // [7:31] no description available
end;

TLPTMR0_CMR_bits = bitpacked record
  COMPARE                : TBits_16;                   // [0:15] Compare Value
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TLPTMR0_CMR_bitbanded = record
  COMPARE                : array[0..15] of longWord;   // [0:15] Compare Value
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TLPTMR0_CNR_bits = bitpacked record
  COUNTER                : TBits_16;                   // [0:15] Counter Value
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TLPTMR0_CNR_bitbanded = record
  COUNTER                : array[0..15] of longWord;   // [0:15] Counter Value
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TLPTMR0_Registers = record
  case boolean of false: (
  CSR                    : longWord;                   // 0x00 Low Power Timer Control Status Register
  PSR                    : longWord;                   // 0x04 Low Power Timer Prescale Register
  CMR                    : longWord;                   // 0x08 Low Power Timer Compare Register
  CNR                    : longWord;                   // 0x0C Low Power Timer Counter Register
);
true : (
CSR_bits                 : TLPTMR0_CSR_bits;           // 0x04 Low Power Timer Control Status Register
PSR_bits                 : TLPTMR0_PSR_bits;           // 0x08 Low Power Timer Prescale Register
CMR_bits                 : TLPTMR0_CMR_bits;           // 0x0C Low Power Timer Compare Register
CNR_bits                 : TLPTMR0_CNR_bits;           // 0x10 Low Power Timer Counter Register
);
end;

TLPTMR0Registers_bitbanded = record
  CSR                    : TLPTMR0_CSR_bitbanded;      // 0x04 Low Power Timer Control Status Register
  PSR                    : TLPTMR0_PSR_bitbanded;      // 0x08 Low Power Timer Prescale Register
  CMR                    : TLPTMR0_CMR_bitbanded;      // 0x0C Low Power Timer Compare Register
  CNR                    : TLPTMR0_CNR_bitbanded;      // 0x10 Low Power Timer Counter Register
end;

// Multipurpose Clock Generator module
TMCG_C1_bits = bitpacked record
  IREFSTEN               : TBits_1;                    // [0:0] Internal Reference Stop Enable
  IRCLKEN                : TBits_1;                    // [1:1] Internal Reference Clock Enable
  IREFS                  : TBits_1;                    // [2:2] Internal Reference Select
  FRDIV                  : TBits_3;                    // [3:5] FLL External Reference Divider
  CLKS                   : TBits_2;                    // [6:7] Clock Source Select
end;

TMCG_C1_bitbanded = record
  IREFSTEN               : longWord;                   // [0:0] Internal Reference Stop Enable
  IRCLKEN                : longWord;                   // [1:1] Internal Reference Clock Enable
  IREFS                  : longWord;                   // [2:2] Internal Reference Select
  FRDIV                  : array[0..2] of longWord;    // [3:5] FLL External Reference Divider
  CLKS                   : array[0..1] of longWord;    // [6:7] Clock Source Select
end;

TMCG_C2_bits = bitpacked record
  IRCS                   : TBits_1;                    // [0:0] Internal Reference Clock Select
  LP                     : TBits_1;                    // [1:1] Low Power Select
  EREFS0                 : TBits_1;                    // [2:2] External Reference Select
  HGO0                   : TBits_1;                    // [3:3] High Gain Oscillator Select
  RANGE0                 : TBits_2;                    // [4:5] Frequency Range Select
  RESERVED0              : TBits_1;                    // [6:6] no description available
  LOCRE0                 : TBits_1;                    // [7:7] Loss of Clock Reset Enable
end;

TMCG_C2_bitbanded = record
  IRCS                   : longWord;                   // [0:0] Internal Reference Clock Select
  LP                     : longWord;                   // [1:1] Low Power Select
  EREFS0                 : longWord;                   // [2:2] External Reference Select
  HGO0                   : longWord;                   // [3:3] High Gain Oscillator Select
  RANGE0                 : array[0..1] of longWord;    // [4:5] Frequency Range Select
  RESERVED0              : longWord;                   // [6:6] no description available
  LOCRE0                 : longWord;                   // [7:7] Loss of Clock Reset Enable
end;

TMCG_C3_bits = bitpacked record
  SCTRIM                 : TBits_8;                    // [0:7] Slow Internal Reference Clock Trim Setting
end;

TMCG_C3_bitbanded = record
  SCTRIM                 : array[0..7] of longWord;    // [0:7] Slow Internal Reference Clock Trim Setting
end;

TMCG_C4_bits = bitpacked record
  SCFTRIM                : TBits_1;                    // [0:0] Slow Internal Reference Clock Fine Trim
  FCTRIM                 : TBits_4;                    // [1:4] Fast Internal Reference Clock Trim Setting
  DRST_DRS               : TBits_2;                    // [5:6] DCO Range Select
  DMX32                  : TBits_1;                    // [7:7] DCO Maximum Frequency with 32.768 kHz Reference
end;

TMCG_C4_bitbanded = record
  SCFTRIM                : longWord;                   // [0:0] Slow Internal Reference Clock Fine Trim
  FCTRIM                 : array[0..3] of longWord;    // [1:4] Fast Internal Reference Clock Trim Setting
  DRST_DRS               : array[0..1] of longWord;    // [5:6] DCO Range Select
  DMX32                  : longWord;                   // [7:7] DCO Maximum Frequency with 32.768 kHz Reference
end;

TMCG_C5_bits = bitpacked record
  PRDIV0                 : TBits_5;                    // [0:4] PLL External Reference Divider
  PLLSTEN0               : TBits_1;                    // [5:5] PLL Stop Enable
  PLLCLKEN0              : TBits_1;                    // [6:6] PLL Clock Enable
  RESERVED0              : TBits_1;                    // [7:7] no description available
end;

TMCG_C5_bitbanded = record
  PRDIV0                 : array[0..4] of longWord;    // [0:4] PLL External Reference Divider
  PLLSTEN0               : longWord;                   // [5:5] PLL Stop Enable
  PLLCLKEN0              : longWord;                   // [6:6] PLL Clock Enable
  RESERVED0              : longWord;                   // [7:7] no description available
end;

TMCG_C6_bits = bitpacked record
  VDIV0                  : TBits_5;                    // [0:4] VCO 0 Divider
  CME0                   : TBits_1;                    // [5:5] Clock Monitor Enable
  PLLS                   : TBits_1;                    // [6:6] PLL Select
  LOLIE0                 : TBits_1;                    // [7:7] Loss of Lock Interrrupt Enable
end;

TMCG_C6_bitbanded = record
  VDIV0                  : array[0..4] of longWord;    // [0:4] VCO 0 Divider
  CME0                   : longWord;                   // [5:5] Clock Monitor Enable
  PLLS                   : longWord;                   // [6:6] PLL Select
  LOLIE0                 : longWord;                   // [7:7] Loss of Lock Interrrupt Enable
end;

TMCG_S_bits = bitpacked record
  IRCST                  : TBits_1;                    // [0:0] Internal Reference Clock Status
  OSCINIT0               : TBits_1;                    // [1:1] OSC Initialization
  CLKST                  : TBits_2;                    // [2:3] Clock Mode Status
  IREFST                 : TBits_1;                    // [4:4] Internal Reference Status
  PLLST                  : TBits_1;                    // [5:5] PLL Select Status
  LOCK0                  : TBits_1;                    // [6:6] Lock Status
  LOLS0                  : TBits_1;                    // [7:7] Loss of Lock Status
end;

TMCG_S_bitbanded = record
  IRCST                  : longWord;                   // [0:0] Internal Reference Clock Status
  OSCINIT0               : longWord;                   // [1:1] OSC Initialization
  CLKST                  : array[0..1] of longWord;    // [2:3] Clock Mode Status
  IREFST                 : longWord;                   // [4:4] Internal Reference Status
  PLLST                  : longWord;                   // [5:5] PLL Select Status
  LOCK0                  : longWord;                   // [6:6] Lock Status
  LOLS0                  : longWord;                   // [7:7] Loss of Lock Status
end;

TMCG_SC_bits = bitpacked record
  LOCS0                  : TBits_1;                    // [0:0] OSC0 Loss of Clock Status
  FCRDIV                 : TBits_3;                    // [1:3] Fast Clock Internal Reference Divider
  FLTPRSRV               : TBits_1;                    // [4:4] FLL Filter Preserve Enable
  ATMF                   : TBits_1;                    // [5:5] Automatic Trim machine Fail Flag
  ATMS                   : TBits_1;                    // [6:6] Automatic Trim Machine Select
  ATME                   : TBits_1;                    // [7:7] Automatic Trim Machine Enable
end;

TMCG_SC_bitbanded = record
  LOCS0                  : longWord;                   // [0:0] OSC0 Loss of Clock Status
  FCRDIV                 : array[0..2] of longWord;    // [1:3] Fast Clock Internal Reference Divider
  FLTPRSRV               : longWord;                   // [4:4] FLL Filter Preserve Enable
  ATMF                   : longWord;                   // [5:5] Automatic Trim machine Fail Flag
  ATMS                   : longWord;                   // [6:6] Automatic Trim Machine Select
  ATME                   : longWord;                   // [7:7] Automatic Trim Machine Enable
end;

TMCG_ATCVH_bits = bitpacked record
  ATCVH                  : TBits_8;                    // [0:7] ATM Compare Value High
end;

TMCG_ATCVH_bitbanded = record
  ATCVH                  : array[0..7] of longWord;    // [0:7] ATM Compare Value High
end;

TMCG_ATCVL_bits = bitpacked record
  ATCVL                  : TBits_8;                    // [0:7] ATM Compare Value Low
end;

TMCG_ATCVL_bitbanded = record
  ATCVL                  : array[0..7] of longWord;    // [0:7] ATM Compare Value Low
end;

TMCG_C7_bits = bitpacked record
  OSCSEL                 : TBits_1;                    // [0:0] MCG OSC Clock Select
  RESERVED0              : TBits_7;                    // [1:7] no description available
end;

TMCG_C7_bitbanded = record
  OSCSEL                 : longWord;                   // [0:0] MCG OSC Clock Select
  RESERVED0              : array[0..6] of longWord;    // [1:7] no description available
end;

TMCG_C8_bits = bitpacked record
  LOCS1                  : TBits_1;                    // [0:0] RTC Loss of Clock Status
  RESERVED0              : TBits_4;                    // [1:4] no description available
  CME1                   : TBits_1;                    // [5:5] Clock Monitor Enable1
  LOLRE                  : TBits_1;                    // [6:6] no description available
  LOCRE1                 : TBits_1;                    // [7:7] Loss of Clock Reset Enable
end;

TMCG_C8_bitbanded = record
  LOCS1                  : longWord;                   // [0:0] RTC Loss of Clock Status
  RESERVED0              : array[0..3] of longWord;    // [1:4] no description available
  CME1                   : longWord;                   // [5:5] Clock Monitor Enable1
  LOLRE                  : longWord;                   // [6:6] no description available
  LOCRE1                 : longWord;                   // [7:7] Loss of Clock Reset Enable
end;

TMCG_Registers = record
  case boolean of false: (
  C1                     : byte;                       // 0x00 MCG Control 1 Register
  C2                     : byte;                       // 0x01 MCG Control 2 Register
  C3                     : byte;                       // 0x02 MCG Control 3 Register
  C4                     : byte;                       // 0x03 MCG Control 4 Register
  C5                     : byte;                       // 0x04 MCG Control 5 Register
  C6                     : byte;                       // 0x05 MCG Control 6 Register
  S                      : byte;                       // 0x06 MCG Status Register
  RESERVED0              : byte;                       // 0x07
  SC                     : byte;                       // 0x08 MCG Status and Control Register
  RESERVED1              : byte;                       // 0x09
  ATCVH                  : byte;                       // 0x0A MCG Auto Trim Compare Value High Register
  ATCVL                  : byte;                       // 0x0B MCG Auto Trim Compare Value Low Register
  C7                     : byte;                       // 0x0C MCG Control 7 Register
  C8                     : byte;                       // 0x0D MCG Control 8 Register
);
true : (
C1_bits                  : TMCG_C1_bits;               // 0x01 MCG Control 1 Register
C2_bits                  : TMCG_C2_bits;               // 0x02 MCG Control 2 Register
C3_bits                  : TMCG_C3_bits;               // 0x03 MCG Control 3 Register
C4_bits                  : TMCG_C4_bits;               // 0x04 MCG Control 4 Register
C5_bits                  : TMCG_C5_bits;               // 0x05 MCG Control 5 Register
C6_bits                  : TMCG_C6_bits;               // 0x06 MCG Control 6 Register
S_bits                   : TMCG_S_bits;                // 0x07 MCG Status Register
RESERVED_bits0           : byte;
SC_bits                  : TMCG_SC_bits;               // 0x09 MCG Status and Control Register
RESERVED_bits1           : byte;
ATCVH_bits               : TMCG_ATCVH_bits;            // 0x0B MCG Auto Trim Compare Value High Register
ATCVL_bits               : TMCG_ATCVL_bits;            // 0x0C MCG Auto Trim Compare Value Low Register
C7_bits                  : TMCG_C7_bits;               // 0x0D MCG Control 7 Register
C8_bits                  : TMCG_C8_bits;               // 0x0E MCG Control 8 Register
);
end;

TMCGRegisters_bitbanded = record
  C1                     : TMCG_C1_bitbanded;          // 0x01 MCG Control 1 Register
  C2                     : TMCG_C2_bitbanded;          // 0x02 MCG Control 2 Register
  C3                     : TMCG_C3_bitbanded;          // 0x03 MCG Control 3 Register
  C4                     : TMCG_C4_bitbanded;          // 0x04 MCG Control 4 Register
  C5                     : TMCG_C5_bitbanded;          // 0x05 MCG Control 5 Register
  C6                     : TMCG_C6_bitbanded;          // 0x06 MCG Control 6 Register
  S                      : TMCG_S_bitbanded;           // 0x07 MCG Status Register
  RESERVED0              : array[0..7] of longWord;
  SC                     : TMCG_SC_bitbanded;          // 0x09 MCG Status and Control Register
  RESERVED1              : array[0..7] of longWord;
  ATCVH                  : TMCG_ATCVH_bitbanded;       // 0x0B MCG Auto Trim Compare Value High Register
  ATCVL                  : TMCG_ATCVL_bitbanded;       // 0x0C MCG Auto Trim Compare Value Low Register
  C7                     : TMCG_C7_bitbanded;          // 0x0D MCG Control 7 Register
  C8                     : TMCG_C8_bitbanded;          // 0x0E MCG Control 8 Register
end;

// Core Platform Miscellaneous Control Module
TMCM_PLASC_bits = bitpacked record
  ASC                    : TBits_8;                    // [0:7] Each bit in the ASC field indicates if there is a corresponding connection to the crossbar switch's slave input port.
  RESERVED0              : TBits_8;                    // [8:15] no description available
end;

TMCM_PLASC_bitbanded = record
  ASC                    : array[0..7] of longWord;    // [0:7] Each bit in the ASC field indicates if there is a corresponding connection to the crossbar switch's slave input port.
  RESERVED0              : array[0..7] of longWord;    // [8:15] no description available
end;

TMCM_PLAMC_bits = bitpacked record
  AMC                    : TBits_8;                    // [0:7] Each bit in the AMC field indicates if there is a corresponding connection to the AXBS master input port.
  RESERVED0              : TBits_8;                    // [8:15] no description available
end;

TMCM_PLAMC_bitbanded = record
  AMC                    : array[0..7] of longWord;    // [0:7] Each bit in the AMC field indicates if there is a corresponding connection to the AXBS master input port.
  RESERVED0              : array[0..7] of longWord;    // [8:15] no description available
end;

TMCM_CR_bits = bitpacked record
  RESERVED0              : TBits_9;                    // [0:8] no description available
  RESERVED1              : TBits_1;                    // [9:9] no description available
  RESERVED2              : TBits_14;                   // [10:23] no description available
  SRAMUAP                : TBits_2;                    // [24:25] SRAM_U arbitration priority
  SRAMUWP                : TBits_1;                    // [26:26] SRAM_U write protect
  RESERVED3              : TBits_1;                    // [27:27] no description available
  SRAMLAP                : TBits_2;                    // [28:29] SRAM_L arbitration priority
  SRAMLWP                : TBits_1;                    // [30:30] SRAM_L write protect
  RESERVED4              : TBits_1;                    // [31:31] no description available
end;

TMCM_CR_bitbanded = record
  RESERVED0              : array[0..8] of longWord;    // [0:8] no description available
  RESERVED1              : longWord;                   // [9:9] no description available
  RESERVED2              : array[0..13] of longWord;   // [10:23] no description available
  SRAMUAP                : array[0..1] of longWord;    // [24:25] SRAM_U arbitration priority
  SRAMUWP                : longWord;                   // [26:26] SRAM_U write protect
  RESERVED3              : longWord;                   // [27:27] no description available
  SRAMLAP                : array[0..1] of longWord;    // [28:29] SRAM_L arbitration priority
  SRAMLWP                : longWord;                   // [30:30] SRAM_L write protect
  RESERVED4              : longWord;                   // [31:31] no description available
end;

TMCM_Registers = record
  case boolean of false: (
  RESERVED0              : array[0..1] of longWord;    // 0x00
  PLASC                  : word;                       // 0x08 Crossbar switch (AXBS) slave configuration
  PLAMC                  : word;                       // 0x0A Crossbar switch (AXBS) master configuration
  CR                     : longWord;                   // 0x0C Control register
);
true : (
RESERVED_bits0           : array[0..1] of longWord;
PLASC_bits               : TMCM_PLASC_bits;            // 0x0A Crossbar switch (AXBS) slave configuration
PLAMC_bits               : TMCM_PLAMC_bits;            // 0x0C Crossbar switch (AXBS) master configuration
CR_bits                  : TMCM_CR_bits;               // 0x10 Control register
);
end;

TMCMRegisters_bitbanded = record
  RESERVED0              : array[0..7] of array[0..7] of longWord;
  PLASC                  : TMCM_PLASC_bitbanded;       // 0x0A Crossbar switch (AXBS) slave configuration
  PLAMC                  : TMCM_PLAMC_bitbanded;       // 0x0C Crossbar switch (AXBS) master configuration
  CR                     : TMCM_CR_bitbanded;          // 0x10 Control register
end;

// Nested Vectored Interrupt Controller
TNVIC_NVICISER0_bits = bitpacked record
  SETENA                 : TBits_32;                   // [0:31] Interrupt set enable bits
end;

TNVIC_NVICISER0_bitbanded = record
  SETENA                 : array[0..31] of longWord;   // [0:31] Interrupt set enable bits
end;

TNVIC_NVICISER1_bits = bitpacked record
  SETENA                 : TBits_32;                   // [0:31] Interrupt set enable bits
end;

TNVIC_NVICISER1_bitbanded = record
  SETENA                 : array[0..31] of longWord;   // [0:31] Interrupt set enable bits
end;

TNVIC_NVICISER2_bits = bitpacked record
  SETENA                 : TBits_32;                   // [0:31] Interrupt set enable bits
end;

TNVIC_NVICISER2_bitbanded = record
  SETENA                 : array[0..31] of longWord;   // [0:31] Interrupt set enable bits
end;

TNVIC_NVICISER3_bits = bitpacked record
  SETENA                 : TBits_32;                   // [0:31] Interrupt set enable bits
end;

TNVIC_NVICISER3_bitbanded = record
  SETENA                 : array[0..31] of longWord;   // [0:31] Interrupt set enable bits
end;

TNVIC_NVICICER0_bits = bitpacked record
  CLRENA                 : TBits_32;                   // [0:31] Interrupt clear-enable bits
end;

TNVIC_NVICICER0_bitbanded = record
  CLRENA                 : array[0..31] of longWord;   // [0:31] Interrupt clear-enable bits
end;

TNVIC_NVICICER1_bits = bitpacked record
  CLRENA                 : TBits_32;                   // [0:31] Interrupt clear-enable bits
end;

TNVIC_NVICICER1_bitbanded = record
  CLRENA                 : array[0..31] of longWord;   // [0:31] Interrupt clear-enable bits
end;

TNVIC_NVICICER2_bits = bitpacked record
  CLRENA                 : TBits_32;                   // [0:31] Interrupt clear-enable bits
end;

TNVIC_NVICICER2_bitbanded = record
  CLRENA                 : array[0..31] of longWord;   // [0:31] Interrupt clear-enable bits
end;

TNVIC_NVICICER3_bits = bitpacked record
  CLRENA                 : TBits_32;                   // [0:31] Interrupt clear-enable bits
end;

TNVIC_NVICICER3_bitbanded = record
  CLRENA                 : array[0..31] of longWord;   // [0:31] Interrupt clear-enable bits
end;

TNVIC_NVICISPR0_bits = bitpacked record
  SETPEND                : TBits_32;                   // [0:31] Interrupt set-pending bits
end;

TNVIC_NVICISPR0_bitbanded = record
  SETPEND                : array[0..31] of longWord;   // [0:31] Interrupt set-pending bits
end;

TNVIC_NVICISPR1_bits = bitpacked record
  SETPEND                : TBits_32;                   // [0:31] Interrupt set-pending bits
end;

TNVIC_NVICISPR1_bitbanded = record
  SETPEND                : array[0..31] of longWord;   // [0:31] Interrupt set-pending bits
end;

TNVIC_NVICISPR2_bits = bitpacked record
  SETPEND                : TBits_32;                   // [0:31] Interrupt set-pending bits
end;

TNVIC_NVICISPR2_bitbanded = record
  SETPEND                : array[0..31] of longWord;   // [0:31] Interrupt set-pending bits
end;

TNVIC_NVICISPR3_bits = bitpacked record
  SETPEND                : TBits_32;                   // [0:31] Interrupt set-pending bits
end;

TNVIC_NVICISPR3_bitbanded = record
  SETPEND                : array[0..31] of longWord;   // [0:31] Interrupt set-pending bits
end;

TNVIC_NVICICPR0_bits = bitpacked record
  CLRPEND                : TBits_32;                   // [0:31] Interrupt clear-pending bits
end;

TNVIC_NVICICPR0_bitbanded = record
  CLRPEND                : array[0..31] of longWord;   // [0:31] Interrupt clear-pending bits
end;

TNVIC_NVICICPR1_bits = bitpacked record
  CLRPEND                : TBits_32;                   // [0:31] Interrupt clear-pending bits
end;

TNVIC_NVICICPR1_bitbanded = record
  CLRPEND                : array[0..31] of longWord;   // [0:31] Interrupt clear-pending bits
end;

TNVIC_NVICICPR2_bits = bitpacked record
  CLRPEND                : TBits_32;                   // [0:31] Interrupt clear-pending bits
end;

TNVIC_NVICICPR2_bitbanded = record
  CLRPEND                : array[0..31] of longWord;   // [0:31] Interrupt clear-pending bits
end;

TNVIC_NVICICPR3_bits = bitpacked record
  CLRPEND                : TBits_32;                   // [0:31] Interrupt clear-pending bits
end;

TNVIC_NVICICPR3_bitbanded = record
  CLRPEND                : array[0..31] of longWord;   // [0:31] Interrupt clear-pending bits
end;

TNVIC_NVICIABR0_bits = bitpacked record
  ACTIVE                 : TBits_32;                   // [0:31] Interrupt active flags
end;

TNVIC_NVICIABR0_bitbanded = record
  ACTIVE                 : array[0..31] of longWord;   // [0:31] Interrupt active flags
end;

TNVIC_NVICIABR1_bits = bitpacked record
  ACTIVE                 : TBits_32;                   // [0:31] Interrupt active flags
end;

TNVIC_NVICIABR1_bitbanded = record
  ACTIVE                 : array[0..31] of longWord;   // [0:31] Interrupt active flags
end;

TNVIC_NVICIABR2_bits = bitpacked record
  ACTIVE                 : TBits_32;                   // [0:31] Interrupt active flags
end;

TNVIC_NVICIABR2_bitbanded = record
  ACTIVE                 : array[0..31] of longWord;   // [0:31] Interrupt active flags
end;

TNVIC_NVICIABR3_bits = bitpacked record
  ACTIVE                 : TBits_32;                   // [0:31] Interrupt active flags
end;

TNVIC_NVICIABR3_bitbanded = record
  ACTIVE                 : array[0..31] of longWord;   // [0:31] Interrupt active flags
end;

TNVIC_NVICIP0_bits = bitpacked record
  PRI0                   : TBits_8;                    // [0:7] Priority of interrupt 0
end;

TNVIC_NVICIP0_bitbanded = record
  PRI0                   : array[0..7] of longWord;    // [0:7] Priority of interrupt 0
end;

TNVIC_NVICIP1_bits = bitpacked record
  PRI1                   : TBits_8;                    // [0:7] Priority of interrupt 1
end;

TNVIC_NVICIP1_bitbanded = record
  PRI1                   : array[0..7] of longWord;    // [0:7] Priority of interrupt 1
end;

TNVIC_NVICIP2_bits = bitpacked record
  PRI2                   : TBits_8;                    // [0:7] Priority of interrupt 2
end;

TNVIC_NVICIP2_bitbanded = record
  PRI2                   : array[0..7] of longWord;    // [0:7] Priority of interrupt 2
end;

TNVIC_NVICIP3_bits = bitpacked record
  PRI3                   : TBits_8;                    // [0:7] Priority of interrupt 3
end;

TNVIC_NVICIP3_bitbanded = record
  PRI3                   : array[0..7] of longWord;    // [0:7] Priority of interrupt 3
end;

TNVIC_NVICIP4_bits = bitpacked record
  PRI4                   : TBits_8;                    // [0:7] Priority of interrupt 4
end;

TNVIC_NVICIP4_bitbanded = record
  PRI4                   : array[0..7] of longWord;    // [0:7] Priority of interrupt 4
end;

TNVIC_NVICIP5_bits = bitpacked record
  PRI5                   : TBits_8;                    // [0:7] Priority of interrupt 5
end;

TNVIC_NVICIP5_bitbanded = record
  PRI5                   : array[0..7] of longWord;    // [0:7] Priority of interrupt 5
end;

TNVIC_NVICIP6_bits = bitpacked record
  PRI6                   : TBits_8;                    // [0:7] Priority of interrupt 6
end;

TNVIC_NVICIP6_bitbanded = record
  PRI6                   : array[0..7] of longWord;    // [0:7] Priority of interrupt 6
end;

TNVIC_NVICIP7_bits = bitpacked record
  PRI7                   : TBits_8;                    // [0:7] Priority of interrupt 7
end;

TNVIC_NVICIP7_bitbanded = record
  PRI7                   : array[0..7] of longWord;    // [0:7] Priority of interrupt 7
end;

TNVIC_NVICIP8_bits = bitpacked record
  PRI8                   : TBits_8;                    // [0:7] Priority of interrupt 8
end;

TNVIC_NVICIP8_bitbanded = record
  PRI8                   : array[0..7] of longWord;    // [0:7] Priority of interrupt 8
end;

TNVIC_NVICIP9_bits = bitpacked record
  PRI9                   : TBits_8;                    // [0:7] Priority of interrupt 9
end;

TNVIC_NVICIP9_bitbanded = record
  PRI9                   : array[0..7] of longWord;    // [0:7] Priority of interrupt 9
end;

TNVIC_NVICIP10_bits = bitpacked record
  PRI10                  : TBits_8;                    // [0:7] Priority of interrupt 10
end;

TNVIC_NVICIP10_bitbanded = record
  PRI10                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 10
end;

TNVIC_NVICIP11_bits = bitpacked record
  PRI11                  : TBits_8;                    // [0:7] Priority of interrupt 11
end;

TNVIC_NVICIP11_bitbanded = record
  PRI11                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 11
end;

TNVIC_NVICIP12_bits = bitpacked record
  PRI12                  : TBits_8;                    // [0:7] Priority of interrupt 12
end;

TNVIC_NVICIP12_bitbanded = record
  PRI12                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 12
end;

TNVIC_NVICIP13_bits = bitpacked record
  PRI13                  : TBits_8;                    // [0:7] Priority of interrupt 13
end;

TNVIC_NVICIP13_bitbanded = record
  PRI13                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 13
end;

TNVIC_NVICIP14_bits = bitpacked record
  PRI14                  : TBits_8;                    // [0:7] Priority of interrupt 14
end;

TNVIC_NVICIP14_bitbanded = record
  PRI14                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 14
end;

TNVIC_NVICIP15_bits = bitpacked record
  PRI15                  : TBits_8;                    // [0:7] Priority of interrupt 15
end;

TNVIC_NVICIP15_bitbanded = record
  PRI15                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 15
end;

TNVIC_NVICIP16_bits = bitpacked record
  PRI16                  : TBits_8;                    // [0:7] Priority of interrupt 16
end;

TNVIC_NVICIP16_bitbanded = record
  PRI16                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 16
end;

TNVIC_NVICIP17_bits = bitpacked record
  PRI17                  : TBits_8;                    // [0:7] Priority of interrupt 17
end;

TNVIC_NVICIP17_bitbanded = record
  PRI17                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 17
end;

TNVIC_NVICIP18_bits = bitpacked record
  PRI18                  : TBits_8;                    // [0:7] Priority of interrupt 18
end;

TNVIC_NVICIP18_bitbanded = record
  PRI18                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 18
end;

TNVIC_NVICIP19_bits = bitpacked record
  PRI19                  : TBits_8;                    // [0:7] Priority of interrupt 19
end;

TNVIC_NVICIP19_bitbanded = record
  PRI19                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 19
end;

TNVIC_NVICIP20_bits = bitpacked record
  PRI20                  : TBits_8;                    // [0:7] Priority of interrupt 20
end;

TNVIC_NVICIP20_bitbanded = record
  PRI20                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 20
end;

TNVIC_NVICIP21_bits = bitpacked record
  PRI21                  : TBits_8;                    // [0:7] Priority of interrupt 21
end;

TNVIC_NVICIP21_bitbanded = record
  PRI21                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 21
end;

TNVIC_NVICIP22_bits = bitpacked record
  PRI22                  : TBits_8;                    // [0:7] Priority of interrupt 22
end;

TNVIC_NVICIP22_bitbanded = record
  PRI22                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 22
end;

TNVIC_NVICIP23_bits = bitpacked record
  PRI23                  : TBits_8;                    // [0:7] Priority of interrupt 23
end;

TNVIC_NVICIP23_bitbanded = record
  PRI23                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 23
end;

TNVIC_NVICIP24_bits = bitpacked record
  PRI24                  : TBits_8;                    // [0:7] Priority of interrupt 24
end;

TNVIC_NVICIP24_bitbanded = record
  PRI24                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 24
end;

TNVIC_NVICIP25_bits = bitpacked record
  PRI25                  : TBits_8;                    // [0:7] Priority of interrupt 25
end;

TNVIC_NVICIP25_bitbanded = record
  PRI25                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 25
end;

TNVIC_NVICIP26_bits = bitpacked record
  PRI26                  : TBits_8;                    // [0:7] Priority of interrupt 26
end;

TNVIC_NVICIP26_bitbanded = record
  PRI26                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 26
end;

TNVIC_NVICIP27_bits = bitpacked record
  PRI27                  : TBits_8;                    // [0:7] Priority of interrupt 27
end;

TNVIC_NVICIP27_bitbanded = record
  PRI27                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 27
end;

TNVIC_NVICIP28_bits = bitpacked record
  PRI28                  : TBits_8;                    // [0:7] Priority of interrupt 28
end;

TNVIC_NVICIP28_bitbanded = record
  PRI28                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 28
end;

TNVIC_NVICIP29_bits = bitpacked record
  PRI29                  : TBits_8;                    // [0:7] Priority of interrupt 29
end;

TNVIC_NVICIP29_bitbanded = record
  PRI29                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 29
end;

TNVIC_NVICIP30_bits = bitpacked record
  PRI30                  : TBits_8;                    // [0:7] Priority of interrupt 30
end;

TNVIC_NVICIP30_bitbanded = record
  PRI30                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 30
end;

TNVIC_NVICIP31_bits = bitpacked record
  PRI31                  : TBits_8;                    // [0:7] Priority of interrupt 31
end;

TNVIC_NVICIP31_bitbanded = record
  PRI31                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 31
end;

TNVIC_NVICIP32_bits = bitpacked record
  PRI32                  : TBits_8;                    // [0:7] Priority of interrupt 32
end;

TNVIC_NVICIP32_bitbanded = record
  PRI32                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 32
end;

TNVIC_NVICIP33_bits = bitpacked record
  PRI33                  : TBits_8;                    // [0:7] Priority of interrupt 33
end;

TNVIC_NVICIP33_bitbanded = record
  PRI33                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 33
end;

TNVIC_NVICIP34_bits = bitpacked record
  PRI34                  : TBits_8;                    // [0:7] Priority of interrupt 34
end;

TNVIC_NVICIP34_bitbanded = record
  PRI34                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 34
end;

TNVIC_NVICIP35_bits = bitpacked record
  PRI35                  : TBits_8;                    // [0:7] Priority of interrupt 35
end;

TNVIC_NVICIP35_bitbanded = record
  PRI35                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 35
end;

TNVIC_NVICIP36_bits = bitpacked record
  PRI36                  : TBits_8;                    // [0:7] Priority of interrupt 36
end;

TNVIC_NVICIP36_bitbanded = record
  PRI36                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 36
end;

TNVIC_NVICIP37_bits = bitpacked record
  PRI37                  : TBits_8;                    // [0:7] Priority of interrupt 37
end;

TNVIC_NVICIP37_bitbanded = record
  PRI37                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 37
end;

TNVIC_NVICIP38_bits = bitpacked record
  PRI38                  : TBits_8;                    // [0:7] Priority of interrupt 38
end;

TNVIC_NVICIP38_bitbanded = record
  PRI38                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 38
end;

TNVIC_NVICIP39_bits = bitpacked record
  PRI39                  : TBits_8;                    // [0:7] Priority of interrupt 39
end;

TNVIC_NVICIP39_bitbanded = record
  PRI39                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 39
end;

TNVIC_NVICIP40_bits = bitpacked record
  PRI40                  : TBits_8;                    // [0:7] Priority of interrupt 40
end;

TNVIC_NVICIP40_bitbanded = record
  PRI40                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 40
end;

TNVIC_NVICIP41_bits = bitpacked record
  PRI41                  : TBits_8;                    // [0:7] Priority of interrupt 41
end;

TNVIC_NVICIP41_bitbanded = record
  PRI41                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 41
end;

TNVIC_NVICIP42_bits = bitpacked record
  PRI42                  : TBits_8;                    // [0:7] Priority of interrupt 42
end;

TNVIC_NVICIP42_bitbanded = record
  PRI42                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 42
end;

TNVIC_NVICIP43_bits = bitpacked record
  PRI43                  : TBits_8;                    // [0:7] Priority of interrupt 43
end;

TNVIC_NVICIP43_bitbanded = record
  PRI43                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 43
end;

TNVIC_NVICIP44_bits = bitpacked record
  PRI44                  : TBits_8;                    // [0:7] Priority of interrupt 44
end;

TNVIC_NVICIP44_bitbanded = record
  PRI44                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 44
end;

TNVIC_NVICIP45_bits = bitpacked record
  PRI45                  : TBits_8;                    // [0:7] Priority of interrupt 45
end;

TNVIC_NVICIP45_bitbanded = record
  PRI45                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 45
end;

TNVIC_NVICIP46_bits = bitpacked record
  PRI46                  : TBits_8;                    // [0:7] Priority of interrupt 46
end;

TNVIC_NVICIP46_bitbanded = record
  PRI46                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 46
end;

TNVIC_NVICIP47_bits = bitpacked record
  PRI47                  : TBits_8;                    // [0:7] Priority of interrupt 47
end;

TNVIC_NVICIP47_bitbanded = record
  PRI47                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 47
end;

TNVIC_NVICIP48_bits = bitpacked record
  PRI48                  : TBits_8;                    // [0:7] Priority of interrupt 48
end;

TNVIC_NVICIP48_bitbanded = record
  PRI48                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 48
end;

TNVIC_NVICIP49_bits = bitpacked record
  PRI49                  : TBits_8;                    // [0:7] Priority of interrupt 49
end;

TNVIC_NVICIP49_bitbanded = record
  PRI49                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 49
end;

TNVIC_NVICIP50_bits = bitpacked record
  PRI50                  : TBits_8;                    // [0:7] Priority of interrupt 50
end;

TNVIC_NVICIP50_bitbanded = record
  PRI50                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 50
end;

TNVIC_NVICIP51_bits = bitpacked record
  PRI51                  : TBits_8;                    // [0:7] Priority of interrupt 51
end;

TNVIC_NVICIP51_bitbanded = record
  PRI51                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 51
end;

TNVIC_NVICIP52_bits = bitpacked record
  PRI52                  : TBits_8;                    // [0:7] Priority of interrupt 52
end;

TNVIC_NVICIP52_bitbanded = record
  PRI52                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 52
end;

TNVIC_NVICIP53_bits = bitpacked record
  PRI53                  : TBits_8;                    // [0:7] Priority of interrupt 53
end;

TNVIC_NVICIP53_bitbanded = record
  PRI53                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 53
end;

TNVIC_NVICIP54_bits = bitpacked record
  PRI54                  : TBits_8;                    // [0:7] Priority of interrupt 54
end;

TNVIC_NVICIP54_bitbanded = record
  PRI54                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 54
end;

TNVIC_NVICIP55_bits = bitpacked record
  PRI55                  : TBits_8;                    // [0:7] Priority of interrupt 55
end;

TNVIC_NVICIP55_bitbanded = record
  PRI55                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 55
end;

TNVIC_NVICIP56_bits = bitpacked record
  PRI56                  : TBits_8;                    // [0:7] Priority of interrupt 56
end;

TNVIC_NVICIP56_bitbanded = record
  PRI56                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 56
end;

TNVIC_NVICIP57_bits = bitpacked record
  PRI57                  : TBits_8;                    // [0:7] Priority of interrupt 57
end;

TNVIC_NVICIP57_bitbanded = record
  PRI57                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 57
end;

TNVIC_NVICIP58_bits = bitpacked record
  PRI58                  : TBits_8;                    // [0:7] Priority of interrupt 58
end;

TNVIC_NVICIP58_bitbanded = record
  PRI58                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 58
end;

TNVIC_NVICIP59_bits = bitpacked record
  PRI59                  : TBits_8;                    // [0:7] Priority of interrupt 59
end;

TNVIC_NVICIP59_bitbanded = record
  PRI59                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 59
end;

TNVIC_NVICIP60_bits = bitpacked record
  PRI60                  : TBits_8;                    // [0:7] Priority of interrupt 60
end;

TNVIC_NVICIP60_bitbanded = record
  PRI60                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 60
end;

TNVIC_NVICIP61_bits = bitpacked record
  PRI61                  : TBits_8;                    // [0:7] Priority of interrupt 61
end;

TNVIC_NVICIP61_bitbanded = record
  PRI61                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 61
end;

TNVIC_NVICIP62_bits = bitpacked record
  PRI62                  : TBits_8;                    // [0:7] Priority of interrupt 62
end;

TNVIC_NVICIP62_bitbanded = record
  PRI62                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 62
end;

TNVIC_NVICIP63_bits = bitpacked record
  PRI63                  : TBits_8;                    // [0:7] Priority of interrupt 63
end;

TNVIC_NVICIP63_bitbanded = record
  PRI63                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 63
end;

TNVIC_NVICIP64_bits = bitpacked record
  PRI64                  : TBits_8;                    // [0:7] Priority of interrupt 64
end;

TNVIC_NVICIP64_bitbanded = record
  PRI64                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 64
end;

TNVIC_NVICIP65_bits = bitpacked record
  PRI65                  : TBits_8;                    // [0:7] Priority of interrupt 65
end;

TNVIC_NVICIP65_bitbanded = record
  PRI65                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 65
end;

TNVIC_NVICIP66_bits = bitpacked record
  PRI66                  : TBits_8;                    // [0:7] Priority of interrupt 66
end;

TNVIC_NVICIP66_bitbanded = record
  PRI66                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 66
end;

TNVIC_NVICIP67_bits = bitpacked record
  PRI67                  : TBits_8;                    // [0:7] Priority of interrupt 67
end;

TNVIC_NVICIP67_bitbanded = record
  PRI67                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 67
end;

TNVIC_NVICIP68_bits = bitpacked record
  PRI68                  : TBits_8;                    // [0:7] Priority of interrupt 68
end;

TNVIC_NVICIP68_bitbanded = record
  PRI68                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 68
end;

TNVIC_NVICIP69_bits = bitpacked record
  PRI69                  : TBits_8;                    // [0:7] Priority of interrupt 69
end;

TNVIC_NVICIP69_bitbanded = record
  PRI69                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 69
end;

TNVIC_NVICIP70_bits = bitpacked record
  PRI70                  : TBits_8;                    // [0:7] Priority of interrupt 70
end;

TNVIC_NVICIP70_bitbanded = record
  PRI70                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 70
end;

TNVIC_NVICIP71_bits = bitpacked record
  PRI71                  : TBits_8;                    // [0:7] Priority of interrupt 71
end;

TNVIC_NVICIP71_bitbanded = record
  PRI71                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 71
end;

TNVIC_NVICIP72_bits = bitpacked record
  PRI72                  : TBits_8;                    // [0:7] Priority of interrupt 72
end;

TNVIC_NVICIP72_bitbanded = record
  PRI72                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 72
end;

TNVIC_NVICIP73_bits = bitpacked record
  PRI73                  : TBits_8;                    // [0:7] Priority of interrupt 73
end;

TNVIC_NVICIP73_bitbanded = record
  PRI73                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 73
end;

TNVIC_NVICIP74_bits = bitpacked record
  PRI74                  : TBits_8;                    // [0:7] Priority of interrupt 74
end;

TNVIC_NVICIP74_bitbanded = record
  PRI74                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 74
end;

TNVIC_NVICIP75_bits = bitpacked record
  PRI75                  : TBits_8;                    // [0:7] Priority of interrupt 75
end;

TNVIC_NVICIP75_bitbanded = record
  PRI75                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 75
end;

TNVIC_NVICIP76_bits = bitpacked record
  PRI76                  : TBits_8;                    // [0:7] Priority of interrupt 76
end;

TNVIC_NVICIP76_bitbanded = record
  PRI76                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 76
end;

TNVIC_NVICIP77_bits = bitpacked record
  PRI77                  : TBits_8;                    // [0:7] Priority of interrupt 77
end;

TNVIC_NVICIP77_bitbanded = record
  PRI77                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 77
end;

TNVIC_NVICIP78_bits = bitpacked record
  PRI78                  : TBits_8;                    // [0:7] Priority of interrupt 78
end;

TNVIC_NVICIP78_bitbanded = record
  PRI78                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 78
end;

TNVIC_NVICIP79_bits = bitpacked record
  PRI79                  : TBits_8;                    // [0:7] Priority of interrupt 79
end;

TNVIC_NVICIP79_bitbanded = record
  PRI79                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 79
end;

TNVIC_NVICIP80_bits = bitpacked record
  PRI80                  : TBits_8;                    // [0:7] Priority of interrupt 80
end;

TNVIC_NVICIP80_bitbanded = record
  PRI80                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 80
end;

TNVIC_NVICIP81_bits = bitpacked record
  PRI81                  : TBits_8;                    // [0:7] Priority of interrupt 81
end;

TNVIC_NVICIP81_bitbanded = record
  PRI81                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 81
end;

TNVIC_NVICIP82_bits = bitpacked record
  PRI82                  : TBits_8;                    // [0:7] Priority of interrupt 82
end;

TNVIC_NVICIP82_bitbanded = record
  PRI82                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 82
end;

TNVIC_NVICIP83_bits = bitpacked record
  PRI83                  : TBits_8;                    // [0:7] Priority of interrupt 83
end;

TNVIC_NVICIP83_bitbanded = record
  PRI83                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 83
end;

TNVIC_NVICIP84_bits = bitpacked record
  PRI84                  : TBits_8;                    // [0:7] Priority of interrupt 84
end;

TNVIC_NVICIP84_bitbanded = record
  PRI84                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 84
end;

TNVIC_NVICIP85_bits = bitpacked record
  PRI85                  : TBits_8;                    // [0:7] Priority of interrupt 85
end;

TNVIC_NVICIP85_bitbanded = record
  PRI85                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 85
end;

TNVIC_NVICIP86_bits = bitpacked record
  PRI86                  : TBits_8;                    // [0:7] Priority of interrupt 86
end;

TNVIC_NVICIP86_bitbanded = record
  PRI86                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 86
end;

TNVIC_NVICIP87_bits = bitpacked record
  PRI87                  : TBits_8;                    // [0:7] Priority of interrupt 87
end;

TNVIC_NVICIP87_bitbanded = record
  PRI87                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 87
end;

TNVIC_NVICIP88_bits = bitpacked record
  PRI88                  : TBits_8;                    // [0:7] Priority of interrupt 88
end;

TNVIC_NVICIP88_bitbanded = record
  PRI88                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 88
end;

TNVIC_NVICIP89_bits = bitpacked record
  PRI89                  : TBits_8;                    // [0:7] Priority of interrupt 89
end;

TNVIC_NVICIP89_bitbanded = record
  PRI89                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 89
end;

TNVIC_NVICIP90_bits = bitpacked record
  PRI90                  : TBits_8;                    // [0:7] Priority of interrupt 90
end;

TNVIC_NVICIP90_bitbanded = record
  PRI90                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 90
end;

TNVIC_NVICIP91_bits = bitpacked record
  PRI91                  : TBits_8;                    // [0:7] Priority of interrupt 91
end;

TNVIC_NVICIP91_bitbanded = record
  PRI91                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 91
end;

TNVIC_NVICIP92_bits = bitpacked record
  PRI92                  : TBits_8;                    // [0:7] Priority of interrupt 92
end;

TNVIC_NVICIP92_bitbanded = record
  PRI92                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 92
end;

TNVIC_NVICIP93_bits = bitpacked record
  PRI93                  : TBits_8;                    // [0:7] Priority of interrupt 93
end;

TNVIC_NVICIP93_bitbanded = record
  PRI93                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 93
end;

TNVIC_NVICIP94_bits = bitpacked record
  PRI94                  : TBits_8;                    // [0:7] Priority of interrupt 94
end;

TNVIC_NVICIP94_bitbanded = record
  PRI94                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 94
end;

TNVIC_NVICIP95_bits = bitpacked record
  PRI95                  : TBits_8;                    // [0:7] Priority of interrupt 95
end;

TNVIC_NVICIP95_bitbanded = record
  PRI95                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 95
end;

TNVIC_NVICIP96_bits = bitpacked record
  PRI96                  : TBits_8;                    // [0:7] Priority of interrupt 96
end;

TNVIC_NVICIP96_bitbanded = record
  PRI96                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 96
end;

TNVIC_NVICIP97_bits = bitpacked record
  PRI97                  : TBits_8;                    // [0:7] Priority of interrupt 97
end;

TNVIC_NVICIP97_bitbanded = record
  PRI97                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 97
end;

TNVIC_NVICIP98_bits = bitpacked record
  PRI98                  : TBits_8;                    // [0:7] Priority of interrupt 98
end;

TNVIC_NVICIP98_bitbanded = record
  PRI98                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 98
end;

TNVIC_NVICIP99_bits = bitpacked record
  PRI99                  : TBits_8;                    // [0:7] Priority of interrupt 99
end;

TNVIC_NVICIP99_bitbanded = record
  PRI99                  : array[0..7] of longWord;    // [0:7] Priority of interrupt 99
end;

TNVIC_NVICIP100_bits = bitpacked record
  PRI100                 : TBits_8;                    // [0:7] Priority of interrupt 100
end;

TNVIC_NVICIP100_bitbanded = record
  PRI100                 : array[0..7] of longWord;    // [0:7] Priority of interrupt 100
end;

TNVIC_NVICIP101_bits = bitpacked record
  PRI101                 : TBits_8;                    // [0:7] Priority of interrupt 101
end;

TNVIC_NVICIP101_bitbanded = record
  PRI101                 : array[0..7] of longWord;    // [0:7] Priority of interrupt 101
end;

TNVIC_NVICIP102_bits = bitpacked record
  PRI102                 : TBits_8;                    // [0:7] Priority of interrupt 102
end;

TNVIC_NVICIP102_bitbanded = record
  PRI102                 : array[0..7] of longWord;    // [0:7] Priority of interrupt 102
end;

TNVIC_NVICIP103_bits = bitpacked record
  PRI103                 : TBits_8;                    // [0:7] Priority of interrupt 103
end;

TNVIC_NVICIP103_bitbanded = record
  PRI103                 : array[0..7] of longWord;    // [0:7] Priority of interrupt 103
end;

TNVIC_NVICIP104_bits = bitpacked record
  PRI104                 : TBits_8;                    // [0:7] Priority of interrupt 104
end;

TNVIC_NVICIP104_bitbanded = record
  PRI104                 : array[0..7] of longWord;    // [0:7] Priority of interrupt 104
end;

TNVIC_NVICIP105_bits = bitpacked record
  PRI105                 : TBits_8;                    // [0:7] Priority of interrupt 105
end;

TNVIC_NVICIP105_bitbanded = record
  PRI105                 : array[0..7] of longWord;    // [0:7] Priority of interrupt 105
end;

TNVIC_NVICSTIR_bits = bitpacked record
  INTID                  : TBits_9;                    // [0:8] Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3.
  RESERVED0              : TBits_1;                    // [9:9] no description available
  RESERVED1              : TBits_1;                    // [10:10] no description available
  RESERVED2              : TBits_1;                    // [11:11] no description available
  RESERVED3              : TBits_1;                    // [12:12] no description available
  RESERVED4              : TBits_1;                    // [13:13] no description available
  RESERVED5              : TBits_1;                    // [14:14] no description available
  RESERVED6              : TBits_1;                    // [15:15] no description available
  RESERVED7              : TBits_1;                    // [16:16] no description available
  RESERVED8              : TBits_1;                    // [17:17] no description available
  RESERVED9              : TBits_1;                    // [18:18] no description available
  RESERVED10             : TBits_1;                    // [19:19] no description available
  RESERVED11             : TBits_1;                    // [20:20] no description available
  RESERVED12             : TBits_1;                    // [21:21] no description available
  RESERVED13             : TBits_1;                    // [22:22] no description available
  RESERVED14             : TBits_1;                    // [23:23] no description available
  RESERVED15             : TBits_1;                    // [24:24] no description available
  RESERVED16             : TBits_1;                    // [25:25] no description available
  RESERVED17             : TBits_1;                    // [26:26] no description available
  RESERVED18             : TBits_1;                    // [27:27] no description available
  RESERVED19             : TBits_1;                    // [28:28] no description available
  RESERVED20             : TBits_1;                    // [29:29] no description available
  RESERVED21             : TBits_1;                    // [30:30] no description available
  RESERVED22             : TBits_1;                    // [31:31] no description available
end;

TNVIC_NVICSTIR_bitbanded = record
  INTID                  : array[0..8] of longWord;    // [0:8] Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3.
  RESERVED0              : longWord;                   // [9:9] no description available
  RESERVED1              : longWord;                   // [10:10] no description available
  RESERVED2              : longWord;                   // [11:11] no description available
  RESERVED3              : longWord;                   // [12:12] no description available
  RESERVED4              : longWord;                   // [13:13] no description available
  RESERVED5              : longWord;                   // [14:14] no description available
  RESERVED6              : longWord;                   // [15:15] no description available
  RESERVED7              : longWord;                   // [16:16] no description available
  RESERVED8              : longWord;                   // [17:17] no description available
  RESERVED9              : longWord;                   // [18:18] no description available
  RESERVED10             : longWord;                   // [19:19] no description available
  RESERVED11             : longWord;                   // [20:20] no description available
  RESERVED12             : longWord;                   // [21:21] no description available
  RESERVED13             : longWord;                   // [22:22] no description available
  RESERVED14             : longWord;                   // [23:23] no description available
  RESERVED15             : longWord;                   // [24:24] no description available
  RESERVED16             : longWord;                   // [25:25] no description available
  RESERVED17             : longWord;                   // [26:26] no description available
  RESERVED18             : longWord;                   // [27:27] no description available
  RESERVED19             : longWord;                   // [28:28] no description available
  RESERVED20             : longWord;                   // [29:29] no description available
  RESERVED21             : longWord;                   // [30:30] no description available
  RESERVED22             : longWord;                   // [31:31] no description available
end;

TNVIC_Registers = record
  case boolean of false: (
  NVICISER0              : longWord;                   // 0x00 Interrupt Set Enable Register n
  NVICISER1              : longWord;                   // 0x04 Interrupt Set Enable Register n
  NVICISER2              : longWord;                   // 0x08 Interrupt Set Enable Register n
  NVICISER3              : longWord;                   // 0x0C Interrupt Set Enable Register n
  RESERVED0              : array[0..27] of longWord;   // 0x10
  NVICICER0              : longWord;                   // 0x80 Interrupt Clear Enable Register n
  NVICICER1              : longWord;                   // 0x84 Interrupt Clear Enable Register n
  NVICICER2              : longWord;                   // 0x88 Interrupt Clear Enable Register n
  NVICICER3              : longWord;                   // 0x8C Interrupt Clear Enable Register n
  RESERVED1              : array[0..27] of longWord;   // 0x90
  NVICISPR0              : longWord;                   // 0x100 Interrupt Set Pending Register n
  NVICISPR1              : longWord;                   // 0x104 Interrupt Set Pending Register n
  NVICISPR2              : longWord;                   // 0x108 Interrupt Set Pending Register n
  NVICISPR3              : longWord;                   // 0x10C Interrupt Set Pending Register n
  RESERVED2              : array[0..27] of longWord;   // 0x110
  NVICICPR0              : longWord;                   // 0x180 Interrupt Clear Pending Register n
  NVICICPR1              : longWord;                   // 0x184 Interrupt Clear Pending Register n
  NVICICPR2              : longWord;                   // 0x188 Interrupt Clear Pending Register n
  NVICICPR3              : longWord;                   // 0x18C Interrupt Clear Pending Register n
  RESERVED3              : array[0..27] of longWord;   // 0x190
  NVICIABR0              : longWord;                   // 0x200 Interrupt Active bit Register n
  NVICIABR1              : longWord;                   // 0x204 Interrupt Active bit Register n
  NVICIABR2              : longWord;                   // 0x208 Interrupt Active bit Register n
  NVICIABR3              : longWord;                   // 0x20C Interrupt Active bit Register n
  RESERVED4              : array[0..59] of longWord;   // 0x210
  NVICIP0                : byte;                       // 0x300 Interrupt Priority Register n
  NVICIP1                : byte;                       // 0x301 Interrupt Priority Register n
  NVICIP2                : byte;                       // 0x302 Interrupt Priority Register n
  NVICIP3                : byte;                       // 0x303 Interrupt Priority Register n
  NVICIP4                : byte;                       // 0x304 Interrupt Priority Register n
  NVICIP5                : byte;                       // 0x305 Interrupt Priority Register n
  NVICIP6                : byte;                       // 0x306 Interrupt Priority Register n
  NVICIP7                : byte;                       // 0x307 Interrupt Priority Register n
  NVICIP8                : byte;                       // 0x308 Interrupt Priority Register n
  NVICIP9                : byte;                       // 0x309 Interrupt Priority Register n
  NVICIP10               : byte;                       // 0x30A Interrupt Priority Register n
  NVICIP11               : byte;                       // 0x30B Interrupt Priority Register n
  NVICIP12               : byte;                       // 0x30C Interrupt Priority Register n
  NVICIP13               : byte;                       // 0x30D Interrupt Priority Register n
  NVICIP14               : byte;                       // 0x30E Interrupt Priority Register n
  NVICIP15               : byte;                       // 0x30F Interrupt Priority Register n
  NVICIP16               : byte;                       // 0x310 Interrupt Priority Register n
  NVICIP17               : byte;                       // 0x311 Interrupt Priority Register n
  NVICIP18               : byte;                       // 0x312 Interrupt Priority Register n
  NVICIP19               : byte;                       // 0x313 Interrupt Priority Register n
  NVICIP20               : byte;                       // 0x314 Interrupt Priority Register n
  NVICIP21               : byte;                       // 0x315 Interrupt Priority Register n
  NVICIP22               : byte;                       // 0x316 Interrupt Priority Register n
  NVICIP23               : byte;                       // 0x317 Interrupt Priority Register n
  NVICIP24               : byte;                       // 0x318 Interrupt Priority Register n
  NVICIP25               : byte;                       // 0x319 Interrupt Priority Register n
  NVICIP26               : byte;                       // 0x31A Interrupt Priority Register n
  NVICIP27               : byte;                       // 0x31B Interrupt Priority Register n
  NVICIP28               : byte;                       // 0x31C Interrupt Priority Register n
  NVICIP29               : byte;                       // 0x31D Interrupt Priority Register n
  NVICIP30               : byte;                       // 0x31E Interrupt Priority Register n
  NVICIP31               : byte;                       // 0x31F Interrupt Priority Register n
  NVICIP32               : byte;                       // 0x320 Interrupt Priority Register n
  NVICIP33               : byte;                       // 0x321 Interrupt Priority Register n
  NVICIP34               : byte;                       // 0x322 Interrupt Priority Register n
  NVICIP35               : byte;                       // 0x323 Interrupt Priority Register n
  NVICIP36               : byte;                       // 0x324 Interrupt Priority Register n
  NVICIP37               : byte;                       // 0x325 Interrupt Priority Register n
  NVICIP38               : byte;                       // 0x326 Interrupt Priority Register n
  NVICIP39               : byte;                       // 0x327 Interrupt Priority Register n
  NVICIP40               : byte;                       // 0x328 Interrupt Priority Register n
  NVICIP41               : byte;                       // 0x329 Interrupt Priority Register n
  NVICIP42               : byte;                       // 0x32A Interrupt Priority Register n
  NVICIP43               : byte;                       // 0x32B Interrupt Priority Register n
  NVICIP44               : byte;                       // 0x32C Interrupt Priority Register n
  NVICIP45               : byte;                       // 0x32D Interrupt Priority Register n
  NVICIP46               : byte;                       // 0x32E Interrupt Priority Register n
  NVICIP47               : byte;                       // 0x32F Interrupt Priority Register n
  NVICIP48               : byte;                       // 0x330 Interrupt Priority Register n
  NVICIP49               : byte;                       // 0x331 Interrupt Priority Register n
  NVICIP50               : byte;                       // 0x332 Interrupt Priority Register n
  NVICIP51               : byte;                       // 0x333 Interrupt Priority Register n
  NVICIP52               : byte;                       // 0x334 Interrupt Priority Register n
  NVICIP53               : byte;                       // 0x335 Interrupt Priority Register n
  NVICIP54               : byte;                       // 0x336 Interrupt Priority Register n
  NVICIP55               : byte;                       // 0x337 Interrupt Priority Register n
  NVICIP56               : byte;                       // 0x338 Interrupt Priority Register n
  NVICIP57               : byte;                       // 0x339 Interrupt Priority Register n
  NVICIP58               : byte;                       // 0x33A Interrupt Priority Register n
  NVICIP59               : byte;                       // 0x33B Interrupt Priority Register n
  NVICIP60               : byte;                       // 0x33C Interrupt Priority Register n
  NVICIP61               : byte;                       // 0x33D Interrupt Priority Register n
  NVICIP62               : byte;                       // 0x33E Interrupt Priority Register n
  NVICIP63               : byte;                       // 0x33F Interrupt Priority Register n
  NVICIP64               : byte;                       // 0x340 Interrupt Priority Register n
  NVICIP65               : byte;                       // 0x341 Interrupt Priority Register n
  NVICIP66               : byte;                       // 0x342 Interrupt Priority Register n
  NVICIP67               : byte;                       // 0x343 Interrupt Priority Register n
  NVICIP68               : byte;                       // 0x344 Interrupt Priority Register n
  NVICIP69               : byte;                       // 0x345 Interrupt Priority Register n
  NVICIP70               : byte;                       // 0x346 Interrupt Priority Register n
  NVICIP71               : byte;                       // 0x347 Interrupt Priority Register n
  NVICIP72               : byte;                       // 0x348 Interrupt Priority Register n
  NVICIP73               : byte;                       // 0x349 Interrupt Priority Register n
  NVICIP74               : byte;                       // 0x34A Interrupt Priority Register n
  NVICIP75               : byte;                       // 0x34B Interrupt Priority Register n
  NVICIP76               : byte;                       // 0x34C Interrupt Priority Register n
  NVICIP77               : byte;                       // 0x34D Interrupt Priority Register n
  NVICIP78               : byte;                       // 0x34E Interrupt Priority Register n
  NVICIP79               : byte;                       // 0x34F Interrupt Priority Register n
  NVICIP80               : byte;                       // 0x350 Interrupt Priority Register n
  NVICIP81               : byte;                       // 0x351 Interrupt Priority Register n
  NVICIP82               : byte;                       // 0x352 Interrupt Priority Register n
  NVICIP83               : byte;                       // 0x353 Interrupt Priority Register n
  NVICIP84               : byte;                       // 0x354 Interrupt Priority Register n
  NVICIP85               : byte;                       // 0x355 Interrupt Priority Register n
  NVICIP86               : byte;                       // 0x356 Interrupt Priority Register n
  NVICIP87               : byte;                       // 0x357 Interrupt Priority Register n
  NVICIP88               : byte;                       // 0x358 Interrupt Priority Register n
  NVICIP89               : byte;                       // 0x359 Interrupt Priority Register n
  NVICIP90               : byte;                       // 0x35A Interrupt Priority Register n
  NVICIP91               : byte;                       // 0x35B Interrupt Priority Register n
  NVICIP92               : byte;                       // 0x35C Interrupt Priority Register n
  NVICIP93               : byte;                       // 0x35D Interrupt Priority Register n
  NVICIP94               : byte;                       // 0x35E Interrupt Priority Register n
  NVICIP95               : byte;                       // 0x35F Interrupt Priority Register n
  NVICIP96               : byte;                       // 0x360 Interrupt Priority Register n
  NVICIP97               : byte;                       // 0x361 Interrupt Priority Register n
  NVICIP98               : byte;                       // 0x362 Interrupt Priority Register n
  NVICIP99               : byte;                       // 0x363 Interrupt Priority Register n
  NVICIP100              : byte;                       // 0x364 Interrupt Priority Register n
  NVICIP101              : byte;                       // 0x365 Interrupt Priority Register n
  NVICIP102              : byte;                       // 0x366 Interrupt Priority Register n
  NVICIP103              : byte;                       // 0x367 Interrupt Priority Register n
  NVICIP104              : byte;                       // 0x368 Interrupt Priority Register n
  NVICIP105              : byte;                       // 0x369 Interrupt Priority Register n
  RESERVED5              : array[0..2709] of byte;     // 0x36A
  NVICSTIR               : longWord;                   // 0xE00 Software Trigger Interrupt Register
);
true : (
NVICISER0_bits           : TNVIC_NVICISER0_bits;       // 0x04 Interrupt Set Enable Register n
NVICISER1_bits           : TNVIC_NVICISER1_bits;       // 0x08 Interrupt Set Enable Register n
NVICISER2_bits           : TNVIC_NVICISER2_bits;       // 0x0C Interrupt Set Enable Register n
NVICISER3_bits           : TNVIC_NVICISER3_bits;       // 0x10 Interrupt Set Enable Register n
RESERVED_bits0           : array[0..27] of longWord;
NVICICER0_bits           : TNVIC_NVICICER0_bits;       // 0x84 Interrupt Clear Enable Register n
NVICICER1_bits           : TNVIC_NVICICER1_bits;       // 0x88 Interrupt Clear Enable Register n
NVICICER2_bits           : TNVIC_NVICICER2_bits;       // 0x8C Interrupt Clear Enable Register n
NVICICER3_bits           : TNVIC_NVICICER3_bits;       // 0x90 Interrupt Clear Enable Register n
RESERVED_bits1           : array[0..27] of longWord;
NVICISPR0_bits           : TNVIC_NVICISPR0_bits;       // 0x104 Interrupt Set Pending Register n
NVICISPR1_bits           : TNVIC_NVICISPR1_bits;       // 0x108 Interrupt Set Pending Register n
NVICISPR2_bits           : TNVIC_NVICISPR2_bits;       // 0x10C Interrupt Set Pending Register n
NVICISPR3_bits           : TNVIC_NVICISPR3_bits;       // 0x110 Interrupt Set Pending Register n
RESERVED_bits2           : array[0..27] of longWord;
NVICICPR0_bits           : TNVIC_NVICICPR0_bits;       // 0x184 Interrupt Clear Pending Register n
NVICICPR1_bits           : TNVIC_NVICICPR1_bits;       // 0x188 Interrupt Clear Pending Register n
NVICICPR2_bits           : TNVIC_NVICICPR2_bits;       // 0x18C Interrupt Clear Pending Register n
NVICICPR3_bits           : TNVIC_NVICICPR3_bits;       // 0x190 Interrupt Clear Pending Register n
RESERVED_bits3           : array[0..27] of longWord;
NVICIABR0_bits           : TNVIC_NVICIABR0_bits;       // 0x204 Interrupt Active bit Register n
NVICIABR1_bits           : TNVIC_NVICIABR1_bits;       // 0x208 Interrupt Active bit Register n
NVICIABR2_bits           : TNVIC_NVICIABR2_bits;       // 0x20C Interrupt Active bit Register n
NVICIABR3_bits           : TNVIC_NVICIABR3_bits;       // 0x210 Interrupt Active bit Register n
RESERVED_bits4           : array[0..59] of longWord;
NVICIP0_bits             : TNVIC_NVICIP0_bits;         // 0x301 Interrupt Priority Register n
NVICIP1_bits             : TNVIC_NVICIP1_bits;         // 0x302 Interrupt Priority Register n
NVICIP2_bits             : TNVIC_NVICIP2_bits;         // 0x303 Interrupt Priority Register n
NVICIP3_bits             : TNVIC_NVICIP3_bits;         // 0x304 Interrupt Priority Register n
NVICIP4_bits             : TNVIC_NVICIP4_bits;         // 0x305 Interrupt Priority Register n
NVICIP5_bits             : TNVIC_NVICIP5_bits;         // 0x306 Interrupt Priority Register n
NVICIP6_bits             : TNVIC_NVICIP6_bits;         // 0x307 Interrupt Priority Register n
NVICIP7_bits             : TNVIC_NVICIP7_bits;         // 0x308 Interrupt Priority Register n
NVICIP8_bits             : TNVIC_NVICIP8_bits;         // 0x309 Interrupt Priority Register n
NVICIP9_bits             : TNVIC_NVICIP9_bits;         // 0x30A Interrupt Priority Register n
NVICIP10_bits            : TNVIC_NVICIP10_bits;        // 0x30B Interrupt Priority Register n
NVICIP11_bits            : TNVIC_NVICIP11_bits;        // 0x30C Interrupt Priority Register n
NVICIP12_bits            : TNVIC_NVICIP12_bits;        // 0x30D Interrupt Priority Register n
NVICIP13_bits            : TNVIC_NVICIP13_bits;        // 0x30E Interrupt Priority Register n
NVICIP14_bits            : TNVIC_NVICIP14_bits;        // 0x30F Interrupt Priority Register n
NVICIP15_bits            : TNVIC_NVICIP15_bits;        // 0x310 Interrupt Priority Register n
NVICIP16_bits            : TNVIC_NVICIP16_bits;        // 0x311 Interrupt Priority Register n
NVICIP17_bits            : TNVIC_NVICIP17_bits;        // 0x312 Interrupt Priority Register n
NVICIP18_bits            : TNVIC_NVICIP18_bits;        // 0x313 Interrupt Priority Register n
NVICIP19_bits            : TNVIC_NVICIP19_bits;        // 0x314 Interrupt Priority Register n
NVICIP20_bits            : TNVIC_NVICIP20_bits;        // 0x315 Interrupt Priority Register n
NVICIP21_bits            : TNVIC_NVICIP21_bits;        // 0x316 Interrupt Priority Register n
NVICIP22_bits            : TNVIC_NVICIP22_bits;        // 0x317 Interrupt Priority Register n
NVICIP23_bits            : TNVIC_NVICIP23_bits;        // 0x318 Interrupt Priority Register n
NVICIP24_bits            : TNVIC_NVICIP24_bits;        // 0x319 Interrupt Priority Register n
NVICIP25_bits            : TNVIC_NVICIP25_bits;        // 0x31A Interrupt Priority Register n
NVICIP26_bits            : TNVIC_NVICIP26_bits;        // 0x31B Interrupt Priority Register n
NVICIP27_bits            : TNVIC_NVICIP27_bits;        // 0x31C Interrupt Priority Register n
NVICIP28_bits            : TNVIC_NVICIP28_bits;        // 0x31D Interrupt Priority Register n
NVICIP29_bits            : TNVIC_NVICIP29_bits;        // 0x31E Interrupt Priority Register n
NVICIP30_bits            : TNVIC_NVICIP30_bits;        // 0x31F Interrupt Priority Register n
NVICIP31_bits            : TNVIC_NVICIP31_bits;        // 0x320 Interrupt Priority Register n
NVICIP32_bits            : TNVIC_NVICIP32_bits;        // 0x321 Interrupt Priority Register n
NVICIP33_bits            : TNVIC_NVICIP33_bits;        // 0x322 Interrupt Priority Register n
NVICIP34_bits            : TNVIC_NVICIP34_bits;        // 0x323 Interrupt Priority Register n
NVICIP35_bits            : TNVIC_NVICIP35_bits;        // 0x324 Interrupt Priority Register n
NVICIP36_bits            : TNVIC_NVICIP36_bits;        // 0x325 Interrupt Priority Register n
NVICIP37_bits            : TNVIC_NVICIP37_bits;        // 0x326 Interrupt Priority Register n
NVICIP38_bits            : TNVIC_NVICIP38_bits;        // 0x327 Interrupt Priority Register n
NVICIP39_bits            : TNVIC_NVICIP39_bits;        // 0x328 Interrupt Priority Register n
NVICIP40_bits            : TNVIC_NVICIP40_bits;        // 0x329 Interrupt Priority Register n
NVICIP41_bits            : TNVIC_NVICIP41_bits;        // 0x32A Interrupt Priority Register n
NVICIP42_bits            : TNVIC_NVICIP42_bits;        // 0x32B Interrupt Priority Register n
NVICIP43_bits            : TNVIC_NVICIP43_bits;        // 0x32C Interrupt Priority Register n
NVICIP44_bits            : TNVIC_NVICIP44_bits;        // 0x32D Interrupt Priority Register n
NVICIP45_bits            : TNVIC_NVICIP45_bits;        // 0x32E Interrupt Priority Register n
NVICIP46_bits            : TNVIC_NVICIP46_bits;        // 0x32F Interrupt Priority Register n
NVICIP47_bits            : TNVIC_NVICIP47_bits;        // 0x330 Interrupt Priority Register n
NVICIP48_bits            : TNVIC_NVICIP48_bits;        // 0x331 Interrupt Priority Register n
NVICIP49_bits            : TNVIC_NVICIP49_bits;        // 0x332 Interrupt Priority Register n
NVICIP50_bits            : TNVIC_NVICIP50_bits;        // 0x333 Interrupt Priority Register n
NVICIP51_bits            : TNVIC_NVICIP51_bits;        // 0x334 Interrupt Priority Register n
NVICIP52_bits            : TNVIC_NVICIP52_bits;        // 0x335 Interrupt Priority Register n
NVICIP53_bits            : TNVIC_NVICIP53_bits;        // 0x336 Interrupt Priority Register n
NVICIP54_bits            : TNVIC_NVICIP54_bits;        // 0x337 Interrupt Priority Register n
NVICIP55_bits            : TNVIC_NVICIP55_bits;        // 0x338 Interrupt Priority Register n
NVICIP56_bits            : TNVIC_NVICIP56_bits;        // 0x339 Interrupt Priority Register n
NVICIP57_bits            : TNVIC_NVICIP57_bits;        // 0x33A Interrupt Priority Register n
NVICIP58_bits            : TNVIC_NVICIP58_bits;        // 0x33B Interrupt Priority Register n
NVICIP59_bits            : TNVIC_NVICIP59_bits;        // 0x33C Interrupt Priority Register n
NVICIP60_bits            : TNVIC_NVICIP60_bits;        // 0x33D Interrupt Priority Register n
NVICIP61_bits            : TNVIC_NVICIP61_bits;        // 0x33E Interrupt Priority Register n
NVICIP62_bits            : TNVIC_NVICIP62_bits;        // 0x33F Interrupt Priority Register n
NVICIP63_bits            : TNVIC_NVICIP63_bits;        // 0x340 Interrupt Priority Register n
NVICIP64_bits            : TNVIC_NVICIP64_bits;        // 0x341 Interrupt Priority Register n
NVICIP65_bits            : TNVIC_NVICIP65_bits;        // 0x342 Interrupt Priority Register n
NVICIP66_bits            : TNVIC_NVICIP66_bits;        // 0x343 Interrupt Priority Register n
NVICIP67_bits            : TNVIC_NVICIP67_bits;        // 0x344 Interrupt Priority Register n
NVICIP68_bits            : TNVIC_NVICIP68_bits;        // 0x345 Interrupt Priority Register n
NVICIP69_bits            : TNVIC_NVICIP69_bits;        // 0x346 Interrupt Priority Register n
NVICIP70_bits            : TNVIC_NVICIP70_bits;        // 0x347 Interrupt Priority Register n
NVICIP71_bits            : TNVIC_NVICIP71_bits;        // 0x348 Interrupt Priority Register n
NVICIP72_bits            : TNVIC_NVICIP72_bits;        // 0x349 Interrupt Priority Register n
NVICIP73_bits            : TNVIC_NVICIP73_bits;        // 0x34A Interrupt Priority Register n
NVICIP74_bits            : TNVIC_NVICIP74_bits;        // 0x34B Interrupt Priority Register n
NVICIP75_bits            : TNVIC_NVICIP75_bits;        // 0x34C Interrupt Priority Register n
NVICIP76_bits            : TNVIC_NVICIP76_bits;        // 0x34D Interrupt Priority Register n
NVICIP77_bits            : TNVIC_NVICIP77_bits;        // 0x34E Interrupt Priority Register n
NVICIP78_bits            : TNVIC_NVICIP78_bits;        // 0x34F Interrupt Priority Register n
NVICIP79_bits            : TNVIC_NVICIP79_bits;        // 0x350 Interrupt Priority Register n
NVICIP80_bits            : TNVIC_NVICIP80_bits;        // 0x351 Interrupt Priority Register n
NVICIP81_bits            : TNVIC_NVICIP81_bits;        // 0x352 Interrupt Priority Register n
NVICIP82_bits            : TNVIC_NVICIP82_bits;        // 0x353 Interrupt Priority Register n
NVICIP83_bits            : TNVIC_NVICIP83_bits;        // 0x354 Interrupt Priority Register n
NVICIP84_bits            : TNVIC_NVICIP84_bits;        // 0x355 Interrupt Priority Register n
NVICIP85_bits            : TNVIC_NVICIP85_bits;        // 0x356 Interrupt Priority Register n
NVICIP86_bits            : TNVIC_NVICIP86_bits;        // 0x357 Interrupt Priority Register n
NVICIP87_bits            : TNVIC_NVICIP87_bits;        // 0x358 Interrupt Priority Register n
NVICIP88_bits            : TNVIC_NVICIP88_bits;        // 0x359 Interrupt Priority Register n
NVICIP89_bits            : TNVIC_NVICIP89_bits;        // 0x35A Interrupt Priority Register n
NVICIP90_bits            : TNVIC_NVICIP90_bits;        // 0x35B Interrupt Priority Register n
NVICIP91_bits            : TNVIC_NVICIP91_bits;        // 0x35C Interrupt Priority Register n
NVICIP92_bits            : TNVIC_NVICIP92_bits;        // 0x35D Interrupt Priority Register n
NVICIP93_bits            : TNVIC_NVICIP93_bits;        // 0x35E Interrupt Priority Register n
NVICIP94_bits            : TNVIC_NVICIP94_bits;        // 0x35F Interrupt Priority Register n
NVICIP95_bits            : TNVIC_NVICIP95_bits;        // 0x360 Interrupt Priority Register n
NVICIP96_bits            : TNVIC_NVICIP96_bits;        // 0x361 Interrupt Priority Register n
NVICIP97_bits            : TNVIC_NVICIP97_bits;        // 0x362 Interrupt Priority Register n
NVICIP98_bits            : TNVIC_NVICIP98_bits;        // 0x363 Interrupt Priority Register n
NVICIP99_bits            : TNVIC_NVICIP99_bits;        // 0x364 Interrupt Priority Register n
NVICIP100_bits           : TNVIC_NVICIP100_bits;       // 0x365 Interrupt Priority Register n
NVICIP101_bits           : TNVIC_NVICIP101_bits;       // 0x366 Interrupt Priority Register n
NVICIP102_bits           : TNVIC_NVICIP102_bits;       // 0x367 Interrupt Priority Register n
NVICIP103_bits           : TNVIC_NVICIP103_bits;       // 0x368 Interrupt Priority Register n
NVICIP104_bits           : TNVIC_NVICIP104_bits;       // 0x369 Interrupt Priority Register n
NVICIP105_bits           : TNVIC_NVICIP105_bits;       // 0x36A Interrupt Priority Register n
RESERVED_bits5           : array[0..2709] of byte;
NVICSTIR_bits            : TNVIC_NVICSTIR_bits;        // 0xE04 Software Trigger Interrupt Register
);
end;

TNVICRegisters_bitbanded = record
  NVICISER0              : TNVIC_NVICISER0_bitbanded;  // 0x04 Interrupt Set Enable Register n
  NVICISER1              : TNVIC_NVICISER1_bitbanded;  // 0x08 Interrupt Set Enable Register n
  NVICISER2              : TNVIC_NVICISER2_bitbanded;  // 0x0C Interrupt Set Enable Register n
  NVICISER3              : TNVIC_NVICISER3_bitbanded;  // 0x10 Interrupt Set Enable Register n
  RESERVED0              : array[0..111] of array[0..7] of longWord;
  NVICICER0              : TNVIC_NVICICER0_bitbanded;  // 0x84 Interrupt Clear Enable Register n
  NVICICER1              : TNVIC_NVICICER1_bitbanded;  // 0x88 Interrupt Clear Enable Register n
  NVICICER2              : TNVIC_NVICICER2_bitbanded;  // 0x8C Interrupt Clear Enable Register n
  NVICICER3              : TNVIC_NVICICER3_bitbanded;  // 0x90 Interrupt Clear Enable Register n
  RESERVED1              : array[0..111] of array[0..7] of longWord;
  NVICISPR0              : TNVIC_NVICISPR0_bitbanded;  // 0x104 Interrupt Set Pending Register n
  NVICISPR1              : TNVIC_NVICISPR1_bitbanded;  // 0x108 Interrupt Set Pending Register n
  NVICISPR2              : TNVIC_NVICISPR2_bitbanded;  // 0x10C Interrupt Set Pending Register n
  NVICISPR3              : TNVIC_NVICISPR3_bitbanded;  // 0x110 Interrupt Set Pending Register n
  RESERVED2              : array[0..111] of array[0..7] of longWord;
  NVICICPR0              : TNVIC_NVICICPR0_bitbanded;  // 0x184 Interrupt Clear Pending Register n
  NVICICPR1              : TNVIC_NVICICPR1_bitbanded;  // 0x188 Interrupt Clear Pending Register n
  NVICICPR2              : TNVIC_NVICICPR2_bitbanded;  // 0x18C Interrupt Clear Pending Register n
  NVICICPR3              : TNVIC_NVICICPR3_bitbanded;  // 0x190 Interrupt Clear Pending Register n
  RESERVED3              : array[0..111] of array[0..7] of longWord;
  NVICIABR0              : TNVIC_NVICIABR0_bitbanded;  // 0x204 Interrupt Active bit Register n
  NVICIABR1              : TNVIC_NVICIABR1_bitbanded;  // 0x208 Interrupt Active bit Register n
  NVICIABR2              : TNVIC_NVICIABR2_bitbanded;  // 0x20C Interrupt Active bit Register n
  NVICIABR3              : TNVIC_NVICIABR3_bitbanded;  // 0x210 Interrupt Active bit Register n
  RESERVED4              : array[0..239] of array[0..7] of longWord;
  NVICIP0                : TNVIC_NVICIP0_bitbanded;    // 0x301 Interrupt Priority Register n
  NVICIP1                : TNVIC_NVICIP1_bitbanded;    // 0x302 Interrupt Priority Register n
  NVICIP2                : TNVIC_NVICIP2_bitbanded;    // 0x303 Interrupt Priority Register n
  NVICIP3                : TNVIC_NVICIP3_bitbanded;    // 0x304 Interrupt Priority Register n
  NVICIP4                : TNVIC_NVICIP4_bitbanded;    // 0x305 Interrupt Priority Register n
  NVICIP5                : TNVIC_NVICIP5_bitbanded;    // 0x306 Interrupt Priority Register n
  NVICIP6                : TNVIC_NVICIP6_bitbanded;    // 0x307 Interrupt Priority Register n
  NVICIP7                : TNVIC_NVICIP7_bitbanded;    // 0x308 Interrupt Priority Register n
  NVICIP8                : TNVIC_NVICIP8_bitbanded;    // 0x309 Interrupt Priority Register n
  NVICIP9                : TNVIC_NVICIP9_bitbanded;    // 0x30A Interrupt Priority Register n
  NVICIP10               : TNVIC_NVICIP10_bitbanded;   // 0x30B Interrupt Priority Register n
  NVICIP11               : TNVIC_NVICIP11_bitbanded;   // 0x30C Interrupt Priority Register n
  NVICIP12               : TNVIC_NVICIP12_bitbanded;   // 0x30D Interrupt Priority Register n
  NVICIP13               : TNVIC_NVICIP13_bitbanded;   // 0x30E Interrupt Priority Register n
  NVICIP14               : TNVIC_NVICIP14_bitbanded;   // 0x30F Interrupt Priority Register n
  NVICIP15               : TNVIC_NVICIP15_bitbanded;   // 0x310 Interrupt Priority Register n
  NVICIP16               : TNVIC_NVICIP16_bitbanded;   // 0x311 Interrupt Priority Register n
  NVICIP17               : TNVIC_NVICIP17_bitbanded;   // 0x312 Interrupt Priority Register n
  NVICIP18               : TNVIC_NVICIP18_bitbanded;   // 0x313 Interrupt Priority Register n
  NVICIP19               : TNVIC_NVICIP19_bitbanded;   // 0x314 Interrupt Priority Register n
  NVICIP20               : TNVIC_NVICIP20_bitbanded;   // 0x315 Interrupt Priority Register n
  NVICIP21               : TNVIC_NVICIP21_bitbanded;   // 0x316 Interrupt Priority Register n
  NVICIP22               : TNVIC_NVICIP22_bitbanded;   // 0x317 Interrupt Priority Register n
  NVICIP23               : TNVIC_NVICIP23_bitbanded;   // 0x318 Interrupt Priority Register n
  NVICIP24               : TNVIC_NVICIP24_bitbanded;   // 0x319 Interrupt Priority Register n
  NVICIP25               : TNVIC_NVICIP25_bitbanded;   // 0x31A Interrupt Priority Register n
  NVICIP26               : TNVIC_NVICIP26_bitbanded;   // 0x31B Interrupt Priority Register n
  NVICIP27               : TNVIC_NVICIP27_bitbanded;   // 0x31C Interrupt Priority Register n
  NVICIP28               : TNVIC_NVICIP28_bitbanded;   // 0x31D Interrupt Priority Register n
  NVICIP29               : TNVIC_NVICIP29_bitbanded;   // 0x31E Interrupt Priority Register n
  NVICIP30               : TNVIC_NVICIP30_bitbanded;   // 0x31F Interrupt Priority Register n
  NVICIP31               : TNVIC_NVICIP31_bitbanded;   // 0x320 Interrupt Priority Register n
  NVICIP32               : TNVIC_NVICIP32_bitbanded;   // 0x321 Interrupt Priority Register n
  NVICIP33               : TNVIC_NVICIP33_bitbanded;   // 0x322 Interrupt Priority Register n
  NVICIP34               : TNVIC_NVICIP34_bitbanded;   // 0x323 Interrupt Priority Register n
  NVICIP35               : TNVIC_NVICIP35_bitbanded;   // 0x324 Interrupt Priority Register n
  NVICIP36               : TNVIC_NVICIP36_bitbanded;   // 0x325 Interrupt Priority Register n
  NVICIP37               : TNVIC_NVICIP37_bitbanded;   // 0x326 Interrupt Priority Register n
  NVICIP38               : TNVIC_NVICIP38_bitbanded;   // 0x327 Interrupt Priority Register n
  NVICIP39               : TNVIC_NVICIP39_bitbanded;   // 0x328 Interrupt Priority Register n
  NVICIP40               : TNVIC_NVICIP40_bitbanded;   // 0x329 Interrupt Priority Register n
  NVICIP41               : TNVIC_NVICIP41_bitbanded;   // 0x32A Interrupt Priority Register n
  NVICIP42               : TNVIC_NVICIP42_bitbanded;   // 0x32B Interrupt Priority Register n
  NVICIP43               : TNVIC_NVICIP43_bitbanded;   // 0x32C Interrupt Priority Register n
  NVICIP44               : TNVIC_NVICIP44_bitbanded;   // 0x32D Interrupt Priority Register n
  NVICIP45               : TNVIC_NVICIP45_bitbanded;   // 0x32E Interrupt Priority Register n
  NVICIP46               : TNVIC_NVICIP46_bitbanded;   // 0x32F Interrupt Priority Register n
  NVICIP47               : TNVIC_NVICIP47_bitbanded;   // 0x330 Interrupt Priority Register n
  NVICIP48               : TNVIC_NVICIP48_bitbanded;   // 0x331 Interrupt Priority Register n
  NVICIP49               : TNVIC_NVICIP49_bitbanded;   // 0x332 Interrupt Priority Register n
  NVICIP50               : TNVIC_NVICIP50_bitbanded;   // 0x333 Interrupt Priority Register n
  NVICIP51               : TNVIC_NVICIP51_bitbanded;   // 0x334 Interrupt Priority Register n
  NVICIP52               : TNVIC_NVICIP52_bitbanded;   // 0x335 Interrupt Priority Register n
  NVICIP53               : TNVIC_NVICIP53_bitbanded;   // 0x336 Interrupt Priority Register n
  NVICIP54               : TNVIC_NVICIP54_bitbanded;   // 0x337 Interrupt Priority Register n
  NVICIP55               : TNVIC_NVICIP55_bitbanded;   // 0x338 Interrupt Priority Register n
  NVICIP56               : TNVIC_NVICIP56_bitbanded;   // 0x339 Interrupt Priority Register n
  NVICIP57               : TNVIC_NVICIP57_bitbanded;   // 0x33A Interrupt Priority Register n
  NVICIP58               : TNVIC_NVICIP58_bitbanded;   // 0x33B Interrupt Priority Register n
  NVICIP59               : TNVIC_NVICIP59_bitbanded;   // 0x33C Interrupt Priority Register n
  NVICIP60               : TNVIC_NVICIP60_bitbanded;   // 0x33D Interrupt Priority Register n
  NVICIP61               : TNVIC_NVICIP61_bitbanded;   // 0x33E Interrupt Priority Register n
  NVICIP62               : TNVIC_NVICIP62_bitbanded;   // 0x33F Interrupt Priority Register n
  NVICIP63               : TNVIC_NVICIP63_bitbanded;   // 0x340 Interrupt Priority Register n
  NVICIP64               : TNVIC_NVICIP64_bitbanded;   // 0x341 Interrupt Priority Register n
  NVICIP65               : TNVIC_NVICIP65_bitbanded;   // 0x342 Interrupt Priority Register n
  NVICIP66               : TNVIC_NVICIP66_bitbanded;   // 0x343 Interrupt Priority Register n
  NVICIP67               : TNVIC_NVICIP67_bitbanded;   // 0x344 Interrupt Priority Register n
  NVICIP68               : TNVIC_NVICIP68_bitbanded;   // 0x345 Interrupt Priority Register n
  NVICIP69               : TNVIC_NVICIP69_bitbanded;   // 0x346 Interrupt Priority Register n
  NVICIP70               : TNVIC_NVICIP70_bitbanded;   // 0x347 Interrupt Priority Register n
  NVICIP71               : TNVIC_NVICIP71_bitbanded;   // 0x348 Interrupt Priority Register n
  NVICIP72               : TNVIC_NVICIP72_bitbanded;   // 0x349 Interrupt Priority Register n
  NVICIP73               : TNVIC_NVICIP73_bitbanded;   // 0x34A Interrupt Priority Register n
  NVICIP74               : TNVIC_NVICIP74_bitbanded;   // 0x34B Interrupt Priority Register n
  NVICIP75               : TNVIC_NVICIP75_bitbanded;   // 0x34C Interrupt Priority Register n
  NVICIP76               : TNVIC_NVICIP76_bitbanded;   // 0x34D Interrupt Priority Register n
  NVICIP77               : TNVIC_NVICIP77_bitbanded;   // 0x34E Interrupt Priority Register n
  NVICIP78               : TNVIC_NVICIP78_bitbanded;   // 0x34F Interrupt Priority Register n
  NVICIP79               : TNVIC_NVICIP79_bitbanded;   // 0x350 Interrupt Priority Register n
  NVICIP80               : TNVIC_NVICIP80_bitbanded;   // 0x351 Interrupt Priority Register n
  NVICIP81               : TNVIC_NVICIP81_bitbanded;   // 0x352 Interrupt Priority Register n
  NVICIP82               : TNVIC_NVICIP82_bitbanded;   // 0x353 Interrupt Priority Register n
  NVICIP83               : TNVIC_NVICIP83_bitbanded;   // 0x354 Interrupt Priority Register n
  NVICIP84               : TNVIC_NVICIP84_bitbanded;   // 0x355 Interrupt Priority Register n
  NVICIP85               : TNVIC_NVICIP85_bitbanded;   // 0x356 Interrupt Priority Register n
  NVICIP86               : TNVIC_NVICIP86_bitbanded;   // 0x357 Interrupt Priority Register n
  NVICIP87               : TNVIC_NVICIP87_bitbanded;   // 0x358 Interrupt Priority Register n
  NVICIP88               : TNVIC_NVICIP88_bitbanded;   // 0x359 Interrupt Priority Register n
  NVICIP89               : TNVIC_NVICIP89_bitbanded;   // 0x35A Interrupt Priority Register n
  NVICIP90               : TNVIC_NVICIP90_bitbanded;   // 0x35B Interrupt Priority Register n
  NVICIP91               : TNVIC_NVICIP91_bitbanded;   // 0x35C Interrupt Priority Register n
  NVICIP92               : TNVIC_NVICIP92_bitbanded;   // 0x35D Interrupt Priority Register n
  NVICIP93               : TNVIC_NVICIP93_bitbanded;   // 0x35E Interrupt Priority Register n
  NVICIP94               : TNVIC_NVICIP94_bitbanded;   // 0x35F Interrupt Priority Register n
  NVICIP95               : TNVIC_NVICIP95_bitbanded;   // 0x360 Interrupt Priority Register n
  NVICIP96               : TNVIC_NVICIP96_bitbanded;   // 0x361 Interrupt Priority Register n
  NVICIP97               : TNVIC_NVICIP97_bitbanded;   // 0x362 Interrupt Priority Register n
  NVICIP98               : TNVIC_NVICIP98_bitbanded;   // 0x363 Interrupt Priority Register n
  NVICIP99               : TNVIC_NVICIP99_bitbanded;   // 0x364 Interrupt Priority Register n
  NVICIP100              : TNVIC_NVICIP100_bitbanded;  // 0x365 Interrupt Priority Register n
  NVICIP101              : TNVIC_NVICIP101_bitbanded;  // 0x366 Interrupt Priority Register n
  NVICIP102              : TNVIC_NVICIP102_bitbanded;  // 0x367 Interrupt Priority Register n
  NVICIP103              : TNVIC_NVICIP103_bitbanded;  // 0x368 Interrupt Priority Register n
  NVICIP104              : TNVIC_NVICIP104_bitbanded;  // 0x369 Interrupt Priority Register n
  NVICIP105              : TNVIC_NVICIP105_bitbanded;  // 0x36A Interrupt Priority Register n
  RESERVED5              : array[0..2709] of array[0..7] of longWord;
  NVICSTIR               : TNVIC_NVICSTIR_bitbanded;   // 0xE04 Software Trigger Interrupt Register
end;

// Oscillator
TOSC_CR_bits = bitpacked record
  SC16P                  : TBits_1;                    // [0:0] Oscillator 16 pF Capacitor Load Configure
  SC8P                   : TBits_1;                    // [1:1] Oscillator 8 pF Capacitor Load Configure
  SC4P                   : TBits_1;                    // [2:2] Oscillator 4 pF Capacitor Load Configure
  SC2P                   : TBits_1;                    // [3:3] Oscillator 2 pF Capacitor Load Configure
  RESERVED0              : TBits_1;                    // [4:4] no description available
  EREFSTEN               : TBits_1;                    // [5:5] External Reference Stop Enable
  RESERVED1              : TBits_1;                    // [6:6] no description available
  ERCLKEN                : TBits_1;                    // [7:7] External Reference Enable
end;

TOSC_CR_bitbanded = record
  SC16P                  : longWord;                   // [0:0] Oscillator 16 pF Capacitor Load Configure
  SC8P                   : longWord;                   // [1:1] Oscillator 8 pF Capacitor Load Configure
  SC4P                   : longWord;                   // [2:2] Oscillator 4 pF Capacitor Load Configure
  SC2P                   : longWord;                   // [3:3] Oscillator 2 pF Capacitor Load Configure
  RESERVED0              : longWord;                   // [4:4] no description available
  EREFSTEN               : longWord;                   // [5:5] External Reference Stop Enable
  RESERVED1              : longWord;                   // [6:6] no description available
  ERCLKEN                : longWord;                   // [7:7] External Reference Enable
end;

TOSC_Registers = record
  case boolean of false: (
  CR                     : byte;                       // 0x00 OSC Control Register
);
true : (
CR_bits                  : TOSC_CR_bits;               // 0x01 OSC Control Register
);
end;

TOSCRegisters_bitbanded = record
  CR                     : TOSC_CR_bitbanded;          // 0x01 OSC Control Register
end;

// Programmable Delay Block
TPDB0_SC_bits = bitpacked record
  LDOK                   : TBits_1;                    // [0:0] Load OK
  CONT                   : TBits_1;                    // [1:1] Continuous Mode Enable
  MULT                   : TBits_2;                    // [2:3] Multiplication Factor Select for Prescaler
  RESERVED0              : TBits_1;                    // [4:4] no description available
  PDBIE                  : TBits_1;                    // [5:5] PDB Interrupt Enable.
  PDBIF                  : TBits_1;                    // [6:6] PDB Interrupt Flag
  PDBEN                  : TBits_1;                    // [7:7] PDB Enable
  TRGSEL                 : TBits_4;                    // [8:11] Trigger Input Source Select
  PRESCALER              : TBits_3;                    // [12:14] Prescaler Divider Select
  DMAEN                  : TBits_1;                    // [15:15] DMA Enable
  SWTRIG                 : TBits_1;                    // [16:16] Software Trigger
  PDBEIE                 : TBits_1;                    // [17:17] PDB Sequence Error Interrupt Enable
  LDMOD                  : TBits_2;                    // [18:19] Load Mode Select
  RESERVED1              : TBits_12;                   // [20:31] no description available
end;

TPDB0_SC_bitbanded = record
  LDOK                   : longWord;                   // [0:0] Load OK
  CONT                   : longWord;                   // [1:1] Continuous Mode Enable
  MULT                   : array[0..1] of longWord;    // [2:3] Multiplication Factor Select for Prescaler
  RESERVED0              : longWord;                   // [4:4] no description available
  PDBIE                  : longWord;                   // [5:5] PDB Interrupt Enable.
  PDBIF                  : longWord;                   // [6:6] PDB Interrupt Flag
  PDBEN                  : longWord;                   // [7:7] PDB Enable
  TRGSEL                 : array[0..3] of longWord;    // [8:11] Trigger Input Source Select
  PRESCALER              : array[0..2] of longWord;    // [12:14] Prescaler Divider Select
  DMAEN                  : longWord;                   // [15:15] DMA Enable
  SWTRIG                 : longWord;                   // [16:16] Software Trigger
  PDBEIE                 : longWord;                   // [17:17] PDB Sequence Error Interrupt Enable
  LDMOD                  : array[0..1] of longWord;    // [18:19] Load Mode Select
  RESERVED1              : array[0..11] of longWord;   // [20:31] no description available
end;

TPDB0_MOD_bits = bitpacked record
  &MOD                   : TBits_16;                   // [0:15] PDB Modulus.
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TPDB0_MOD_bitbanded = record
  &MOD                   : array[0..15] of longWord;   // [0:15] PDB Modulus.
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TPDB0_CNT_bits = bitpacked record
  CNT                    : TBits_16;                   // [0:15] PDB Counter
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TPDB0_CNT_bitbanded = record
  CNT                    : array[0..15] of longWord;   // [0:15] PDB Counter
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TPDB0_IDLY_bits = bitpacked record
  IDLY                   : TBits_16;                   // [0:15] PDB Interrupt Delay
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TPDB0_IDLY_bitbanded = record
  IDLY                   : array[0..15] of longWord;   // [0:15] PDB Interrupt Delay
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TPDB0_CHC1_bits = bitpacked record
  EN                     : TBits_8;                    // [0:7] PDB Channel Pre-Trigger Enable
  TOS                    : TBits_8;                    // [8:15] PDB Channel Pre-Trigger Output Select
  BB                     : TBits_8;                    // [16:23] PDB Channel Pre-Trigger Back-to-Back Operation Enable
  RESERVED0              : TBits_8;                    // [24:31] no description available
end;

TPDB0_CHC1_bitbanded = record
  EN                     : array[0..7] of longWord;    // [0:7] PDB Channel Pre-Trigger Enable
  TOS                    : array[0..7] of longWord;    // [8:15] PDB Channel Pre-Trigger Output Select
  BB                     : array[0..7] of longWord;    // [16:23] PDB Channel Pre-Trigger Back-to-Back Operation Enable
  RESERVED0              : array[0..7] of longWord;    // [24:31] no description available
end;

TPDB0_CHS_bits = bitpacked record
  ERR                    : TBits_8;                    // [0:7] PDB Channel Sequence Error Flags
  RESERVED0              : TBits_8;                    // [8:15] no description available
  CF                     : TBits_8;                    // [16:23] PDB Channel Flags
  RESERVED1              : TBits_8;                    // [24:31] no description available
end;

TPDB0_CHS_bitbanded = record
  ERR                    : array[0..7] of longWord;    // [0:7] PDB Channel Sequence Error Flags
  RESERVED0              : array[0..7] of longWord;    // [8:15] no description available
  CF                     : array[0..7] of longWord;    // [16:23] PDB Channel Flags
  RESERVED1              : array[0..7] of longWord;    // [24:31] no description available
end;

TPDB0_CHDLY0_bits = bitpacked record
  DLY                    : TBits_16;                   // [0:15] PDB Channel Delay
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TPDB0_CHDLY0_bitbanded = record
  DLY                    : array[0..15] of longWord;   // [0:15] PDB Channel Delay
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TPDB0_CHDLY1_bits = bitpacked record
  DLY                    : TBits_16;                   // [0:15] PDB Channel Delay
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TPDB0_CHDLY1_bitbanded = record
  DLY                    : array[0..15] of longWord;   // [0:15] PDB Channel Delay
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TPDB0_DACINTC_bits = bitpacked record
  TOE                    : TBits_1;                    // [0:0] DAC Interval Trigger Enable
  EXT                    : TBits_1;                    // [1:1] DAC External Trigger Input Enable
  RESERVED0              : TBits_30;                   // [2:31] no description available
end;

TPDB0_DACINTC_bitbanded = record
  TOE                    : longWord;                   // [0:0] DAC Interval Trigger Enable
  EXT                    : longWord;                   // [1:1] DAC External Trigger Input Enable
  RESERVED0              : array[0..29] of longWord;   // [2:31] no description available
end;

TPDB0_DACINT_bits = bitpacked record
  INT                    : TBits_16;                   // [0:15] DAC Interval
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TPDB0_DACINT_bitbanded = record
  INT                    : array[0..15] of longWord;   // [0:15] DAC Interval
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TPDB0_POEN_bits = bitpacked record
  POEN                   : TBits_8;                    // [0:7] PDB Pulse-Out Enable
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TPDB0_POEN_bitbanded = record
  POEN                   : array[0..7] of longWord;    // [0:7] PDB Pulse-Out Enable
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TPDB0_PODLY_bits = bitpacked record
  DLY2                   : TBits_16;                   // [0:15] PDB Pulse-Out Delay 2
  DLY1                   : TBits_16;                   // [16:31] PDB Pulse-Out Delay 1
end;

TPDB0_PODLY_bitbanded = record
  DLY2                   : array[0..15] of longWord;   // [0:15] PDB Pulse-Out Delay 2
  DLY1                   : array[0..15] of longWord;   // [16:31] PDB Pulse-Out Delay 1
end;

TPDB0_Registers = record
  case boolean of false: (
  SC                     : longWord;                   // 0x00 Status and Control Register
  &MOD                   : longWord;                   // 0x04 Modulus Register
  CNT                    : longWord;                   // 0x08 Counter Register
  IDLY                   : longWord;                   // 0x0C Interrupt Delay Register
  CH0C1                  : longWord;                   // 0x10 Channel n Control Register 1
  CH0S                   : longWord;                   // 0x14 Channel n Status Register
  CH0DLY0                : longWord;                   // 0x18 Channel n Delay 0 Register
  CH0DLY1                : longWord;                   // 0x1C Channel n Delay 1 Register
  RESERVED0              : array[0..5] of longWord;    // 0x20
  CH1C1                  : longWord;                   // 0x38 Channel n Control Register 1
  CH1S                   : longWord;                   // 0x3C Channel n Status Register
  CH1DLY0                : longWord;                   // 0x40 Channel n Delay 0 Register
  CH1DLY1                : longWord;                   // 0x44 Channel n Delay 1 Register
  RESERVED1              : array[0..65] of longWord;   // 0x48
  DACINTC                : longWord;                   // 0x150 DAC Interval Trigger n Control Register
  DACINT                 : longWord;                   // 0x154 DAC Interval n Register
  RESERVED2              : array[0..13] of longWord;   // 0x158
  POEN                   : longWord;                   // 0x190 Pulse-Out n Enable Register
  PO0DLY                 : longWord;                   // 0x194 Pulse-Out n Delay Register
  PO1DLY                 : longWord;                   // 0x198 Pulse-Out n Delay Register
  PO2DLY                 : longWord;                   // 0x19C Pulse-Out n Delay Register
);
true : (
SC_bits                  : TPDB0_SC_bits;              // 0x04 Status and Control Register
MOD_bits                 : TPDB0_MOD_bits;             // 0x08 Modulus Register
CNT_bits                 : TPDB0_CNT_bits;             // 0x0C Counter Register
IDLY_bits                : TPDB0_IDLY_bits;            // 0x10 Interrupt Delay Register
CH0C1_bits               : longWord;                   // 0x10 Channel n Control Register 1
CH0S_bits                : longWord;                   // 0x14 Channel n Status Register
CH0DLY0_bits             : longWord;                   // 0x18 Channel n Delay 0 Register
CH0DLY1_bits             : longWord;                   // 0x1C Channel n Delay 1 Register
RESERVED_bits0           : array[0..5] of longWord;
CH1C1_bits               : longWord;                   // 0x38 Channel n Control Register 1
CH1S_bits                : longWord;                   // 0x3C Channel n Status Register
CH1DLY0_bits             : longWord;                   // 0x40 Channel n Delay 0 Register
CH1DLY1_bits             : longWord;                   // 0x44 Channel n Delay 1 Register
RESERVED_bits1           : array[0..65] of longWord;
DACINTC_bits             : TPDB0_DACINTC_bits;         // 0x154 DAC Interval Trigger n Control Register
DACINT_bits              : TPDB0_DACINT_bits;          // 0x158 DAC Interval n Register
RESERVED_bits2           : array[0..13] of longWord;
POEN_bits                : TPDB0_POEN_bits;            // 0x194 Pulse-Out n Enable Register
PO0DLY_bits              : longWord;                   // 0x194 Pulse-Out n Delay Register
PO1DLY_bits              : longWord;                   // 0x198 Pulse-Out n Delay Register
PO2DLY_bits              : longWord;                   // 0x19C Pulse-Out n Delay Register
);
end;

TPDB0Registers_bitbanded = record
  SC                     : TPDB0_SC_bitbanded;         // 0x04 Status and Control Register
  &MOD                   : TPDB0_MOD_bitbanded;        // 0x08 Modulus Register
  CNT                    : TPDB0_CNT_bitbanded;        // 0x0C Counter Register
  IDLY                   : TPDB0_IDLY_bitbanded;       // 0x10 Interrupt Delay Register
  CH0C1_bitbanded        : longWord;                   // 0x10 Channel n Control Register 1
  CH0S_bitbanded         : longWord;                   // 0x14 Channel n Status Register
  CH0DLY0_bitbanded      : longWord;                   // 0x18 Channel n Delay 0 Register
  CH0DLY1_bitbanded      : longWord;                   // 0x1C Channel n Delay 1 Register
  RESERVED0              : array[0..23] of array[0..7] of longWord;
  CH1C1_bitbanded        : longWord;                   // 0x38 Channel n Control Register 1
  CH1S_bitbanded         : longWord;                   // 0x3C Channel n Status Register
  CH1DLY0_bitbanded      : longWord;                   // 0x40 Channel n Delay 0 Register
  CH1DLY1_bitbanded      : longWord;                   // 0x44 Channel n Delay 1 Register
  RESERVED1              : array[0..263] of array[0..7] of longWord;
  DACINTC                : TPDB0_DACINTC_bitbanded;    // 0x154 DAC Interval Trigger n Control Register
  DACINT                 : TPDB0_DACINT_bitbanded;     // 0x158 DAC Interval n Register
  RESERVED2              : array[0..55] of array[0..7] of longWord;
  POEN                   : TPDB0_POEN_bitbanded;       // 0x194 Pulse-Out n Enable Register
  PO0DLY_bitbanded       : longWord;                   // 0x194 Pulse-Out n Delay Register
  PO1DLY_bitbanded       : longWord;                   // 0x198 Pulse-Out n Delay Register
  PO2DLY_bitbanded       : longWord;                   // 0x19C Pulse-Out n Delay Register
end;

// Periodic Interrupt Timer
TPIT_MCR_bits = bitpacked record
  FRZ                    : TBits_1;                    // [0:0] Freeze
  MDIS                   : TBits_1;                    // [1:1] Module Disable
  RESERVED0              : TBits_30;                   // [2:31] no description available
end;

TPIT_MCR_bitbanded = record
  FRZ                    : longWord;                   // [0:0] Freeze
  MDIS                   : longWord;                   // [1:1] Module Disable
  RESERVED0              : array[0..29] of longWord;   // [2:31] no description available
end;

TPIT_LDVAL_bits = bitpacked record
  TSV                    : TBits_32;                   // [0:31] Timer Start Value Bits
end;

TPIT_LDVAL_bitbanded = record
  TSV                    : array[0..31] of longWord;   // [0:31] Timer Start Value Bits
end;

TPIT_CVAL_bits = bitpacked record
  TVL                    : TBits_32;                   // [0:31] Current Timer Value
end;

TPIT_CVAL_bitbanded = record
  TVL                    : array[0..31] of longWord;   // [0:31] Current Timer Value
end;

TPIT_TCTRL_bits = bitpacked record
  TEN                    : TBits_1;                    // [0:0] Timer Enable Bit.
  TIE                    : TBits_1;                    // [1:1] Timer Interrupt Enable Bit.
  RESERVED0              : TBits_30;                   // [2:31] no description available
end;

TPIT_TCTRL_bitbanded = record
  TEN                    : longWord;                   // [0:0] Timer Enable Bit.
  TIE                    : longWord;                   // [1:1] Timer Interrupt Enable Bit.
  RESERVED0              : array[0..29] of longWord;   // [2:31] no description available
end;

TPIT_TFLG_bits = bitpacked record
  TIF                    : TBits_1;                    // [0:0] Timer Interrupt Flag.
  RESERVED0              : TBits_31;                   // [1:31] no description available
end;

TPIT_TFLG_bitbanded = record
  TIF                    : longWord;                   // [0:0] Timer Interrupt Flag.
  RESERVED0              : array[0..30] of longWord;   // [1:31] no description available
end;

TPIT_Registers = record
  case boolean of false: (
  MCR                    : longWord;                   // 0x00 PIT Module Control Register
  RESERVED0              : array[0..62] of longWord;   // 0x04
  LDVAL0                 : longWord;                   // 0x100 Timer Load Value Register
  CVAL0                  : longWord;                   // 0x104 Current Timer Value Register
  TCTRL0                 : longWord;                   // 0x108 Timer Control Register
  TFLG0                  : longWord;                   // 0x10C Timer Flag Register
  LDVAL1                 : longWord;                   // 0x110 Timer Load Value Register
  CVAL1                  : longWord;                   // 0x114 Current Timer Value Register
  TCTRL1                 : longWord;                   // 0x118 Timer Control Register
  TFLG1                  : longWord;                   // 0x11C Timer Flag Register
  LDVAL2                 : longWord;                   // 0x120 Timer Load Value Register
  CVAL2                  : longWord;                   // 0x124 Current Timer Value Register
  TCTRL2                 : longWord;                   // 0x128 Timer Control Register
  TFLG2                  : longWord;                   // 0x12C Timer Flag Register
  LDVAL3                 : longWord;                   // 0x130 Timer Load Value Register
  CVAL3                  : longWord;                   // 0x134 Current Timer Value Register
  TCTRL3                 : longWord;                   // 0x138 Timer Control Register
  TFLG3                  : longWord;                   // 0x13C Timer Flag Register
);
true : (
MCR_bits                 : TPIT_MCR_bits;              // 0x04 PIT Module Control Register
RESERVED_bits0           : array[0..62] of longWord;
LDVAL0_bits              : TPIT_LDVAL_bits;            // 0x104 Timer Load Value Register
CVAL0_bits               : TPIT_CVAL_bits;             // 0x108 Current Timer Value Register
TCTRL0_bits              : TPIT_TCTRL_bits;            // 0x10C Timer Control Register
TFLG0_bits               : TPIT_TFLG_bits;             // 0x110 Timer Flag Register
LDVAL1_bits              : TPIT_LDVAL_bits;            // 0x114 Timer Load Value Register
CVAL1_bits               : TPIT_CVAL_bits;             // 0x118 Current Timer Value Register
TCTRL1_bits              : TPIT_TCTRL_bits;            // 0x11C Timer Control Register
TFLG1_bits               : TPIT_TFLG_bits;             // 0x120 Timer Flag Register
LDVAL2_bits              : TPIT_LDVAL_bits;            // 0x124 Timer Load Value Register
CVAL2_bits               : TPIT_CVAL_bits;             // 0x128 Current Timer Value Register
TCTRL2_bits              : TPIT_TCTRL_bits;            // 0x12C Timer Control Register
TFLG2_bits               : TPIT_TFLG_bits;             // 0x130 Timer Flag Register
LDVAL3_bits              : TPIT_LDVAL_bits;            // 0x134 Timer Load Value Register
CVAL3_bits               : TPIT_CVAL_bits;             // 0x138 Current Timer Value Register
TCTRL3_bits              : TPIT_TCTRL_bits;            // 0x13C Timer Control Register
TFLG3_bits               : TPIT_TFLG_bits;             // 0x140 Timer Flag Register
);
end;

TPITRegisters_bitbanded = record
  MCR                    : TPIT_MCR_bitbanded;         // 0x04 PIT Module Control Register
  RESERVED0              : array[0..251] of array[0..7] of longWord;
  LDVAL0                 : TPIT_LDVAL_bitbanded;       // 0x104 Timer Load Value Register
  CVAL0                  : TPIT_CVAL_bitbanded;        // 0x108 Current Timer Value Register
  TCTRL0                 : TPIT_TCTRL_bitbanded;       // 0x10C Timer Control Register
  TFLG0                  : TPIT_TFLG_bitbanded;        // 0x110 Timer Flag Register
  LDVAL1                 : TPIT_LDVAL_bitbanded;       // 0x114 Timer Load Value Register
  CVAL1                  : TPIT_CVAL_bitbanded;        // 0x118 Current Timer Value Register
  TCTRL1                 : TPIT_TCTRL_bitbanded;       // 0x11C Timer Control Register
  TFLG1                  : TPIT_TFLG_bitbanded;        // 0x120 Timer Flag Register
  LDVAL2                 : TPIT_LDVAL_bitbanded;       // 0x124 Timer Load Value Register
  CVAL2                  : TPIT_CVAL_bitbanded;        // 0x128 Current Timer Value Register
  TCTRL2                 : TPIT_TCTRL_bitbanded;       // 0x12C Timer Control Register
  TFLG2                  : TPIT_TFLG_bitbanded;        // 0x130 Timer Flag Register
  LDVAL3                 : TPIT_LDVAL_bitbanded;       // 0x134 Timer Load Value Register
  CVAL3                  : TPIT_CVAL_bitbanded;        // 0x138 Current Timer Value Register
  TCTRL3                 : TPIT_TCTRL_bitbanded;       // 0x13C Timer Control Register
  TFLG3                  : TPIT_TFLG_bitbanded;        // 0x140 Timer Flag Register
end;

// Power Management Controller
TPMC_LVDSC1_bits = bitpacked record
  LVDV                   : TBits_2;                    // [0:1] Low-Voltage Detect Voltage Select
  RESERVED0              : TBits_2;                    // [2:3] no description available
  LVDRE                  : TBits_1;                    // [4:4] Low-Voltage Detect Reset Enable
  LVDIE                  : TBits_1;                    // [5:5] Low-Voltage Detect Interrupt Enable
  LVDACK                 : TBits_1;                    // [6:6] Low-Voltage Detect Acknowledge
  LVDF                   : TBits_1;                    // [7:7] Low-Voltage Detect Flag
end;

TPMC_LVDSC1_bitbanded = record
  LVDV                   : array[0..1] of longWord;    // [0:1] Low-Voltage Detect Voltage Select
  RESERVED0              : array[0..1] of longWord;    // [2:3] no description available
  LVDRE                  : longWord;                   // [4:4] Low-Voltage Detect Reset Enable
  LVDIE                  : longWord;                   // [5:5] Low-Voltage Detect Interrupt Enable
  LVDACK                 : longWord;                   // [6:6] Low-Voltage Detect Acknowledge
  LVDF                   : longWord;                   // [7:7] Low-Voltage Detect Flag
end;

TPMC_LVDSC2_bits = bitpacked record
  LVWV                   : TBits_2;                    // [0:1] Low-Voltage Warning Voltage Select
  RESERVED0              : TBits_3;                    // [2:4] no description available
  LVWIE                  : TBits_1;                    // [5:5] Low-Voltage Warning Interrupt Enable
  LVWACK                 : TBits_1;                    // [6:6] Low-Voltage Warning Acknowledge
  LVWF                   : TBits_1;                    // [7:7] Low-Voltage Warning Flag
end;

TPMC_LVDSC2_bitbanded = record
  LVWV                   : array[0..1] of longWord;    // [0:1] Low-Voltage Warning Voltage Select
  RESERVED0              : array[0..2] of longWord;    // [2:4] no description available
  LVWIE                  : longWord;                   // [5:5] Low-Voltage Warning Interrupt Enable
  LVWACK                 : longWord;                   // [6:6] Low-Voltage Warning Acknowledge
  LVWF                   : longWord;                   // [7:7] Low-Voltage Warning Flag
end;

TPMC_REGSC_bits = bitpacked record
  BGBE                   : TBits_1;                    // [0:0] Bandgap Buffer Enable
  RESERVED0              : TBits_1;                    // [1:1] no description available
  REGONS                 : TBits_1;                    // [2:2] Regulator in Run Regulation Status
  ACKISO                 : TBits_1;                    // [3:3] Acknowledge Isolation
  BGEN                   : TBits_1;                    // [4:4] Bandgap enable in VLPx operation
  RESERVED1              : TBits_3;                    // [5:7] no description available
end;

TPMC_REGSC_bitbanded = record
  BGBE                   : longWord;                   // [0:0] Bandgap Buffer Enable
  RESERVED0              : longWord;                   // [1:1] no description available
  REGONS                 : longWord;                   // [2:2] Regulator in Run Regulation Status
  ACKISO                 : longWord;                   // [3:3] Acknowledge Isolation
  BGEN                   : longWord;                   // [4:4] Bandgap enable in VLPx operation
  RESERVED1              : array[0..2] of longWord;    // [5:7] no description available
end;

TPMC_Registers = record
  case boolean of false: (
  LVDSC1                 : byte;                       // 0x00 Low Voltage Detect Status and Control 1 Register
  LVDSC2                 : byte;                       // 0x01 Low Voltage Detect Status and Control 2 Register
  REGSC                  : byte;                       // 0x02 Regulator Status and Control Register
);
true : (
LVDSC1_bits              : TPMC_LVDSC1_bits;           // 0x01 Low Voltage Detect Status and Control 1 Register
LVDSC2_bits              : TPMC_LVDSC2_bits;           // 0x02 Low Voltage Detect Status and Control 2 Register
REGSC_bits               : TPMC_REGSC_bits;            // 0x03 Regulator Status and Control Register
);
end;

TPMCRegisters_bitbanded = record
  LVDSC1                 : TPMC_LVDSC1_bitbanded;      // 0x01 Low Voltage Detect Status and Control 1 Register
  LVDSC2                 : TPMC_LVDSC2_bitbanded;      // 0x02 Low Voltage Detect Status and Control 2 Register
  REGSC                  : TPMC_REGSC_bitbanded;       // 0x03 Regulator Status and Control Register
end;

// Pin Control and Interrupts
TPORTA_PCR_bits = bitpacked record
  PS                     : TBits_1;                    // [0:0] Pull Select
  PE                     : TBits_1;                    // [1:1] Pull Enable
  SRE                    : TBits_1;                    // [2:2] Slew Rate Enable
  RESERVED0              : TBits_1;                    // [3:3] no description available
  PFE                    : TBits_1;                    // [4:4] Passive Filter Enable
  ODE                    : TBits_1;                    // [5:5] Open Drain Enable
  DSE                    : TBits_1;                    // [6:6] Drive Strength Enable
  RESERVED1              : TBits_1;                    // [7:7] no description available
  MUX                    : TBits_3;                    // [8:10] Pin Mux Control
  RESERVED2              : TBits_4;                    // [11:14] no description available
  LK                     : TBits_1;                    // [15:15] Lock Register
  IRQC                   : TBits_4;                    // [16:19] Interrupt Configuration
  RESERVED3              : TBits_4;                    // [20:23] no description available
  ISF                    : TBits_1;                    // [24:24] Interrupt Status Flag
  RESERVED4              : TBits_7;                    // [25:31] no description available
end;

TPORTA_PCR_bitbanded = record
  PS                     : longWord;                   // [0:0] Pull Select
  PE                     : longWord;                   // [1:1] Pull Enable
  SRE                    : longWord;                   // [2:2] Slew Rate Enable
  RESERVED0              : longWord;                   // [3:3] no description available
  PFE                    : longWord;                   // [4:4] Passive Filter Enable
  ODE                    : longWord;                   // [5:5] Open Drain Enable
  DSE                    : longWord;                   // [6:6] Drive Strength Enable
  RESERVED1              : longWord;                   // [7:7] no description available
  MUX                    : array[0..2] of longWord;    // [8:10] Pin Mux Control
  RESERVED2              : array[0..3] of longWord;    // [11:14] no description available
  LK                     : longWord;                   // [15:15] Lock Register
  IRQC                   : array[0..3] of longWord;    // [16:19] Interrupt Configuration
  RESERVED3              : array[0..3] of longWord;    // [20:23] no description available
  ISF                    : longWord;                   // [24:24] Interrupt Status Flag
  RESERVED4              : array[0..6] of longWord;    // [25:31] no description available
end;

TPORTA_GPCLR_bits = bitpacked record
  GPWD                   : TBits_16;                   // [0:15] Global Pin Write Data
  GPWE                   : TBits_16;                   // [16:31] Global Pin Write Enable
end;

TPORTA_GPCLR_bitbanded = record
  GPWD                   : array[0..15] of longWord;   // [0:15] Global Pin Write Data
  GPWE                   : array[0..15] of longWord;   // [16:31] Global Pin Write Enable
end;

TPORTA_GPCHR_bits = bitpacked record
  GPWD                   : TBits_16;                   // [0:15] Global Pin Write Data
  GPWE                   : TBits_16;                   // [16:31] Global Pin Write Enable
end;

TPORTA_GPCHR_bitbanded = record
  GPWD                   : array[0..15] of longWord;   // [0:15] Global Pin Write Data
  GPWE                   : array[0..15] of longWord;   // [16:31] Global Pin Write Enable
end;

TPORTA_ISFR_bits = bitpacked record
  ISF                    : TBits_32;                   // [0:31] Interrupt Status Flag
end;

TPORTA_ISFR_bitbanded = record
  ISF                    : array[0..31] of longWord;   // [0:31] Interrupt Status Flag
end;

TPORTA_DFER_bits = bitpacked record
  DFE                    : TBits_32;                   // [0:31] Digital Filter Enable
end;

TPORTA_DFER_bitbanded = record
  DFE                    : array[0..31] of longWord;   // [0:31] Digital Filter Enable
end;

TPORTA_DFCR_bits = bitpacked record
  CS                     : TBits_1;                    // [0:0] Clock Source
  RESERVED0              : TBits_31;                   // [1:31] no description available
end;

TPORTA_DFCR_bitbanded = record
  CS                     : longWord;                   // [0:0] Clock Source
  RESERVED0              : array[0..30] of longWord;   // [1:31] no description available
end;

TPORTA_DFWR_bits = bitpacked record
  FILT                   : TBits_5;                    // [0:4] Filter Length
  RESERVED0              : TBits_27;                   // [5:31] no description available
end;

TPORTA_DFWR_bitbanded = record
  FILT                   : array[0..4] of longWord;    // [0:4] Filter Length
  RESERVED0              : array[0..26] of longWord;   // [5:31] no description available
end;

TPORTA_Registers = record
  case boolean of false: (
  PCR0                   : longWord;                   // 0x00 Pin Control Register n
  PCR1                   : longWord;                   // 0x04 Pin Control Register n
  PCR2                   : longWord;                   // 0x08 Pin Control Register n
  PCR3                   : longWord;                   // 0x0C Pin Control Register n
  PCR4                   : longWord;                   // 0x10 Pin Control Register n
  PCR5                   : longWord;                   // 0x14 Pin Control Register n
  PCR6                   : longWord;                   // 0x18 Pin Control Register n
  PCR7                   : longWord;                   // 0x1C Pin Control Register n
  PCR8                   : longWord;                   // 0x20 Pin Control Register n
  PCR9                   : longWord;                   // 0x24 Pin Control Register n
  PCR10                  : longWord;                   // 0x28 Pin Control Register n
  PCR11                  : longWord;                   // 0x2C Pin Control Register n
  PCR12                  : longWord;                   // 0x30 Pin Control Register n
  PCR13                  : longWord;                   // 0x34 Pin Control Register n
  PCR14                  : longWord;                   // 0x38 Pin Control Register n
  PCR15                  : longWord;                   // 0x3C Pin Control Register n
  PCR16                  : longWord;                   // 0x40 Pin Control Register n
  PCR17                  : longWord;                   // 0x44 Pin Control Register n
  PCR18                  : longWord;                   // 0x48 Pin Control Register n
  PCR19                  : longWord;                   // 0x4C Pin Control Register n
  PCR20                  : longWord;                   // 0x50 Pin Control Register n
  PCR21                  : longWord;                   // 0x54 Pin Control Register n
  PCR22                  : longWord;                   // 0x58 Pin Control Register n
  PCR23                  : longWord;                   // 0x5C Pin Control Register n
  PCR24                  : longWord;                   // 0x60 Pin Control Register n
  PCR25                  : longWord;                   // 0x64 Pin Control Register n
  PCR26                  : longWord;                   // 0x68 Pin Control Register n
  PCR27                  : longWord;                   // 0x6C Pin Control Register n
  PCR28                  : longWord;                   // 0x70 Pin Control Register n
  PCR29                  : longWord;                   // 0x74 Pin Control Register n
  PCR30                  : longWord;                   // 0x78 Pin Control Register n
  PCR31                  : longWord;                   // 0x7C Pin Control Register n
  GPCLR                  : longWord;                   // 0x80 Global Pin Control Low Register
  GPCHR                  : longWord;                   // 0x84 Global Pin Control High Register
  RESERVED0              : array[0..5] of longWord;    // 0x88
  ISFR                   : longWord;                   // 0xA0 Interrupt Status Flag Register
  RESERVED1              : array[0..6] of longWord;    // 0xA4
  DFER                   : longWord;                   // 0xC0 Digital Filter Enable Register
  DFCR                   : longWord;                   // 0xC4 Digital Filter Clock Register
  DFWR                   : longWord;                   // 0xC8 Digital Filter Width Register
);
true : (
PCR0_bits                : TPORTA_PCR_bits;            // 0x04 Pin Control Register n
PCR1_bits                : TPORTA_PCR_bits;            // 0x08 Pin Control Register n
PCR2_bits                : TPORTA_PCR_bits;            // 0x0C Pin Control Register n
PCR3_bits                : TPORTA_PCR_bits;            // 0x10 Pin Control Register n
PCR4_bits                : TPORTA_PCR_bits;            // 0x14 Pin Control Register n
PCR5_bits                : TPORTA_PCR_bits;            // 0x18 Pin Control Register n
PCR6_bits                : TPORTA_PCR_bits;            // 0x1C Pin Control Register n
PCR7_bits                : TPORTA_PCR_bits;            // 0x20 Pin Control Register n
PCR8_bits                : TPORTA_PCR_bits;            // 0x24 Pin Control Register n
PCR9_bits                : TPORTA_PCR_bits;            // 0x28 Pin Control Register n
PCR10_bits               : TPORTA_PCR_bits;            // 0x2C Pin Control Register n
PCR11_bits               : TPORTA_PCR_bits;            // 0x30 Pin Control Register n
PCR12_bits               : TPORTA_PCR_bits;            // 0x34 Pin Control Register n
PCR13_bits               : TPORTA_PCR_bits;            // 0x38 Pin Control Register n
PCR14_bits               : TPORTA_PCR_bits;            // 0x3C Pin Control Register n
PCR15_bits               : TPORTA_PCR_bits;            // 0x40 Pin Control Register n
PCR16_bits               : TPORTA_PCR_bits;            // 0x44 Pin Control Register n
PCR17_bits               : TPORTA_PCR_bits;            // 0x48 Pin Control Register n
PCR18_bits               : TPORTA_PCR_bits;            // 0x4C Pin Control Register n
PCR19_bits               : TPORTA_PCR_bits;            // 0x50 Pin Control Register n
PCR20_bits               : TPORTA_PCR_bits;            // 0x54 Pin Control Register n
PCR21_bits               : TPORTA_PCR_bits;            // 0x58 Pin Control Register n
PCR22_bits               : TPORTA_PCR_bits;            // 0x5C Pin Control Register n
PCR23_bits               : TPORTA_PCR_bits;            // 0x60 Pin Control Register n
PCR24_bits               : TPORTA_PCR_bits;            // 0x64 Pin Control Register n
PCR25_bits               : TPORTA_PCR_bits;            // 0x68 Pin Control Register n
PCR26_bits               : TPORTA_PCR_bits;            // 0x6C Pin Control Register n
PCR27_bits               : TPORTA_PCR_bits;            // 0x70 Pin Control Register n
PCR28_bits               : TPORTA_PCR_bits;            // 0x74 Pin Control Register n
PCR29_bits               : TPORTA_PCR_bits;            // 0x78 Pin Control Register n
PCR30_bits               : TPORTA_PCR_bits;            // 0x7C Pin Control Register n
PCR31_bits               : TPORTA_PCR_bits;            // 0x80 Pin Control Register n
GPCLR_bits               : TPORTA_GPCLR_bits;          // 0x84 Global Pin Control Low Register
GPCHR_bits               : TPORTA_GPCHR_bits;          // 0x88 Global Pin Control High Register
RESERVED_bits0           : array[0..5] of longWord;
ISFR_bits                : TPORTA_ISFR_bits;           // 0xA4 Interrupt Status Flag Register
RESERVED_bits1           : array[0..6] of longWord;
DFER_bits                : TPORTA_DFER_bits;           // 0xC4 Digital Filter Enable Register
DFCR_bits                : TPORTA_DFCR_bits;           // 0xC8 Digital Filter Clock Register
DFWR_bits                : TPORTA_DFWR_bits;           // 0xCC Digital Filter Width Register
);
end;

TPORTARegisters_bitbanded = record
  PCR0                   : TPORTA_PCR_bitbanded;       // 0x04 Pin Control Register n
  PCR1                   : TPORTA_PCR_bitbanded;       // 0x08 Pin Control Register n
  PCR2                   : TPORTA_PCR_bitbanded;       // 0x0C Pin Control Register n
  PCR3                   : TPORTA_PCR_bitbanded;       // 0x10 Pin Control Register n
  PCR4                   : TPORTA_PCR_bitbanded;       // 0x14 Pin Control Register n
  PCR5                   : TPORTA_PCR_bitbanded;       // 0x18 Pin Control Register n
  PCR6                   : TPORTA_PCR_bitbanded;       // 0x1C Pin Control Register n
  PCR7                   : TPORTA_PCR_bitbanded;       // 0x20 Pin Control Register n
  PCR8                   : TPORTA_PCR_bitbanded;       // 0x24 Pin Control Register n
  PCR9                   : TPORTA_PCR_bitbanded;       // 0x28 Pin Control Register n
  PCR10                  : TPORTA_PCR_bitbanded;       // 0x2C Pin Control Register n
  PCR11                  : TPORTA_PCR_bitbanded;       // 0x30 Pin Control Register n
  PCR12                  : TPORTA_PCR_bitbanded;       // 0x34 Pin Control Register n
  PCR13                  : TPORTA_PCR_bitbanded;       // 0x38 Pin Control Register n
  PCR14                  : TPORTA_PCR_bitbanded;       // 0x3C Pin Control Register n
  PCR15                  : TPORTA_PCR_bitbanded;       // 0x40 Pin Control Register n
  PCR16                  : TPORTA_PCR_bitbanded;       // 0x44 Pin Control Register n
  PCR17                  : TPORTA_PCR_bitbanded;       // 0x48 Pin Control Register n
  PCR18                  : TPORTA_PCR_bitbanded;       // 0x4C Pin Control Register n
  PCR19                  : TPORTA_PCR_bitbanded;       // 0x50 Pin Control Register n
  PCR20                  : TPORTA_PCR_bitbanded;       // 0x54 Pin Control Register n
  PCR21                  : TPORTA_PCR_bitbanded;       // 0x58 Pin Control Register n
  PCR22                  : TPORTA_PCR_bitbanded;       // 0x5C Pin Control Register n
  PCR23                  : TPORTA_PCR_bitbanded;       // 0x60 Pin Control Register n
  PCR24                  : TPORTA_PCR_bitbanded;       // 0x64 Pin Control Register n
  PCR25                  : TPORTA_PCR_bitbanded;       // 0x68 Pin Control Register n
  PCR26                  : TPORTA_PCR_bitbanded;       // 0x6C Pin Control Register n
  PCR27                  : TPORTA_PCR_bitbanded;       // 0x70 Pin Control Register n
  PCR28                  : TPORTA_PCR_bitbanded;       // 0x74 Pin Control Register n
  PCR29                  : TPORTA_PCR_bitbanded;       // 0x78 Pin Control Register n
  PCR30                  : TPORTA_PCR_bitbanded;       // 0x7C Pin Control Register n
  PCR31                  : TPORTA_PCR_bitbanded;       // 0x80 Pin Control Register n
  GPCLR                  : TPORTA_GPCLR_bitbanded;     // 0x84 Global Pin Control Low Register
  GPCHR                  : TPORTA_GPCHR_bitbanded;     // 0x88 Global Pin Control High Register
  RESERVED0              : array[0..23] of array[0..7] of longWord;
  ISFR                   : TPORTA_ISFR_bitbanded;      // 0xA4 Interrupt Status Flag Register
  RESERVED1              : array[0..27] of array[0..7] of longWord;
  DFER                   : TPORTA_DFER_bitbanded;      // 0xC4 Digital Filter Enable Register
  DFCR                   : TPORTA_DFCR_bitbanded;      // 0xC8 Digital Filter Clock Register
  DFWR                   : TPORTA_DFWR_bitbanded;      // 0xCC Digital Filter Width Register
end;

// Pin Control and Interrupts
TPORTB_PCR_bits = bitpacked record
  PS                     : TBits_1;                    // [0:0] Pull Select
  PE                     : TBits_1;                    // [1:1] Pull Enable
  SRE                    : TBits_1;                    // [2:2] Slew Rate Enable
  RESERVED0              : TBits_1;                    // [3:3] no description available
  PFE                    : TBits_1;                    // [4:4] Passive Filter Enable
  ODE                    : TBits_1;                    // [5:5] Open Drain Enable
  DSE                    : TBits_1;                    // [6:6] Drive Strength Enable
  RESERVED1              : TBits_1;                    // [7:7] no description available
  MUX                    : TBits_3;                    // [8:10] Pin Mux Control
  RESERVED2              : TBits_4;                    // [11:14] no description available
  LK                     : TBits_1;                    // [15:15] Lock Register
  IRQC                   : TBits_4;                    // [16:19] Interrupt Configuration
  RESERVED3              : TBits_4;                    // [20:23] no description available
  ISF                    : TBits_1;                    // [24:24] Interrupt Status Flag
  RESERVED4              : TBits_7;                    // [25:31] no description available
end;

TPORTB_PCR_bitbanded = record
  PS                     : longWord;                   // [0:0] Pull Select
  PE                     : longWord;                   // [1:1] Pull Enable
  SRE                    : longWord;                   // [2:2] Slew Rate Enable
  RESERVED0              : longWord;                   // [3:3] no description available
  PFE                    : longWord;                   // [4:4] Passive Filter Enable
  ODE                    : longWord;                   // [5:5] Open Drain Enable
  DSE                    : longWord;                   // [6:6] Drive Strength Enable
  RESERVED1              : longWord;                   // [7:7] no description available
  MUX                    : array[0..2] of longWord;    // [8:10] Pin Mux Control
  RESERVED2              : array[0..3] of longWord;    // [11:14] no description available
  LK                     : longWord;                   // [15:15] Lock Register
  IRQC                   : array[0..3] of longWord;    // [16:19] Interrupt Configuration
  RESERVED3              : array[0..3] of longWord;    // [20:23] no description available
  ISF                    : longWord;                   // [24:24] Interrupt Status Flag
  RESERVED4              : array[0..6] of longWord;    // [25:31] no description available
end;

TPORTB_GPCLR_bits = bitpacked record
  GPWD                   : TBits_16;                   // [0:15] Global Pin Write Data
  GPWE                   : TBits_16;                   // [16:31] Global Pin Write Enable
end;

TPORTB_GPCLR_bitbanded = record
  GPWD                   : array[0..15] of longWord;   // [0:15] Global Pin Write Data
  GPWE                   : array[0..15] of longWord;   // [16:31] Global Pin Write Enable
end;

TPORTB_GPCHR_bits = bitpacked record
  GPWD                   : TBits_16;                   // [0:15] Global Pin Write Data
  GPWE                   : TBits_16;                   // [16:31] Global Pin Write Enable
end;

TPORTB_GPCHR_bitbanded = record
  GPWD                   : array[0..15] of longWord;   // [0:15] Global Pin Write Data
  GPWE                   : array[0..15] of longWord;   // [16:31] Global Pin Write Enable
end;

TPORTB_ISFR_bits = bitpacked record
  ISF                    : TBits_32;                   // [0:31] Interrupt Status Flag
end;

TPORTB_ISFR_bitbanded = record
  ISF                    : array[0..31] of longWord;   // [0:31] Interrupt Status Flag
end;

TPORTB_DFER_bits = bitpacked record
  DFE                    : TBits_32;                   // [0:31] Digital Filter Enable
end;

TPORTB_DFER_bitbanded = record
  DFE                    : array[0..31] of longWord;   // [0:31] Digital Filter Enable
end;

TPORTB_DFCR_bits = bitpacked record
  CS                     : TBits_1;                    // [0:0] Clock Source
  RESERVED0              : TBits_31;                   // [1:31] no description available
end;

TPORTB_DFCR_bitbanded = record
  CS                     : longWord;                   // [0:0] Clock Source
  RESERVED0              : array[0..30] of longWord;   // [1:31] no description available
end;

TPORTB_DFWR_bits = bitpacked record
  FILT                   : TBits_5;                    // [0:4] Filter Length
  RESERVED0              : TBits_27;                   // [5:31] no description available
end;

TPORTB_DFWR_bitbanded = record
  FILT                   : array[0..4] of longWord;    // [0:4] Filter Length
  RESERVED0              : array[0..26] of longWord;   // [5:31] no description available
end;

TPORTB_Registers = record
  case boolean of false: (
  PCR0                   : longWord;                   // 0x00 Pin Control Register n
  PCR1                   : longWord;                   // 0x04 Pin Control Register n
  PCR2                   : longWord;                   // 0x08 Pin Control Register n
  PCR3                   : longWord;                   // 0x0C Pin Control Register n
  PCR4                   : longWord;                   // 0x10 Pin Control Register n
  PCR5                   : longWord;                   // 0x14 Pin Control Register n
  PCR6                   : longWord;                   // 0x18 Pin Control Register n
  PCR7                   : longWord;                   // 0x1C Pin Control Register n
  PCR8                   : longWord;                   // 0x20 Pin Control Register n
  PCR9                   : longWord;                   // 0x24 Pin Control Register n
  PCR10                  : longWord;                   // 0x28 Pin Control Register n
  PCR11                  : longWord;                   // 0x2C Pin Control Register n
  PCR12                  : longWord;                   // 0x30 Pin Control Register n
  PCR13                  : longWord;                   // 0x34 Pin Control Register n
  PCR14                  : longWord;                   // 0x38 Pin Control Register n
  PCR15                  : longWord;                   // 0x3C Pin Control Register n
  PCR16                  : longWord;                   // 0x40 Pin Control Register n
  PCR17                  : longWord;                   // 0x44 Pin Control Register n
  PCR18                  : longWord;                   // 0x48 Pin Control Register n
  PCR19                  : longWord;                   // 0x4C Pin Control Register n
  PCR20                  : longWord;                   // 0x50 Pin Control Register n
  PCR21                  : longWord;                   // 0x54 Pin Control Register n
  PCR22                  : longWord;                   // 0x58 Pin Control Register n
  PCR23                  : longWord;                   // 0x5C Pin Control Register n
  PCR24                  : longWord;                   // 0x60 Pin Control Register n
  PCR25                  : longWord;                   // 0x64 Pin Control Register n
  PCR26                  : longWord;                   // 0x68 Pin Control Register n
  PCR27                  : longWord;                   // 0x6C Pin Control Register n
  PCR28                  : longWord;                   // 0x70 Pin Control Register n
  PCR29                  : longWord;                   // 0x74 Pin Control Register n
  PCR30                  : longWord;                   // 0x78 Pin Control Register n
  PCR31                  : longWord;                   // 0x7C Pin Control Register n
  GPCLR                  : longWord;                   // 0x80 Global Pin Control Low Register
  GPCHR                  : longWord;                   // 0x84 Global Pin Control High Register
  RESERVED0              : array[0..5] of longWord;    // 0x88
  ISFR                   : longWord;                   // 0xA0 Interrupt Status Flag Register
  RESERVED1              : array[0..6] of longWord;    // 0xA4
  DFER                   : longWord;                   // 0xC0 Digital Filter Enable Register
  DFCR                   : longWord;                   // 0xC4 Digital Filter Clock Register
  DFWR                   : longWord;                   // 0xC8 Digital Filter Width Register
);
true : (
PCR0_bits                : TPORTB_PCR_bits;            // 0x04 Pin Control Register n
PCR1_bits                : TPORTB_PCR_bits;            // 0x08 Pin Control Register n
PCR2_bits                : TPORTB_PCR_bits;            // 0x0C Pin Control Register n
PCR3_bits                : TPORTB_PCR_bits;            // 0x10 Pin Control Register n
PCR4_bits                : TPORTB_PCR_bits;            // 0x14 Pin Control Register n
PCR5_bits                : TPORTB_PCR_bits;            // 0x18 Pin Control Register n
PCR6_bits                : TPORTB_PCR_bits;            // 0x1C Pin Control Register n
PCR7_bits                : TPORTB_PCR_bits;            // 0x20 Pin Control Register n
PCR8_bits                : TPORTB_PCR_bits;            // 0x24 Pin Control Register n
PCR9_bits                : TPORTB_PCR_bits;            // 0x28 Pin Control Register n
PCR10_bits               : TPORTB_PCR_bits;            // 0x2C Pin Control Register n
PCR11_bits               : TPORTB_PCR_bits;            // 0x30 Pin Control Register n
PCR12_bits               : TPORTB_PCR_bits;            // 0x34 Pin Control Register n
PCR13_bits               : TPORTB_PCR_bits;            // 0x38 Pin Control Register n
PCR14_bits               : TPORTB_PCR_bits;            // 0x3C Pin Control Register n
PCR15_bits               : TPORTB_PCR_bits;            // 0x40 Pin Control Register n
PCR16_bits               : TPORTB_PCR_bits;            // 0x44 Pin Control Register n
PCR17_bits               : TPORTB_PCR_bits;            // 0x48 Pin Control Register n
PCR18_bits               : TPORTB_PCR_bits;            // 0x4C Pin Control Register n
PCR19_bits               : TPORTB_PCR_bits;            // 0x50 Pin Control Register n
PCR20_bits               : TPORTB_PCR_bits;            // 0x54 Pin Control Register n
PCR21_bits               : TPORTB_PCR_bits;            // 0x58 Pin Control Register n
PCR22_bits               : TPORTB_PCR_bits;            // 0x5C Pin Control Register n
PCR23_bits               : TPORTB_PCR_bits;            // 0x60 Pin Control Register n
PCR24_bits               : TPORTB_PCR_bits;            // 0x64 Pin Control Register n
PCR25_bits               : TPORTB_PCR_bits;            // 0x68 Pin Control Register n
PCR26_bits               : TPORTB_PCR_bits;            // 0x6C Pin Control Register n
PCR27_bits               : TPORTB_PCR_bits;            // 0x70 Pin Control Register n
PCR28_bits               : TPORTB_PCR_bits;            // 0x74 Pin Control Register n
PCR29_bits               : TPORTB_PCR_bits;            // 0x78 Pin Control Register n
PCR30_bits               : TPORTB_PCR_bits;            // 0x7C Pin Control Register n
PCR31_bits               : TPORTB_PCR_bits;            // 0x80 Pin Control Register n
GPCLR_bits               : TPORTB_GPCLR_bits;          // 0x84 Global Pin Control Low Register
GPCHR_bits               : TPORTB_GPCHR_bits;          // 0x88 Global Pin Control High Register
RESERVED_bits0           : array[0..5] of longWord;
ISFR_bits                : TPORTB_ISFR_bits;           // 0xA4 Interrupt Status Flag Register
RESERVED_bits1           : array[0..6] of longWord;
DFER_bits                : TPORTB_DFER_bits;           // 0xC4 Digital Filter Enable Register
DFCR_bits                : TPORTB_DFCR_bits;           // 0xC8 Digital Filter Clock Register
DFWR_bits                : TPORTB_DFWR_bits;           // 0xCC Digital Filter Width Register
);
end;

TPORTBRegisters_bitbanded = record
  PCR0                   : TPORTB_PCR_bitbanded;       // 0x04 Pin Control Register n
  PCR1                   : TPORTB_PCR_bitbanded;       // 0x08 Pin Control Register n
  PCR2                   : TPORTB_PCR_bitbanded;       // 0x0C Pin Control Register n
  PCR3                   : TPORTB_PCR_bitbanded;       // 0x10 Pin Control Register n
  PCR4                   : TPORTB_PCR_bitbanded;       // 0x14 Pin Control Register n
  PCR5                   : TPORTB_PCR_bitbanded;       // 0x18 Pin Control Register n
  PCR6                   : TPORTB_PCR_bitbanded;       // 0x1C Pin Control Register n
  PCR7                   : TPORTB_PCR_bitbanded;       // 0x20 Pin Control Register n
  PCR8                   : TPORTB_PCR_bitbanded;       // 0x24 Pin Control Register n
  PCR9                   : TPORTB_PCR_bitbanded;       // 0x28 Pin Control Register n
  PCR10                  : TPORTB_PCR_bitbanded;       // 0x2C Pin Control Register n
  PCR11                  : TPORTB_PCR_bitbanded;       // 0x30 Pin Control Register n
  PCR12                  : TPORTB_PCR_bitbanded;       // 0x34 Pin Control Register n
  PCR13                  : TPORTB_PCR_bitbanded;       // 0x38 Pin Control Register n
  PCR14                  : TPORTB_PCR_bitbanded;       // 0x3C Pin Control Register n
  PCR15                  : TPORTB_PCR_bitbanded;       // 0x40 Pin Control Register n
  PCR16                  : TPORTB_PCR_bitbanded;       // 0x44 Pin Control Register n
  PCR17                  : TPORTB_PCR_bitbanded;       // 0x48 Pin Control Register n
  PCR18                  : TPORTB_PCR_bitbanded;       // 0x4C Pin Control Register n
  PCR19                  : TPORTB_PCR_bitbanded;       // 0x50 Pin Control Register n
  PCR20                  : TPORTB_PCR_bitbanded;       // 0x54 Pin Control Register n
  PCR21                  : TPORTB_PCR_bitbanded;       // 0x58 Pin Control Register n
  PCR22                  : TPORTB_PCR_bitbanded;       // 0x5C Pin Control Register n
  PCR23                  : TPORTB_PCR_bitbanded;       // 0x60 Pin Control Register n
  PCR24                  : TPORTB_PCR_bitbanded;       // 0x64 Pin Control Register n
  PCR25                  : TPORTB_PCR_bitbanded;       // 0x68 Pin Control Register n
  PCR26                  : TPORTB_PCR_bitbanded;       // 0x6C Pin Control Register n
  PCR27                  : TPORTB_PCR_bitbanded;       // 0x70 Pin Control Register n
  PCR28                  : TPORTB_PCR_bitbanded;       // 0x74 Pin Control Register n
  PCR29                  : TPORTB_PCR_bitbanded;       // 0x78 Pin Control Register n
  PCR30                  : TPORTB_PCR_bitbanded;       // 0x7C Pin Control Register n
  PCR31                  : TPORTB_PCR_bitbanded;       // 0x80 Pin Control Register n
  GPCLR                  : TPORTB_GPCLR_bitbanded;     // 0x84 Global Pin Control Low Register
  GPCHR                  : TPORTB_GPCHR_bitbanded;     // 0x88 Global Pin Control High Register
  RESERVED0              : array[0..23] of array[0..7] of longWord;
  ISFR                   : TPORTB_ISFR_bitbanded;      // 0xA4 Interrupt Status Flag Register
  RESERVED1              : array[0..27] of array[0..7] of longWord;
  DFER                   : TPORTB_DFER_bitbanded;      // 0xC4 Digital Filter Enable Register
  DFCR                   : TPORTB_DFCR_bitbanded;      // 0xC8 Digital Filter Clock Register
  DFWR                   : TPORTB_DFWR_bitbanded;      // 0xCC Digital Filter Width Register
end;

// Pin Control and Interrupts
TPORTC_PCR_bits = bitpacked record
  PS                     : TBits_1;                    // [0:0] Pull Select
  PE                     : TBits_1;                    // [1:1] Pull Enable
  SRE                    : TBits_1;                    // [2:2] Slew Rate Enable
  RESERVED0              : TBits_1;                    // [3:3] no description available
  PFE                    : TBits_1;                    // [4:4] Passive Filter Enable
  ODE                    : TBits_1;                    // [5:5] Open Drain Enable
  DSE                    : TBits_1;                    // [6:6] Drive Strength Enable
  RESERVED1              : TBits_1;                    // [7:7] no description available
  MUX                    : TBits_3;                    // [8:10] Pin Mux Control
  RESERVED2              : TBits_4;                    // [11:14] no description available
  LK                     : TBits_1;                    // [15:15] Lock Register
  IRQC                   : TBits_4;                    // [16:19] Interrupt Configuration
  RESERVED3              : TBits_4;                    // [20:23] no description available
  ISF                    : TBits_1;                    // [24:24] Interrupt Status Flag
  RESERVED4              : TBits_7;                    // [25:31] no description available
end;

TPORTC_PCR_bitbanded = record
  PS                     : longWord;                   // [0:0] Pull Select
  PE                     : longWord;                   // [1:1] Pull Enable
  SRE                    : longWord;                   // [2:2] Slew Rate Enable
  RESERVED0              : longWord;                   // [3:3] no description available
  PFE                    : longWord;                   // [4:4] Passive Filter Enable
  ODE                    : longWord;                   // [5:5] Open Drain Enable
  DSE                    : longWord;                   // [6:6] Drive Strength Enable
  RESERVED1              : longWord;                   // [7:7] no description available
  MUX                    : array[0..2] of longWord;    // [8:10] Pin Mux Control
  RESERVED2              : array[0..3] of longWord;    // [11:14] no description available
  LK                     : longWord;                   // [15:15] Lock Register
  IRQC                   : array[0..3] of longWord;    // [16:19] Interrupt Configuration
  RESERVED3              : array[0..3] of longWord;    // [20:23] no description available
  ISF                    : longWord;                   // [24:24] Interrupt Status Flag
  RESERVED4              : array[0..6] of longWord;    // [25:31] no description available
end;

TPORTC_GPCLR_bits = bitpacked record
  GPWD                   : TBits_16;                   // [0:15] Global Pin Write Data
  GPWE                   : TBits_16;                   // [16:31] Global Pin Write Enable
end;

TPORTC_GPCLR_bitbanded = record
  GPWD                   : array[0..15] of longWord;   // [0:15] Global Pin Write Data
  GPWE                   : array[0..15] of longWord;   // [16:31] Global Pin Write Enable
end;

TPORTC_GPCHR_bits = bitpacked record
  GPWD                   : TBits_16;                   // [0:15] Global Pin Write Data
  GPWE                   : TBits_16;                   // [16:31] Global Pin Write Enable
end;

TPORTC_GPCHR_bitbanded = record
  GPWD                   : array[0..15] of longWord;   // [0:15] Global Pin Write Data
  GPWE                   : array[0..15] of longWord;   // [16:31] Global Pin Write Enable
end;

TPORTC_ISFR_bits = bitpacked record
  ISF                    : TBits_32;                   // [0:31] Interrupt Status Flag
end;

TPORTC_ISFR_bitbanded = record
  ISF                    : array[0..31] of longWord;   // [0:31] Interrupt Status Flag
end;

TPORTC_DFER_bits = bitpacked record
  DFE                    : TBits_32;                   // [0:31] Digital Filter Enable
end;

TPORTC_DFER_bitbanded = record
  DFE                    : array[0..31] of longWord;   // [0:31] Digital Filter Enable
end;

TPORTC_DFCR_bits = bitpacked record
  CS                     : TBits_1;                    // [0:0] Clock Source
  RESERVED0              : TBits_31;                   // [1:31] no description available
end;

TPORTC_DFCR_bitbanded = record
  CS                     : longWord;                   // [0:0] Clock Source
  RESERVED0              : array[0..30] of longWord;   // [1:31] no description available
end;

TPORTC_DFWR_bits = bitpacked record
  FILT                   : TBits_5;                    // [0:4] Filter Length
  RESERVED0              : TBits_27;                   // [5:31] no description available
end;

TPORTC_DFWR_bitbanded = record
  FILT                   : array[0..4] of longWord;    // [0:4] Filter Length
  RESERVED0              : array[0..26] of longWord;   // [5:31] no description available
end;

TPORTC_Registers = record
  case boolean of false: (
  PCR0                   : longWord;                   // 0x00 Pin Control Register n
  PCR1                   : longWord;                   // 0x04 Pin Control Register n
  PCR2                   : longWord;                   // 0x08 Pin Control Register n
  PCR3                   : longWord;                   // 0x0C Pin Control Register n
  PCR4                   : longWord;                   // 0x10 Pin Control Register n
  PCR5                   : longWord;                   // 0x14 Pin Control Register n
  PCR6                   : longWord;                   // 0x18 Pin Control Register n
  PCR7                   : longWord;                   // 0x1C Pin Control Register n
  PCR8                   : longWord;                   // 0x20 Pin Control Register n
  PCR9                   : longWord;                   // 0x24 Pin Control Register n
  PCR10                  : longWord;                   // 0x28 Pin Control Register n
  PCR11                  : longWord;                   // 0x2C Pin Control Register n
  PCR12                  : longWord;                   // 0x30 Pin Control Register n
  PCR13                  : longWord;                   // 0x34 Pin Control Register n
  PCR14                  : longWord;                   // 0x38 Pin Control Register n
  PCR15                  : longWord;                   // 0x3C Pin Control Register n
  PCR16                  : longWord;                   // 0x40 Pin Control Register n
  PCR17                  : longWord;                   // 0x44 Pin Control Register n
  PCR18                  : longWord;                   // 0x48 Pin Control Register n
  PCR19                  : longWord;                   // 0x4C Pin Control Register n
  PCR20                  : longWord;                   // 0x50 Pin Control Register n
  PCR21                  : longWord;                   // 0x54 Pin Control Register n
  PCR22                  : longWord;                   // 0x58 Pin Control Register n
  PCR23                  : longWord;                   // 0x5C Pin Control Register n
  PCR24                  : longWord;                   // 0x60 Pin Control Register n
  PCR25                  : longWord;                   // 0x64 Pin Control Register n
  PCR26                  : longWord;                   // 0x68 Pin Control Register n
  PCR27                  : longWord;                   // 0x6C Pin Control Register n
  PCR28                  : longWord;                   // 0x70 Pin Control Register n
  PCR29                  : longWord;                   // 0x74 Pin Control Register n
  PCR30                  : longWord;                   // 0x78 Pin Control Register n
  PCR31                  : longWord;                   // 0x7C Pin Control Register n
  GPCLR                  : longWord;                   // 0x80 Global Pin Control Low Register
  GPCHR                  : longWord;                   // 0x84 Global Pin Control High Register
  RESERVED0              : array[0..5] of longWord;    // 0x88
  ISFR                   : longWord;                   // 0xA0 Interrupt Status Flag Register
  RESERVED1              : array[0..6] of longWord;    // 0xA4
  DFER                   : longWord;                   // 0xC0 Digital Filter Enable Register
  DFCR                   : longWord;                   // 0xC4 Digital Filter Clock Register
  DFWR                   : longWord;                   // 0xC8 Digital Filter Width Register
);
true : (
PCR0_bits                : TPORTC_PCR_bits;            // 0x04 Pin Control Register n
PCR1_bits                : TPORTC_PCR_bits;            // 0x08 Pin Control Register n
PCR2_bits                : TPORTC_PCR_bits;            // 0x0C Pin Control Register n
PCR3_bits                : TPORTC_PCR_bits;            // 0x10 Pin Control Register n
PCR4_bits                : TPORTC_PCR_bits;            // 0x14 Pin Control Register n
PCR5_bits                : TPORTC_PCR_bits;            // 0x18 Pin Control Register n
PCR6_bits                : TPORTC_PCR_bits;            // 0x1C Pin Control Register n
PCR7_bits                : TPORTC_PCR_bits;            // 0x20 Pin Control Register n
PCR8_bits                : TPORTC_PCR_bits;            // 0x24 Pin Control Register n
PCR9_bits                : TPORTC_PCR_bits;            // 0x28 Pin Control Register n
PCR10_bits               : TPORTC_PCR_bits;            // 0x2C Pin Control Register n
PCR11_bits               : TPORTC_PCR_bits;            // 0x30 Pin Control Register n
PCR12_bits               : TPORTC_PCR_bits;            // 0x34 Pin Control Register n
PCR13_bits               : TPORTC_PCR_bits;            // 0x38 Pin Control Register n
PCR14_bits               : TPORTC_PCR_bits;            // 0x3C Pin Control Register n
PCR15_bits               : TPORTC_PCR_bits;            // 0x40 Pin Control Register n
PCR16_bits               : TPORTC_PCR_bits;            // 0x44 Pin Control Register n
PCR17_bits               : TPORTC_PCR_bits;            // 0x48 Pin Control Register n
PCR18_bits               : TPORTC_PCR_bits;            // 0x4C Pin Control Register n
PCR19_bits               : TPORTC_PCR_bits;            // 0x50 Pin Control Register n
PCR20_bits               : TPORTC_PCR_bits;            // 0x54 Pin Control Register n
PCR21_bits               : TPORTC_PCR_bits;            // 0x58 Pin Control Register n
PCR22_bits               : TPORTC_PCR_bits;            // 0x5C Pin Control Register n
PCR23_bits               : TPORTC_PCR_bits;            // 0x60 Pin Control Register n
PCR24_bits               : TPORTC_PCR_bits;            // 0x64 Pin Control Register n
PCR25_bits               : TPORTC_PCR_bits;            // 0x68 Pin Control Register n
PCR26_bits               : TPORTC_PCR_bits;            // 0x6C Pin Control Register n
PCR27_bits               : TPORTC_PCR_bits;            // 0x70 Pin Control Register n
PCR28_bits               : TPORTC_PCR_bits;            // 0x74 Pin Control Register n
PCR29_bits               : TPORTC_PCR_bits;            // 0x78 Pin Control Register n
PCR30_bits               : TPORTC_PCR_bits;            // 0x7C Pin Control Register n
PCR31_bits               : TPORTC_PCR_bits;            // 0x80 Pin Control Register n
GPCLR_bits               : TPORTC_GPCLR_bits;          // 0x84 Global Pin Control Low Register
GPCHR_bits               : TPORTC_GPCHR_bits;          // 0x88 Global Pin Control High Register
RESERVED_bits0           : array[0..5] of longWord;
ISFR_bits                : TPORTC_ISFR_bits;           // 0xA4 Interrupt Status Flag Register
RESERVED_bits1           : array[0..6] of longWord;
DFER_bits                : TPORTC_DFER_bits;           // 0xC4 Digital Filter Enable Register
DFCR_bits                : TPORTC_DFCR_bits;           // 0xC8 Digital Filter Clock Register
DFWR_bits                : TPORTC_DFWR_bits;           // 0xCC Digital Filter Width Register
);
end;

TPORTCRegisters_bitbanded = record
  PCR0                   : TPORTC_PCR_bitbanded;       // 0x04 Pin Control Register n
  PCR1                   : TPORTC_PCR_bitbanded;       // 0x08 Pin Control Register n
  PCR2                   : TPORTC_PCR_bitbanded;       // 0x0C Pin Control Register n
  PCR3                   : TPORTC_PCR_bitbanded;       // 0x10 Pin Control Register n
  PCR4                   : TPORTC_PCR_bitbanded;       // 0x14 Pin Control Register n
  PCR5                   : TPORTC_PCR_bitbanded;       // 0x18 Pin Control Register n
  PCR6                   : TPORTC_PCR_bitbanded;       // 0x1C Pin Control Register n
  PCR7                   : TPORTC_PCR_bitbanded;       // 0x20 Pin Control Register n
  PCR8                   : TPORTC_PCR_bitbanded;       // 0x24 Pin Control Register n
  PCR9                   : TPORTC_PCR_bitbanded;       // 0x28 Pin Control Register n
  PCR10                  : TPORTC_PCR_bitbanded;       // 0x2C Pin Control Register n
  PCR11                  : TPORTC_PCR_bitbanded;       // 0x30 Pin Control Register n
  PCR12                  : TPORTC_PCR_bitbanded;       // 0x34 Pin Control Register n
  PCR13                  : TPORTC_PCR_bitbanded;       // 0x38 Pin Control Register n
  PCR14                  : TPORTC_PCR_bitbanded;       // 0x3C Pin Control Register n
  PCR15                  : TPORTC_PCR_bitbanded;       // 0x40 Pin Control Register n
  PCR16                  : TPORTC_PCR_bitbanded;       // 0x44 Pin Control Register n
  PCR17                  : TPORTC_PCR_bitbanded;       // 0x48 Pin Control Register n
  PCR18                  : TPORTC_PCR_bitbanded;       // 0x4C Pin Control Register n
  PCR19                  : TPORTC_PCR_bitbanded;       // 0x50 Pin Control Register n
  PCR20                  : TPORTC_PCR_bitbanded;       // 0x54 Pin Control Register n
  PCR21                  : TPORTC_PCR_bitbanded;       // 0x58 Pin Control Register n
  PCR22                  : TPORTC_PCR_bitbanded;       // 0x5C Pin Control Register n
  PCR23                  : TPORTC_PCR_bitbanded;       // 0x60 Pin Control Register n
  PCR24                  : TPORTC_PCR_bitbanded;       // 0x64 Pin Control Register n
  PCR25                  : TPORTC_PCR_bitbanded;       // 0x68 Pin Control Register n
  PCR26                  : TPORTC_PCR_bitbanded;       // 0x6C Pin Control Register n
  PCR27                  : TPORTC_PCR_bitbanded;       // 0x70 Pin Control Register n
  PCR28                  : TPORTC_PCR_bitbanded;       // 0x74 Pin Control Register n
  PCR29                  : TPORTC_PCR_bitbanded;       // 0x78 Pin Control Register n
  PCR30                  : TPORTC_PCR_bitbanded;       // 0x7C Pin Control Register n
  PCR31                  : TPORTC_PCR_bitbanded;       // 0x80 Pin Control Register n
  GPCLR                  : TPORTC_GPCLR_bitbanded;     // 0x84 Global Pin Control Low Register
  GPCHR                  : TPORTC_GPCHR_bitbanded;     // 0x88 Global Pin Control High Register
  RESERVED0              : array[0..23] of array[0..7] of longWord;
  ISFR                   : TPORTC_ISFR_bitbanded;      // 0xA4 Interrupt Status Flag Register
  RESERVED1              : array[0..27] of array[0..7] of longWord;
  DFER                   : TPORTC_DFER_bitbanded;      // 0xC4 Digital Filter Enable Register
  DFCR                   : TPORTC_DFCR_bitbanded;      // 0xC8 Digital Filter Clock Register
  DFWR                   : TPORTC_DFWR_bitbanded;      // 0xCC Digital Filter Width Register
end;

// Pin Control and Interrupts
TPORTD_PCR_bits = bitpacked record
  PS                     : TBits_1;                    // [0:0] Pull Select
  PE                     : TBits_1;                    // [1:1] Pull Enable
  SRE                    : TBits_1;                    // [2:2] Slew Rate Enable
  RESERVED0              : TBits_1;                    // [3:3] no description available
  PFE                    : TBits_1;                    // [4:4] Passive Filter Enable
  ODE                    : TBits_1;                    // [5:5] Open Drain Enable
  DSE                    : TBits_1;                    // [6:6] Drive Strength Enable
  RESERVED1              : TBits_1;                    // [7:7] no description available
  MUX                    : TBits_3;                    // [8:10] Pin Mux Control
  RESERVED2              : TBits_4;                    // [11:14] no description available
  LK                     : TBits_1;                    // [15:15] Lock Register
  IRQC                   : TBits_4;                    // [16:19] Interrupt Configuration
  RESERVED3              : TBits_4;                    // [20:23] no description available
  ISF                    : TBits_1;                    // [24:24] Interrupt Status Flag
  RESERVED4              : TBits_7;                    // [25:31] no description available
end;

TPORTD_PCR_bitbanded = record
  PS                     : longWord;                   // [0:0] Pull Select
  PE                     : longWord;                   // [1:1] Pull Enable
  SRE                    : longWord;                   // [2:2] Slew Rate Enable
  RESERVED0              : longWord;                   // [3:3] no description available
  PFE                    : longWord;                   // [4:4] Passive Filter Enable
  ODE                    : longWord;                   // [5:5] Open Drain Enable
  DSE                    : longWord;                   // [6:6] Drive Strength Enable
  RESERVED1              : longWord;                   // [7:7] no description available
  MUX                    : array[0..2] of longWord;    // [8:10] Pin Mux Control
  RESERVED2              : array[0..3] of longWord;    // [11:14] no description available
  LK                     : longWord;                   // [15:15] Lock Register
  IRQC                   : array[0..3] of longWord;    // [16:19] Interrupt Configuration
  RESERVED3              : array[0..3] of longWord;    // [20:23] no description available
  ISF                    : longWord;                   // [24:24] Interrupt Status Flag
  RESERVED4              : array[0..6] of longWord;    // [25:31] no description available
end;

TPORTD_GPCLR_bits = bitpacked record
  GPWD                   : TBits_16;                   // [0:15] Global Pin Write Data
  GPWE                   : TBits_16;                   // [16:31] Global Pin Write Enable
end;

TPORTD_GPCLR_bitbanded = record
  GPWD                   : array[0..15] of longWord;   // [0:15] Global Pin Write Data
  GPWE                   : array[0..15] of longWord;   // [16:31] Global Pin Write Enable
end;

TPORTD_GPCHR_bits = bitpacked record
  GPWD                   : TBits_16;                   // [0:15] Global Pin Write Data
  GPWE                   : TBits_16;                   // [16:31] Global Pin Write Enable
end;

TPORTD_GPCHR_bitbanded = record
  GPWD                   : array[0..15] of longWord;   // [0:15] Global Pin Write Data
  GPWE                   : array[0..15] of longWord;   // [16:31] Global Pin Write Enable
end;

TPORTD_ISFR_bits = bitpacked record
  ISF                    : TBits_32;                   // [0:31] Interrupt Status Flag
end;

TPORTD_ISFR_bitbanded = record
  ISF                    : array[0..31] of longWord;   // [0:31] Interrupt Status Flag
end;

TPORTD_DFER_bits = bitpacked record
  DFE                    : TBits_32;                   // [0:31] Digital Filter Enable
end;

TPORTD_DFER_bitbanded = record
  DFE                    : array[0..31] of longWord;   // [0:31] Digital Filter Enable
end;

TPORTD_DFCR_bits = bitpacked record
  CS                     : TBits_1;                    // [0:0] Clock Source
  RESERVED0              : TBits_31;                   // [1:31] no description available
end;

TPORTD_DFCR_bitbanded = record
  CS                     : longWord;                   // [0:0] Clock Source
  RESERVED0              : array[0..30] of longWord;   // [1:31] no description available
end;

TPORTD_DFWR_bits = bitpacked record
  FILT                   : TBits_5;                    // [0:4] Filter Length
  RESERVED0              : TBits_27;                   // [5:31] no description available
end;

TPORTD_DFWR_bitbanded = record
  FILT                   : array[0..4] of longWord;    // [0:4] Filter Length
  RESERVED0              : array[0..26] of longWord;   // [5:31] no description available
end;

TPORTD_Registers = record
  case boolean of false: (
  PCR0                   : longWord;                   // 0x00 Pin Control Register n
  PCR1                   : longWord;                   // 0x04 Pin Control Register n
  PCR2                   : longWord;                   // 0x08 Pin Control Register n
  PCR3                   : longWord;                   // 0x0C Pin Control Register n
  PCR4                   : longWord;                   // 0x10 Pin Control Register n
  PCR5                   : longWord;                   // 0x14 Pin Control Register n
  PCR6                   : longWord;                   // 0x18 Pin Control Register n
  PCR7                   : longWord;                   // 0x1C Pin Control Register n
  PCR8                   : longWord;                   // 0x20 Pin Control Register n
  PCR9                   : longWord;                   // 0x24 Pin Control Register n
  PCR10                  : longWord;                   // 0x28 Pin Control Register n
  PCR11                  : longWord;                   // 0x2C Pin Control Register n
  PCR12                  : longWord;                   // 0x30 Pin Control Register n
  PCR13                  : longWord;                   // 0x34 Pin Control Register n
  PCR14                  : longWord;                   // 0x38 Pin Control Register n
  PCR15                  : longWord;                   // 0x3C Pin Control Register n
  PCR16                  : longWord;                   // 0x40 Pin Control Register n
  PCR17                  : longWord;                   // 0x44 Pin Control Register n
  PCR18                  : longWord;                   // 0x48 Pin Control Register n
  PCR19                  : longWord;                   // 0x4C Pin Control Register n
  PCR20                  : longWord;                   // 0x50 Pin Control Register n
  PCR21                  : longWord;                   // 0x54 Pin Control Register n
  PCR22                  : longWord;                   // 0x58 Pin Control Register n
  PCR23                  : longWord;                   // 0x5C Pin Control Register n
  PCR24                  : longWord;                   // 0x60 Pin Control Register n
  PCR25                  : longWord;                   // 0x64 Pin Control Register n
  PCR26                  : longWord;                   // 0x68 Pin Control Register n
  PCR27                  : longWord;                   // 0x6C Pin Control Register n
  PCR28                  : longWord;                   // 0x70 Pin Control Register n
  PCR29                  : longWord;                   // 0x74 Pin Control Register n
  PCR30                  : longWord;                   // 0x78 Pin Control Register n
  PCR31                  : longWord;                   // 0x7C Pin Control Register n
  GPCLR                  : longWord;                   // 0x80 Global Pin Control Low Register
  GPCHR                  : longWord;                   // 0x84 Global Pin Control High Register
  RESERVED0              : array[0..5] of longWord;    // 0x88
  ISFR                   : longWord;                   // 0xA0 Interrupt Status Flag Register
  RESERVED1              : array[0..6] of longWord;    // 0xA4
  DFER                   : longWord;                   // 0xC0 Digital Filter Enable Register
  DFCR                   : longWord;                   // 0xC4 Digital Filter Clock Register
  DFWR                   : longWord;                   // 0xC8 Digital Filter Width Register
);
true : (
PCR0_bits                : TPORTD_PCR_bits;            // 0x04 Pin Control Register n
PCR1_bits                : TPORTD_PCR_bits;            // 0x08 Pin Control Register n
PCR2_bits                : TPORTD_PCR_bits;            // 0x0C Pin Control Register n
PCR3_bits                : TPORTD_PCR_bits;            // 0x10 Pin Control Register n
PCR4_bits                : TPORTD_PCR_bits;            // 0x14 Pin Control Register n
PCR5_bits                : TPORTD_PCR_bits;            // 0x18 Pin Control Register n
PCR6_bits                : TPORTD_PCR_bits;            // 0x1C Pin Control Register n
PCR7_bits                : TPORTD_PCR_bits;            // 0x20 Pin Control Register n
PCR8_bits                : TPORTD_PCR_bits;            // 0x24 Pin Control Register n
PCR9_bits                : TPORTD_PCR_bits;            // 0x28 Pin Control Register n
PCR10_bits               : TPORTD_PCR_bits;            // 0x2C Pin Control Register n
PCR11_bits               : TPORTD_PCR_bits;            // 0x30 Pin Control Register n
PCR12_bits               : TPORTD_PCR_bits;            // 0x34 Pin Control Register n
PCR13_bits               : TPORTD_PCR_bits;            // 0x38 Pin Control Register n
PCR14_bits               : TPORTD_PCR_bits;            // 0x3C Pin Control Register n
PCR15_bits               : TPORTD_PCR_bits;            // 0x40 Pin Control Register n
PCR16_bits               : TPORTD_PCR_bits;            // 0x44 Pin Control Register n
PCR17_bits               : TPORTD_PCR_bits;            // 0x48 Pin Control Register n
PCR18_bits               : TPORTD_PCR_bits;            // 0x4C Pin Control Register n
PCR19_bits               : TPORTD_PCR_bits;            // 0x50 Pin Control Register n
PCR20_bits               : TPORTD_PCR_bits;            // 0x54 Pin Control Register n
PCR21_bits               : TPORTD_PCR_bits;            // 0x58 Pin Control Register n
PCR22_bits               : TPORTD_PCR_bits;            // 0x5C Pin Control Register n
PCR23_bits               : TPORTD_PCR_bits;            // 0x60 Pin Control Register n
PCR24_bits               : TPORTD_PCR_bits;            // 0x64 Pin Control Register n
PCR25_bits               : TPORTD_PCR_bits;            // 0x68 Pin Control Register n
PCR26_bits               : TPORTD_PCR_bits;            // 0x6C Pin Control Register n
PCR27_bits               : TPORTD_PCR_bits;            // 0x70 Pin Control Register n
PCR28_bits               : TPORTD_PCR_bits;            // 0x74 Pin Control Register n
PCR29_bits               : TPORTD_PCR_bits;            // 0x78 Pin Control Register n
PCR30_bits               : TPORTD_PCR_bits;            // 0x7C Pin Control Register n
PCR31_bits               : TPORTD_PCR_bits;            // 0x80 Pin Control Register n
GPCLR_bits               : TPORTD_GPCLR_bits;          // 0x84 Global Pin Control Low Register
GPCHR_bits               : TPORTD_GPCHR_bits;          // 0x88 Global Pin Control High Register
RESERVED_bits0           : array[0..5] of longWord;
ISFR_bits                : TPORTD_ISFR_bits;           // 0xA4 Interrupt Status Flag Register
RESERVED_bits1           : array[0..6] of longWord;
DFER_bits                : TPORTD_DFER_bits;           // 0xC4 Digital Filter Enable Register
DFCR_bits                : TPORTD_DFCR_bits;           // 0xC8 Digital Filter Clock Register
DFWR_bits                : TPORTD_DFWR_bits;           // 0xCC Digital Filter Width Register
);
end;

TPORTDRegisters_bitbanded = record
  PCR0                   : TPORTD_PCR_bitbanded;       // 0x04 Pin Control Register n
  PCR1                   : TPORTD_PCR_bitbanded;       // 0x08 Pin Control Register n
  PCR2                   : TPORTD_PCR_bitbanded;       // 0x0C Pin Control Register n
  PCR3                   : TPORTD_PCR_bitbanded;       // 0x10 Pin Control Register n
  PCR4                   : TPORTD_PCR_bitbanded;       // 0x14 Pin Control Register n
  PCR5                   : TPORTD_PCR_bitbanded;       // 0x18 Pin Control Register n
  PCR6                   : TPORTD_PCR_bitbanded;       // 0x1C Pin Control Register n
  PCR7                   : TPORTD_PCR_bitbanded;       // 0x20 Pin Control Register n
  PCR8                   : TPORTD_PCR_bitbanded;       // 0x24 Pin Control Register n
  PCR9                   : TPORTD_PCR_bitbanded;       // 0x28 Pin Control Register n
  PCR10                  : TPORTD_PCR_bitbanded;       // 0x2C Pin Control Register n
  PCR11                  : TPORTD_PCR_bitbanded;       // 0x30 Pin Control Register n
  PCR12                  : TPORTD_PCR_bitbanded;       // 0x34 Pin Control Register n
  PCR13                  : TPORTD_PCR_bitbanded;       // 0x38 Pin Control Register n
  PCR14                  : TPORTD_PCR_bitbanded;       // 0x3C Pin Control Register n
  PCR15                  : TPORTD_PCR_bitbanded;       // 0x40 Pin Control Register n
  PCR16                  : TPORTD_PCR_bitbanded;       // 0x44 Pin Control Register n
  PCR17                  : TPORTD_PCR_bitbanded;       // 0x48 Pin Control Register n
  PCR18                  : TPORTD_PCR_bitbanded;       // 0x4C Pin Control Register n
  PCR19                  : TPORTD_PCR_bitbanded;       // 0x50 Pin Control Register n
  PCR20                  : TPORTD_PCR_bitbanded;       // 0x54 Pin Control Register n
  PCR21                  : TPORTD_PCR_bitbanded;       // 0x58 Pin Control Register n
  PCR22                  : TPORTD_PCR_bitbanded;       // 0x5C Pin Control Register n
  PCR23                  : TPORTD_PCR_bitbanded;       // 0x60 Pin Control Register n
  PCR24                  : TPORTD_PCR_bitbanded;       // 0x64 Pin Control Register n
  PCR25                  : TPORTD_PCR_bitbanded;       // 0x68 Pin Control Register n
  PCR26                  : TPORTD_PCR_bitbanded;       // 0x6C Pin Control Register n
  PCR27                  : TPORTD_PCR_bitbanded;       // 0x70 Pin Control Register n
  PCR28                  : TPORTD_PCR_bitbanded;       // 0x74 Pin Control Register n
  PCR29                  : TPORTD_PCR_bitbanded;       // 0x78 Pin Control Register n
  PCR30                  : TPORTD_PCR_bitbanded;       // 0x7C Pin Control Register n
  PCR31                  : TPORTD_PCR_bitbanded;       // 0x80 Pin Control Register n
  GPCLR                  : TPORTD_GPCLR_bitbanded;     // 0x84 Global Pin Control Low Register
  GPCHR                  : TPORTD_GPCHR_bitbanded;     // 0x88 Global Pin Control High Register
  RESERVED0              : array[0..23] of array[0..7] of longWord;
  ISFR                   : TPORTD_ISFR_bitbanded;      // 0xA4 Interrupt Status Flag Register
  RESERVED1              : array[0..27] of array[0..7] of longWord;
  DFER                   : TPORTD_DFER_bitbanded;      // 0xC4 Digital Filter Enable Register
  DFCR                   : TPORTD_DFCR_bitbanded;      // 0xC8 Digital Filter Clock Register
  DFWR                   : TPORTD_DFWR_bitbanded;      // 0xCC Digital Filter Width Register
end;

// Pin Control and Interrupts
TPORTE_PCR_bits = bitpacked record
  PS                     : TBits_1;                    // [0:0] Pull Select
  PE                     : TBits_1;                    // [1:1] Pull Enable
  SRE                    : TBits_1;                    // [2:2] Slew Rate Enable
  RESERVED0              : TBits_1;                    // [3:3] no description available
  PFE                    : TBits_1;                    // [4:4] Passive Filter Enable
  ODE                    : TBits_1;                    // [5:5] Open Drain Enable
  DSE                    : TBits_1;                    // [6:6] Drive Strength Enable
  RESERVED1              : TBits_1;                    // [7:7] no description available
  MUX                    : TBits_3;                    // [8:10] Pin Mux Control
  RESERVED2              : TBits_4;                    // [11:14] no description available
  LK                     : TBits_1;                    // [15:15] Lock Register
  IRQC                   : TBits_4;                    // [16:19] Interrupt Configuration
  RESERVED3              : TBits_4;                    // [20:23] no description available
  ISF                    : TBits_1;                    // [24:24] Interrupt Status Flag
  RESERVED4              : TBits_7;                    // [25:31] no description available
end;

TPORTE_PCR_bitbanded = record
  PS                     : longWord;                   // [0:0] Pull Select
  PE                     : longWord;                   // [1:1] Pull Enable
  SRE                    : longWord;                   // [2:2] Slew Rate Enable
  RESERVED0              : longWord;                   // [3:3] no description available
  PFE                    : longWord;                   // [4:4] Passive Filter Enable
  ODE                    : longWord;                   // [5:5] Open Drain Enable
  DSE                    : longWord;                   // [6:6] Drive Strength Enable
  RESERVED1              : longWord;                   // [7:7] no description available
  MUX                    : array[0..2] of longWord;    // [8:10] Pin Mux Control
  RESERVED2              : array[0..3] of longWord;    // [11:14] no description available
  LK                     : longWord;                   // [15:15] Lock Register
  IRQC                   : array[0..3] of longWord;    // [16:19] Interrupt Configuration
  RESERVED3              : array[0..3] of longWord;    // [20:23] no description available
  ISF                    : longWord;                   // [24:24] Interrupt Status Flag
  RESERVED4              : array[0..6] of longWord;    // [25:31] no description available
end;

TPORTE_GPCLR_bits = bitpacked record
  GPWD                   : TBits_16;                   // [0:15] Global Pin Write Data
  GPWE                   : TBits_16;                   // [16:31] Global Pin Write Enable
end;

TPORTE_GPCLR_bitbanded = record
  GPWD                   : array[0..15] of longWord;   // [0:15] Global Pin Write Data
  GPWE                   : array[0..15] of longWord;   // [16:31] Global Pin Write Enable
end;

TPORTE_GPCHR_bits = bitpacked record
  GPWD                   : TBits_16;                   // [0:15] Global Pin Write Data
  GPWE                   : TBits_16;                   // [16:31] Global Pin Write Enable
end;

TPORTE_GPCHR_bitbanded = record
  GPWD                   : array[0..15] of longWord;   // [0:15] Global Pin Write Data
  GPWE                   : array[0..15] of longWord;   // [16:31] Global Pin Write Enable
end;

TPORTE_ISFR_bits = bitpacked record
  ISF                    : TBits_32;                   // [0:31] Interrupt Status Flag
end;

TPORTE_ISFR_bitbanded = record
  ISF                    : array[0..31] of longWord;   // [0:31] Interrupt Status Flag
end;

TPORTE_DFER_bits = bitpacked record
  DFE                    : TBits_32;                   // [0:31] Digital Filter Enable
end;

TPORTE_DFER_bitbanded = record
  DFE                    : array[0..31] of longWord;   // [0:31] Digital Filter Enable
end;

TPORTE_DFCR_bits = bitpacked record
  CS                     : TBits_1;                    // [0:0] Clock Source
  RESERVED0              : TBits_31;                   // [1:31] no description available
end;

TPORTE_DFCR_bitbanded = record
  CS                     : longWord;                   // [0:0] Clock Source
  RESERVED0              : array[0..30] of longWord;   // [1:31] no description available
end;

TPORTE_DFWR_bits = bitpacked record
  FILT                   : TBits_5;                    // [0:4] Filter Length
  RESERVED0              : TBits_27;                   // [5:31] no description available
end;

TPORTE_DFWR_bitbanded = record
  FILT                   : array[0..4] of longWord;    // [0:4] Filter Length
  RESERVED0              : array[0..26] of longWord;   // [5:31] no description available
end;

TPORTE_Registers = record
  case boolean of false: (
  PCR0                   : longWord;                   // 0x00 Pin Control Register n
  PCR1                   : longWord;                   // 0x04 Pin Control Register n
  PCR2                   : longWord;                   // 0x08 Pin Control Register n
  PCR3                   : longWord;                   // 0x0C Pin Control Register n
  PCR4                   : longWord;                   // 0x10 Pin Control Register n
  PCR5                   : longWord;                   // 0x14 Pin Control Register n
  PCR6                   : longWord;                   // 0x18 Pin Control Register n
  PCR7                   : longWord;                   // 0x1C Pin Control Register n
  PCR8                   : longWord;                   // 0x20 Pin Control Register n
  PCR9                   : longWord;                   // 0x24 Pin Control Register n
  PCR10                  : longWord;                   // 0x28 Pin Control Register n
  PCR11                  : longWord;                   // 0x2C Pin Control Register n
  PCR12                  : longWord;                   // 0x30 Pin Control Register n
  PCR13                  : longWord;                   // 0x34 Pin Control Register n
  PCR14                  : longWord;                   // 0x38 Pin Control Register n
  PCR15                  : longWord;                   // 0x3C Pin Control Register n
  PCR16                  : longWord;                   // 0x40 Pin Control Register n
  PCR17                  : longWord;                   // 0x44 Pin Control Register n
  PCR18                  : longWord;                   // 0x48 Pin Control Register n
  PCR19                  : longWord;                   // 0x4C Pin Control Register n
  PCR20                  : longWord;                   // 0x50 Pin Control Register n
  PCR21                  : longWord;                   // 0x54 Pin Control Register n
  PCR22                  : longWord;                   // 0x58 Pin Control Register n
  PCR23                  : longWord;                   // 0x5C Pin Control Register n
  PCR24                  : longWord;                   // 0x60 Pin Control Register n
  PCR25                  : longWord;                   // 0x64 Pin Control Register n
  PCR26                  : longWord;                   // 0x68 Pin Control Register n
  PCR27                  : longWord;                   // 0x6C Pin Control Register n
  PCR28                  : longWord;                   // 0x70 Pin Control Register n
  PCR29                  : longWord;                   // 0x74 Pin Control Register n
  PCR30                  : longWord;                   // 0x78 Pin Control Register n
  PCR31                  : longWord;                   // 0x7C Pin Control Register n
  GPCLR                  : longWord;                   // 0x80 Global Pin Control Low Register
  GPCHR                  : longWord;                   // 0x84 Global Pin Control High Register
  RESERVED0              : array[0..5] of longWord;    // 0x88
  ISFR                   : longWord;                   // 0xA0 Interrupt Status Flag Register
  RESERVED1              : array[0..6] of longWord;    // 0xA4
  DFER                   : longWord;                   // 0xC0 Digital Filter Enable Register
  DFCR                   : longWord;                   // 0xC4 Digital Filter Clock Register
  DFWR                   : longWord;                   // 0xC8 Digital Filter Width Register
);
true : (
PCR0_bits                : TPORTE_PCR_bits;            // 0x04 Pin Control Register n
PCR1_bits                : TPORTE_PCR_bits;            // 0x08 Pin Control Register n
PCR2_bits                : TPORTE_PCR_bits;            // 0x0C Pin Control Register n
PCR3_bits                : TPORTE_PCR_bits;            // 0x10 Pin Control Register n
PCR4_bits                : TPORTE_PCR_bits;            // 0x14 Pin Control Register n
PCR5_bits                : TPORTE_PCR_bits;            // 0x18 Pin Control Register n
PCR6_bits                : TPORTE_PCR_bits;            // 0x1C Pin Control Register n
PCR7_bits                : TPORTE_PCR_bits;            // 0x20 Pin Control Register n
PCR8_bits                : TPORTE_PCR_bits;            // 0x24 Pin Control Register n
PCR9_bits                : TPORTE_PCR_bits;            // 0x28 Pin Control Register n
PCR10_bits               : TPORTE_PCR_bits;            // 0x2C Pin Control Register n
PCR11_bits               : TPORTE_PCR_bits;            // 0x30 Pin Control Register n
PCR12_bits               : TPORTE_PCR_bits;            // 0x34 Pin Control Register n
PCR13_bits               : TPORTE_PCR_bits;            // 0x38 Pin Control Register n
PCR14_bits               : TPORTE_PCR_bits;            // 0x3C Pin Control Register n
PCR15_bits               : TPORTE_PCR_bits;            // 0x40 Pin Control Register n
PCR16_bits               : TPORTE_PCR_bits;            // 0x44 Pin Control Register n
PCR17_bits               : TPORTE_PCR_bits;            // 0x48 Pin Control Register n
PCR18_bits               : TPORTE_PCR_bits;            // 0x4C Pin Control Register n
PCR19_bits               : TPORTE_PCR_bits;            // 0x50 Pin Control Register n
PCR20_bits               : TPORTE_PCR_bits;            // 0x54 Pin Control Register n
PCR21_bits               : TPORTE_PCR_bits;            // 0x58 Pin Control Register n
PCR22_bits               : TPORTE_PCR_bits;            // 0x5C Pin Control Register n
PCR23_bits               : TPORTE_PCR_bits;            // 0x60 Pin Control Register n
PCR24_bits               : TPORTE_PCR_bits;            // 0x64 Pin Control Register n
PCR25_bits               : TPORTE_PCR_bits;            // 0x68 Pin Control Register n
PCR26_bits               : TPORTE_PCR_bits;            // 0x6C Pin Control Register n
PCR27_bits               : TPORTE_PCR_bits;            // 0x70 Pin Control Register n
PCR28_bits               : TPORTE_PCR_bits;            // 0x74 Pin Control Register n
PCR29_bits               : TPORTE_PCR_bits;            // 0x78 Pin Control Register n
PCR30_bits               : TPORTE_PCR_bits;            // 0x7C Pin Control Register n
PCR31_bits               : TPORTE_PCR_bits;            // 0x80 Pin Control Register n
GPCLR_bits               : TPORTE_GPCLR_bits;          // 0x84 Global Pin Control Low Register
GPCHR_bits               : TPORTE_GPCHR_bits;          // 0x88 Global Pin Control High Register
RESERVED_bits0           : array[0..5] of longWord;
ISFR_bits                : TPORTE_ISFR_bits;           // 0xA4 Interrupt Status Flag Register
RESERVED_bits1           : array[0..6] of longWord;
DFER_bits                : TPORTE_DFER_bits;           // 0xC4 Digital Filter Enable Register
DFCR_bits                : TPORTE_DFCR_bits;           // 0xC8 Digital Filter Clock Register
DFWR_bits                : TPORTE_DFWR_bits;           // 0xCC Digital Filter Width Register
);
end;

TPORTERegisters_bitbanded = record
  PCR0                   : TPORTE_PCR_bitbanded;       // 0x04 Pin Control Register n
  PCR1                   : TPORTE_PCR_bitbanded;       // 0x08 Pin Control Register n
  PCR2                   : TPORTE_PCR_bitbanded;       // 0x0C Pin Control Register n
  PCR3                   : TPORTE_PCR_bitbanded;       // 0x10 Pin Control Register n
  PCR4                   : TPORTE_PCR_bitbanded;       // 0x14 Pin Control Register n
  PCR5                   : TPORTE_PCR_bitbanded;       // 0x18 Pin Control Register n
  PCR6                   : TPORTE_PCR_bitbanded;       // 0x1C Pin Control Register n
  PCR7                   : TPORTE_PCR_bitbanded;       // 0x20 Pin Control Register n
  PCR8                   : TPORTE_PCR_bitbanded;       // 0x24 Pin Control Register n
  PCR9                   : TPORTE_PCR_bitbanded;       // 0x28 Pin Control Register n
  PCR10                  : TPORTE_PCR_bitbanded;       // 0x2C Pin Control Register n
  PCR11                  : TPORTE_PCR_bitbanded;       // 0x30 Pin Control Register n
  PCR12                  : TPORTE_PCR_bitbanded;       // 0x34 Pin Control Register n
  PCR13                  : TPORTE_PCR_bitbanded;       // 0x38 Pin Control Register n
  PCR14                  : TPORTE_PCR_bitbanded;       // 0x3C Pin Control Register n
  PCR15                  : TPORTE_PCR_bitbanded;       // 0x40 Pin Control Register n
  PCR16                  : TPORTE_PCR_bitbanded;       // 0x44 Pin Control Register n
  PCR17                  : TPORTE_PCR_bitbanded;       // 0x48 Pin Control Register n
  PCR18                  : TPORTE_PCR_bitbanded;       // 0x4C Pin Control Register n
  PCR19                  : TPORTE_PCR_bitbanded;       // 0x50 Pin Control Register n
  PCR20                  : TPORTE_PCR_bitbanded;       // 0x54 Pin Control Register n
  PCR21                  : TPORTE_PCR_bitbanded;       // 0x58 Pin Control Register n
  PCR22                  : TPORTE_PCR_bitbanded;       // 0x5C Pin Control Register n
  PCR23                  : TPORTE_PCR_bitbanded;       // 0x60 Pin Control Register n
  PCR24                  : TPORTE_PCR_bitbanded;       // 0x64 Pin Control Register n
  PCR25                  : TPORTE_PCR_bitbanded;       // 0x68 Pin Control Register n
  PCR26                  : TPORTE_PCR_bitbanded;       // 0x6C Pin Control Register n
  PCR27                  : TPORTE_PCR_bitbanded;       // 0x70 Pin Control Register n
  PCR28                  : TPORTE_PCR_bitbanded;       // 0x74 Pin Control Register n
  PCR29                  : TPORTE_PCR_bitbanded;       // 0x78 Pin Control Register n
  PCR30                  : TPORTE_PCR_bitbanded;       // 0x7C Pin Control Register n
  PCR31                  : TPORTE_PCR_bitbanded;       // 0x80 Pin Control Register n
  GPCLR                  : TPORTE_GPCLR_bitbanded;     // 0x84 Global Pin Control Low Register
  GPCHR                  : TPORTE_GPCHR_bitbanded;     // 0x88 Global Pin Control High Register
  RESERVED0              : array[0..23] of array[0..7] of longWord;
  ISFR                   : TPORTE_ISFR_bitbanded;      // 0xA4 Interrupt Status Flag Register
  RESERVED1              : array[0..27] of array[0..7] of longWord;
  DFER                   : TPORTE_DFER_bitbanded;      // 0xC4 Digital Filter Enable Register
  DFCR                   : TPORTE_DFCR_bitbanded;      // 0xC8 Digital Filter Clock Register
  DFWR                   : TPORTE_DFWR_bitbanded;      // 0xCC Digital Filter Width Register
end;

// Reset Control Module
TRCM_SRS0_bits = bitpacked record
  WAKEUP                 : TBits_1;                    // [0:0] Low leakage wakeup reset
  LVD                    : TBits_1;                    // [1:1] Low-voltage detect reset
  LOC                    : TBits_1;                    // [2:2] Loss-of-clock reset
  LOL                    : TBits_1;                    // [3:3] Loss-of-lock reset
  RESERVED0              : TBits_1;                    // [4:4] no description available
  WDOG                   : TBits_1;                    // [5:5] Watchdog
  PIN                    : TBits_1;                    // [6:6] External reset pin
  POR                    : TBits_1;                    // [7:7] Power-on reset
end;

TRCM_SRS0_bitbanded = record
  WAKEUP                 : longWord;                   // [0:0] Low leakage wakeup reset
  LVD                    : longWord;                   // [1:1] Low-voltage detect reset
  LOC                    : longWord;                   // [2:2] Loss-of-clock reset
  LOL                    : longWord;                   // [3:3] Loss-of-lock reset
  RESERVED0              : longWord;                   // [4:4] no description available
  WDOG                   : longWord;                   // [5:5] Watchdog
  PIN                    : longWord;                   // [6:6] External reset pin
  POR                    : longWord;                   // [7:7] Power-on reset
end;

TRCM_SRS1_bits = bitpacked record
  JTAG                   : TBits_1;                    // [0:0] JTAG generated reset
  LOCKUP                 : TBits_1;                    // [1:1] Core Lockup
  SW                     : TBits_1;                    // [2:2] Software
  MDM_AP                 : TBits_1;                    // [3:3] MDM-AP system reset request
  EZPT                   : TBits_1;                    // [4:4] EzPort Reset
  SACKERR                : TBits_1;                    // [5:5] Stop Mode Acknowledge Error Reset
  RESERVED0              : TBits_1;                    // [6:6] no description available
  RESERVED1              : TBits_1;                    // [7:7] no description available
end;

TRCM_SRS1_bitbanded = record
  JTAG                   : longWord;                   // [0:0] JTAG generated reset
  LOCKUP                 : longWord;                   // [1:1] Core Lockup
  SW                     : longWord;                   // [2:2] Software
  MDM_AP                 : longWord;                   // [3:3] MDM-AP system reset request
  EZPT                   : longWord;                   // [4:4] EzPort Reset
  SACKERR                : longWord;                   // [5:5] Stop Mode Acknowledge Error Reset
  RESERVED0              : longWord;                   // [6:6] no description available
  RESERVED1              : longWord;                   // [7:7] no description available
end;

TRCM_RPFC_bits = bitpacked record
  RSTFLTSRW              : TBits_2;                    // [0:1] Reset pin filter select in run and wait modes
  RSTFLTSS               : TBits_1;                    // [2:2] Reset pin filter select in stop mode
  RESERVED0              : TBits_5;                    // [3:7] no description available
end;

TRCM_RPFC_bitbanded = record
  RSTFLTSRW              : array[0..1] of longWord;    // [0:1] Reset pin filter select in run and wait modes
  RSTFLTSS               : longWord;                   // [2:2] Reset pin filter select in stop mode
  RESERVED0              : array[0..4] of longWord;    // [3:7] no description available
end;

TRCM_RPFW_bits = bitpacked record
  RSTFLTSEL              : TBits_5;                    // [0:4] Reset pin filter bus clock select
  RESERVED0              : TBits_3;                    // [5:7] no description available
end;

TRCM_RPFW_bitbanded = record
  RSTFLTSEL              : array[0..4] of longWord;    // [0:4] Reset pin filter bus clock select
  RESERVED0              : array[0..2] of longWord;    // [5:7] no description available
end;

TRCM_MR_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] no description available
  EZP_MS                 : TBits_1;                    // [1:1] EZP_MS_B pin state
  RESERVED1              : TBits_6;                    // [2:7] no description available
end;

TRCM_MR_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] no description available
  EZP_MS                 : longWord;                   // [1:1] EZP_MS_B pin state
  RESERVED1              : array[0..5] of longWord;    // [2:7] no description available
end;

TRCM_Registers = record
  case boolean of false: (
  SRS0                   : byte;                       // 0x00 System Reset Status Register 0
  SRS1                   : byte;                       // 0x01 System Reset Status Register 1
  RESERVED0              : word;                       // 0x02
  RPFC                   : byte;                       // 0x04 Reset Pin Filter Control Register
  RPFW                   : byte;                       // 0x05 Reset Pin Filter Width Register
  RESERVED1              : byte;                       // 0x06
  MR                     : byte;                       // 0x07 Mode Register
);
true : (
SRS0_bits                : TRCM_SRS0_bits;             // 0x01 System Reset Status Register 0
SRS1_bits                : TRCM_SRS1_bits;             // 0x02 System Reset Status Register 1
RESERVED_bits0           : word;
RPFC_bits                : TRCM_RPFC_bits;             // 0x05 Reset Pin Filter Control Register
RPFW_bits                : TRCM_RPFW_bits;             // 0x06 Reset Pin Filter Width Register
RESERVED_bits1           : byte;
MR_bits                  : TRCM_MR_bits;               // 0x08 Mode Register
);
end;

TRCMRegisters_bitbanded = record
  SRS0                   : TRCM_SRS0_bitbanded;        // 0x01 System Reset Status Register 0
  SRS1                   : TRCM_SRS1_bitbanded;        // 0x02 System Reset Status Register 1
  RESERVED0              : array[0..1] of array[0..7] of longWord;
  RPFC                   : TRCM_RPFC_bitbanded;        // 0x05 Reset Pin Filter Control Register
  RPFW                   : TRCM_RPFW_bitbanded;        // 0x06 Reset Pin Filter Width Register
  RESERVED1              : array[0..7] of longWord;
  MR                     : TRCM_MR_bitbanded;          // 0x08 Mode Register
end;

// System register file
TRFSYS_REG_bits = bitpacked record
  LL                     : TBits_8;                    // [0:7] no description available
  LH                     : TBits_8;                    // [8:15] no description available
  HL                     : TBits_8;                    // [16:23] no description available
  HH                     : TBits_8;                    // [24:31] no description available
end;

TRFSYS_REG_bitbanded = record
  LL                     : array[0..7] of longWord;    // [0:7] no description available
  LH                     : array[0..7] of longWord;    // [8:15] no description available
  HL                     : array[0..7] of longWord;    // [16:23] no description available
  HH                     : array[0..7] of longWord;    // [24:31] no description available
end;

TRFSYS_Registers = record
  case boolean of false: (
  REG0                   : longWord;                   // 0x00 Register file register
  REG1                   : longWord;                   // 0x04 Register file register
  REG2                   : longWord;                   // 0x08 Register file register
  REG3                   : longWord;                   // 0x0C Register file register
  REG4                   : longWord;                   // 0x10 Register file register
  REG5                   : longWord;                   // 0x14 Register file register
  REG6                   : longWord;                   // 0x18 Register file register
  REG7                   : longWord;                   // 0x1C Register file register
);
true : (
REG0_bits                : TRFSYS_REG_bits;            // 0x04 Register file register
REG1_bits                : TRFSYS_REG_bits;            // 0x08 Register file register
REG2_bits                : TRFSYS_REG_bits;            // 0x0C Register file register
REG3_bits                : TRFSYS_REG_bits;            // 0x10 Register file register
REG4_bits                : TRFSYS_REG_bits;            // 0x14 Register file register
REG5_bits                : TRFSYS_REG_bits;            // 0x18 Register file register
REG6_bits                : TRFSYS_REG_bits;            // 0x1C Register file register
REG7_bits                : TRFSYS_REG_bits;            // 0x20 Register file register
);
end;

TRFSYSRegisters_bitbanded = record
  REG0                   : TRFSYS_REG_bitbanded;       // 0x04 Register file register
  REG1                   : TRFSYS_REG_bitbanded;       // 0x08 Register file register
  REG2                   : TRFSYS_REG_bitbanded;       // 0x0C Register file register
  REG3                   : TRFSYS_REG_bitbanded;       // 0x10 Register file register
  REG4                   : TRFSYS_REG_bitbanded;       // 0x14 Register file register
  REG5                   : TRFSYS_REG_bitbanded;       // 0x18 Register file register
  REG6                   : TRFSYS_REG_bitbanded;       // 0x1C Register file register
  REG7                   : TRFSYS_REG_bitbanded;       // 0x20 Register file register
end;

// VBAT register file
TRFVBAT_REG_bits = bitpacked record
  LL                     : TBits_8;                    // [0:7] no description available
  LH                     : TBits_8;                    // [8:15] no description available
  HL                     : TBits_8;                    // [16:23] no description available
  HH                     : TBits_8;                    // [24:31] no description available
end;

TRFVBAT_REG_bitbanded = record
  LL                     : array[0..7] of longWord;    // [0:7] no description available
  LH                     : array[0..7] of longWord;    // [8:15] no description available
  HL                     : array[0..7] of longWord;    // [16:23] no description available
  HH                     : array[0..7] of longWord;    // [24:31] no description available
end;

TRFVBAT_Registers = record
  case boolean of false: (
  REG0                   : longWord;                   // 0x00 VBAT register file register
  REG1                   : longWord;                   // 0x04 VBAT register file register
  REG2                   : longWord;                   // 0x08 VBAT register file register
  REG3                   : longWord;                   // 0x0C VBAT register file register
  REG4                   : longWord;                   // 0x10 VBAT register file register
  REG5                   : longWord;                   // 0x14 VBAT register file register
  REG6                   : longWord;                   // 0x18 VBAT register file register
  REG7                   : longWord;                   // 0x1C VBAT register file register
);
true : (
REG0_bits                : TRFVBAT_REG_bits;           // 0x04 VBAT register file register
REG1_bits                : TRFVBAT_REG_bits;           // 0x08 VBAT register file register
REG2_bits                : TRFVBAT_REG_bits;           // 0x0C VBAT register file register
REG3_bits                : TRFVBAT_REG_bits;           // 0x10 VBAT register file register
REG4_bits                : TRFVBAT_REG_bits;           // 0x14 VBAT register file register
REG5_bits                : TRFVBAT_REG_bits;           // 0x18 VBAT register file register
REG6_bits                : TRFVBAT_REG_bits;           // 0x1C VBAT register file register
REG7_bits                : TRFVBAT_REG_bits;           // 0x20 VBAT register file register
);
end;

TRFVBATRegisters_bitbanded = record
  REG0                   : TRFVBAT_REG_bitbanded;      // 0x04 VBAT register file register
  REG1                   : TRFVBAT_REG_bitbanded;      // 0x08 VBAT register file register
  REG2                   : TRFVBAT_REG_bitbanded;      // 0x0C VBAT register file register
  REG3                   : TRFVBAT_REG_bitbanded;      // 0x10 VBAT register file register
  REG4                   : TRFVBAT_REG_bitbanded;      // 0x14 VBAT register file register
  REG5                   : TRFVBAT_REG_bitbanded;      // 0x18 VBAT register file register
  REG6                   : TRFVBAT_REG_bitbanded;      // 0x1C VBAT register file register
  REG7                   : TRFVBAT_REG_bitbanded;      // 0x20 VBAT register file register
end;

// Secure Real Time Clock
TRTC_TSR_bits = bitpacked record
  TSR                    : TBits_32;                   // [0:31] Time Seconds Register
end;

TRTC_TSR_bitbanded = record
  TSR                    : array[0..31] of longWord;   // [0:31] Time Seconds Register
end;

TRTC_TPR_bits = bitpacked record
  TPR                    : TBits_16;                   // [0:15] Time Prescaler Register
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TRTC_TPR_bitbanded = record
  TPR                    : array[0..15] of longWord;   // [0:15] Time Prescaler Register
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TRTC_TAR_bits = bitpacked record
  TAR                    : TBits_32;                   // [0:31] Time Alarm Register
end;

TRTC_TAR_bitbanded = record
  TAR                    : array[0..31] of longWord;   // [0:31] Time Alarm Register
end;

TRTC_TCR_bits = bitpacked record
  TCR                    : TBits_8;                    // [0:7] Time Compensation Register
  CIR                    : TBits_8;                    // [8:15] Compensation Interval Register
  TCV                    : TBits_8;                    // [16:23] Time Compensation Value
  CIC                    : TBits_8;                    // [24:31] Compensation Interval Counter
end;

TRTC_TCR_bitbanded = record
  TCR                    : array[0..7] of longWord;    // [0:7] Time Compensation Register
  CIR                    : array[0..7] of longWord;    // [8:15] Compensation Interval Register
  TCV                    : array[0..7] of longWord;    // [16:23] Time Compensation Value
  CIC                    : array[0..7] of longWord;    // [24:31] Compensation Interval Counter
end;

TRTC_CR_bits = bitpacked record
  SWR                    : TBits_1;                    // [0:0] Software Reset
  WPE                    : TBits_1;                    // [1:1] Wakeup Pin Enable
  SUP                    : TBits_1;                    // [2:2] Supervisor Access
  UM                     : TBits_1;                    // [3:3] Update Mode
  RESERVED0              : TBits_4;                    // [4:7] no description available
  OSCE                   : TBits_1;                    // [8:8] Oscillator Enable
  CLKO                   : TBits_1;                    // [9:9] Clock Output
  SC16P                  : TBits_1;                    // [10:10] Oscillator 16pF load configure
  SC8P                   : TBits_1;                    // [11:11] Oscillator 8pF load configure
  SC4P                   : TBits_1;                    // [12:12] Oscillator 4pF load configure
  SC2P                   : TBits_1;                    // [13:13] Oscillator 2pF load configure
  RESERVED1              : TBits_1;                    // [14:14] no description available
  RESERVED2              : TBits_17;                   // [15:31] no description available
end;

TRTC_CR_bitbanded = record
  SWR                    : longWord;                   // [0:0] Software Reset
  WPE                    : longWord;                   // [1:1] Wakeup Pin Enable
  SUP                    : longWord;                   // [2:2] Supervisor Access
  UM                     : longWord;                   // [3:3] Update Mode
  RESERVED0              : array[0..3] of longWord;    // [4:7] no description available
  OSCE                   : longWord;                   // [8:8] Oscillator Enable
  CLKO                   : longWord;                   // [9:9] Clock Output
  SC16P                  : longWord;                   // [10:10] Oscillator 16pF load configure
  SC8P                   : longWord;                   // [11:11] Oscillator 8pF load configure
  SC4P                   : longWord;                   // [12:12] Oscillator 4pF load configure
  SC2P                   : longWord;                   // [13:13] Oscillator 2pF load configure
  RESERVED1              : longWord;                   // [14:14] no description available
  RESERVED2              : array[0..16] of longWord;   // [15:31] no description available
end;

TRTC_SR_bits = bitpacked record
  TIF                    : TBits_1;                    // [0:0] Time Invalid Flag
  TOF                    : TBits_1;                    // [1:1] Time Overflow Flag
  TAF                    : TBits_1;                    // [2:2] Time Alarm Flag
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TCE                    : TBits_1;                    // [4:4] Time Counter Enable
  RESERVED1              : TBits_27;                   // [5:31] no description available
end;

TRTC_SR_bitbanded = record
  TIF                    : longWord;                   // [0:0] Time Invalid Flag
  TOF                    : longWord;                   // [1:1] Time Overflow Flag
  TAF                    : longWord;                   // [2:2] Time Alarm Flag
  RESERVED0              : longWord;                   // [3:3] no description available
  TCE                    : longWord;                   // [4:4] Time Counter Enable
  RESERVED1              : array[0..26] of longWord;   // [5:31] no description available
end;

TRTC_LR_bits = bitpacked record
  RESERVED0              : TBits_3;                    // [0:2] no description available
  TCL                    : TBits_1;                    // [3:3] Time Compensation Lock
  CRL                    : TBits_1;                    // [4:4] Control Register Lock
  SRL                    : TBits_1;                    // [5:5] Status Register Lock
  LRL                    : TBits_1;                    // [6:6] Lock Register Lock
  RESERVED1              : TBits_1;                    // [7:7] no description available
  RESERVED2              : TBits_24;                   // [8:31] no description available
end;

TRTC_LR_bitbanded = record
  RESERVED0              : array[0..2] of longWord;    // [0:2] no description available
  TCL                    : longWord;                   // [3:3] Time Compensation Lock
  CRL                    : longWord;                   // [4:4] Control Register Lock
  SRL                    : longWord;                   // [5:5] Status Register Lock
  LRL                    : longWord;                   // [6:6] Lock Register Lock
  RESERVED1              : longWord;                   // [7:7] no description available
  RESERVED2              : array[0..23] of longWord;   // [8:31] no description available
end;

TRTC_IER_bits = bitpacked record
  TIIE                   : TBits_1;                    // [0:0] Time Invalid Interrupt Enable
  TOIE                   : TBits_1;                    // [1:1] Time Overflow Interrupt Enable
  TAIE                   : TBits_1;                    // [2:2] Time Alarm Interrupt Enable
  RESERVED0              : TBits_1;                    // [3:3] no description available
  TSIE                   : TBits_1;                    // [4:4] Time Seconds Interrupt Enable
  RESERVED1              : TBits_3;                    // [5:7] no description available
  RESERVED2              : TBits_24;                   // [8:31] no description available
end;

TRTC_IER_bitbanded = record
  TIIE                   : longWord;                   // [0:0] Time Invalid Interrupt Enable
  TOIE                   : longWord;                   // [1:1] Time Overflow Interrupt Enable
  TAIE                   : longWord;                   // [2:2] Time Alarm Interrupt Enable
  RESERVED0              : longWord;                   // [3:3] no description available
  TSIE                   : longWord;                   // [4:4] Time Seconds Interrupt Enable
  RESERVED1              : array[0..2] of longWord;    // [5:7] no description available
  RESERVED2              : array[0..23] of longWord;   // [8:31] no description available
end;

TRTC_WAR_bits = bitpacked record
  TSRW                   : TBits_1;                    // [0:0] Time Seconds Register Write
  TPRW                   : TBits_1;                    // [1:1] Time Prescaler Register Write
  TARW                   : TBits_1;                    // [2:2] Time Alarm Register Write
  TCRW                   : TBits_1;                    // [3:3] Time Compensation Register Write
  CRW                    : TBits_1;                    // [4:4] Control Register Write
  SRW                    : TBits_1;                    // [5:5] Status Register Write
  LRW                    : TBits_1;                    // [6:6] Lock Register Write
  IERW                   : TBits_1;                    // [7:7] Interrupt Enable Register Write
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TRTC_WAR_bitbanded = record
  TSRW                   : longWord;                   // [0:0] Time Seconds Register Write
  TPRW                   : longWord;                   // [1:1] Time Prescaler Register Write
  TARW                   : longWord;                   // [2:2] Time Alarm Register Write
  TCRW                   : longWord;                   // [3:3] Time Compensation Register Write
  CRW                    : longWord;                   // [4:4] Control Register Write
  SRW                    : longWord;                   // [5:5] Status Register Write
  LRW                    : longWord;                   // [6:6] Lock Register Write
  IERW                   : longWord;                   // [7:7] Interrupt Enable Register Write
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TRTC_RAR_bits = bitpacked record
  TSRR                   : TBits_1;                    // [0:0] Time Seconds Register Read
  TPRR                   : TBits_1;                    // [1:1] Time Prescaler Register Read
  TARR                   : TBits_1;                    // [2:2] Time Alarm Register Read
  TCRR                   : TBits_1;                    // [3:3] Time Compensation Register Read
  CRR                    : TBits_1;                    // [4:4] Control Register Read
  SRR                    : TBits_1;                    // [5:5] Status Register Read
  LRR                    : TBits_1;                    // [6:6] Lock Register Read
  IERR                   : TBits_1;                    // [7:7] Interrupt Enable Register Read
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TRTC_RAR_bitbanded = record
  TSRR                   : longWord;                   // [0:0] Time Seconds Register Read
  TPRR                   : longWord;                   // [1:1] Time Prescaler Register Read
  TARR                   : longWord;                   // [2:2] Time Alarm Register Read
  TCRR                   : longWord;                   // [3:3] Time Compensation Register Read
  CRR                    : longWord;                   // [4:4] Control Register Read
  SRR                    : longWord;                   // [5:5] Status Register Read
  LRR                    : longWord;                   // [6:6] Lock Register Read
  IERR                   : longWord;                   // [7:7] Interrupt Enable Register Read
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TRTC_Registers = record
  case boolean of false: (
  TSR                    : longWord;                   // 0x00 RTC Time Seconds Register
  TPR                    : longWord;                   // 0x04 RTC Time Prescaler Register
  TAR                    : longWord;                   // 0x08 RTC Time Alarm Register
  TCR                    : longWord;                   // 0x0C RTC Time Compensation Register
  CR                     : longWord;                   // 0x10 RTC Control Register
  SR                     : longWord;                   // 0x14 RTC Status Register
  LR                     : longWord;                   // 0x18 RTC Lock Register
  IER                    : longWord;                   // 0x1C RTC Interrupt Enable Register
  RESERVED0              : array[0..503] of longWord;  // 0x20
  WAR                    : longWord;                   // 0x800 RTC Write Access Register
  RAR                    : longWord;                   // 0x804 RTC Read Access Register
);
true : (
TSR_bits                 : TRTC_TSR_bits;              // 0x04 RTC Time Seconds Register
TPR_bits                 : TRTC_TPR_bits;              // 0x08 RTC Time Prescaler Register
TAR_bits                 : TRTC_TAR_bits;              // 0x0C RTC Time Alarm Register
TCR_bits                 : TRTC_TCR_bits;              // 0x10 RTC Time Compensation Register
CR_bits                  : TRTC_CR_bits;               // 0x14 RTC Control Register
SR_bits                  : TRTC_SR_bits;               // 0x18 RTC Status Register
LR_bits                  : TRTC_LR_bits;               // 0x1C RTC Lock Register
IER_bits                 : TRTC_IER_bits;              // 0x20 RTC Interrupt Enable Register
RESERVED_bits0           : array[0..503] of longWord;
WAR_bits                 : TRTC_WAR_bits;              // 0x804 RTC Write Access Register
RAR_bits                 : TRTC_RAR_bits;              // 0x808 RTC Read Access Register
);
end;

TRTCRegisters_bitbanded = record
  TSR                    : TRTC_TSR_bitbanded;         // 0x04 RTC Time Seconds Register
  TPR                    : TRTC_TPR_bitbanded;         // 0x08 RTC Time Prescaler Register
  TAR                    : TRTC_TAR_bitbanded;         // 0x0C RTC Time Alarm Register
  TCR                    : TRTC_TCR_bitbanded;         // 0x10 RTC Time Compensation Register
  CR                     : TRTC_CR_bitbanded;          // 0x14 RTC Control Register
  SR                     : TRTC_SR_bitbanded;          // 0x18 RTC Status Register
  LR                     : TRTC_LR_bitbanded;          // 0x1C RTC Lock Register
  IER                    : TRTC_IER_bitbanded;         // 0x20 RTC Interrupt Enable Register
  RESERVED0              : array[0..2015] of array[0..7] of longWord;
  WAR                    : TRTC_WAR_bitbanded;         // 0x804 RTC Write Access Register
  RAR                    : TRTC_RAR_bitbanded;         // 0x808 RTC Read Access Register
end;

// System Integration Module
TSIM_SOPT1_bits = bitpacked record
  RESERVED0              : TBits_6;                    // [0:5] no description available
  RESERVED1              : TBits_6;                    // [6:11] no description available
  RAMSIZE                : TBits_4;                    // [12:15] RAM size
  RESERVED2              : TBits_2;                    // [16:17] no description available
  OSC32KSEL              : TBits_2;                    // [18:19] 32K oscillator clock select
  RESERVED3              : TBits_9;                    // [20:28] no description available
  USBVSTBY               : TBits_1;                    // [29:29] USB voltage regulator in standby mode during VLPR and VLPW modes
  USBSSTBY               : TBits_1;                    // [30:30] USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes.
  USBREGEN               : TBits_1;                    // [31:31] USB voltage regulator enable
end;

TSIM_SOPT1_bitbanded = record
  RESERVED0              : array[0..5] of longWord;    // [0:5] no description available
  RESERVED1              : array[0..5] of longWord;    // [6:11] no description available
  RAMSIZE                : array[0..3] of longWord;    // [12:15] RAM size
  RESERVED2              : array[0..1] of longWord;    // [16:17] no description available
  OSC32KSEL              : array[0..1] of longWord;    // [18:19] 32K oscillator clock select
  RESERVED3              : array[0..8] of longWord;    // [20:28] no description available
  USBVSTBY               : longWord;                   // [29:29] USB voltage regulator in standby mode during VLPR and VLPW modes
  USBSSTBY               : longWord;                   // [30:30] USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes.
  USBREGEN               : longWord;                   // [31:31] USB voltage regulator enable
end;

TSIM_SOPT1CFG_bits = bitpacked record
  RESERVED0              : TBits_8;                    // [0:7] no description available
  RESERVED1              : TBits_2;                    // [8:9] no description available
  RESERVED2              : TBits_14;                   // [10:23] no description available
  URWE                   : TBits_1;                    // [24:24] USB voltage regulator enable write enable
  UVSWE                  : TBits_1;                    // [25:25] USB voltage regulator VLP standby write enable
  USSWE                  : TBits_1;                    // [26:26] USB voltage regulator stop standby write enable
  RESERVED3              : TBits_5;                    // [27:31] no description available
end;

TSIM_SOPT1CFG_bitbanded = record
  RESERVED0              : array[0..7] of longWord;    // [0:7] no description available
  RESERVED1              : array[0..1] of longWord;    // [8:9] no description available
  RESERVED2              : array[0..13] of longWord;   // [10:23] no description available
  URWE                   : longWord;                   // [24:24] USB voltage regulator enable write enable
  UVSWE                  : longWord;                   // [25:25] USB voltage regulator VLP standby write enable
  USSWE                  : longWord;                   // [26:26] USB voltage regulator stop standby write enable
  RESERVED3              : array[0..4] of longWord;    // [27:31] no description available
end;

TSIM_SOPT2_bits = bitpacked record
  RESERVED0              : TBits_4;                    // [0:3] no description available
  RTCCLKOUTSEL           : TBits_1;                    // [4:4] RTC clock out select
  CLKOUTSEL              : TBits_3;                    // [5:7] CLKOUT select
  FBSL                   : TBits_2;                    // [8:9] FlexBus security level
  RESERVED1              : TBits_1;                    // [10:10] no description available
  PTD7PAD                : TBits_1;                    // [11:11] PTD7 pad drive strength
  TRACECLKSEL            : TBits_1;                    // [12:12] Debug trace clock select
  RESERVED2              : TBits_3;                    // [13:15] no description available
  PLLFLLSEL              : TBits_1;                    // [16:16] PLL/FLL clock select
  RESERVED3              : TBits_1;                    // [17:17] no description available
  USBSRC                 : TBits_1;                    // [18:18] USB clock source select
  RESERVED4              : TBits_3;                    // [19:21] no description available
  RESERVED5              : TBits_6;                    // [22:27] no description available
  RESERVED6              : TBits_2;                    // [28:29] no description available
  RESERVED7              : TBits_2;                    // [30:31] no description available
end;

TSIM_SOPT2_bitbanded = record
  RESERVED0              : array[0..3] of longWord;    // [0:3] no description available
  RTCCLKOUTSEL           : longWord;                   // [4:4] RTC clock out select
  CLKOUTSEL              : array[0..2] of longWord;    // [5:7] CLKOUT select
  FBSL                   : array[0..1] of longWord;    // [8:9] FlexBus security level
  RESERVED1              : longWord;                   // [10:10] no description available
  PTD7PAD                : longWord;                   // [11:11] PTD7 pad drive strength
  TRACECLKSEL            : longWord;                   // [12:12] Debug trace clock select
  RESERVED2              : array[0..2] of longWord;    // [13:15] no description available
  PLLFLLSEL              : longWord;                   // [16:16] PLL/FLL clock select
  RESERVED3              : longWord;                   // [17:17] no description available
  USBSRC                 : longWord;                   // [18:18] USB clock source select
  RESERVED4              : array[0..2] of longWord;    // [19:21] no description available
  RESERVED5              : array[0..5] of longWord;    // [22:27] no description available
  RESERVED6              : array[0..1] of longWord;    // [28:29] no description available
  RESERVED7              : array[0..1] of longWord;    // [30:31] no description available
end;

TSIM_SOPT4_bits = bitpacked record
  FTM0FLT0               : TBits_1;                    // [0:0] FTM0 Fault 0 Select
  FTM0FLT1               : TBits_1;                    // [1:1] FTM0 Fault 1 Select
  FTM0FLT2               : TBits_1;                    // [2:2] FTM0 Fault 2 Select
  RESERVED0              : TBits_1;                    // [3:3] no description available
  FTM1FLT0               : TBits_1;                    // [4:4] FTM1 Fault 0 Select
  RESERVED1              : TBits_3;                    // [5:7] no description available
  FTM2FLT0               : TBits_1;                    // [8:8] FTM2 Fault 0 Select
  RESERVED2              : TBits_9;                    // [9:17] no description available
  FTM1CH0SRC             : TBits_2;                    // [18:19] FTM1 channel 0 input capture source select
  FTM2CH0SRC             : TBits_2;                    // [20:21] FTM2 channel 0 input capture source select
  RESERVED3              : TBits_2;                    // [22:23] no description available
  FTM0CLKSEL             : TBits_1;                    // [24:24] FlexTimer 0 External Clock Pin Select
  FTM1CLKSEL             : TBits_1;                    // [25:25] FTM1 External Clock Pin Select
  FTM2CLKSEL             : TBits_1;                    // [26:26] FlexTimer 2 External Clock Pin Select
  RESERVED4              : TBits_1;                    // [27:27] no description available
  FTM0TRG0SRC            : TBits_1;                    // [28:28] FlexTimer 0 Hardware Trigger 0 Source Select
  FTM0TRG1SRC            : TBits_1;                    // [29:29] FlexTimer 0 Hardware Trigger 1 Source Select
  RESERVED5              : TBits_2;                    // [30:31] no description available
end;

TSIM_SOPT4_bitbanded = record
  FTM0FLT0               : longWord;                   // [0:0] FTM0 Fault 0 Select
  FTM0FLT1               : longWord;                   // [1:1] FTM0 Fault 1 Select
  FTM0FLT2               : longWord;                   // [2:2] FTM0 Fault 2 Select
  RESERVED0              : longWord;                   // [3:3] no description available
  FTM1FLT0               : longWord;                   // [4:4] FTM1 Fault 0 Select
  RESERVED1              : array[0..2] of longWord;    // [5:7] no description available
  FTM2FLT0               : longWord;                   // [8:8] FTM2 Fault 0 Select
  RESERVED2              : array[0..8] of longWord;    // [9:17] no description available
  FTM1CH0SRC             : array[0..1] of longWord;    // [18:19] FTM1 channel 0 input capture source select
  FTM2CH0SRC             : array[0..1] of longWord;    // [20:21] FTM2 channel 0 input capture source select
  RESERVED3              : array[0..1] of longWord;    // [22:23] no description available
  FTM0CLKSEL             : longWord;                   // [24:24] FlexTimer 0 External Clock Pin Select
  FTM1CLKSEL             : longWord;                   // [25:25] FTM1 External Clock Pin Select
  FTM2CLKSEL             : longWord;                   // [26:26] FlexTimer 2 External Clock Pin Select
  RESERVED4              : longWord;                   // [27:27] no description available
  FTM0TRG0SRC            : longWord;                   // [28:28] FlexTimer 0 Hardware Trigger 0 Source Select
  FTM0TRG1SRC            : longWord;                   // [29:29] FlexTimer 0 Hardware Trigger 1 Source Select
  RESERVED5              : array[0..1] of longWord;    // [30:31] no description available
end;

TSIM_SOPT5_bits = bitpacked record
  UART0TXSRC             : TBits_2;                    // [0:1] UART 0 transmit data source select
  UART0RXSRC             : TBits_2;                    // [2:3] UART 0 receive data source select
  UART1TXSRC             : TBits_2;                    // [4:5] UART 1 transmit data source select
  UART1RXSRC             : TBits_2;                    // [6:7] UART 1 receive data source select
  RESERVED0              : TBits_24;                   // [8:31] no description available
end;

TSIM_SOPT5_bitbanded = record
  UART0TXSRC             : array[0..1] of longWord;    // [0:1] UART 0 transmit data source select
  UART0RXSRC             : array[0..1] of longWord;    // [2:3] UART 0 receive data source select
  UART1TXSRC             : array[0..1] of longWord;    // [4:5] UART 1 transmit data source select
  UART1RXSRC             : array[0..1] of longWord;    // [6:7] UART 1 receive data source select
  RESERVED0              : array[0..23] of longWord;   // [8:31] no description available
end;

TSIM_SOPT7_bits = bitpacked record
  ADC0TRGSEL             : TBits_4;                    // [0:3] ADC0 trigger select
  ADC0PRETRGSEL          : TBits_1;                    // [4:4] ADC0 pretrigger select
  RESERVED0              : TBits_2;                    // [5:6] no description available
  ADC0ALTTRGEN           : TBits_1;                    // [7:7] ADC0 alternate trigger enable
  ADC1TRGSEL             : TBits_4;                    // [8:11] ADC1 trigger select
  ADC1PRETRGSEL          : TBits_1;                    // [12:12] ADC1 pre-trigger select
  RESERVED1              : TBits_2;                    // [13:14] no description available
  ADC1ALTTRGEN           : TBits_1;                    // [15:15] ADC1 alternate trigger enable
  RESERVED2              : TBits_16;                   // [16:31] no description available
end;

TSIM_SOPT7_bitbanded = record
  ADC0TRGSEL             : array[0..3] of longWord;    // [0:3] ADC0 trigger select
  ADC0PRETRGSEL          : longWord;                   // [4:4] ADC0 pretrigger select
  RESERVED0              : array[0..1] of longWord;    // [5:6] no description available
  ADC0ALTTRGEN           : longWord;                   // [7:7] ADC0 alternate trigger enable
  ADC1TRGSEL             : array[0..3] of longWord;    // [8:11] ADC1 trigger select
  ADC1PRETRGSEL          : longWord;                   // [12:12] ADC1 pre-trigger select
  RESERVED1              : array[0..1] of longWord;    // [13:14] no description available
  ADC1ALTTRGEN           : longWord;                   // [15:15] ADC1 alternate trigger enable
  RESERVED2              : array[0..15] of longWord;   // [16:31] no description available
end;

TSIM_SDID_bits = bitpacked record
  PINID                  : TBits_4;                    // [0:3] Pincount identification
  FAMID                  : TBits_3;                    // [4:6] Kinetis family identification
  RESERVED0              : TBits_1;                    // [7:7] no description available
  RESERVED1              : TBits_1;                    // [8:8] no description available
  RESERVED2              : TBits_1;                    // [9:9] no description available
  RESERVED3              : TBits_1;                    // [10:10] no description available
  RESERVED4              : TBits_1;                    // [11:11] no description available
  REVID                  : TBits_4;                    // [12:15] Device revision number
  RESERVED5              : TBits_16;                   // [16:31] no description available
end;

TSIM_SDID_bitbanded = record
  PINID                  : array[0..3] of longWord;    // [0:3] Pincount identification
  FAMID                  : array[0..2] of longWord;    // [4:6] Kinetis family identification
  RESERVED0              : longWord;                   // [7:7] no description available
  RESERVED1              : longWord;                   // [8:8] no description available
  RESERVED2              : longWord;                   // [9:9] no description available
  RESERVED3              : longWord;                   // [10:10] no description available
  RESERVED4              : longWord;                   // [11:11] no description available
  REVID                  : array[0..3] of longWord;    // [12:15] Device revision number
  RESERVED5              : array[0..15] of longWord;   // [16:31] no description available
end;

TSIM_SCGC1_bits = bitpacked record
  RESERVED0              : TBits_6;                    // [0:5] no description available
  RESERVED1              : TBits_1;                    // [6:6] no description available
  RESERVED2              : TBits_1;                    // [7:7] no description available
  RESERVED3              : TBits_2;                    // [8:9] no description available
  UART4                  : TBits_1;                    // [10:10] UART4 Clock Gate Control
  RESERVED4              : TBits_1;                    // [11:11] no description available
  RESERVED5              : TBits_9;                    // [12:20] no description available
  RESERVED6              : TBits_1;                    // [21:21] no description available
  RESERVED7              : TBits_2;                    // [22:23] no description available
  RESERVED8              : TBits_1;                    // [24:24] no description available
  RESERVED9              : TBits_7;                    // [25:31] no description available
end;

TSIM_SCGC1_bitbanded = record
  RESERVED0              : array[0..5] of longWord;    // [0:5] no description available
  RESERVED1              : longWord;                   // [6:6] no description available
  RESERVED2              : longWord;                   // [7:7] no description available
  RESERVED3              : array[0..1] of longWord;    // [8:9] no description available
  UART4                  : longWord;                   // [10:10] UART4 Clock Gate Control
  RESERVED4              : longWord;                   // [11:11] no description available
  RESERVED5              : array[0..8] of longWord;    // [12:20] no description available
  RESERVED6              : longWord;                   // [21:21] no description available
  RESERVED7              : array[0..1] of longWord;    // [22:23] no description available
  RESERVED8              : longWord;                   // [24:24] no description available
  RESERVED9              : array[0..6] of longWord;    // [25:31] no description available
end;

TSIM_SCGC2_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] no description available
  RESERVED1              : TBits_11;                   // [1:11] no description available
  DAC0                   : TBits_1;                    // [12:12] DAC0 Clock Gate Control
  RESERVED2              : TBits_1;                    // [13:13] no description available
  RESERVED3              : TBits_18;                   // [14:31] no description available
end;

TSIM_SCGC2_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] no description available
  RESERVED1              : array[0..10] of longWord;   // [1:11] no description available
  DAC0                   : longWord;                   // [12:12] DAC0 Clock Gate Control
  RESERVED2              : longWord;                   // [13:13] no description available
  RESERVED3              : array[0..17] of longWord;   // [14:31] no description available
end;

TSIM_SCGC3_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] no description available
  RESERVED1              : TBits_3;                    // [1:3] no description available
  RESERVED2              : TBits_1;                    // [4:4] no description available
  RESERVED3              : TBits_7;                    // [5:11] no description available
  RESERVED4              : TBits_1;                    // [12:12] no description available
  RESERVED5              : TBits_4;                    // [13:16] no description available
  RESERVED6              : TBits_1;                    // [17:17] no description available
  RESERVED7              : TBits_6;                    // [18:23] no description available
  FTM2                   : TBits_1;                    // [24:24] FTM2 Clock Gate Control
  RESERVED8              : TBits_2;                    // [25:26] no description available
  ADC1                   : TBits_1;                    // [27:27] ADC1 Clock Gate Control
  RESERVED9              : TBits_2;                    // [28:29] no description available
  RESERVED10             : TBits_1;                    // [30:30] no description available
  RESERVED11             : TBits_1;                    // [31:31] no description available
end;

TSIM_SCGC3_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] no description available
  RESERVED1              : array[0..2] of longWord;    // [1:3] no description available
  RESERVED2              : longWord;                   // [4:4] no description available
  RESERVED3              : array[0..6] of longWord;    // [5:11] no description available
  RESERVED4              : longWord;                   // [12:12] no description available
  RESERVED5              : array[0..3] of longWord;    // [13:16] no description available
  RESERVED6              : longWord;                   // [17:17] no description available
  RESERVED7              : array[0..5] of longWord;    // [18:23] no description available
  FTM2                   : longWord;                   // [24:24] FTM2 Clock Gate Control
  RESERVED8              : array[0..1] of longWord;    // [25:26] no description available
  ADC1                   : longWord;                   // [27:27] ADC1 Clock Gate Control
  RESERVED9              : array[0..1] of longWord;    // [28:29] no description available
  RESERVED10             : longWord;                   // [30:30] no description available
  RESERVED11             : longWord;                   // [31:31] no description available
end;

TSIM_SCGC4_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] no description available
  EWM                    : TBits_1;                    // [1:1] EWM Clock Gate Control
  CMT                    : TBits_1;                    // [2:2] CMT Clock Gate Control
  RESERVED1              : TBits_1;                    // [3:3] no description available
  RESERVED2              : TBits_2;                    // [4:5] no description available
  I2C0                   : TBits_1;                    // [6:6] I2C0 Clock Gate Control
  I2C1                   : TBits_1;                    // [7:7] I2C1 Clock Gate Control
  RESERVED3              : TBits_2;                    // [8:9] no description available
  UART0                  : TBits_1;                    // [10:10] UART0 Clock Gate Control
  UART1                  : TBits_1;                    // [11:11] UART1 Clock Gate Control
  UART2                  : TBits_1;                    // [12:12] UART2 Clock Gate Control
  UART3                  : TBits_1;                    // [13:13] UART3 Clock Gate Control
  RESERVED4              : TBits_4;                    // [14:17] no description available
  USBOTG                 : TBits_1;                    // [18:18] USB Clock Gate Control
  CMP                    : TBits_1;                    // [19:19] Comparator Clock Gate Control
  VREF                   : TBits_1;                    // [20:20] VREF Clock Gate Control
  RESERVED5              : TBits_7;                    // [21:27] no description available
  RESERVED6              : TBits_4;                    // [28:31] no description available
end;

TSIM_SCGC4_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] no description available
  EWM                    : longWord;                   // [1:1] EWM Clock Gate Control
  CMT                    : longWord;                   // [2:2] CMT Clock Gate Control
  RESERVED1              : longWord;                   // [3:3] no description available
  RESERVED2              : array[0..1] of longWord;    // [4:5] no description available
  I2C0                   : longWord;                   // [6:6] I2C0 Clock Gate Control
  I2C1                   : longWord;                   // [7:7] I2C1 Clock Gate Control
  RESERVED3              : array[0..1] of longWord;    // [8:9] no description available
  UART0                  : longWord;                   // [10:10] UART0 Clock Gate Control
  UART1                  : longWord;                   // [11:11] UART1 Clock Gate Control
  UART2                  : longWord;                   // [12:12] UART2 Clock Gate Control
  UART3                  : longWord;                   // [13:13] UART3 Clock Gate Control
  RESERVED4              : array[0..3] of longWord;    // [14:17] no description available
  USBOTG                 : longWord;                   // [18:18] USB Clock Gate Control
  CMP                    : longWord;                   // [19:19] Comparator Clock Gate Control
  VREF                   : longWord;                   // [20:20] VREF Clock Gate Control
  RESERVED5              : array[0..6] of longWord;    // [21:27] no description available
  RESERVED6              : array[0..3] of longWord;    // [28:31] no description available
end;

TSIM_SCGC5_bits = bitpacked record
  LPTIMER                : TBits_1;                    // [0:0] Low Power Timer Access Control
  RESERVED0              : TBits_1;                    // [1:1] no description available
  RESERVED1              : TBits_2;                    // [2:3] no description available
  RESERVED2              : TBits_1;                    // [4:4] no description available
  TSI                    : TBits_1;                    // [5:5] TSI Clock Gate Control
  RESERVED3              : TBits_1;                    // [6:6] no description available
  RESERVED4              : TBits_2;                    // [7:8] no description available
  PORTA                  : TBits_1;                    // [9:9] Port A Clock Gate Control
  PORTB                  : TBits_1;                    // [10:10] Port B Clock Gate Control
  PORTC                  : TBits_1;                    // [11:11] Port C Clock Gate Control
  PORTD                  : TBits_1;                    // [12:12] Port D Clock Gate Control
  PORTE                  : TBits_1;                    // [13:13] Port E Clock Gate Control
  RESERVED5              : TBits_4;                    // [14:17] no description available
  RESERVED6              : TBits_1;                    // [18:18] no description available
  RESERVED7              : TBits_13;                   // [19:31] no description available
end;

TSIM_SCGC5_bitbanded = record
  LPTIMER                : longWord;                   // [0:0] Low Power Timer Access Control
  RESERVED0              : longWord;                   // [1:1] no description available
  RESERVED1              : array[0..1] of longWord;    // [2:3] no description available
  RESERVED2              : longWord;                   // [4:4] no description available
  TSI                    : longWord;                   // [5:5] TSI Clock Gate Control
  RESERVED3              : longWord;                   // [6:6] no description available
  RESERVED4              : array[0..1] of longWord;    // [7:8] no description available
  PORTA                  : longWord;                   // [9:9] Port A Clock Gate Control
  PORTB                  : longWord;                   // [10:10] Port B Clock Gate Control
  PORTC                  : longWord;                   // [11:11] Port C Clock Gate Control
  PORTD                  : longWord;                   // [12:12] Port D Clock Gate Control
  PORTE                  : longWord;                   // [13:13] Port E Clock Gate Control
  RESERVED5              : array[0..3] of longWord;    // [14:17] no description available
  RESERVED6              : longWord;                   // [18:18] no description available
  RESERVED7              : array[0..12] of longWord;   // [19:31] no description available
end;

TSIM_SCGC6_bits = bitpacked record
  FTFL                   : TBits_1;                    // [0:0] Flash Memory Clock Gate Control
  DMAMUX                 : TBits_1;                    // [1:1] DMA Mux Clock Gate Control
  RESERVED0              : TBits_2;                    // [2:3] no description available
  FLEXCAN0               : TBits_1;                    // [4:4] FlexCAN0 Clock Gate Control
  RESERVED1              : TBits_4;                    // [5:8] no description available
  RESERVED2              : TBits_1;                    // [9:9] no description available
  RESERVED3              : TBits_2;                    // [10:11] no description available
  SPI0                   : TBits_1;                    // [12:12] SPI0 Clock Gate Control
  SPI1                   : TBits_1;                    // [13:13] SPI1 Clock Gate Control
  RESERVED4              : TBits_1;                    // [14:14] no description available
  I2S                    : TBits_1;                    // [15:15] I2S Clock Gate Control
  RESERVED5              : TBits_2;                    // [16:17] no description available
  CRC                    : TBits_1;                    // [18:18] CRC Clock Gate Control
  RESERVED6              : TBits_2;                    // [19:20] no description available
  USBDCD                 : TBits_1;                    // [21:21] USB DCD Clock Gate Control
  PDB                    : TBits_1;                    // [22:22] PDB Clock Gate Control
  PIT                    : TBits_1;                    // [23:23] PIT Clock Gate Control
  FTM0                   : TBits_1;                    // [24:24] FTM0 Clock Gate Control
  FTM1                   : TBits_1;                    // [25:25] FTM1 Clock Gate Control
  RESERVED7              : TBits_1;                    // [26:26] no description available
  ADC0                   : TBits_1;                    // [27:27] ADC0 Clock Gate Control
  RESERVED8              : TBits_1;                    // [28:28] no description available
  RTC                    : TBits_1;                    // [29:29] RTC Access Control
  RESERVED9              : TBits_1;                    // [30:30] no description available
  RESERVED10             : TBits_1;                    // [31:31] no description available
end;

TSIM_SCGC6_bitbanded = record
  FTFL                   : longWord;                   // [0:0] Flash Memory Clock Gate Control
  DMAMUX                 : longWord;                   // [1:1] DMA Mux Clock Gate Control
  RESERVED0              : array[0..1] of longWord;    // [2:3] no description available
  FLEXCAN0               : longWord;                   // [4:4] FlexCAN0 Clock Gate Control
  RESERVED1              : array[0..3] of longWord;    // [5:8] no description available
  RESERVED2              : longWord;                   // [9:9] no description available
  RESERVED3              : array[0..1] of longWord;    // [10:11] no description available
  SPI0                   : longWord;                   // [12:12] SPI0 Clock Gate Control
  SPI1                   : longWord;                   // [13:13] SPI1 Clock Gate Control
  RESERVED4              : longWord;                   // [14:14] no description available
  I2S                    : longWord;                   // [15:15] I2S Clock Gate Control
  RESERVED5              : array[0..1] of longWord;    // [16:17] no description available
  CRC                    : longWord;                   // [18:18] CRC Clock Gate Control
  RESERVED6              : array[0..1] of longWord;    // [19:20] no description available
  USBDCD                 : longWord;                   // [21:21] USB DCD Clock Gate Control
  PDB                    : longWord;                   // [22:22] PDB Clock Gate Control
  PIT                    : longWord;                   // [23:23] PIT Clock Gate Control
  FTM0                   : longWord;                   // [24:24] FTM0 Clock Gate Control
  FTM1                   : longWord;                   // [25:25] FTM1 Clock Gate Control
  RESERVED7              : longWord;                   // [26:26] no description available
  ADC0                   : longWord;                   // [27:27] ADC0 Clock Gate Control
  RESERVED8              : longWord;                   // [28:28] no description available
  RTC                    : longWord;                   // [29:29] RTC Access Control
  RESERVED9              : longWord;                   // [30:30] no description available
  RESERVED10             : longWord;                   // [31:31] no description available
end;

TSIM_SCGC7_bits = bitpacked record
  FLEXBUS                : TBits_1;                    // [0:0] FlexBus Clock Gate Control
  DMA                    : TBits_1;                    // [1:1] DMA Clock Gate Control
  RESERVED0              : TBits_1;                    // [2:2] no description available
  RESERVED1              : TBits_29;                   // [3:31] no description available
end;

TSIM_SCGC7_bitbanded = record
  FLEXBUS                : longWord;                   // [0:0] FlexBus Clock Gate Control
  DMA                    : longWord;                   // [1:1] DMA Clock Gate Control
  RESERVED0              : longWord;                   // [2:2] no description available
  RESERVED1              : array[0..28] of longWord;   // [3:31] no description available
end;

TSIM_CLKDIV1_bits = bitpacked record
  RESERVED0              : TBits_16;                   // [0:15] no description available
  OUTDIV4                : TBits_4;                    // [16:19] Clock 4 output divider value
  OUTDIV3                : TBits_4;                    // [20:23] Clock 3 output divider value
  OUTDIV2                : TBits_4;                    // [24:27] Clock 2 output divider value
  OUTDIV1                : TBits_4;                    // [28:31] Clock 1 output divider value
end;

TSIM_CLKDIV1_bitbanded = record
  RESERVED0              : array[0..15] of longWord;   // [0:15] no description available
  OUTDIV4                : array[0..3] of longWord;    // [16:19] Clock 4 output divider value
  OUTDIV3                : array[0..3] of longWord;    // [20:23] Clock 3 output divider value
  OUTDIV2                : array[0..3] of longWord;    // [24:27] Clock 2 output divider value
  OUTDIV1                : array[0..3] of longWord;    // [28:31] Clock 1 output divider value
end;

TSIM_CLKDIV2_bits = bitpacked record
  USBFRAC                : TBits_1;                    // [0:0] USB clock divider fraction
  USBDIV                 : TBits_3;                    // [1:3] USB clock divider divisor
  RESERVED0              : TBits_28;                   // [4:31] no description available
end;

TSIM_CLKDIV2_bitbanded = record
  USBFRAC                : longWord;                   // [0:0] USB clock divider fraction
  USBDIV                 : array[0..2] of longWord;    // [1:3] USB clock divider divisor
  RESERVED0              : array[0..27] of longWord;   // [4:31] no description available
end;

TSIM_FCFG1_bits = bitpacked record
  FLASHDIS               : TBits_1;                    // [0:0] Flash Disable
  FLASHDOZE              : TBits_1;                    // [1:1] Flash Doze
  RESERVED0              : TBits_6;                    // [2:7] no description available
  DEPART                 : TBits_4;                    // [8:11] FlexNVM partition
  RESERVED1              : TBits_4;                    // [12:15] no description available
  EESIZE                 : TBits_4;                    // [16:19] EEPROM size
  RESERVED2              : TBits_4;                    // [20:23] no description available
  PFSIZE                 : TBits_4;                    // [24:27] Program flash size
  NVMSIZE                : TBits_4;                    // [28:31] FlexNVM size
end;

TSIM_FCFG1_bitbanded = record
  FLASHDIS               : longWord;                   // [0:0] Flash Disable
  FLASHDOZE              : longWord;                   // [1:1] Flash Doze
  RESERVED0              : array[0..5] of longWord;    // [2:7] no description available
  DEPART                 : array[0..3] of longWord;    // [8:11] FlexNVM partition
  RESERVED1              : array[0..3] of longWord;    // [12:15] no description available
  EESIZE                 : array[0..3] of longWord;    // [16:19] EEPROM size
  RESERVED2              : array[0..3] of longWord;    // [20:23] no description available
  PFSIZE                 : array[0..3] of longWord;    // [24:27] Program flash size
  NVMSIZE                : array[0..3] of longWord;    // [28:31] FlexNVM size
end;

TSIM_FCFG2_bits = bitpacked record
  RESERVED0              : TBits_16;                   // [0:15] no description available
  MAXADDR1               : TBits_7;                    // [16:22] Max address block 1
  PFLSH                  : TBits_1;                    // [23:23] Program flash
  MAXADDR0               : TBits_7;                    // [24:30] Max address block 0
  SWAPPFLSH              : TBits_1;                    // [31:31] Swap program flash
end;

TSIM_FCFG2_bitbanded = record
  RESERVED0              : array[0..15] of longWord;   // [0:15] no description available
  MAXADDR1               : array[0..6] of longWord;    // [16:22] Max address block 1
  PFLSH                  : longWord;                   // [23:23] Program flash
  MAXADDR0               : array[0..6] of longWord;    // [24:30] Max address block 0
  SWAPPFLSH              : longWord;                   // [31:31] Swap program flash
end;

TSIM_UIDH_bits = bitpacked record
  UID                    : TBits_32;                   // [0:31] Unique Identification
end;

TSIM_UIDH_bitbanded = record
  UID                    : array[0..31] of longWord;   // [0:31] Unique Identification
end;

TSIM_UIDMH_bits = bitpacked record
  UID                    : TBits_32;                   // [0:31] Unique Identification
end;

TSIM_UIDMH_bitbanded = record
  UID                    : array[0..31] of longWord;   // [0:31] Unique Identification
end;

TSIM_UIDML_bits = bitpacked record
  UID                    : TBits_32;                   // [0:31] Unique Identification
end;

TSIM_UIDML_bitbanded = record
  UID                    : array[0..31] of longWord;   // [0:31] Unique Identification
end;

TSIM_UIDL_bits = bitpacked record
  UID                    : TBits_32;                   // [0:31] Unique Identification
end;

TSIM_UIDL_bitbanded = record
  UID                    : array[0..31] of longWord;   // [0:31] Unique Identification
end;

TSIM_Registers = record
  case boolean of false: (
  SOPT1                  : longWord;                   // 0x00 System Options Register 1
  SOPT1CFG               : longWord;                   // 0x04 SOPT1 Configuration Register
  RESERVED0              : array[0..1022] of longWord; // 0x08
  SOPT2                  : longWord;                   // 0x1004 System Options Register 2
  RESERVED1              : longWord;                   // 0x1008
  SOPT4                  : longWord;                   // 0x100C System Options Register 4
  SOPT5                  : longWord;                   // 0x1010 System Options Register 5
  RESERVED2              : longWord;                   // 0x1014
  SOPT7                  : longWord;                   // 0x1018 System Options Register 7
  RESERVED3              : array[0..1] of longWord;    // 0x101C
  SDID                   : longWord;                   // 0x1024 System Device Identification Register
  SCGC1                  : longWord;                   // 0x1028 System Clock Gating Control Register 1
  SCGC2                  : longWord;                   // 0x102C System Clock Gating Control Register 2
  SCGC3                  : longWord;                   // 0x1030 System Clock Gating Control Register 3
  SCGC4                  : longWord;                   // 0x1034 System Clock Gating Control Register 4
  SCGC5                  : longWord;                   // 0x1038 System Clock Gating Control Register 5
  SCGC6                  : longWord;                   // 0x103C System Clock Gating Control Register 6
  SCGC7                  : longWord;                   // 0x1040 System Clock Gating Control Register 7
  CLKDIV1                : longWord;                   // 0x1044 System Clock Divider Register 1
  CLKDIV2                : longWord;                   // 0x1048 System Clock Divider Register 2
  FCFG1                  : longWord;                   // 0x104C Flash Configuration Register 1
  FCFG2                  : longWord;                   // 0x1050 Flash Configuration Register 2
  UIDH                   : longWord;                   // 0x1054 Unique Identification Register High
  UIDMH                  : longWord;                   // 0x1058 Unique Identification Register Mid-High
  UIDML                  : longWord;                   // 0x105C Unique Identification Register Mid Low
  UIDL                   : longWord;                   // 0x1060 Unique Identification Register Low
);
true : (
SOPT1_bits               : TSIM_SOPT1_bits;            // 0x04 System Options Register 1
SOPT1CFG_bits            : TSIM_SOPT1CFG_bits;         // 0x08 SOPT1 Configuration Register
RESERVED_bits0           : array[0..1022] of longWord;
SOPT2_bits               : TSIM_SOPT2_bits;            // 0x1008 System Options Register 2
RESERVED_bits1           : longWord;
SOPT4_bits               : TSIM_SOPT4_bits;            // 0x1010 System Options Register 4
SOPT5_bits               : TSIM_SOPT5_bits;            // 0x1014 System Options Register 5
RESERVED_bits2           : longWord;
SOPT7_bits               : TSIM_SOPT7_bits;            // 0x101C System Options Register 7
RESERVED_bits3           : array[0..1] of longWord;
SDID_bits                : TSIM_SDID_bits;             // 0x1028 System Device Identification Register
SCGC1_bits               : TSIM_SCGC1_bits;            // 0x102C System Clock Gating Control Register 1
SCGC2_bits               : TSIM_SCGC2_bits;            // 0x1030 System Clock Gating Control Register 2
SCGC3_bits               : TSIM_SCGC3_bits;            // 0x1034 System Clock Gating Control Register 3
SCGC4_bits               : TSIM_SCGC4_bits;            // 0x1038 System Clock Gating Control Register 4
SCGC5_bits               : TSIM_SCGC5_bits;            // 0x103C System Clock Gating Control Register 5
SCGC6_bits               : TSIM_SCGC6_bits;            // 0x1040 System Clock Gating Control Register 6
SCGC7_bits               : TSIM_SCGC7_bits;            // 0x1044 System Clock Gating Control Register 7
CLKDIV1_bits             : TSIM_CLKDIV1_bits;          // 0x1048 System Clock Divider Register 1
CLKDIV2_bits             : TSIM_CLKDIV2_bits;          // 0x104C System Clock Divider Register 2
FCFG1_bits               : TSIM_FCFG1_bits;            // 0x1050 Flash Configuration Register 1
FCFG2_bits               : TSIM_FCFG2_bits;            // 0x1054 Flash Configuration Register 2
UIDH_bits                : TSIM_UIDH_bits;             // 0x1058 Unique Identification Register High
UIDMH_bits               : TSIM_UIDMH_bits;            // 0x105C Unique Identification Register Mid-High
UIDML_bits               : TSIM_UIDML_bits;            // 0x1060 Unique Identification Register Mid Low
UIDL_bits                : TSIM_UIDL_bits;             // 0x1064 Unique Identification Register Low
);
end;

TSIMRegisters_bitbanded = record
  SOPT1                  : TSIM_SOPT1_bitbanded;       // 0x04 System Options Register 1
  SOPT1CFG               : TSIM_SOPT1CFG_bitbanded;    // 0x08 SOPT1 Configuration Register
  RESERVED0              : array[0..4091] of array[0..7] of longWord;
  SOPT2                  : TSIM_SOPT2_bitbanded;       // 0x1008 System Options Register 2
  RESERVED1              : array[0..3] of array[0..7] of longWord;
  SOPT4                  : TSIM_SOPT4_bitbanded;       // 0x1010 System Options Register 4
  SOPT5                  : TSIM_SOPT5_bitbanded;       // 0x1014 System Options Register 5
  RESERVED2              : array[0..3] of array[0..7] of longWord;
  SOPT7                  : TSIM_SOPT7_bitbanded;       // 0x101C System Options Register 7
  RESERVED3              : array[0..7] of array[0..7] of longWord;
  SDID                   : TSIM_SDID_bitbanded;        // 0x1028 System Device Identification Register
  SCGC1                  : TSIM_SCGC1_bitbanded;       // 0x102C System Clock Gating Control Register 1
  SCGC2                  : TSIM_SCGC2_bitbanded;       // 0x1030 System Clock Gating Control Register 2
  SCGC3                  : TSIM_SCGC3_bitbanded;       // 0x1034 System Clock Gating Control Register 3
  SCGC4                  : TSIM_SCGC4_bitbanded;       // 0x1038 System Clock Gating Control Register 4
  SCGC5                  : TSIM_SCGC5_bitbanded;       // 0x103C System Clock Gating Control Register 5
  SCGC6                  : TSIM_SCGC6_bitbanded;       // 0x1040 System Clock Gating Control Register 6
  SCGC7                  : TSIM_SCGC7_bitbanded;       // 0x1044 System Clock Gating Control Register 7
  CLKDIV1                : TSIM_CLKDIV1_bitbanded;     // 0x1048 System Clock Divider Register 1
  CLKDIV2                : TSIM_CLKDIV2_bitbanded;     // 0x104C System Clock Divider Register 2
  FCFG1                  : TSIM_FCFG1_bitbanded;       // 0x1050 Flash Configuration Register 1
  FCFG2                  : TSIM_FCFG2_bitbanded;       // 0x1054 Flash Configuration Register 2
  UIDH                   : TSIM_UIDH_bitbanded;        // 0x1058 Unique Identification Register High
  UIDMH                  : TSIM_UIDMH_bitbanded;       // 0x105C Unique Identification Register Mid-High
  UIDML                  : TSIM_UIDML_bitbanded;       // 0x1060 Unique Identification Register Mid Low
  UIDL                   : TSIM_UIDL_bitbanded;        // 0x1064 Unique Identification Register Low
end;

// System Mode Controller
TSMC_PMPROT_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] no description available
  AVLLS                  : TBits_1;                    // [1:1] Allow very low leakage stop mode
  RESERVED1              : TBits_1;                    // [2:2] no description available
  ALLS                   : TBits_1;                    // [3:3] Allow low leakage stop mode
  RESERVED2              : TBits_1;                    // [4:4] no description available
  AVLP                   : TBits_1;                    // [5:5] Allow very low power modes
  RESERVED3              : TBits_2;                    // [6:7] no description available
end;

TSMC_PMPROT_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] no description available
  AVLLS                  : longWord;                   // [1:1] Allow very low leakage stop mode
  RESERVED1              : longWord;                   // [2:2] no description available
  ALLS                   : longWord;                   // [3:3] Allow low leakage stop mode
  RESERVED2              : longWord;                   // [4:4] no description available
  AVLP                   : longWord;                   // [5:5] Allow very low power modes
  RESERVED3              : array[0..1] of longWord;    // [6:7] no description available
end;

TSMC_PMCTRL_bits = bitpacked record
  STOPM                  : TBits_3;                    // [0:2] Stop Mode Control
  STOPA                  : TBits_1;                    // [3:3] Stop Aborted
  RESERVED0              : TBits_1;                    // [4:4] no description available
  RUNM                   : TBits_2;                    // [5:6] Run Mode Control
  RESERVED1              : TBits_1;                    // [7:7] no description available
end;

TSMC_PMCTRL_bitbanded = record
  STOPM                  : array[0..2] of longWord;    // [0:2] Stop Mode Control
  STOPA                  : longWord;                   // [3:3] Stop Aborted
  RESERVED0              : longWord;                   // [4:4] no description available
  RUNM                   : array[0..1] of longWord;    // [5:6] Run Mode Control
  RESERVED1              : longWord;                   // [7:7] no description available
end;

TSMC_VLLSCTRL_bits = bitpacked record
  VLLSM                  : TBits_3;                    // [0:2] VLLS Mode Control
  RESERVED0              : TBits_1;                    // [3:3] no description available
  RESERVED1              : TBits_1;                    // [4:4] no description available
  RESERVED2              : TBits_1;                    // [5:5] no description available
  RESERVED3              : TBits_2;                    // [6:7] no description available
end;

TSMC_VLLSCTRL_bitbanded = record
  VLLSM                  : array[0..2] of longWord;    // [0:2] VLLS Mode Control
  RESERVED0              : longWord;                   // [3:3] no description available
  RESERVED1              : longWord;                   // [4:4] no description available
  RESERVED2              : longWord;                   // [5:5] no description available
  RESERVED3              : array[0..1] of longWord;    // [6:7] no description available
end;

TSMC_PMSTAT_bits = bitpacked record
  PMSTAT                 : TBits_7;                    // [0:6] no description available
  RESERVED0              : TBits_1;                    // [7:7] no description available
end;

TSMC_PMSTAT_bitbanded = record
  PMSTAT                 : array[0..6] of longWord;    // [0:6] no description available
  RESERVED0              : longWord;                   // [7:7] no description available
end;

TSMC_Registers = record
  case boolean of false: (
  PMPROT                 : byte;                       // 0x00 Power Mode Protection Register
  PMCTRL                 : byte;                       // 0x01 Power Mode Control Register
  VLLSCTRL               : byte;                       // 0x02 VLLS Control Register
  PMSTAT                 : byte;                       // 0x03 Power Mode Status Register
);
true : (
PMPROT_bits              : TSMC_PMPROT_bits;           // 0x01 Power Mode Protection Register
PMCTRL_bits              : TSMC_PMCTRL_bits;           // 0x02 Power Mode Control Register
VLLSCTRL_bits            : TSMC_VLLSCTRL_bits;         // 0x03 VLLS Control Register
PMSTAT_bits              : TSMC_PMSTAT_bits;           // 0x04 Power Mode Status Register
);
end;

TSMCRegisters_bitbanded = record
  PMPROT                 : TSMC_PMPROT_bitbanded;      // 0x01 Power Mode Protection Register
  PMCTRL                 : TSMC_PMCTRL_bitbanded;      // 0x02 Power Mode Control Register
  VLLSCTRL               : TSMC_VLLSCTRL_bitbanded;    // 0x03 VLLS Control Register
  PMSTAT                 : TSMC_PMSTAT_bitbanded;      // 0x04 Power Mode Status Register
end;

// Deserial Serial Peripheral Interface
TSPI0_MCR_bits = bitpacked record
  HALT                   : TBits_1;                    // [0:0] Halt
  RESERVED0              : TBits_1;                    // [1:1] no description available
  RESERVED1              : TBits_6;                    // [2:7] no description available
  SMPL_PT                : TBits_2;                    // [8:9] Sample Point
  CLR_RXF                : TBits_1;                    // [10:10] no description available
  CLR_TXF                : TBits_1;                    // [11:11] Clear TX FIFO
  DIS_RXF                : TBits_1;                    // [12:12] Disable Receive FIFO
  DIS_TXF                : TBits_1;                    // [13:13] Disable Transmit FIFO
  MDIS                   : TBits_1;                    // [14:14] Module Disable
  DOZE                   : TBits_1;                    // [15:15] Doze Enable
  PCSIS                  : TBits_6;                    // [16:21] Peripheral Chip Select x Inactive State
  RESERVED2              : TBits_2;                    // [22:23] no description available
  ROOE                   : TBits_1;                    // [24:24] Receive FIFO Overflow Overwrite Enable
  PCSSE                  : TBits_1;                    // [25:25] Peripheral Chip Select Strobe Enable
  MTFE                   : TBits_1;                    // [26:26] Modified Timing Format Enable
  FRZ                    : TBits_1;                    // [27:27] Freeze
  DCONF                  : TBits_2;                    // [28:29] DSPI Configuration
  CONT_SCKE              : TBits_1;                    // [30:30] Continuous SCK Enable
  MSTR                   : TBits_1;                    // [31:31] Master/Slave Mode Select
end;

TSPI0_MCR_bitbanded = record
  HALT                   : longWord;                   // [0:0] Halt
  RESERVED0              : longWord;                   // [1:1] no description available
  RESERVED1              : array[0..5] of longWord;    // [2:7] no description available
  SMPL_PT                : array[0..1] of longWord;    // [8:9] Sample Point
  CLR_RXF                : longWord;                   // [10:10] no description available
  CLR_TXF                : longWord;                   // [11:11] Clear TX FIFO
  DIS_RXF                : longWord;                   // [12:12] Disable Receive FIFO
  DIS_TXF                : longWord;                   // [13:13] Disable Transmit FIFO
  MDIS                   : longWord;                   // [14:14] Module Disable
  DOZE                   : longWord;                   // [15:15] Doze Enable
  PCSIS                  : array[0..5] of longWord;    // [16:21] Peripheral Chip Select x Inactive State
  RESERVED2              : array[0..1] of longWord;    // [22:23] no description available
  ROOE                   : longWord;                   // [24:24] Receive FIFO Overflow Overwrite Enable
  PCSSE                  : longWord;                   // [25:25] Peripheral Chip Select Strobe Enable
  MTFE                   : longWord;                   // [26:26] Modified Timing Format Enable
  FRZ                    : longWord;                   // [27:27] Freeze
  DCONF                  : array[0..1] of longWord;    // [28:29] DSPI Configuration
  CONT_SCKE              : longWord;                   // [30:30] Continuous SCK Enable
  MSTR                   : longWord;                   // [31:31] Master/Slave Mode Select
end;

TSPI0_TCR_bits = bitpacked record
  RESERVED0              : TBits_16;                   // [0:15] no description available
  SPI_TCNT               : TBits_16;                   // [16:31] SPI Transfer Counter
end;

TSPI0_TCR_bitbanded = record
  RESERVED0              : array[0..15] of longWord;   // [0:15] no description available
  SPI_TCNT               : array[0..15] of longWord;   // [16:31] SPI Transfer Counter
end;

TSPI0_CTAR_SLAVE_bits = bitpacked record
  RESERVED0              : TBits_23;                   // [0:22] no description available
  RESERVED1              : TBits_2;                    // [23:24] no description available
  CPHA                   : TBits_1;                    // [25:25] Clock Phase
  CPOL                   : TBits_1;                    // [26:26] Clock Polarity
  FMSZ                   : TBits_5;                    // [27:31] Frame Size
end;

TSPI0_CTAR_SLAVE_bitbanded = record
  RESERVED0              : array[0..22] of longWord;   // [0:22] no description available
  RESERVED1              : array[0..1] of longWord;    // [23:24] no description available
  CPHA                   : longWord;                   // [25:25] Clock Phase
  CPOL                   : longWord;                   // [26:26] Clock Polarity
  FMSZ                   : array[0..4] of longWord;    // [27:31] Frame Size
end;

TSPI0_CTAR_bits = bitpacked record
  BR                     : TBits_4;                    // [0:3] Baud Rate Scaler
  DT                     : TBits_4;                    // [4:7] Delay After Transfer Scaler
  ASC                    : TBits_4;                    // [8:11] After SCK Delay Scaler
  CSSCK                  : TBits_4;                    // [12:15] PCS to SCK Delay Scaler
  PBR                    : TBits_2;                    // [16:17] Baud Rate Prescaler
  PDT                    : TBits_2;                    // [18:19] Delay after Transfer Prescaler
  PASC                   : TBits_2;                    // [20:21] After SCK Delay Prescaler
  PCSSCK                 : TBits_2;                    // [22:23] PCS to SCK Delay Prescaler
  LSBFE                  : TBits_1;                    // [24:24] LBS First
  CPHA                   : TBits_1;                    // [25:25] Clock Phase
  CPOL                   : TBits_1;                    // [26:26] Clock Polarity
  FMSZ                   : TBits_4;                    // [27:30] Frame Size
  DBR                    : TBits_1;                    // [31:31] Double Baud Rate
end;

TSPI0_CTAR_bitbanded = record
  BR                     : array[0..3] of longWord;    // [0:3] Baud Rate Scaler
  DT                     : array[0..3] of longWord;    // [4:7] Delay After Transfer Scaler
  ASC                    : array[0..3] of longWord;    // [8:11] After SCK Delay Scaler
  CSSCK                  : array[0..3] of longWord;    // [12:15] PCS to SCK Delay Scaler
  PBR                    : array[0..1] of longWord;    // [16:17] Baud Rate Prescaler
  PDT                    : array[0..1] of longWord;    // [18:19] Delay after Transfer Prescaler
  PASC                   : array[0..1] of longWord;    // [20:21] After SCK Delay Prescaler
  PCSSCK                 : array[0..1] of longWord;    // [22:23] PCS to SCK Delay Prescaler
  LSBFE                  : longWord;                   // [24:24] LBS First
  CPHA                   : longWord;                   // [25:25] Clock Phase
  CPOL                   : longWord;                   // [26:26] Clock Polarity
  FMSZ                   : array[0..3] of longWord;    // [27:30] Frame Size
  DBR                    : longWord;                   // [31:31] Double Baud Rate
end;

TSPI0_SR_bits = bitpacked record
  POPNXTPTR              : TBits_4;                    // [0:3] Pop Next Pointer
  RXCTR                  : TBits_4;                    // [4:7] RX FIFO Counter
  TXNXTPTR               : TBits_4;                    // [8:11] Transmit Next Pointer
  TXCTR                  : TBits_4;                    // [12:15] TX FIFO Counter
  RESERVED0              : TBits_1;                    // [16:16] no description available
  RFDF                   : TBits_1;                    // [17:17] Receive FIFO Drain Flag
  RESERVED1              : TBits_1;                    // [18:18] no description available
  RFOF                   : TBits_1;                    // [19:19] Receive FIFO Overflow Flag
  RESERVED2              : TBits_1;                    // [20:20] no description available
  RESERVED3              : TBits_1;                    // [21:21] no description available
  RESERVED4              : TBits_1;                    // [22:22] no description available
  RESERVED5              : TBits_1;                    // [23:23] no description available
  RESERVED6              : TBits_1;                    // [24:24] no description available
  TFFF                   : TBits_1;                    // [25:25] Transmit FIFO Fill Flag
  RESERVED7              : TBits_1;                    // [26:26] no description available
  TFUF                   : TBits_1;                    // [27:27] Transmit FIFO Underflow Flag
  EOQF                   : TBits_1;                    // [28:28] End of Queue Flag
  RESERVED8              : TBits_1;                    // [29:29] no description available
  TXRXS                  : TBits_1;                    // [30:30] TX and RX Status
  TCF                    : TBits_1;                    // [31:31] Transfer Complete Flag
end;

TSPI0_SR_bitbanded = record
  POPNXTPTR              : array[0..3] of longWord;    // [0:3] Pop Next Pointer
  RXCTR                  : array[0..3] of longWord;    // [4:7] RX FIFO Counter
  TXNXTPTR               : array[0..3] of longWord;    // [8:11] Transmit Next Pointer
  TXCTR                  : array[0..3] of longWord;    // [12:15] TX FIFO Counter
  RESERVED0              : longWord;                   // [16:16] no description available
  RFDF                   : longWord;                   // [17:17] Receive FIFO Drain Flag
  RESERVED1              : longWord;                   // [18:18] no description available
  RFOF                   : longWord;                   // [19:19] Receive FIFO Overflow Flag
  RESERVED2              : longWord;                   // [20:20] no description available
  RESERVED3              : longWord;                   // [21:21] no description available
  RESERVED4              : longWord;                   // [22:22] no description available
  RESERVED5              : longWord;                   // [23:23] no description available
  RESERVED6              : longWord;                   // [24:24] no description available
  TFFF                   : longWord;                   // [25:25] Transmit FIFO Fill Flag
  RESERVED7              : longWord;                   // [26:26] no description available
  TFUF                   : longWord;                   // [27:27] Transmit FIFO Underflow Flag
  EOQF                   : longWord;                   // [28:28] End of Queue Flag
  RESERVED8              : longWord;                   // [29:29] no description available
  TXRXS                  : longWord;                   // [30:30] TX and RX Status
  TCF                    : longWord;                   // [31:31] Transfer Complete Flag
end;

TSPI0_RSER_bits = bitpacked record
  RESERVED0              : TBits_16;                   // [0:15] no description available
  RFDF_DIRS              : TBits_1;                    // [16:16] Receive FIFO Drain DMA or Interrupt Request Select.
  RFDF_RE                : TBits_1;                    // [17:17] Receive FIFO Drain Request Enable
  RESERVED1              : TBits_1;                    // [18:18] no description available
  RFOF_RE                : TBits_1;                    // [19:19] Receive FIFO Overflow Request Enable
  RESERVED2              : TBits_1;                    // [20:20] no description available
  RESERVED3              : TBits_1;                    // [21:21] no description available
  RESERVED4              : TBits_1;                    // [22:22] no description available
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TFFF_DIRS              : TBits_1;                    // [24:24] Transmit FIFO Fill DMA or Interrupt Request Select
  TFFF_RE                : TBits_1;                    // [25:25] Transmit FIFO Fill Request Enable
  RESERVED6              : TBits_1;                    // [26:26] no description available
  TFUF_RE                : TBits_1;                    // [27:27] Transmit FIFO Underflow Request Enable
  EOQF_RE                : TBits_1;                    // [28:28] DSPI Finished Request Enable
  RESERVED7              : TBits_1;                    // [29:29] no description available
  RESERVED8              : TBits_1;                    // [30:30] no description available
  TCF_RE                 : TBits_1;                    // [31:31] Transmission Complete Request Enable
end;

TSPI0_RSER_bitbanded = record
  RESERVED0              : array[0..15] of longWord;   // [0:15] no description available
  RFDF_DIRS              : longWord;                   // [16:16] Receive FIFO Drain DMA or Interrupt Request Select.
  RFDF_RE                : longWord;                   // [17:17] Receive FIFO Drain Request Enable
  RESERVED1              : longWord;                   // [18:18] no description available
  RFOF_RE                : longWord;                   // [19:19] Receive FIFO Overflow Request Enable
  RESERVED2              : longWord;                   // [20:20] no description available
  RESERVED3              : longWord;                   // [21:21] no description available
  RESERVED4              : longWord;                   // [22:22] no description available
  RESERVED5              : longWord;                   // [23:23] no description available
  TFFF_DIRS              : longWord;                   // [24:24] Transmit FIFO Fill DMA or Interrupt Request Select
  TFFF_RE                : longWord;                   // [25:25] Transmit FIFO Fill Request Enable
  RESERVED6              : longWord;                   // [26:26] no description available
  TFUF_RE                : longWord;                   // [27:27] Transmit FIFO Underflow Request Enable
  EOQF_RE                : longWord;                   // [28:28] DSPI Finished Request Enable
  RESERVED7              : longWord;                   // [29:29] no description available
  RESERVED8              : longWord;                   // [30:30] no description available
  TCF_RE                 : longWord;                   // [31:31] Transmission Complete Request Enable
end;

TSPI0_PUSHR_bits = bitpacked record
  TXDATA                 : TBits_16;                   // [0:15] Transmit Data
  PCS                    : TBits_6;                    // [16:21] no description available
  RESERVED0              : TBits_2;                    // [22:23] no description available
  RESERVED1              : TBits_2;                    // [24:25] no description available
  CTCNT                  : TBits_1;                    // [26:26] Clear Transfer Counter.
  EOQ                    : TBits_1;                    // [27:27] End Of Queue
  CTAS                   : TBits_3;                    // [28:30] Clock and Transfer Attributes Select.
  CONT                   : TBits_1;                    // [31:31] Continuous Peripheral Chip Select Enable
end;

TSPI0_PUSHR_bitbanded = record
  TXDATA                 : array[0..15] of longWord;   // [0:15] Transmit Data
  PCS                    : array[0..5] of longWord;    // [16:21] no description available
  RESERVED0              : array[0..1] of longWord;    // [22:23] no description available
  RESERVED1              : array[0..1] of longWord;    // [24:25] no description available
  CTCNT                  : longWord;                   // [26:26] Clear Transfer Counter.
  EOQ                    : longWord;                   // [27:27] End Of Queue
  CTAS                   : array[0..2] of longWord;    // [28:30] Clock and Transfer Attributes Select.
  CONT                   : longWord;                   // [31:31] Continuous Peripheral Chip Select Enable
end;

TSPI0_PUSHR_SLAVE_bits = bitpacked record
  TXDATA                 : TBits_32;                   // [0:31] Transmit Data
end;

TSPI0_PUSHR_SLAVE_bitbanded = record
  TXDATA                 : array[0..31] of longWord;   // [0:31] Transmit Data
end;

TSPI0_POPR_bits = bitpacked record
  RXDATA                 : TBits_32;                   // [0:31] Received Data
end;

TSPI0_POPR_bitbanded = record
  RXDATA                 : array[0..31] of longWord;   // [0:31] Received Data
end;

TSPI0_TXFR_bits = bitpacked record
  TXDATA                 : TBits_16;                   // [0:15] Transmit Data
  TXCMD_TXDATA           : TBits_16;                   // [16:31] Transmit Command or Transmit Data
end;

TSPI0_TXFR_bitbanded = record
  TXDATA                 : array[0..15] of longWord;   // [0:15] Transmit Data
  TXCMD_TXDATA           : array[0..15] of longWord;   // [16:31] Transmit Command or Transmit Data
end;

TSPI0_RXFR_bits = bitpacked record
  RXDATA                 : TBits_32;                   // [0:31] Receive Data
end;

TSPI0_RXFR_bitbanded = record
  RXDATA                 : array[0..31] of longWord;   // [0:31] Receive Data
end;

TSPI0_Registers = record
  case boolean of false: (
  MCR                    : longWord;                   // 0x00 DSPI Module Configuration Register
  RESERVED0              : longWord;                   // 0x04
  TCR                    : longWord;                   // 0x08 DSPI Transfer Count Register
  CTAR0                  : longWord;                   // 0x0C DSPI Clock and Transfer Attributes Register (In Master Mode)
  CTAR1                  : longWord;                   // 0x10 DSPI Clock and Transfer Attributes Register (In Master Mode)
  RESERVED1              : array[0..5] of longWord;    // 0x14
  SR                     : longWord;                   // 0x2C DSPI Status Register
  RSER                   : longWord;                   // 0x30 DSPI DMA/Interrupt Request Select and Enable Register
  PUSHR_SLAVE            : longWord;                   // 0x34 DSPI PUSH TX FIFO Register In Slave Mode
  POPR                   : longWord;                   // 0x38 DSPI POP RX FIFO Register
  TXFR0                  : longWord;                   // 0x3C DSPI Transmit FIFO Registers
  TXFR1                  : longWord;                   // 0x40 DSPI Transmit FIFO Registers
  TXFR2                  : longWord;                   // 0x44 DSPI Transmit FIFO Registers
  TXFR3                  : longWord;                   // 0x48 DSPI Transmit FIFO Registers
  RESERVED2              : array[0..11] of longWord;   // 0x4C
  RXFR0                  : longWord;                   // 0x7C DSPI Receive FIFO Registers
  RXFR1                  : longWord;                   // 0x80 DSPI Receive FIFO Registers
  RXFR2                  : longWord;                   // 0x84 DSPI Receive FIFO Registers
  RXFR3                  : longWord;                   // 0x88 DSPI Receive FIFO Registers
);
true : (
MCR_bits                 : TSPI0_MCR_bits;             // 0x04 DSPI Module Configuration Register
RESERVED_bits0           : longWord;
TCR_bits                 : TSPI0_TCR_bits;             // 0x0C DSPI Transfer Count Register
CTAR0_bits               : TSPI0_CTAR_bits;            // 0x10 DSPI Clock and Transfer Attributes Register (In Master Mode)
CTAR1_bits               : TSPI0_CTAR_bits;            // 0x14 DSPI Clock and Transfer Attributes Register (In Master Mode)
RESERVED_bits1           : array[0..5] of longWord;
SR_bits                  : TSPI0_SR_bits;              // 0x30 DSPI Status Register
RSER_bits                : TSPI0_RSER_bits;            // 0x34 DSPI DMA/Interrupt Request Select and Enable Register
PUSHR_SLAVE_bits         : TSPI0_PUSHR_SLAVE_bits;     // 0x38 DSPI PUSH TX FIFO Register In Slave Mode
POPR_bits                : TSPI0_POPR_bits;            // 0x3C DSPI POP RX FIFO Register
TXFR0_bits               : TSPI0_TXFR_bits;            // 0x40 DSPI Transmit FIFO Registers
TXFR1_bits               : TSPI0_TXFR_bits;            // 0x44 DSPI Transmit FIFO Registers
TXFR2_bits               : TSPI0_TXFR_bits;            // 0x48 DSPI Transmit FIFO Registers
TXFR3_bits               : TSPI0_TXFR_bits;            // 0x4C DSPI Transmit FIFO Registers
RESERVED_bits2           : array[0..11] of longWord;
RXFR0_bits               : TSPI0_RXFR_bits;            // 0x80 DSPI Receive FIFO Registers
RXFR1_bits               : TSPI0_RXFR_bits;            // 0x84 DSPI Receive FIFO Registers
RXFR2_bits               : TSPI0_RXFR_bits;            // 0x88 DSPI Receive FIFO Registers
RXFR3_bits               : TSPI0_RXFR_bits;            // 0x8C DSPI Receive FIFO Registers
);
end;

TSPI0Registers_bitbanded = record
  MCR                    : TSPI0_MCR_bitbanded;        // 0x04 DSPI Module Configuration Register
  RESERVED0              : array[0..3] of array[0..7] of longWord;
  TCR                    : TSPI0_TCR_bitbanded;        // 0x0C DSPI Transfer Count Register
  CTAR0                  : TSPI0_CTAR_bitbanded;       // 0x10 DSPI Clock and Transfer Attributes Register (In Master Mode)
  CTAR1                  : TSPI0_CTAR_bitbanded;       // 0x14 DSPI Clock and Transfer Attributes Register (In Master Mode)
  RESERVED1              : array[0..23] of array[0..7] of longWord;
  SR                     : TSPI0_SR_bitbanded;         // 0x30 DSPI Status Register
  RSER                   : TSPI0_RSER_bitbanded;       // 0x34 DSPI DMA/Interrupt Request Select and Enable Register
  PUSHR_SLAVE            : TSPI0_PUSHR_SLAVE_bitbanded;// 0x38 DSPI PUSH TX FIFO Register In Slave Mode
  POPR                   : TSPI0_POPR_bitbanded;       // 0x3C DSPI POP RX FIFO Register
  TXFR0                  : TSPI0_TXFR_bitbanded;       // 0x40 DSPI Transmit FIFO Registers
  TXFR1                  : TSPI0_TXFR_bitbanded;       // 0x44 DSPI Transmit FIFO Registers
  TXFR2                  : TSPI0_TXFR_bitbanded;       // 0x48 DSPI Transmit FIFO Registers
  TXFR3                  : TSPI0_TXFR_bitbanded;       // 0x4C DSPI Transmit FIFO Registers
  RESERVED2              : array[0..47] of array[0..7] of longWord;
  RXFR0                  : TSPI0_RXFR_bitbanded;       // 0x80 DSPI Receive FIFO Registers
  RXFR1                  : TSPI0_RXFR_bitbanded;       // 0x84 DSPI Receive FIFO Registers
  RXFR2                  : TSPI0_RXFR_bitbanded;       // 0x88 DSPI Receive FIFO Registers
  RXFR3                  : TSPI0_RXFR_bitbanded;       // 0x8C DSPI Receive FIFO Registers
end;

// Deserial Serial Peripheral Interface
TSPI1_MCR_bits = bitpacked record
  HALT                   : TBits_1;                    // [0:0] Halt
  RESERVED0              : TBits_1;                    // [1:1] no description available
  RESERVED1              : TBits_6;                    // [2:7] no description available
  SMPL_PT                : TBits_2;                    // [8:9] Sample Point
  CLR_RXF                : TBits_1;                    // [10:10] no description available
  CLR_TXF                : TBits_1;                    // [11:11] Clear TX FIFO
  DIS_RXF                : TBits_1;                    // [12:12] Disable Receive FIFO
  DIS_TXF                : TBits_1;                    // [13:13] Disable Transmit FIFO
  MDIS                   : TBits_1;                    // [14:14] Module Disable
  DOZE                   : TBits_1;                    // [15:15] Doze Enable
  PCSIS                  : TBits_6;                    // [16:21] Peripheral Chip Select x Inactive State
  RESERVED2              : TBits_2;                    // [22:23] no description available
  ROOE                   : TBits_1;                    // [24:24] Receive FIFO Overflow Overwrite Enable
  PCSSE                  : TBits_1;                    // [25:25] Peripheral Chip Select Strobe Enable
  MTFE                   : TBits_1;                    // [26:26] Modified Timing Format Enable
  FRZ                    : TBits_1;                    // [27:27] Freeze
  DCONF                  : TBits_2;                    // [28:29] DSPI Configuration
  CONT_SCKE              : TBits_1;                    // [30:30] Continuous SCK Enable
  MSTR                   : TBits_1;                    // [31:31] Master/Slave Mode Select
end;

TSPI1_MCR_bitbanded = record
  HALT                   : longWord;                   // [0:0] Halt
  RESERVED0              : longWord;                   // [1:1] no description available
  RESERVED1              : array[0..5] of longWord;    // [2:7] no description available
  SMPL_PT                : array[0..1] of longWord;    // [8:9] Sample Point
  CLR_RXF                : longWord;                   // [10:10] no description available
  CLR_TXF                : longWord;                   // [11:11] Clear TX FIFO
  DIS_RXF                : longWord;                   // [12:12] Disable Receive FIFO
  DIS_TXF                : longWord;                   // [13:13] Disable Transmit FIFO
  MDIS                   : longWord;                   // [14:14] Module Disable
  DOZE                   : longWord;                   // [15:15] Doze Enable
  PCSIS                  : array[0..5] of longWord;    // [16:21] Peripheral Chip Select x Inactive State
  RESERVED2              : array[0..1] of longWord;    // [22:23] no description available
  ROOE                   : longWord;                   // [24:24] Receive FIFO Overflow Overwrite Enable
  PCSSE                  : longWord;                   // [25:25] Peripheral Chip Select Strobe Enable
  MTFE                   : longWord;                   // [26:26] Modified Timing Format Enable
  FRZ                    : longWord;                   // [27:27] Freeze
  DCONF                  : array[0..1] of longWord;    // [28:29] DSPI Configuration
  CONT_SCKE              : longWord;                   // [30:30] Continuous SCK Enable
  MSTR                   : longWord;                   // [31:31] Master/Slave Mode Select
end;

TSPI1_TCR_bits = bitpacked record
  RESERVED0              : TBits_16;                   // [0:15] no description available
  SPI_TCNT               : TBits_16;                   // [16:31] SPI Transfer Counter
end;

TSPI1_TCR_bitbanded = record
  RESERVED0              : array[0..15] of longWord;   // [0:15] no description available
  SPI_TCNT               : array[0..15] of longWord;   // [16:31] SPI Transfer Counter
end;

TSPI1_CTAR_SLAVE_bits = bitpacked record
  RESERVED0              : TBits_23;                   // [0:22] no description available
  RESERVED1              : TBits_2;                    // [23:24] no description available
  CPHA                   : TBits_1;                    // [25:25] Clock Phase
  CPOL                   : TBits_1;                    // [26:26] Clock Polarity
  FMSZ                   : TBits_5;                    // [27:31] Frame Size
end;

TSPI1_CTAR_SLAVE_bitbanded = record
  RESERVED0              : array[0..22] of longWord;   // [0:22] no description available
  RESERVED1              : array[0..1] of longWord;    // [23:24] no description available
  CPHA                   : longWord;                   // [25:25] Clock Phase
  CPOL                   : longWord;                   // [26:26] Clock Polarity
  FMSZ                   : array[0..4] of longWord;    // [27:31] Frame Size
end;

TSPI1_CTAR_bits = bitpacked record
  BR                     : TBits_4;                    // [0:3] Baud Rate Scaler
  DT                     : TBits_4;                    // [4:7] Delay After Transfer Scaler
  ASC                    : TBits_4;                    // [8:11] After SCK Delay Scaler
  CSSCK                  : TBits_4;                    // [12:15] PCS to SCK Delay Scaler
  PBR                    : TBits_2;                    // [16:17] Baud Rate Prescaler
  PDT                    : TBits_2;                    // [18:19] Delay after Transfer Prescaler
  PASC                   : TBits_2;                    // [20:21] After SCK Delay Prescaler
  PCSSCK                 : TBits_2;                    // [22:23] PCS to SCK Delay Prescaler
  LSBFE                  : TBits_1;                    // [24:24] LBS First
  CPHA                   : TBits_1;                    // [25:25] Clock Phase
  CPOL                   : TBits_1;                    // [26:26] Clock Polarity
  FMSZ                   : TBits_4;                    // [27:30] Frame Size
  DBR                    : TBits_1;                    // [31:31] Double Baud Rate
end;

TSPI1_CTAR_bitbanded = record
  BR                     : array[0..3] of longWord;    // [0:3] Baud Rate Scaler
  DT                     : array[0..3] of longWord;    // [4:7] Delay After Transfer Scaler
  ASC                    : array[0..3] of longWord;    // [8:11] After SCK Delay Scaler
  CSSCK                  : array[0..3] of longWord;    // [12:15] PCS to SCK Delay Scaler
  PBR                    : array[0..1] of longWord;    // [16:17] Baud Rate Prescaler
  PDT                    : array[0..1] of longWord;    // [18:19] Delay after Transfer Prescaler
  PASC                   : array[0..1] of longWord;    // [20:21] After SCK Delay Prescaler
  PCSSCK                 : array[0..1] of longWord;    // [22:23] PCS to SCK Delay Prescaler
  LSBFE                  : longWord;                   // [24:24] LBS First
  CPHA                   : longWord;                   // [25:25] Clock Phase
  CPOL                   : longWord;                   // [26:26] Clock Polarity
  FMSZ                   : array[0..3] of longWord;    // [27:30] Frame Size
  DBR                    : longWord;                   // [31:31] Double Baud Rate
end;

TSPI1_SR_bits = bitpacked record
  POPNXTPTR              : TBits_4;                    // [0:3] Pop Next Pointer
  RXCTR                  : TBits_4;                    // [4:7] RX FIFO Counter
  TXNXTPTR               : TBits_4;                    // [8:11] Transmit Next Pointer
  TXCTR                  : TBits_4;                    // [12:15] TX FIFO Counter
  RESERVED0              : TBits_1;                    // [16:16] no description available
  RFDF                   : TBits_1;                    // [17:17] Receive FIFO Drain Flag
  RESERVED1              : TBits_1;                    // [18:18] no description available
  RFOF                   : TBits_1;                    // [19:19] Receive FIFO Overflow Flag
  RESERVED2              : TBits_1;                    // [20:20] no description available
  RESERVED3              : TBits_1;                    // [21:21] no description available
  RESERVED4              : TBits_1;                    // [22:22] no description available
  RESERVED5              : TBits_1;                    // [23:23] no description available
  RESERVED6              : TBits_1;                    // [24:24] no description available
  TFFF                   : TBits_1;                    // [25:25] Transmit FIFO Fill Flag
  RESERVED7              : TBits_1;                    // [26:26] no description available
  TFUF                   : TBits_1;                    // [27:27] Transmit FIFO Underflow Flag
  EOQF                   : TBits_1;                    // [28:28] End of Queue Flag
  RESERVED8              : TBits_1;                    // [29:29] no description available
  TXRXS                  : TBits_1;                    // [30:30] TX and RX Status
  TCF                    : TBits_1;                    // [31:31] Transfer Complete Flag
end;

TSPI1_SR_bitbanded = record
  POPNXTPTR              : array[0..3] of longWord;    // [0:3] Pop Next Pointer
  RXCTR                  : array[0..3] of longWord;    // [4:7] RX FIFO Counter
  TXNXTPTR               : array[0..3] of longWord;    // [8:11] Transmit Next Pointer
  TXCTR                  : array[0..3] of longWord;    // [12:15] TX FIFO Counter
  RESERVED0              : longWord;                   // [16:16] no description available
  RFDF                   : longWord;                   // [17:17] Receive FIFO Drain Flag
  RESERVED1              : longWord;                   // [18:18] no description available
  RFOF                   : longWord;                   // [19:19] Receive FIFO Overflow Flag
  RESERVED2              : longWord;                   // [20:20] no description available
  RESERVED3              : longWord;                   // [21:21] no description available
  RESERVED4              : longWord;                   // [22:22] no description available
  RESERVED5              : longWord;                   // [23:23] no description available
  RESERVED6              : longWord;                   // [24:24] no description available
  TFFF                   : longWord;                   // [25:25] Transmit FIFO Fill Flag
  RESERVED7              : longWord;                   // [26:26] no description available
  TFUF                   : longWord;                   // [27:27] Transmit FIFO Underflow Flag
  EOQF                   : longWord;                   // [28:28] End of Queue Flag
  RESERVED8              : longWord;                   // [29:29] no description available
  TXRXS                  : longWord;                   // [30:30] TX and RX Status
  TCF                    : longWord;                   // [31:31] Transfer Complete Flag
end;

TSPI1_RSER_bits = bitpacked record
  RESERVED0              : TBits_16;                   // [0:15] no description available
  RFDF_DIRS              : TBits_1;                    // [16:16] Receive FIFO Drain DMA or Interrupt Request Select.
  RFDF_RE                : TBits_1;                    // [17:17] Receive FIFO Drain Request Enable
  RESERVED1              : TBits_1;                    // [18:18] no description available
  RFOF_RE                : TBits_1;                    // [19:19] Receive FIFO Overflow Request Enable
  RESERVED2              : TBits_1;                    // [20:20] no description available
  RESERVED3              : TBits_1;                    // [21:21] no description available
  RESERVED4              : TBits_1;                    // [22:22] no description available
  RESERVED5              : TBits_1;                    // [23:23] no description available
  TFFF_DIRS              : TBits_1;                    // [24:24] Transmit FIFO Fill DMA or Interrupt Request Select
  TFFF_RE                : TBits_1;                    // [25:25] Transmit FIFO Fill Request Enable
  RESERVED6              : TBits_1;                    // [26:26] no description available
  TFUF_RE                : TBits_1;                    // [27:27] Transmit FIFO Underflow Request Enable
  EOQF_RE                : TBits_1;                    // [28:28] DSPI Finished Request Enable
  RESERVED7              : TBits_1;                    // [29:29] no description available
  RESERVED8              : TBits_1;                    // [30:30] no description available
  TCF_RE                 : TBits_1;                    // [31:31] Transmission Complete Request Enable
end;

TSPI1_RSER_bitbanded = record
  RESERVED0              : array[0..15] of longWord;   // [0:15] no description available
  RFDF_DIRS              : longWord;                   // [16:16] Receive FIFO Drain DMA or Interrupt Request Select.
  RFDF_RE                : longWord;                   // [17:17] Receive FIFO Drain Request Enable
  RESERVED1              : longWord;                   // [18:18] no description available
  RFOF_RE                : longWord;                   // [19:19] Receive FIFO Overflow Request Enable
  RESERVED2              : longWord;                   // [20:20] no description available
  RESERVED3              : longWord;                   // [21:21] no description available
  RESERVED4              : longWord;                   // [22:22] no description available
  RESERVED5              : longWord;                   // [23:23] no description available
  TFFF_DIRS              : longWord;                   // [24:24] Transmit FIFO Fill DMA or Interrupt Request Select
  TFFF_RE                : longWord;                   // [25:25] Transmit FIFO Fill Request Enable
  RESERVED6              : longWord;                   // [26:26] no description available
  TFUF_RE                : longWord;                   // [27:27] Transmit FIFO Underflow Request Enable
  EOQF_RE                : longWord;                   // [28:28] DSPI Finished Request Enable
  RESERVED7              : longWord;                   // [29:29] no description available
  RESERVED8              : longWord;                   // [30:30] no description available
  TCF_RE                 : longWord;                   // [31:31] Transmission Complete Request Enable
end;

TSPI1_PUSHR_bits = bitpacked record
  TXDATA                 : TBits_16;                   // [0:15] Transmit Data
  PCS                    : TBits_6;                    // [16:21] no description available
  RESERVED0              : TBits_2;                    // [22:23] no description available
  RESERVED1              : TBits_2;                    // [24:25] no description available
  CTCNT                  : TBits_1;                    // [26:26] Clear Transfer Counter.
  EOQ                    : TBits_1;                    // [27:27] End Of Queue
  CTAS                   : TBits_3;                    // [28:30] Clock and Transfer Attributes Select.
  CONT                   : TBits_1;                    // [31:31] Continuous Peripheral Chip Select Enable
end;

TSPI1_PUSHR_bitbanded = record
  TXDATA                 : array[0..15] of longWord;   // [0:15] Transmit Data
  PCS                    : array[0..5] of longWord;    // [16:21] no description available
  RESERVED0              : array[0..1] of longWord;    // [22:23] no description available
  RESERVED1              : array[0..1] of longWord;    // [24:25] no description available
  CTCNT                  : longWord;                   // [26:26] Clear Transfer Counter.
  EOQ                    : longWord;                   // [27:27] End Of Queue
  CTAS                   : array[0..2] of longWord;    // [28:30] Clock and Transfer Attributes Select.
  CONT                   : longWord;                   // [31:31] Continuous Peripheral Chip Select Enable
end;

TSPI1_PUSHR_SLAVE_bits = bitpacked record
  TXDATA                 : TBits_32;                   // [0:31] Transmit Data
end;

TSPI1_PUSHR_SLAVE_bitbanded = record
  TXDATA                 : array[0..31] of longWord;   // [0:31] Transmit Data
end;

TSPI1_POPR_bits = bitpacked record
  RXDATA                 : TBits_32;                   // [0:31] Received Data
end;

TSPI1_POPR_bitbanded = record
  RXDATA                 : array[0..31] of longWord;   // [0:31] Received Data
end;

TSPI1_TXFR_bits = bitpacked record
  TXDATA                 : TBits_16;                   // [0:15] Transmit Data
  TXCMD_TXDATA           : TBits_16;                   // [16:31] Transmit Command or Transmit Data
end;

TSPI1_TXFR_bitbanded = record
  TXDATA                 : array[0..15] of longWord;   // [0:15] Transmit Data
  TXCMD_TXDATA           : array[0..15] of longWord;   // [16:31] Transmit Command or Transmit Data
end;

TSPI1_RXFR_bits = bitpacked record
  RXDATA                 : TBits_32;                   // [0:31] Receive Data
end;

TSPI1_RXFR_bitbanded = record
  RXDATA                 : array[0..31] of longWord;   // [0:31] Receive Data
end;

TSPI1_Registers = record
  case boolean of false: (
  MCR                    : longWord;                   // 0x00 DSPI Module Configuration Register
  RESERVED0              : longWord;                   // 0x04
  TCR                    : longWord;                   // 0x08 DSPI Transfer Count Register
  CTAR0                  : longWord;                   // 0x0C DSPI Clock and Transfer Attributes Register (In Master Mode)
  CTAR1                  : longWord;                   // 0x10 DSPI Clock and Transfer Attributes Register (In Master Mode)
  RESERVED1              : array[0..5] of longWord;    // 0x14
  SR                     : longWord;                   // 0x2C DSPI Status Register
  RSER                   : longWord;                   // 0x30 DSPI DMA/Interrupt Request Select and Enable Register
  PUSHR_SLAVE            : longWord;                   // 0x34 DSPI PUSH TX FIFO Register In Slave Mode
  POPR                   : longWord;                   // 0x38 DSPI POP RX FIFO Register
  TXFR0                  : longWord;                   // 0x3C DSPI Transmit FIFO Registers
  TXFR1                  : longWord;                   // 0x40 DSPI Transmit FIFO Registers
  TXFR2                  : longWord;                   // 0x44 DSPI Transmit FIFO Registers
  TXFR3                  : longWord;                   // 0x48 DSPI Transmit FIFO Registers
  RESERVED2              : array[0..11] of longWord;   // 0x4C
  RXFR0                  : longWord;                   // 0x7C DSPI Receive FIFO Registers
  RXFR1                  : longWord;                   // 0x80 DSPI Receive FIFO Registers
  RXFR2                  : longWord;                   // 0x84 DSPI Receive FIFO Registers
  RXFR3                  : longWord;                   // 0x88 DSPI Receive FIFO Registers
);
true : (
MCR_bits                 : TSPI1_MCR_bits;             // 0x04 DSPI Module Configuration Register
RESERVED_bits0           : longWord;
TCR_bits                 : TSPI1_TCR_bits;             // 0x0C DSPI Transfer Count Register
CTAR0_bits               : TSPI1_CTAR_bits;            // 0x10 DSPI Clock and Transfer Attributes Register (In Master Mode)
CTAR1_bits               : TSPI1_CTAR_bits;            // 0x14 DSPI Clock and Transfer Attributes Register (In Master Mode)
RESERVED_bits1           : array[0..5] of longWord;
SR_bits                  : TSPI1_SR_bits;              // 0x30 DSPI Status Register
RSER_bits                : TSPI1_RSER_bits;            // 0x34 DSPI DMA/Interrupt Request Select and Enable Register
PUSHR_SLAVE_bits         : TSPI1_PUSHR_SLAVE_bits;     // 0x38 DSPI PUSH TX FIFO Register In Slave Mode
POPR_bits                : TSPI1_POPR_bits;            // 0x3C DSPI POP RX FIFO Register
TXFR0_bits               : TSPI1_TXFR_bits;            // 0x40 DSPI Transmit FIFO Registers
TXFR1_bits               : TSPI1_TXFR_bits;            // 0x44 DSPI Transmit FIFO Registers
TXFR2_bits               : TSPI1_TXFR_bits;            // 0x48 DSPI Transmit FIFO Registers
TXFR3_bits               : TSPI1_TXFR_bits;            // 0x4C DSPI Transmit FIFO Registers
RESERVED_bits2           : array[0..11] of longWord;
RXFR0_bits               : TSPI1_RXFR_bits;            // 0x80 DSPI Receive FIFO Registers
RXFR1_bits               : TSPI1_RXFR_bits;            // 0x84 DSPI Receive FIFO Registers
RXFR2_bits               : TSPI1_RXFR_bits;            // 0x88 DSPI Receive FIFO Registers
RXFR3_bits               : TSPI1_RXFR_bits;            // 0x8C DSPI Receive FIFO Registers
);
end;

TSPI1Registers_bitbanded = record
  MCR                    : TSPI1_MCR_bitbanded;        // 0x04 DSPI Module Configuration Register
  RESERVED0              : array[0..3] of array[0..7] of longWord;
  TCR                    : TSPI1_TCR_bitbanded;        // 0x0C DSPI Transfer Count Register
  CTAR0                  : TSPI1_CTAR_bitbanded;       // 0x10 DSPI Clock and Transfer Attributes Register (In Master Mode)
  CTAR1                  : TSPI1_CTAR_bitbanded;       // 0x14 DSPI Clock and Transfer Attributes Register (In Master Mode)
  RESERVED1              : array[0..23] of array[0..7] of longWord;
  SR                     : TSPI1_SR_bitbanded;         // 0x30 DSPI Status Register
  RSER                   : TSPI1_RSER_bitbanded;       // 0x34 DSPI DMA/Interrupt Request Select and Enable Register
  PUSHR_SLAVE            : TSPI1_PUSHR_SLAVE_bitbanded;// 0x38 DSPI PUSH TX FIFO Register In Slave Mode
  POPR                   : TSPI1_POPR_bitbanded;       // 0x3C DSPI POP RX FIFO Register
  TXFR0                  : TSPI1_TXFR_bitbanded;       // 0x40 DSPI Transmit FIFO Registers
  TXFR1                  : TSPI1_TXFR_bitbanded;       // 0x44 DSPI Transmit FIFO Registers
  TXFR2                  : TSPI1_TXFR_bitbanded;       // 0x48 DSPI Transmit FIFO Registers
  TXFR3                  : TSPI1_TXFR_bitbanded;       // 0x4C DSPI Transmit FIFO Registers
  RESERVED2              : array[0..47] of array[0..7] of longWord;
  RXFR0                  : TSPI1_RXFR_bitbanded;       // 0x80 DSPI Receive FIFO Registers
  RXFR1                  : TSPI1_RXFR_bitbanded;       // 0x84 DSPI Receive FIFO Registers
  RXFR2                  : TSPI1_RXFR_bitbanded;       // 0x88 DSPI Receive FIFO Registers
  RXFR3                  : TSPI1_RXFR_bitbanded;       // 0x8C DSPI Receive FIFO Registers
end;

// System timer
TSysTick_CSR_bits = bitpacked record
  ENABLE                 : TBits_1;                    // [0:0] no description available
  TICKINT                : TBits_1;                    // [1:1] no description available
  CLKSOURCE              : TBits_1;                    // [2:2] no description available
  RESERVED0              : TBits_1;                    // [3:3] no description available
  RESERVED1              : TBits_1;                    // [4:4] no description available
  RESERVED2              : TBits_1;                    // [5:5] no description available
  RESERVED3              : TBits_1;                    // [6:6] no description available
  RESERVED4              : TBits_1;                    // [7:7] no description available
  RESERVED5              : TBits_1;                    // [8:8] no description available
  RESERVED6              : TBits_1;                    // [9:9] no description available
  RESERVED7              : TBits_1;                    // [10:10] no description available
  RESERVED8              : TBits_1;                    // [11:11] no description available
  RESERVED9              : TBits_1;                    // [12:12] no description available
  RESERVED10             : TBits_1;                    // [13:13] no description available
  RESERVED11             : TBits_1;                    // [14:14] no description available
  RESERVED12             : TBits_1;                    // [15:15] no description available
  COUNTFLAG              : TBits_1;                    // [16:16] no description available
  RESERVED13             : TBits_1;                    // [17:17] no description available
  RESERVED14             : TBits_1;                    // [18:18] no description available
  RESERVED15             : TBits_1;                    // [19:19] no description available
  RESERVED16             : TBits_1;                    // [20:20] no description available
  RESERVED17             : TBits_1;                    // [21:21] no description available
  RESERVED18             : TBits_1;                    // [22:22] no description available
  RESERVED19             : TBits_1;                    // [23:23] no description available
  RESERVED20             : TBits_1;                    // [24:24] no description available
  RESERVED21             : TBits_1;                    // [25:25] no description available
  RESERVED22             : TBits_1;                    // [26:26] no description available
  RESERVED23             : TBits_1;                    // [27:27] no description available
  RESERVED24             : TBits_1;                    // [28:28] no description available
  RESERVED25             : TBits_1;                    // [29:29] no description available
  RESERVED26             : TBits_1;                    // [30:30] no description available
  RESERVED27             : TBits_1;                    // [31:31] no description available
end;

TSysTick_CSR_bitbanded = record
  ENABLE                 : longWord;                   // [0:0] no description available
  TICKINT                : longWord;                   // [1:1] no description available
  CLKSOURCE              : longWord;                   // [2:2] no description available
  RESERVED0              : longWord;                   // [3:3] no description available
  RESERVED1              : longWord;                   // [4:4] no description available
  RESERVED2              : longWord;                   // [5:5] no description available
  RESERVED3              : longWord;                   // [6:6] no description available
  RESERVED4              : longWord;                   // [7:7] no description available
  RESERVED5              : longWord;                   // [8:8] no description available
  RESERVED6              : longWord;                   // [9:9] no description available
  RESERVED7              : longWord;                   // [10:10] no description available
  RESERVED8              : longWord;                   // [11:11] no description available
  RESERVED9              : longWord;                   // [12:12] no description available
  RESERVED10             : longWord;                   // [13:13] no description available
  RESERVED11             : longWord;                   // [14:14] no description available
  RESERVED12             : longWord;                   // [15:15] no description available
  COUNTFLAG              : longWord;                   // [16:16] no description available
  RESERVED13             : longWord;                   // [17:17] no description available
  RESERVED14             : longWord;                   // [18:18] no description available
  RESERVED15             : longWord;                   // [19:19] no description available
  RESERVED16             : longWord;                   // [20:20] no description available
  RESERVED17             : longWord;                   // [21:21] no description available
  RESERVED18             : longWord;                   // [22:22] no description available
  RESERVED19             : longWord;                   // [23:23] no description available
  RESERVED20             : longWord;                   // [24:24] no description available
  RESERVED21             : longWord;                   // [25:25] no description available
  RESERVED22             : longWord;                   // [26:26] no description available
  RESERVED23             : longWord;                   // [27:27] no description available
  RESERVED24             : longWord;                   // [28:28] no description available
  RESERVED25             : longWord;                   // [29:29] no description available
  RESERVED26             : longWord;                   // [30:30] no description available
  RESERVED27             : longWord;                   // [31:31] no description available
end;

TSysTick_RVR_bits = bitpacked record
  RELOAD                 : TBits_24;                   // [0:23] Value to load into the SysTick Current Value Register when the counter reaches 0
  RESERVED0              : TBits_1;                    // [24:24] no description available
  RESERVED1              : TBits_1;                    // [25:25] no description available
  RESERVED2              : TBits_1;                    // [26:26] no description available
  RESERVED3              : TBits_1;                    // [27:27] no description available
  RESERVED4              : TBits_1;                    // [28:28] no description available
  RESERVED5              : TBits_1;                    // [29:29] no description available
  RESERVED6              : TBits_1;                    // [30:30] no description available
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TSysTick_RVR_bitbanded = record
  RELOAD                 : array[0..23] of longWord;   // [0:23] Value to load into the SysTick Current Value Register when the counter reaches 0
  RESERVED0              : longWord;                   // [24:24] no description available
  RESERVED1              : longWord;                   // [25:25] no description available
  RESERVED2              : longWord;                   // [26:26] no description available
  RESERVED3              : longWord;                   // [27:27] no description available
  RESERVED4              : longWord;                   // [28:28] no description available
  RESERVED5              : longWord;                   // [29:29] no description available
  RESERVED6              : longWord;                   // [30:30] no description available
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TSysTick_CVR_bits = bitpacked record
  CURRENT                : TBits_24;                   // [0:23] Current value at the time the register is accessed
  RESERVED0              : TBits_1;                    // [24:24] no description available
  RESERVED1              : TBits_1;                    // [25:25] no description available
  RESERVED2              : TBits_1;                    // [26:26] no description available
  RESERVED3              : TBits_1;                    // [27:27] no description available
  RESERVED4              : TBits_1;                    // [28:28] no description available
  RESERVED5              : TBits_1;                    // [29:29] no description available
  RESERVED6              : TBits_1;                    // [30:30] no description available
  RESERVED7              : TBits_1;                    // [31:31] no description available
end;

TSysTick_CVR_bitbanded = record
  CURRENT                : array[0..23] of longWord;   // [0:23] Current value at the time the register is accessed
  RESERVED0              : longWord;                   // [24:24] no description available
  RESERVED1              : longWord;                   // [25:25] no description available
  RESERVED2              : longWord;                   // [26:26] no description available
  RESERVED3              : longWord;                   // [27:27] no description available
  RESERVED4              : longWord;                   // [28:28] no description available
  RESERVED5              : longWord;                   // [29:29] no description available
  RESERVED6              : longWord;                   // [30:30] no description available
  RESERVED7              : longWord;                   // [31:31] no description available
end;

TSysTick_CALIB_bits = bitpacked record
  TENMS                  : TBits_24;                   // [0:23] Reload value to use for 10ms timing
  RESERVED0              : TBits_1;                    // [24:24] no description available
  RESERVED1              : TBits_1;                    // [25:25] no description available
  RESERVED2              : TBits_1;                    // [26:26] no description available
  RESERVED3              : TBits_1;                    // [27:27] no description available
  RESERVED4              : TBits_1;                    // [28:28] no description available
  RESERVED5              : TBits_1;                    // [29:29] no description available
  SKEW                   : TBits_1;                    // [30:30] no description available
  NOREF                  : TBits_1;                    // [31:31] no description available
end;

TSysTick_CALIB_bitbanded = record
  TENMS                  : array[0..23] of longWord;   // [0:23] Reload value to use for 10ms timing
  RESERVED0              : longWord;                   // [24:24] no description available
  RESERVED1              : longWord;                   // [25:25] no description available
  RESERVED2              : longWord;                   // [26:26] no description available
  RESERVED3              : longWord;                   // [27:27] no description available
  RESERVED4              : longWord;                   // [28:28] no description available
  RESERVED5              : longWord;                   // [29:29] no description available
  SKEW                   : longWord;                   // [30:30] no description available
  NOREF                  : longWord;                   // [31:31] no description available
end;

TSysTick_Registers = record
  case boolean of false: (
  CSR                    : longWord;                   // 0x00 SysTick Control and Status Register
  RVR                    : longWord;                   // 0x04 SysTick Reload Value Register
  CVR                    : longWord;                   // 0x08 SysTick Current Value Register
  CALIB                  : longWord;                   // 0x0C SysTick Calibration Value Register
);
true : (
CSR_bits                 : TSysTick_CSR_bits;          // 0x04 SysTick Control and Status Register
RVR_bits                 : TSysTick_RVR_bits;          // 0x08 SysTick Reload Value Register
CVR_bits                 : TSysTick_CVR_bits;          // 0x0C SysTick Current Value Register
CALIB_bits               : TSysTick_CALIB_bits;        // 0x10 SysTick Calibration Value Register
);
end;

TSysTickRegisters_bitbanded = record
  CSR                    : TSysTick_CSR_bitbanded;     // 0x04 SysTick Control and Status Register
  RVR                    : TSysTick_RVR_bitbanded;     // 0x08 SysTick Reload Value Register
  CVR                    : TSysTick_CVR_bitbanded;     // 0x0C SysTick Current Value Register
  CALIB                  : TSysTick_CALIB_bitbanded;   // 0x10 SysTick Calibration Value Register
end;

// System Control Registers
TSystemControl_ACTLR_bits = bitpacked record
  DISMCYCINT             : TBits_1;                    // [0:0] Disables interruption of multi-cycle instructions.
  DISDEFWBUF             : TBits_1;                    // [1:1] Disables write buffer use during default memory map accesses.
  DISFOLD                : TBits_1;                    // [2:2] Disables folding of IT instructions.
  RESERVED0              : TBits_1;                    // [3:3] Reserved
  RESERVED1              : TBits_1;                    // [4:4] Reserved
  RESERVED2              : TBits_1;                    // [5:5] Reserved
  RESERVED3              : TBits_1;                    // [6:6] Reserved
  RESERVED4              : TBits_1;                    // [7:7] Reserved
  RESERVED5              : TBits_1;                    // [8:8] Reserved
  RESERVED6              : TBits_1;                    // [9:9] Reserved
  RESERVED7              : TBits_1;                    // [10:10] Reserved
  RESERVED8              : TBits_1;                    // [11:11] Reserved
  RESERVED9              : TBits_1;                    // [12:12] Reserved
  RESERVED10             : TBits_1;                    // [13:13] Reserved
  RESERVED11             : TBits_1;                    // [14:14] Reserved
  RESERVED12             : TBits_1;                    // [15:15] Reserved
  RESERVED13             : TBits_1;                    // [16:16] Reserved
  RESERVED14             : TBits_1;                    // [17:17] Reserved
  RESERVED15             : TBits_1;                    // [18:18] Reserved
  RESERVED16             : TBits_1;                    // [19:19] Reserved
  RESERVED17             : TBits_1;                    // [20:20] Reserved
  RESERVED18             : TBits_1;                    // [21:21] Reserved
  RESERVED19             : TBits_1;                    // [22:22] Reserved
  RESERVED20             : TBits_1;                    // [23:23] Reserved
  RESERVED21             : TBits_1;                    // [24:24] Reserved
  RESERVED22             : TBits_1;                    // [25:25] Reserved
  RESERVED23             : TBits_1;                    // [26:26] Reserved
  RESERVED24             : TBits_1;                    // [27:27] Reserved
  RESERVED25             : TBits_1;                    // [28:28] Reserved
  RESERVED26             : TBits_1;                    // [29:29] Reserved
  RESERVED27             : TBits_1;                    // [30:30] Reserved
  RESERVED28             : TBits_1;                    // [31:31] Reserved
end;

TSystemControl_ACTLR_bitbanded = record
  DISMCYCINT             : longWord;                   // [0:0] Disables interruption of multi-cycle instructions.
  DISDEFWBUF             : longWord;                   // [1:1] Disables write buffer use during default memory map accesses.
  DISFOLD                : longWord;                   // [2:2] Disables folding of IT instructions.
  RESERVED0              : longWord;                   // [3:3] Reserved
  RESERVED1              : longWord;                   // [4:4] Reserved
  RESERVED2              : longWord;                   // [5:5] Reserved
  RESERVED3              : longWord;                   // [6:6] Reserved
  RESERVED4              : longWord;                   // [7:7] Reserved
  RESERVED5              : longWord;                   // [8:8] Reserved
  RESERVED6              : longWord;                   // [9:9] Reserved
  RESERVED7              : longWord;                   // [10:10] Reserved
  RESERVED8              : longWord;                   // [11:11] Reserved
  RESERVED9              : longWord;                   // [12:12] Reserved
  RESERVED10             : longWord;                   // [13:13] Reserved
  RESERVED11             : longWord;                   // [14:14] Reserved
  RESERVED12             : longWord;                   // [15:15] Reserved
  RESERVED13             : longWord;                   // [16:16] Reserved
  RESERVED14             : longWord;                   // [17:17] Reserved
  RESERVED15             : longWord;                   // [18:18] Reserved
  RESERVED16             : longWord;                   // [19:19] Reserved
  RESERVED17             : longWord;                   // [20:20] Reserved
  RESERVED18             : longWord;                   // [21:21] Reserved
  RESERVED19             : longWord;                   // [22:22] Reserved
  RESERVED20             : longWord;                   // [23:23] Reserved
  RESERVED21             : longWord;                   // [24:24] Reserved
  RESERVED22             : longWord;                   // [25:25] Reserved
  RESERVED23             : longWord;                   // [26:26] Reserved
  RESERVED24             : longWord;                   // [27:27] Reserved
  RESERVED25             : longWord;                   // [28:28] Reserved
  RESERVED26             : longWord;                   // [29:29] Reserved
  RESERVED27             : longWord;                   // [30:30] Reserved
  RESERVED28             : longWord;                   // [31:31] Reserved
end;

TSystemControl_CPUID_bits = bitpacked record
  REVISION               : TBits_4;                    // [0:3] Indicates patch release: 0x0 = Patch 0
  PARTNO                 : TBits_12;                   // [4:15] Indicates part number
  RESERVED0              : TBits_1;                    // [16:16] (Constant) Reads as 1
  RESERVED1              : TBits_1;                    // [17:17] (Constant) Reads as 1
  RESERVED2              : TBits_1;                    // [18:18] (Constant) Reads as 1
  RESERVED3              : TBits_1;                    // [19:19] (Constant) Reads as 1
  VARIANT                : TBits_4;                    // [20:23] Indicates processor revision: 0x2 = Revision 2
  IMPLEMENTER            : TBits_8;                    // [24:31] Implementer code
end;

TSystemControl_CPUID_bitbanded = record
  REVISION               : array[0..3] of longWord;    // [0:3] Indicates patch release: 0x0 = Patch 0
  PARTNO                 : array[0..11] of longWord;   // [4:15] Indicates part number
  RESERVED0              : longWord;                   // [16:16] (Constant) Reads as 1
  RESERVED1              : longWord;                   // [17:17] (Constant) Reads as 1
  RESERVED2              : longWord;                   // [18:18] (Constant) Reads as 1
  RESERVED3              : longWord;                   // [19:19] (Constant) Reads as 1
  VARIANT                : array[0..3] of longWord;    // [20:23] Indicates processor revision: 0x2 = Revision 2
  IMPLEMENTER            : array[0..7] of longWord;    // [24:31] Implementer code
end;

TSystemControl_ICSR_bits = bitpacked record
  VECTACTIVE             : TBits_9;                    // [0:8] Active exception number
  RESERVED0              : TBits_1;                    // [9:9] Reserved
  RESERVED1              : TBits_1;                    // [10:10] Reserved
  RETTOBASE              : TBits_1;                    // [11:11] no description available
  VECTPENDING            : TBits_6;                    // [12:17] Exception number of the highest priority pending enabled exception
  RESERVED2              : TBits_1;                    // [18:18] Reserved
  RESERVED3              : TBits_1;                    // [19:19] Reserved
  RESERVED4              : TBits_1;                    // [20:20] Reserved
  RESERVED5              : TBits_1;                    // [21:21] Reserved
  ISRPENDING             : TBits_1;                    // [22:22] no description available
  ISRPREEMPT             : TBits_1;                    // [23:23] no description available
  RESERVED6              : TBits_1;                    // [24:24] Reserved
  PENDSTCLR              : TBits_1;                    // [25:25] no description available
  PENDSTSET              : TBits_1;                    // [26:26] no description available
  PENDSVCLR              : TBits_1;                    // [27:27] no description available
  PENDSVSET              : TBits_1;                    // [28:28] no description available
  RESERVED7              : TBits_1;                    // [29:29] Reserved
  RESERVED8              : TBits_1;                    // [30:30] Reserved
  NMIPENDSET             : TBits_1;                    // [31:31] no description available
end;

TSystemControl_ICSR_bitbanded = record
  VECTACTIVE             : array[0..8] of longWord;    // [0:8] Active exception number
  RESERVED0              : longWord;                   // [9:9] Reserved
  RESERVED1              : longWord;                   // [10:10] Reserved
  RETTOBASE              : longWord;                   // [11:11] no description available
  VECTPENDING            : array[0..5] of longWord;    // [12:17] Exception number of the highest priority pending enabled exception
  RESERVED2              : longWord;                   // [18:18] Reserved
  RESERVED3              : longWord;                   // [19:19] Reserved
  RESERVED4              : longWord;                   // [20:20] Reserved
  RESERVED5              : longWord;                   // [21:21] Reserved
  ISRPENDING             : longWord;                   // [22:22] no description available
  ISRPREEMPT             : longWord;                   // [23:23] no description available
  RESERVED6              : longWord;                   // [24:24] Reserved
  PENDSTCLR              : longWord;                   // [25:25] no description available
  PENDSTSET              : longWord;                   // [26:26] no description available
  PENDSVCLR              : longWord;                   // [27:27] no description available
  PENDSVSET              : longWord;                   // [28:28] no description available
  RESERVED7              : longWord;                   // [29:29] Reserved
  RESERVED8              : longWord;                   // [30:30] Reserved
  NMIPENDSET             : longWord;                   // [31:31] no description available
end;

TSystemControl_VTOR_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] Reserved
  RESERVED1              : TBits_1;                    // [1:1] Reserved
  RESERVED2              : TBits_1;                    // [2:2] Reserved
  RESERVED3              : TBits_1;                    // [3:3] Reserved
  RESERVED4              : TBits_1;                    // [4:4] Reserved
  RESERVED5              : TBits_1;                    // [5:5] Reserved
  RESERVED6              : TBits_1;                    // [6:6] Reserved
  TBLOFF                 : TBits_25;                   // [7:31] Vector table base offset
end;

TSystemControl_VTOR_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] Reserved
  RESERVED1              : longWord;                   // [1:1] Reserved
  RESERVED2              : longWord;                   // [2:2] Reserved
  RESERVED3              : longWord;                   // [3:3] Reserved
  RESERVED4              : longWord;                   // [4:4] Reserved
  RESERVED5              : longWord;                   // [5:5] Reserved
  RESERVED6              : longWord;                   // [6:6] Reserved
  TBLOFF                 : array[0..24] of longWord;   // [7:31] Vector table base offset
end;

TSystemControl_AIRCR_bits = bitpacked record
  VECTRESET              : TBits_1;                    // [0:0] no description available
  VECTCLRACTIVE          : TBits_1;                    // [1:1] no description available
  SYSRESETREQ            : TBits_1;                    // [2:2] no description available
  RESERVED0              : TBits_1;                    // [3:3] Reserved
  RESERVED1              : TBits_1;                    // [4:4] Reserved
  RESERVED2              : TBits_1;                    // [5:5] Reserved
  RESERVED3              : TBits_1;                    // [6:6] Reserved
  RESERVED4              : TBits_1;                    // [7:7] Reserved
  PRIGROUP               : TBits_3;                    // [8:10] Interrupt priority grouping field. This field determines the split of group priority from subpriority.
  RESERVED5              : TBits_1;                    // [11:11] Reserved
  RESERVED6              : TBits_1;                    // [12:12] Reserved
  RESERVED7              : TBits_1;                    // [13:13] Reserved
  RESERVED8              : TBits_1;                    // [14:14] Reserved
  ENDIANNESS             : TBits_1;                    // [15:15] no description available
  VECTKEY                : TBits_16;                   // [16:31] Register key
end;

TSystemControl_AIRCR_bitbanded = record
  VECTRESET              : longWord;                   // [0:0] no description available
  VECTCLRACTIVE          : longWord;                   // [1:1] no description available
  SYSRESETREQ            : longWord;                   // [2:2] no description available
  RESERVED0              : longWord;                   // [3:3] Reserved
  RESERVED1              : longWord;                   // [4:4] Reserved
  RESERVED2              : longWord;                   // [5:5] Reserved
  RESERVED3              : longWord;                   // [6:6] Reserved
  RESERVED4              : longWord;                   // [7:7] Reserved
  PRIGROUP               : array[0..2] of longWord;    // [8:10] Interrupt priority grouping field. This field determines the split of group priority from subpriority.
  RESERVED5              : longWord;                   // [11:11] Reserved
  RESERVED6              : longWord;                   // [12:12] Reserved
  RESERVED7              : longWord;                   // [13:13] Reserved
  RESERVED8              : longWord;                   // [14:14] Reserved
  ENDIANNESS             : longWord;                   // [15:15] no description available
  VECTKEY                : array[0..15] of longWord;   // [16:31] Register key
end;

TSystemControl_SCR_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] Reserved
  SLEEPONEXIT            : TBits_1;                    // [1:1] no description available
  SLEEPDEEP              : TBits_1;                    // [2:2] no description available
  RESERVED1              : TBits_1;                    // [3:3] Reserved
  SEVONPEND              : TBits_1;                    // [4:4] no description available
  RESERVED2              : TBits_1;                    // [5:5] Reserved
  RESERVED3              : TBits_1;                    // [6:6] Reserved
  RESERVED4              : TBits_1;                    // [7:7] Reserved
  RESERVED5              : TBits_1;                    // [8:8] Reserved
  RESERVED6              : TBits_1;                    // [9:9] Reserved
  RESERVED7              : TBits_1;                    // [10:10] Reserved
  RESERVED8              : TBits_1;                    // [11:11] Reserved
  RESERVED9              : TBits_1;                    // [12:12] Reserved
  RESERVED10             : TBits_1;                    // [13:13] Reserved
  RESERVED11             : TBits_1;                    // [14:14] Reserved
  RESERVED12             : TBits_1;                    // [15:15] Reserved
  RESERVED13             : TBits_1;                    // [16:16] Reserved
  RESERVED14             : TBits_1;                    // [17:17] Reserved
  RESERVED15             : TBits_1;                    // [18:18] Reserved
  RESERVED16             : TBits_1;                    // [19:19] Reserved
  RESERVED17             : TBits_1;                    // [20:20] Reserved
  RESERVED18             : TBits_1;                    // [21:21] Reserved
  RESERVED19             : TBits_1;                    // [22:22] Reserved
  RESERVED20             : TBits_1;                    // [23:23] Reserved
  RESERVED21             : TBits_1;                    // [24:24] Reserved
  RESERVED22             : TBits_1;                    // [25:25] Reserved
  RESERVED23             : TBits_1;                    // [26:26] Reserved
  RESERVED24             : TBits_1;                    // [27:27] Reserved
  RESERVED25             : TBits_1;                    // [28:28] Reserved
  RESERVED26             : TBits_1;                    // [29:29] Reserved
  RESERVED27             : TBits_1;                    // [30:30] Reserved
  RESERVED28             : TBits_1;                    // [31:31] Reserved
end;

TSystemControl_SCR_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] Reserved
  SLEEPONEXIT            : longWord;                   // [1:1] no description available
  SLEEPDEEP              : longWord;                   // [2:2] no description available
  RESERVED1              : longWord;                   // [3:3] Reserved
  SEVONPEND              : longWord;                   // [4:4] no description available
  RESERVED2              : longWord;                   // [5:5] Reserved
  RESERVED3              : longWord;                   // [6:6] Reserved
  RESERVED4              : longWord;                   // [7:7] Reserved
  RESERVED5              : longWord;                   // [8:8] Reserved
  RESERVED6              : longWord;                   // [9:9] Reserved
  RESERVED7              : longWord;                   // [10:10] Reserved
  RESERVED8              : longWord;                   // [11:11] Reserved
  RESERVED9              : longWord;                   // [12:12] Reserved
  RESERVED10             : longWord;                   // [13:13] Reserved
  RESERVED11             : longWord;                   // [14:14] Reserved
  RESERVED12             : longWord;                   // [15:15] Reserved
  RESERVED13             : longWord;                   // [16:16] Reserved
  RESERVED14             : longWord;                   // [17:17] Reserved
  RESERVED15             : longWord;                   // [18:18] Reserved
  RESERVED16             : longWord;                   // [19:19] Reserved
  RESERVED17             : longWord;                   // [20:20] Reserved
  RESERVED18             : longWord;                   // [21:21] Reserved
  RESERVED19             : longWord;                   // [22:22] Reserved
  RESERVED20             : longWord;                   // [23:23] Reserved
  RESERVED21             : longWord;                   // [24:24] Reserved
  RESERVED22             : longWord;                   // [25:25] Reserved
  RESERVED23             : longWord;                   // [26:26] Reserved
  RESERVED24             : longWord;                   // [27:27] Reserved
  RESERVED25             : longWord;                   // [28:28] Reserved
  RESERVED26             : longWord;                   // [29:29] Reserved
  RESERVED27             : longWord;                   // [30:30] Reserved
  RESERVED28             : longWord;                   // [31:31] Reserved
end;

TSystemControl_CCR_bits = bitpacked record
  NONBASETHRDENA         : TBits_1;                    // [0:0] no description available
  USERSETMPEND           : TBits_1;                    // [1:1] Enables unprivileged software access to the STIR
  RESERVED0              : TBits_1;                    // [2:2] Reserved
  UNALIGN_TRP            : TBits_1;                    // [3:3] Enables unaligned access traps
  DIV_0_TRP              : TBits_1;                    // [4:4] Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0
  RESERVED1              : TBits_1;                    // [5:5] Reserved
  RESERVED2              : TBits_1;                    // [6:6] Reserved
  RESERVED3              : TBits_1;                    // [7:7] Reserved
  BFHFNMIGN              : TBits_1;                    // [8:8] Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.
  STKALIGN               : TBits_1;                    // [9:9] Indicates stack alignment on exception entry
  RESERVED4              : TBits_1;                    // [10:10] Reserved
  RESERVED5              : TBits_1;                    // [11:11] Reserved
  RESERVED6              : TBits_1;                    // [12:12] Reserved
  RESERVED7              : TBits_1;                    // [13:13] Reserved
  RESERVED8              : TBits_1;                    // [14:14] Reserved
  RESERVED9              : TBits_1;                    // [15:15] Reserved
  RESERVED10             : TBits_1;                    // [16:16] Reserved
  RESERVED11             : TBits_1;                    // [17:17] Reserved
  RESERVED12             : TBits_1;                    // [18:18] Reserved
  RESERVED13             : TBits_1;                    // [19:19] Reserved
  RESERVED14             : TBits_1;                    // [20:20] Reserved
  RESERVED15             : TBits_1;                    // [21:21] Reserved
  RESERVED16             : TBits_1;                    // [22:22] Reserved
  RESERVED17             : TBits_1;                    // [23:23] Reserved
  RESERVED18             : TBits_1;                    // [24:24] Reserved
  RESERVED19             : TBits_1;                    // [25:25] Reserved
  RESERVED20             : TBits_1;                    // [26:26] Reserved
  RESERVED21             : TBits_1;                    // [27:27] Reserved
  RESERVED22             : TBits_1;                    // [28:28] Reserved
  RESERVED23             : TBits_1;                    // [29:29] Reserved
  RESERVED24             : TBits_1;                    // [30:30] Reserved
  RESERVED25             : TBits_1;                    // [31:31] Reserved
end;

TSystemControl_CCR_bitbanded = record
  NONBASETHRDENA         : longWord;                   // [0:0] no description available
  USERSETMPEND           : longWord;                   // [1:1] Enables unprivileged software access to the STIR
  RESERVED0              : longWord;                   // [2:2] Reserved
  UNALIGN_TRP            : longWord;                   // [3:3] Enables unaligned access traps
  DIV_0_TRP              : longWord;                   // [4:4] Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0
  RESERVED1              : longWord;                   // [5:5] Reserved
  RESERVED2              : longWord;                   // [6:6] Reserved
  RESERVED3              : longWord;                   // [7:7] Reserved
  BFHFNMIGN              : longWord;                   // [8:8] Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.
  STKALIGN               : longWord;                   // [9:9] Indicates stack alignment on exception entry
  RESERVED4              : longWord;                   // [10:10] Reserved
  RESERVED5              : longWord;                   // [11:11] Reserved
  RESERVED6              : longWord;                   // [12:12] Reserved
  RESERVED7              : longWord;                   // [13:13] Reserved
  RESERVED8              : longWord;                   // [14:14] Reserved
  RESERVED9              : longWord;                   // [15:15] Reserved
  RESERVED10             : longWord;                   // [16:16] Reserved
  RESERVED11             : longWord;                   // [17:17] Reserved
  RESERVED12             : longWord;                   // [18:18] Reserved
  RESERVED13             : longWord;                   // [19:19] Reserved
  RESERVED14             : longWord;                   // [20:20] Reserved
  RESERVED15             : longWord;                   // [21:21] Reserved
  RESERVED16             : longWord;                   // [22:22] Reserved
  RESERVED17             : longWord;                   // [23:23] Reserved
  RESERVED18             : longWord;                   // [24:24] Reserved
  RESERVED19             : longWord;                   // [25:25] Reserved
  RESERVED20             : longWord;                   // [26:26] Reserved
  RESERVED21             : longWord;                   // [27:27] Reserved
  RESERVED22             : longWord;                   // [28:28] Reserved
  RESERVED23             : longWord;                   // [29:29] Reserved
  RESERVED24             : longWord;                   // [30:30] Reserved
  RESERVED25             : longWord;                   // [31:31] Reserved
end;

TSystemControl_SHPR1_bits = bitpacked record
  PRI_4                  : TBits_8;                    // [0:7] Priority of system handler 4, MemManage
  PRI_5                  : TBits_8;                    // [8:15] Priority of system handler 5, BusFault
  PRI_6                  : TBits_8;                    // [16:23] Priority of system handler 6, UsageFault
  RESERVED0              : TBits_1;                    // [24:24] Reserved
  RESERVED1              : TBits_1;                    // [25:25] Reserved
  RESERVED2              : TBits_1;                    // [26:26] Reserved
  RESERVED3              : TBits_1;                    // [27:27] Reserved
  RESERVED4              : TBits_1;                    // [28:28] Reserved
  RESERVED5              : TBits_1;                    // [29:29] Reserved
  RESERVED6              : TBits_1;                    // [30:30] Reserved
  RESERVED7              : TBits_1;                    // [31:31] Reserved
end;

TSystemControl_SHPR1_bitbanded = record
  PRI_4                  : array[0..7] of longWord;    // [0:7] Priority of system handler 4, MemManage
  PRI_5                  : array[0..7] of longWord;    // [8:15] Priority of system handler 5, BusFault
  PRI_6                  : array[0..7] of longWord;    // [16:23] Priority of system handler 6, UsageFault
  RESERVED0              : longWord;                   // [24:24] Reserved
  RESERVED1              : longWord;                   // [25:25] Reserved
  RESERVED2              : longWord;                   // [26:26] Reserved
  RESERVED3              : longWord;                   // [27:27] Reserved
  RESERVED4              : longWord;                   // [28:28] Reserved
  RESERVED5              : longWord;                   // [29:29] Reserved
  RESERVED6              : longWord;                   // [30:30] Reserved
  RESERVED7              : longWord;                   // [31:31] Reserved
end;

TSystemControl_SHPR2_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] Reserved
  RESERVED1              : TBits_1;                    // [1:1] Reserved
  RESERVED2              : TBits_1;                    // [2:2] Reserved
  RESERVED3              : TBits_1;                    // [3:3] Reserved
  RESERVED4              : TBits_1;                    // [4:4] Reserved
  RESERVED5              : TBits_1;                    // [5:5] Reserved
  RESERVED6              : TBits_1;                    // [6:6] Reserved
  RESERVED7              : TBits_1;                    // [7:7] Reserved
  RESERVED8              : TBits_1;                    // [8:8] Reserved
  RESERVED9              : TBits_1;                    // [9:9] Reserved
  RESERVED10             : TBits_1;                    // [10:10] Reserved
  RESERVED11             : TBits_1;                    // [11:11] Reserved
  RESERVED12             : TBits_1;                    // [12:12] Reserved
  RESERVED13             : TBits_1;                    // [13:13] Reserved
  RESERVED14             : TBits_1;                    // [14:14] Reserved
  RESERVED15             : TBits_1;                    // [15:15] Reserved
  RESERVED16             : TBits_1;                    // [16:16] Reserved
  RESERVED17             : TBits_1;                    // [17:17] Reserved
  RESERVED18             : TBits_1;                    // [18:18] Reserved
  RESERVED19             : TBits_1;                    // [19:19] Reserved
  RESERVED20             : TBits_1;                    // [20:20] Reserved
  RESERVED21             : TBits_1;                    // [21:21] Reserved
  RESERVED22             : TBits_1;                    // [22:22] Reserved
  RESERVED23             : TBits_1;                    // [23:23] Reserved
  PRI_11                 : TBits_8;                    // [24:31] Priority of system handler 11, SVCall
end;

TSystemControl_SHPR2_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] Reserved
  RESERVED1              : longWord;                   // [1:1] Reserved
  RESERVED2              : longWord;                   // [2:2] Reserved
  RESERVED3              : longWord;                   // [3:3] Reserved
  RESERVED4              : longWord;                   // [4:4] Reserved
  RESERVED5              : longWord;                   // [5:5] Reserved
  RESERVED6              : longWord;                   // [6:6] Reserved
  RESERVED7              : longWord;                   // [7:7] Reserved
  RESERVED8              : longWord;                   // [8:8] Reserved
  RESERVED9              : longWord;                   // [9:9] Reserved
  RESERVED10             : longWord;                   // [10:10] Reserved
  RESERVED11             : longWord;                   // [11:11] Reserved
  RESERVED12             : longWord;                   // [12:12] Reserved
  RESERVED13             : longWord;                   // [13:13] Reserved
  RESERVED14             : longWord;                   // [14:14] Reserved
  RESERVED15             : longWord;                   // [15:15] Reserved
  RESERVED16             : longWord;                   // [16:16] Reserved
  RESERVED17             : longWord;                   // [17:17] Reserved
  RESERVED18             : longWord;                   // [18:18] Reserved
  RESERVED19             : longWord;                   // [19:19] Reserved
  RESERVED20             : longWord;                   // [20:20] Reserved
  RESERVED21             : longWord;                   // [21:21] Reserved
  RESERVED22             : longWord;                   // [22:22] Reserved
  RESERVED23             : longWord;                   // [23:23] Reserved
  PRI_11                 : array[0..7] of longWord;    // [24:31] Priority of system handler 11, SVCall
end;

TSystemControl_SHPR3_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] Reserved
  RESERVED1              : TBits_1;                    // [1:1] Reserved
  RESERVED2              : TBits_1;                    // [2:2] Reserved
  RESERVED3              : TBits_1;                    // [3:3] Reserved
  RESERVED4              : TBits_1;                    // [4:4] Reserved
  RESERVED5              : TBits_1;                    // [5:5] Reserved
  RESERVED6              : TBits_1;                    // [6:6] Reserved
  RESERVED7              : TBits_1;                    // [7:7] Reserved
  RESERVED8              : TBits_1;                    // [8:8] Reserved
  RESERVED9              : TBits_1;                    // [9:9] Reserved
  RESERVED10             : TBits_1;                    // [10:10] Reserved
  RESERVED11             : TBits_1;                    // [11:11] Reserved
  RESERVED12             : TBits_1;                    // [12:12] Reserved
  RESERVED13             : TBits_1;                    // [13:13] Reserved
  RESERVED14             : TBits_1;                    // [14:14] Reserved
  RESERVED15             : TBits_1;                    // [15:15] Reserved
  PRI_14                 : TBits_8;                    // [16:23] Priority of system handler 14, PendSV
  PRI_15                 : TBits_8;                    // [24:31] Priority of system handler 15, SysTick exception
end;

TSystemControl_SHPR3_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] Reserved
  RESERVED1              : longWord;                   // [1:1] Reserved
  RESERVED2              : longWord;                   // [2:2] Reserved
  RESERVED3              : longWord;                   // [3:3] Reserved
  RESERVED4              : longWord;                   // [4:4] Reserved
  RESERVED5              : longWord;                   // [5:5] Reserved
  RESERVED6              : longWord;                   // [6:6] Reserved
  RESERVED7              : longWord;                   // [7:7] Reserved
  RESERVED8              : longWord;                   // [8:8] Reserved
  RESERVED9              : longWord;                   // [9:9] Reserved
  RESERVED10             : longWord;                   // [10:10] Reserved
  RESERVED11             : longWord;                   // [11:11] Reserved
  RESERVED12             : longWord;                   // [12:12] Reserved
  RESERVED13             : longWord;                   // [13:13] Reserved
  RESERVED14             : longWord;                   // [14:14] Reserved
  RESERVED15             : longWord;                   // [15:15] Reserved
  PRI_14                 : array[0..7] of longWord;    // [16:23] Priority of system handler 14, PendSV
  PRI_15                 : array[0..7] of longWord;    // [24:31] Priority of system handler 15, SysTick exception
end;

TSystemControl_SHCSR_bits = bitpacked record
  MEMFAULTACT            : TBits_1;                    // [0:0] no description available
  BUSFAULTACT            : TBits_1;                    // [1:1] no description available
  RESERVED0              : TBits_1;                    // [2:2] Reserved
  USGFAULTACT            : TBits_1;                    // [3:3] no description available
  RESERVED1              : TBits_1;                    // [4:4] Reserved
  RESERVED2              : TBits_1;                    // [5:5] Reserved
  RESERVED3              : TBits_1;                    // [6:6] Reserved
  SVCALLACT              : TBits_1;                    // [7:7] no description available
  MONITORACT             : TBits_1;                    // [8:8] no description available
  RESERVED4              : TBits_1;                    // [9:9] Reserved
  PENDSVACT              : TBits_1;                    // [10:10] no description available
  SYSTICKACT             : TBits_1;                    // [11:11] no description available
  USGFAULTPENDED         : TBits_1;                    // [12:12] no description available
  MEMFAULTPENDED         : TBits_1;                    // [13:13] no description available
  BUSFAULTPENDED         : TBits_1;                    // [14:14] no description available
  SVCALLPENDED           : TBits_1;                    // [15:15] no description available
  MEMFAULTENA            : TBits_1;                    // [16:16] no description available
  BUSFAULTENA            : TBits_1;                    // [17:17] no description available
  USGFAULTENA            : TBits_1;                    // [18:18] no description available
  RESERVED5              : TBits_1;                    // [19:19] Reserved
  RESERVED6              : TBits_1;                    // [20:20] Reserved
  RESERVED7              : TBits_1;                    // [21:21] Reserved
  RESERVED8              : TBits_1;                    // [22:22] Reserved
  RESERVED9              : TBits_1;                    // [23:23] Reserved
  RESERVED10             : TBits_1;                    // [24:24] Reserved
  RESERVED11             : TBits_1;                    // [25:25] Reserved
  RESERVED12             : TBits_1;                    // [26:26] Reserved
  RESERVED13             : TBits_1;                    // [27:27] Reserved
  RESERVED14             : TBits_1;                    // [28:28] Reserved
  RESERVED15             : TBits_1;                    // [29:29] Reserved
  RESERVED16             : TBits_1;                    // [30:30] Reserved
  RESERVED17             : TBits_1;                    // [31:31] Reserved
end;

TSystemControl_SHCSR_bitbanded = record
  MEMFAULTACT            : longWord;                   // [0:0] no description available
  BUSFAULTACT            : longWord;                   // [1:1] no description available
  RESERVED0              : longWord;                   // [2:2] Reserved
  USGFAULTACT            : longWord;                   // [3:3] no description available
  RESERVED1              : longWord;                   // [4:4] Reserved
  RESERVED2              : longWord;                   // [5:5] Reserved
  RESERVED3              : longWord;                   // [6:6] Reserved
  SVCALLACT              : longWord;                   // [7:7] no description available
  MONITORACT             : longWord;                   // [8:8] no description available
  RESERVED4              : longWord;                   // [9:9] Reserved
  PENDSVACT              : longWord;                   // [10:10] no description available
  SYSTICKACT             : longWord;                   // [11:11] no description available
  USGFAULTPENDED         : longWord;                   // [12:12] no description available
  MEMFAULTPENDED         : longWord;                   // [13:13] no description available
  BUSFAULTPENDED         : longWord;                   // [14:14] no description available
  SVCALLPENDED           : longWord;                   // [15:15] no description available
  MEMFAULTENA            : longWord;                   // [16:16] no description available
  BUSFAULTENA            : longWord;                   // [17:17] no description available
  USGFAULTENA            : longWord;                   // [18:18] no description available
  RESERVED5              : longWord;                   // [19:19] Reserved
  RESERVED6              : longWord;                   // [20:20] Reserved
  RESERVED7              : longWord;                   // [21:21] Reserved
  RESERVED8              : longWord;                   // [22:22] Reserved
  RESERVED9              : longWord;                   // [23:23] Reserved
  RESERVED10             : longWord;                   // [24:24] Reserved
  RESERVED11             : longWord;                   // [25:25] Reserved
  RESERVED12             : longWord;                   // [26:26] Reserved
  RESERVED13             : longWord;                   // [27:27] Reserved
  RESERVED14             : longWord;                   // [28:28] Reserved
  RESERVED15             : longWord;                   // [29:29] Reserved
  RESERVED16             : longWord;                   // [30:30] Reserved
  RESERVED17             : longWord;                   // [31:31] Reserved
end;

TSystemControl_CFSR_bits = bitpacked record
  IACCVIOL               : TBits_1;                    // [0:0] no description available
  DACCVIOL               : TBits_1;                    // [1:1] no description available
  RESERVED0              : TBits_1;                    // [2:2] Reserved
  MUNSTKERR              : TBits_1;                    // [3:3] no description available
  MSTKERR                : TBits_1;                    // [4:4] no description available
  MLSPERR                : TBits_1;                    // [5:5] no description available
  RESERVED1              : TBits_1;                    // [6:6] Reserved
  MMARVALID              : TBits_1;                    // [7:7] no description available
  IBUSERR                : TBits_1;                    // [8:8] no description available
  PRECISERR              : TBits_1;                    // [9:9] no description available
  IMPRECISERR            : TBits_1;                    // [10:10] no description available
  UNSTKERR               : TBits_1;                    // [11:11] no description available
  STKERR                 : TBits_1;                    // [12:12] no description available
  LSPERR                 : TBits_1;                    // [13:13] no description available
  RESERVED2              : TBits_1;                    // [14:14] Reserved
  BFARVALID              : TBits_1;                    // [15:15] no description available
  UNDEFINSTR             : TBits_1;                    // [16:16] no description available
  INVSTATE               : TBits_1;                    // [17:17] no description available
  INVPC                  : TBits_1;                    // [18:18] no description available
  NOCP                   : TBits_1;                    // [19:19] no description available
  RESERVED3              : TBits_1;                    // [20:20] Reserved
  RESERVED4              : TBits_1;                    // [21:21] Reserved
  RESERVED5              : TBits_1;                    // [22:22] Reserved
  RESERVED6              : TBits_1;                    // [23:23] Reserved
  UNALIGNED              : TBits_1;                    // [24:24] no description available
  DIVBYZERO              : TBits_1;                    // [25:25] no description available
  RESERVED7              : TBits_1;                    // [26:26] Reserved
  RESERVED8              : TBits_1;                    // [27:27] Reserved
  RESERVED9              : TBits_1;                    // [28:28] Reserved
  RESERVED10             : TBits_1;                    // [29:29] Reserved
  RESERVED11             : TBits_1;                    // [30:30] Reserved
  RESERVED12             : TBits_1;                    // [31:31] Reserved
end;

TSystemControl_CFSR_bitbanded = record
  IACCVIOL               : longWord;                   // [0:0] no description available
  DACCVIOL               : longWord;                   // [1:1] no description available
  RESERVED0              : longWord;                   // [2:2] Reserved
  MUNSTKERR              : longWord;                   // [3:3] no description available
  MSTKERR                : longWord;                   // [4:4] no description available
  MLSPERR                : longWord;                   // [5:5] no description available
  RESERVED1              : longWord;                   // [6:6] Reserved
  MMARVALID              : longWord;                   // [7:7] no description available
  IBUSERR                : longWord;                   // [8:8] no description available
  PRECISERR              : longWord;                   // [9:9] no description available
  IMPRECISERR            : longWord;                   // [10:10] no description available
  UNSTKERR               : longWord;                   // [11:11] no description available
  STKERR                 : longWord;                   // [12:12] no description available
  LSPERR                 : longWord;                   // [13:13] no description available
  RESERVED2              : longWord;                   // [14:14] Reserved
  BFARVALID              : longWord;                   // [15:15] no description available
  UNDEFINSTR             : longWord;                   // [16:16] no description available
  INVSTATE               : longWord;                   // [17:17] no description available
  INVPC                  : longWord;                   // [18:18] no description available
  NOCP                   : longWord;                   // [19:19] no description available
  RESERVED3              : longWord;                   // [20:20] Reserved
  RESERVED4              : longWord;                   // [21:21] Reserved
  RESERVED5              : longWord;                   // [22:22] Reserved
  RESERVED6              : longWord;                   // [23:23] Reserved
  UNALIGNED              : longWord;                   // [24:24] no description available
  DIVBYZERO              : longWord;                   // [25:25] no description available
  RESERVED7              : longWord;                   // [26:26] Reserved
  RESERVED8              : longWord;                   // [27:27] Reserved
  RESERVED9              : longWord;                   // [28:28] Reserved
  RESERVED10             : longWord;                   // [29:29] Reserved
  RESERVED11             : longWord;                   // [30:30] Reserved
  RESERVED12             : longWord;                   // [31:31] Reserved
end;

TSystemControl_HFSR_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] Reserved
  VECTTBL                : TBits_1;                    // [1:1] no description available
  RESERVED1              : TBits_1;                    // [2:2] Reserved
  RESERVED2              : TBits_1;                    // [3:3] Reserved
  RESERVED3              : TBits_1;                    // [4:4] Reserved
  RESERVED4              : TBits_1;                    // [5:5] Reserved
  RESERVED5              : TBits_1;                    // [6:6] Reserved
  RESERVED6              : TBits_1;                    // [7:7] Reserved
  RESERVED7              : TBits_1;                    // [8:8] Reserved
  RESERVED8              : TBits_1;                    // [9:9] Reserved
  RESERVED9              : TBits_1;                    // [10:10] Reserved
  RESERVED10             : TBits_1;                    // [11:11] Reserved
  RESERVED11             : TBits_1;                    // [12:12] Reserved
  RESERVED12             : TBits_1;                    // [13:13] Reserved
  RESERVED13             : TBits_1;                    // [14:14] Reserved
  RESERVED14             : TBits_1;                    // [15:15] Reserved
  RESERVED15             : TBits_1;                    // [16:16] Reserved
  RESERVED16             : TBits_1;                    // [17:17] Reserved
  RESERVED17             : TBits_1;                    // [18:18] Reserved
  RESERVED18             : TBits_1;                    // [19:19] Reserved
  RESERVED19             : TBits_1;                    // [20:20] Reserved
  RESERVED20             : TBits_1;                    // [21:21] Reserved
  RESERVED21             : TBits_1;                    // [22:22] Reserved
  RESERVED22             : TBits_1;                    // [23:23] Reserved
  RESERVED23             : TBits_1;                    // [24:24] Reserved
  RESERVED24             : TBits_1;                    // [25:25] Reserved
  RESERVED25             : TBits_1;                    // [26:26] Reserved
  RESERVED26             : TBits_1;                    // [27:27] Reserved
  RESERVED27             : TBits_1;                    // [28:28] Reserved
  RESERVED28             : TBits_1;                    // [29:29] Reserved
  FORCED                 : TBits_1;                    // [30:30] no description available
  DEBUGEVT               : TBits_1;                    // [31:31] no description available
end;

TSystemControl_HFSR_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] Reserved
  VECTTBL                : longWord;                   // [1:1] no description available
  RESERVED1              : longWord;                   // [2:2] Reserved
  RESERVED2              : longWord;                   // [3:3] Reserved
  RESERVED3              : longWord;                   // [4:4] Reserved
  RESERVED4              : longWord;                   // [5:5] Reserved
  RESERVED5              : longWord;                   // [6:6] Reserved
  RESERVED6              : longWord;                   // [7:7] Reserved
  RESERVED7              : longWord;                   // [8:8] Reserved
  RESERVED8              : longWord;                   // [9:9] Reserved
  RESERVED9              : longWord;                   // [10:10] Reserved
  RESERVED10             : longWord;                   // [11:11] Reserved
  RESERVED11             : longWord;                   // [12:12] Reserved
  RESERVED12             : longWord;                   // [13:13] Reserved
  RESERVED13             : longWord;                   // [14:14] Reserved
  RESERVED14             : longWord;                   // [15:15] Reserved
  RESERVED15             : longWord;                   // [16:16] Reserved
  RESERVED16             : longWord;                   // [17:17] Reserved
  RESERVED17             : longWord;                   // [18:18] Reserved
  RESERVED18             : longWord;                   // [19:19] Reserved
  RESERVED19             : longWord;                   // [20:20] Reserved
  RESERVED20             : longWord;                   // [21:21] Reserved
  RESERVED21             : longWord;                   // [22:22] Reserved
  RESERVED22             : longWord;                   // [23:23] Reserved
  RESERVED23             : longWord;                   // [24:24] Reserved
  RESERVED24             : longWord;                   // [25:25] Reserved
  RESERVED25             : longWord;                   // [26:26] Reserved
  RESERVED26             : longWord;                   // [27:27] Reserved
  RESERVED27             : longWord;                   // [28:28] Reserved
  RESERVED28             : longWord;                   // [29:29] Reserved
  FORCED                 : longWord;                   // [30:30] no description available
  DEBUGEVT               : longWord;                   // [31:31] no description available
end;

TSystemControl_DFSR_bits = bitpacked record
  HALTED                 : TBits_1;                    // [0:0] no description available
  BKPT                   : TBits_1;                    // [1:1] no description available
  DWTTRAP                : TBits_1;                    // [2:2] no description available
  VCATCH                 : TBits_1;                    // [3:3] no description available
  EXTERNAL               : TBits_1;                    // [4:4] no description available
  RESERVED0              : TBits_1;                    // [5:5] Reserved
  RESERVED1              : TBits_1;                    // [6:6] Reserved
  RESERVED2              : TBits_1;                    // [7:7] Reserved
  RESERVED3              : TBits_1;                    // [8:8] Reserved
  RESERVED4              : TBits_1;                    // [9:9] Reserved
  RESERVED5              : TBits_1;                    // [10:10] Reserved
  RESERVED6              : TBits_1;                    // [11:11] Reserved
  RESERVED7              : TBits_1;                    // [12:12] Reserved
  RESERVED8              : TBits_1;                    // [13:13] Reserved
  RESERVED9              : TBits_1;                    // [14:14] Reserved
  RESERVED10             : TBits_1;                    // [15:15] Reserved
  RESERVED11             : TBits_1;                    // [16:16] Reserved
  RESERVED12             : TBits_1;                    // [17:17] Reserved
  RESERVED13             : TBits_1;                    // [18:18] Reserved
  RESERVED14             : TBits_1;                    // [19:19] Reserved
  RESERVED15             : TBits_1;                    // [20:20] Reserved
  RESERVED16             : TBits_1;                    // [21:21] Reserved
  RESERVED17             : TBits_1;                    // [22:22] Reserved
  RESERVED18             : TBits_1;                    // [23:23] Reserved
  RESERVED19             : TBits_1;                    // [24:24] Reserved
  RESERVED20             : TBits_1;                    // [25:25] Reserved
  RESERVED21             : TBits_1;                    // [26:26] Reserved
  RESERVED22             : TBits_1;                    // [27:27] Reserved
  RESERVED23             : TBits_1;                    // [28:28] Reserved
  RESERVED24             : TBits_1;                    // [29:29] Reserved
  RESERVED25             : TBits_1;                    // [30:30] Reserved
  RESERVED26             : TBits_1;                    // [31:31] Reserved
end;

TSystemControl_DFSR_bitbanded = record
  HALTED                 : longWord;                   // [0:0] no description available
  BKPT                   : longWord;                   // [1:1] no description available
  DWTTRAP                : longWord;                   // [2:2] no description available
  VCATCH                 : longWord;                   // [3:3] no description available
  EXTERNAL               : longWord;                   // [4:4] no description available
  RESERVED0              : longWord;                   // [5:5] Reserved
  RESERVED1              : longWord;                   // [6:6] Reserved
  RESERVED2              : longWord;                   // [7:7] Reserved
  RESERVED3              : longWord;                   // [8:8] Reserved
  RESERVED4              : longWord;                   // [9:9] Reserved
  RESERVED5              : longWord;                   // [10:10] Reserved
  RESERVED6              : longWord;                   // [11:11] Reserved
  RESERVED7              : longWord;                   // [12:12] Reserved
  RESERVED8              : longWord;                   // [13:13] Reserved
  RESERVED9              : longWord;                   // [14:14] Reserved
  RESERVED10             : longWord;                   // [15:15] Reserved
  RESERVED11             : longWord;                   // [16:16] Reserved
  RESERVED12             : longWord;                   // [17:17] Reserved
  RESERVED13             : longWord;                   // [18:18] Reserved
  RESERVED14             : longWord;                   // [19:19] Reserved
  RESERVED15             : longWord;                   // [20:20] Reserved
  RESERVED16             : longWord;                   // [21:21] Reserved
  RESERVED17             : longWord;                   // [22:22] Reserved
  RESERVED18             : longWord;                   // [23:23] Reserved
  RESERVED19             : longWord;                   // [24:24] Reserved
  RESERVED20             : longWord;                   // [25:25] Reserved
  RESERVED21             : longWord;                   // [26:26] Reserved
  RESERVED22             : longWord;                   // [27:27] Reserved
  RESERVED23             : longWord;                   // [28:28] Reserved
  RESERVED24             : longWord;                   // [29:29] Reserved
  RESERVED25             : longWord;                   // [30:30] Reserved
  RESERVED26             : longWord;                   // [31:31] Reserved
end;

TSystemControl_MMFAR_bits = bitpacked record
  ADDRESS                : TBits_32;                   // [0:31] Address of MemManage fault location
end;

TSystemControl_MMFAR_bitbanded = record
  ADDRESS                : array[0..31] of longWord;   // [0:31] Address of MemManage fault location
end;

TSystemControl_BFAR_bits = bitpacked record
  ADDRESS                : TBits_32;                   // [0:31] Address of the BusFault location
end;

TSystemControl_BFAR_bitbanded = record
  ADDRESS                : array[0..31] of longWord;   // [0:31] Address of the BusFault location
end;

TSystemControl_AFSR_bits = bitpacked record
  AUXFAULT               : TBits_32;                   // [0:31] Latched version of the AUXFAULT inputs
end;

TSystemControl_AFSR_bitbanded = record
  AUXFAULT               : array[0..31] of longWord;   // [0:31] Latched version of the AUXFAULT inputs
end;

TSystemControl_Registers = record
  case boolean of false: (
  RESERVED0              : array[0..1] of longWord;    // 0x00
  ACTLR                  : longWord;                   // 0x08 Auxiliary Control Register,
  RESERVED1              : array[0..828] of longWord;  // 0x0C
  CPUID                  : longWord;                   // 0xD00 CPUID Base Register
  ICSR                   : longWord;                   // 0xD04 Interrupt Control and State Register
  VTOR                   : longWord;                   // 0xD08 Vector Table Offset Register
  AIRCR                  : longWord;                   // 0xD0C Application Interrupt and Reset Control Register
  SCR                    : longWord;                   // 0xD10 System Control Register
  CCR                    : longWord;                   // 0xD14 Configuration and Control Register
  SHPR1                  : longWord;                   // 0xD18 System Handler Priority Register 1
  SHPR2                  : longWord;                   // 0xD1C System Handler Priority Register 2
  SHPR3                  : longWord;                   // 0xD20 System Handler Priority Register 3
  SHCSR                  : longWord;                   // 0xD24 System Handler Control and State Register
  CFSR                   : longWord;                   // 0xD28 Configurable Fault Status Registers
  HFSR                   : longWord;                   // 0xD2C HardFault Status register
  DFSR                   : longWord;                   // 0xD30 Debug Fault Status Register
  MMFAR                  : longWord;                   // 0xD34 MemManage Address Register
  BFAR                   : longWord;                   // 0xD38 BusFault Address Register
  AFSR                   : longWord;                   // 0xD3C Auxiliary Fault Status Register
);
true : (
RESERVED_bits0           : array[0..1] of longWord;
ACTLR_bits               : TSystemControl_ACTLR_bits;  // 0x0C Auxiliary Control Register,
RESERVED_bits1           : array[0..828] of longWord;
CPUID_bits               : TSystemControl_CPUID_bits;  // 0xD04 CPUID Base Register
ICSR_bits                : TSystemControl_ICSR_bits;   // 0xD08 Interrupt Control and State Register
VTOR_bits                : TSystemControl_VTOR_bits;   // 0xD0C Vector Table Offset Register
AIRCR_bits               : TSystemControl_AIRCR_bits;  // 0xD10 Application Interrupt and Reset Control Register
SCR_bits                 : TSystemControl_SCR_bits;    // 0xD14 System Control Register
CCR_bits                 : TSystemControl_CCR_bits;    // 0xD18 Configuration and Control Register
SHPR1_bits               : TSystemControl_SHPR1_bits;  // 0xD1C System Handler Priority Register 1
SHPR2_bits               : TSystemControl_SHPR2_bits;  // 0xD20 System Handler Priority Register 2
SHPR3_bits               : TSystemControl_SHPR3_bits;  // 0xD24 System Handler Priority Register 3
SHCSR_bits               : TSystemControl_SHCSR_bits;  // 0xD28 System Handler Control and State Register
CFSR_bits                : TSystemControl_CFSR_bits;   // 0xD2C Configurable Fault Status Registers
HFSR_bits                : TSystemControl_HFSR_bits;   // 0xD30 HardFault Status register
DFSR_bits                : TSystemControl_DFSR_bits;   // 0xD34 Debug Fault Status Register
MMFAR_bits               : TSystemControl_MMFAR_bits;  // 0xD38 MemManage Address Register
BFAR_bits                : TSystemControl_BFAR_bits;   // 0xD3C BusFault Address Register
AFSR_bits                : TSystemControl_AFSR_bits;   // 0xD40 Auxiliary Fault Status Register
);
end;

TSystemControlRegisters_bitbanded = record
  RESERVED0              : array[0..7] of array[0..7] of longWord;
  ACTLR                  : TSystemControl_ACTLR_bitbanded;// 0x0C Auxiliary Control Register,
  RESERVED1              : array[0..3315] of array[0..7] of longWord;
  CPUID                  : TSystemControl_CPUID_bitbanded;// 0xD04 CPUID Base Register
  ICSR                   : TSystemControl_ICSR_bitbanded;// 0xD08 Interrupt Control and State Register
  VTOR                   : TSystemControl_VTOR_bitbanded;// 0xD0C Vector Table Offset Register
  AIRCR                  : TSystemControl_AIRCR_bitbanded;// 0xD10 Application Interrupt and Reset Control Register
  SCR                    : TSystemControl_SCR_bitbanded;// 0xD14 System Control Register
  CCR                    : TSystemControl_CCR_bitbanded;// 0xD18 Configuration and Control Register
  SHPR1                  : TSystemControl_SHPR1_bitbanded;// 0xD1C System Handler Priority Register 1
  SHPR2                  : TSystemControl_SHPR2_bitbanded;// 0xD20 System Handler Priority Register 2
  SHPR3                  : TSystemControl_SHPR3_bitbanded;// 0xD24 System Handler Priority Register 3
  SHCSR                  : TSystemControl_SHCSR_bitbanded;// 0xD28 System Handler Control and State Register
  CFSR                   : TSystemControl_CFSR_bitbanded;// 0xD2C Configurable Fault Status Registers
  HFSR                   : TSystemControl_HFSR_bitbanded;// 0xD30 HardFault Status register
  DFSR                   : TSystemControl_DFSR_bitbanded;// 0xD34 Debug Fault Status Register
  MMFAR                  : TSystemControl_MMFAR_bitbanded;// 0xD38 MemManage Address Register
  BFAR                   : TSystemControl_BFAR_bitbanded;// 0xD3C BusFault Address Register
  AFSR                   : TSystemControl_AFSR_bitbanded;// 0xD40 Auxiliary Fault Status Register
end;

// Touch Sensing Input
TTSI0_GENCS_bits = bitpacked record
  STPE                   : TBits_1;                    // [0:0] no description available
  STM                    : TBits_1;                    // [1:1] Scan Trigger Mode. This bit-field can only be changed if the TSI module is disabled (TSIEN bit = 0).
  RESERVED0              : TBits_1;                    // [2:2] Reserved
  RESERVED1              : TBits_1;                    // [3:3] no description available
  ESOR                   : TBits_1;                    // [4:4] End-of-Scan or Out-of-Range Interrupt select
  ERIE                   : TBits_1;                    // [5:5] Error Interrupt Enable
  TSIIE                  : TBits_1;                    // [6:6] Touch Sensing Input Interrupt Module Enable
  TSIEN                  : TBits_1;                    // [7:7] Touch Sensing Input Module Enable
  SWTS                   : TBits_1;                    // [8:8] Software Trigger Start
  SCNIP                  : TBits_1;                    // [9:9] Scan In Progress status
  RESERVED2              : TBits_2;                    // [10:11] no description available
  OVRF                   : TBits_1;                    // [12:12] Overrun error Flag. This flag is set when a scan trigger occurs while a scan is still in progress. Write "1", when this flag is set, to clear it.
  EXTERF                 : TBits_1;                    // [13:13] External Electrode error occurred
  OUTRGF                 : TBits_1;                    // [14:14] Out of Range Flag.
  EOSF                   : TBits_1;                    // [15:15] End of Scan Flag.
  PS                     : TBits_3;                    // [16:18] Electrode Oscillator prescaler. .
  NSCN                   : TBits_5;                    // [19:23] Number of Consecutive Scans per Electrode electrode.
  LPSCNITV               : TBits_4;                    // [24:27] TSI Low Power Mode Scan Interval.
  LPCLKS                 : TBits_1;                    // [28:28] Low Power Mode Clock Source Selection.
  RESERVED3              : TBits_3;                    // [29:31] no description available
end;

TTSI0_GENCS_bitbanded = record
  STPE                   : longWord;                   // [0:0] no description available
  STM                    : longWord;                   // [1:1] Scan Trigger Mode. This bit-field can only be changed if the TSI module is disabled (TSIEN bit = 0).
  RESERVED0              : longWord;                   // [2:2] Reserved
  RESERVED1              : longWord;                   // [3:3] no description available
  ESOR                   : longWord;                   // [4:4] End-of-Scan or Out-of-Range Interrupt select
  ERIE                   : longWord;                   // [5:5] Error Interrupt Enable
  TSIIE                  : longWord;                   // [6:6] Touch Sensing Input Interrupt Module Enable
  TSIEN                  : longWord;                   // [7:7] Touch Sensing Input Module Enable
  SWTS                   : longWord;                   // [8:8] Software Trigger Start
  SCNIP                  : longWord;                   // [9:9] Scan In Progress status
  RESERVED2              : array[0..1] of longWord;    // [10:11] no description available
  OVRF                   : longWord;                   // [12:12] Overrun error Flag. This flag is set when a scan trigger occurs while a scan is still in progress. Write "1", when this flag is set, to clear it.
  EXTERF                 : longWord;                   // [13:13] External Electrode error occurred
  OUTRGF                 : longWord;                   // [14:14] Out of Range Flag.
  EOSF                   : longWord;                   // [15:15] End of Scan Flag.
  PS                     : array[0..2] of longWord;    // [16:18] Electrode Oscillator prescaler. .
  NSCN                   : array[0..4] of longWord;    // [19:23] Number of Consecutive Scans per Electrode electrode.
  LPSCNITV               : array[0..3] of longWord;    // [24:27] TSI Low Power Mode Scan Interval.
  LPCLKS                 : longWord;                   // [28:28] Low Power Mode Clock Source Selection.
  RESERVED3              : array[0..2] of longWord;    // [29:31] no description available
end;

TTSI0_SCANC_bits = bitpacked record
  AMPSC                  : TBits_3;                    // [0:2] Active Mode Prescaler
  AMCLKS                 : TBits_2;                    // [3:4] Active Mode Clock Source
  RESERVED0              : TBits_1;                    // [5:5] no description available
  RESERVED1              : TBits_2;                    // [6:7] no description available
  SMOD                   : TBits_8;                    // [8:15] Scan Module
  EXTCHRG                : TBits_4;                    // [16:19] External OSC Charge Current select
  RESERVED2              : TBits_4;                    // [20:23] no description available
  REFCHRG                : TBits_4;                    // [24:27] Ref OSC Charge Current select
  RESERVED3              : TBits_4;                    // [28:31] no description available
end;

TTSI0_SCANC_bitbanded = record
  AMPSC                  : array[0..2] of longWord;    // [0:2] Active Mode Prescaler
  AMCLKS                 : array[0..1] of longWord;    // [3:4] Active Mode Clock Source
  RESERVED0              : longWord;                   // [5:5] no description available
  RESERVED1              : array[0..1] of longWord;    // [6:7] no description available
  SMOD                   : array[0..7] of longWord;    // [8:15] Scan Module
  EXTCHRG                : array[0..3] of longWord;    // [16:19] External OSC Charge Current select
  RESERVED2              : array[0..3] of longWord;    // [20:23] no description available
  REFCHRG                : array[0..3] of longWord;    // [24:27] Ref OSC Charge Current select
  RESERVED3              : array[0..3] of longWord;    // [28:31] no description available
end;

TTSI0_PEN_bits = bitpacked record
  PEN0                   : TBits_1;                    // [0:0] Touch Sensing Input Pin Enable Register 0
  PEN1                   : TBits_1;                    // [1:1] Touch Sensing Input Pin Enable Register 1
  PEN2                   : TBits_1;                    // [2:2] Touch Sensing Input Pin Enable Register 2
  PEN3                   : TBits_1;                    // [3:3] Touch Sensing Input Pin Enable Register 3
  PEN4                   : TBits_1;                    // [4:4] Touch Sensing Input Pin Enable Register 4
  PEN5                   : TBits_1;                    // [5:5] Touch Sensing Input Pin Enable Register 5
  PEN6                   : TBits_1;                    // [6:6] Touch Sensing Input Pin Enable Register 6
  PEN7                   : TBits_1;                    // [7:7] Touch Sensing Input Pin Enable Register 7
  PEN8                   : TBits_1;                    // [8:8] Touch Sensing Input Pin Enable Register 8
  PEN9                   : TBits_1;                    // [9:9] Touch Sensing Input Pin Enable Register 9
  PEN10                  : TBits_1;                    // [10:10] Touch Sensing Input Pin Enable Register 10
  PEN11                  : TBits_1;                    // [11:11] Touch Sensing Input Pin Enable Register 11
  PEN12                  : TBits_1;                    // [12:12] Touch Sensing Input Pin Enable Register 12
  PEN13                  : TBits_1;                    // [13:13] Touch Sensing Input Pin Enable Register 13
  PEN14                  : TBits_1;                    // [14:14] Touch Sensing Input Pin Enable Register 14
  PEN15                  : TBits_1;                    // [15:15] Touch Sensing Input Pin Enable Register 15
  LPSP                   : TBits_4;                    // [16:19] Low Power Scan Pin
  RESERVED0              : TBits_12;                   // [20:31] no description available
end;

TTSI0_PEN_bitbanded = record
  PEN0                   : longWord;                   // [0:0] Touch Sensing Input Pin Enable Register 0
  PEN1                   : longWord;                   // [1:1] Touch Sensing Input Pin Enable Register 1
  PEN2                   : longWord;                   // [2:2] Touch Sensing Input Pin Enable Register 2
  PEN3                   : longWord;                   // [3:3] Touch Sensing Input Pin Enable Register 3
  PEN4                   : longWord;                   // [4:4] Touch Sensing Input Pin Enable Register 4
  PEN5                   : longWord;                   // [5:5] Touch Sensing Input Pin Enable Register 5
  PEN6                   : longWord;                   // [6:6] Touch Sensing Input Pin Enable Register 6
  PEN7                   : longWord;                   // [7:7] Touch Sensing Input Pin Enable Register 7
  PEN8                   : longWord;                   // [8:8] Touch Sensing Input Pin Enable Register 8
  PEN9                   : longWord;                   // [9:9] Touch Sensing Input Pin Enable Register 9
  PEN10                  : longWord;                   // [10:10] Touch Sensing Input Pin Enable Register 10
  PEN11                  : longWord;                   // [11:11] Touch Sensing Input Pin Enable Register 11
  PEN12                  : longWord;                   // [12:12] Touch Sensing Input Pin Enable Register 12
  PEN13                  : longWord;                   // [13:13] Touch Sensing Input Pin Enable Register 13
  PEN14                  : longWord;                   // [14:14] Touch Sensing Input Pin Enable Register 14
  PEN15                  : longWord;                   // [15:15] Touch Sensing Input Pin Enable Register 15
  LPSP                   : array[0..3] of longWord;    // [16:19] Low Power Scan Pin
  RESERVED0              : array[0..11] of longWord;   // [20:31] no description available
end;

TTSI0_WUCNTR_bits = bitpacked record
  WUCNT                  : TBits_16;                   // [0:15] TouchSensing wake-up Channel 16bit counter value
  RESERVED0              : TBits_16;                   // [16:31] no description available
end;

TTSI0_WUCNTR_bitbanded = record
  WUCNT                  : array[0..15] of longWord;   // [0:15] TouchSensing wake-up Channel 16bit counter value
  RESERVED0              : array[0..15] of longWord;   // [16:31] no description available
end;

TTSI0_CNTR_bits = bitpacked record
  CTN1                   : TBits_16;                   // [0:15] TouchSensing Channel n-1 16-bit counter value
  CTN                    : TBits_16;                   // [16:31] TouchSensing Channel n 16-bit counter value
end;

TTSI0_CNTR_bitbanded = record
  CTN1                   : array[0..15] of longWord;   // [0:15] TouchSensing Channel n-1 16-bit counter value
  CTN                    : array[0..15] of longWord;   // [16:31] TouchSensing Channel n 16-bit counter value
end;

TTSI0_THRESHOLD_bits = bitpacked record
  HTHH                   : TBits_16;                   // [0:15] Touch Sensing Channel High Threshold value
  LTHH                   : TBits_16;                   // [16:31] Touch Sensing Channel Low Threshold value
end;

TTSI0_THRESHOLD_bitbanded = record
  HTHH                   : array[0..15] of longWord;   // [0:15] Touch Sensing Channel High Threshold value
  LTHH                   : array[0..15] of longWord;   // [16:31] Touch Sensing Channel Low Threshold value
end;

TTSI0_Registers = record
  case boolean of false: (
  GENCS                  : longWord;                   // 0x00 General Control and Status Register
  SCANC                  : longWord;                   // 0x04 SCAN Control Register
  PEN                    : longWord;                   // 0x08 Pin Enable Register
  WUCNTR                 : longWord;                   // 0x0C Wake-Up Channel Counter Register
  RESERVED0              : array[0..59] of longWord;   // 0x10
  CNTR1                  : longWord;                   // 0x100 Counter Register
  CNTR3                  : longWord;                   // 0x104 Counter Register
  CNTR5                  : longWord;                   // 0x108 Counter Register
  CNTR7                  : longWord;                   // 0x10C Counter Register
  CNTR9                  : longWord;                   // 0x110 Counter Register
  CNTR11                 : longWord;                   // 0x114 Counter Register
  CNTR13                 : longWord;                   // 0x118 Counter Register
  CNTR15                 : longWord;                   // 0x11C Counter Register
  THRESHOLD              : longWord;                   // 0x120 Low Power Channel Threshold Register
);
true : (
GENCS_bits               : TTSI0_GENCS_bits;           // 0x04 General Control and Status Register
SCANC_bits               : TTSI0_SCANC_bits;           // 0x08 SCAN Control Register
PEN_bits                 : TTSI0_PEN_bits;             // 0x0C Pin Enable Register
WUCNTR_bits              : TTSI0_WUCNTR_bits;          // 0x10 Wake-Up Channel Counter Register
RESERVED_bits0           : array[0..59] of longWord;
CNTR1_bits               : TTSI0_CNTR_bits;            // 0x104 Counter Register
CNTR3_bits               : TTSI0_CNTR_bits;            // 0x108 Counter Register
CNTR5_bits               : TTSI0_CNTR_bits;            // 0x10C Counter Register
CNTR7_bits               : TTSI0_CNTR_bits;            // 0x110 Counter Register
CNTR9_bits               : TTSI0_CNTR_bits;            // 0x114 Counter Register
CNTR11_bits              : TTSI0_CNTR_bits;            // 0x118 Counter Register
CNTR13_bits              : TTSI0_CNTR_bits;            // 0x11C Counter Register
CNTR15_bits              : TTSI0_CNTR_bits;            // 0x120 Counter Register
THRESHOLD_bits           : TTSI0_THRESHOLD_bits;       // 0x124 Low Power Channel Threshold Register
);
end;

TTSI0Registers_bitbanded = record
  GENCS                  : TTSI0_GENCS_bitbanded;      // 0x04 General Control and Status Register
  SCANC                  : TTSI0_SCANC_bitbanded;      // 0x08 SCAN Control Register
  PEN                    : TTSI0_PEN_bitbanded;        // 0x0C Pin Enable Register
  WUCNTR                 : TTSI0_WUCNTR_bitbanded;     // 0x10 Wake-Up Channel Counter Register
  RESERVED0              : array[0..239] of array[0..7] of longWord;
  CNTR1                  : TTSI0_CNTR_bitbanded;       // 0x104 Counter Register
  CNTR3                  : TTSI0_CNTR_bitbanded;       // 0x108 Counter Register
  CNTR5                  : TTSI0_CNTR_bitbanded;       // 0x10C Counter Register
  CNTR7                  : TTSI0_CNTR_bitbanded;       // 0x110 Counter Register
  CNTR9                  : TTSI0_CNTR_bitbanded;       // 0x114 Counter Register
  CNTR11                 : TTSI0_CNTR_bitbanded;       // 0x118 Counter Register
  CNTR13                 : TTSI0_CNTR_bitbanded;       // 0x11C Counter Register
  CNTR15                 : TTSI0_CNTR_bitbanded;       // 0x120 Counter Register
  THRESHOLD              : TTSI0_THRESHOLD_bitbanded;  // 0x124 Low Power Channel Threshold Register
end;

// Serial Communication Interface
TUART0_BDH_bits = bitpacked record
  SBR                    : TBits_5;                    // [0:4] UART Baud Rate Bits
  RESERVED0              : TBits_1;                    // [5:5] no description available
  RXEDGIE                : TBits_1;                    // [6:6] RxD Input Active Edge Interrupt Enable
  LBKDIE                 : TBits_1;                    // [7:7] LIN Break Detect Interrupt Enable
end;

TUART0_BDH_bitbanded = record
  SBR                    : array[0..4] of longWord;    // [0:4] UART Baud Rate Bits
  RESERVED0              : longWord;                   // [5:5] no description available
  RXEDGIE                : longWord;                   // [6:6] RxD Input Active Edge Interrupt Enable
  LBKDIE                 : longWord;                   // [7:7] LIN Break Detect Interrupt Enable
end;

TUART0_BDL_bits = bitpacked record
  SBR                    : TBits_8;                    // [0:7] UART Baud Rate Bits
end;

TUART0_BDL_bitbanded = record
  SBR                    : array[0..7] of longWord;    // [0:7] UART Baud Rate Bits
end;

TUART0_C1_bits = bitpacked record
  PT                     : TBits_1;                    // [0:0] Parity Type
  PE                     : TBits_1;                    // [1:1] Parity Enable
  ILT                    : TBits_1;                    // [2:2] Idle Line Type Select
  WAKE                   : TBits_1;                    // [3:3] Receiver Wakeup Method Select
  M                      : TBits_1;                    // [4:4] 9-bit or 8-bit Mode Select
  RSRC                   : TBits_1;                    // [5:5] Receiver Source Select
  UARTSWAI               : TBits_1;                    // [6:6] UART Stops in Wait Mode
  LOOPS                  : TBits_1;                    // [7:7] Loop Mode Select
end;

TUART0_C1_bitbanded = record
  PT                     : longWord;                   // [0:0] Parity Type
  PE                     : longWord;                   // [1:1] Parity Enable
  ILT                    : longWord;                   // [2:2] Idle Line Type Select
  WAKE                   : longWord;                   // [3:3] Receiver Wakeup Method Select
  M                      : longWord;                   // [4:4] 9-bit or 8-bit Mode Select
  RSRC                   : longWord;                   // [5:5] Receiver Source Select
  UARTSWAI               : longWord;                   // [6:6] UART Stops in Wait Mode
  LOOPS                  : longWord;                   // [7:7] Loop Mode Select
end;

TUART0_C2_bits = bitpacked record
  SBK                    : TBits_1;                    // [0:0] Send Break
  RWU                    : TBits_1;                    // [1:1] Receiver Wakeup Control
  RE                     : TBits_1;                    // [2:2] Receiver Enable
  TE                     : TBits_1;                    // [3:3] Transmitter Enable
  ILIE                   : TBits_1;                    // [4:4] Idle Line Interrupt Enable
  RIE                    : TBits_1;                    // [5:5] Receiver Full Interrupt or DMA Transfer Enable
  TCIE                   : TBits_1;                    // [6:6] Transmission Complete Interrupt Enable
  TIE                    : TBits_1;                    // [7:7] Transmitter Interrupt or DMA Transfer Enable.
end;

TUART0_C2_bitbanded = record
  SBK                    : longWord;                   // [0:0] Send Break
  RWU                    : longWord;                   // [1:1] Receiver Wakeup Control
  RE                     : longWord;                   // [2:2] Receiver Enable
  TE                     : longWord;                   // [3:3] Transmitter Enable
  ILIE                   : longWord;                   // [4:4] Idle Line Interrupt Enable
  RIE                    : longWord;                   // [5:5] Receiver Full Interrupt or DMA Transfer Enable
  TCIE                   : longWord;                   // [6:6] Transmission Complete Interrupt Enable
  TIE                    : longWord;                   // [7:7] Transmitter Interrupt or DMA Transfer Enable.
end;

TUART0_S1_bits = bitpacked record
  PF                     : TBits_1;                    // [0:0] Parity Error Flag
  FE                     : TBits_1;                    // [1:1] Framing Error Flag
  NF                     : TBits_1;                    // [2:2] Noise Flag
  &OR                    : TBits_1;                    // [3:3] Receiver Overrun Flag
  IDLE                   : TBits_1;                    // [4:4] Idle Line Flag
  RDRF                   : TBits_1;                    // [5:5] Receive Data Register Full Flag
  TC                     : TBits_1;                    // [6:6] Transmit Complete Flag
  TDRE                   : TBits_1;                    // [7:7] Transmit Data Register Empty Flag
end;

TUART0_S1_bitbanded = record
  PF                     : longWord;                   // [0:0] Parity Error Flag
  FE                     : longWord;                   // [1:1] Framing Error Flag
  NF                     : longWord;                   // [2:2] Noise Flag
  &OR                    : longWord;                   // [3:3] Receiver Overrun Flag
  IDLE                   : longWord;                   // [4:4] Idle Line Flag
  RDRF                   : longWord;                   // [5:5] Receive Data Register Full Flag
  TC                     : longWord;                   // [6:6] Transmit Complete Flag
  TDRE                   : longWord;                   // [7:7] Transmit Data Register Empty Flag
end;

TUART0_S2_bits = bitpacked record
  RAF                    : TBits_1;                    // [0:0] Receiver Active Flag
  LBKDE                  : TBits_1;                    // [1:1] LIN Break Detection Enable
  BRK13                  : TBits_1;                    // [2:2] Break Transmit Character Length
  RWUID                  : TBits_1;                    // [3:3] Receive Wakeup Idle Detect
  RXINV                  : TBits_1;                    // [4:4] Receive Data Inversion
  MSBF                   : TBits_1;                    // [5:5] Most Significant Bit First
  RXEDGIF                : TBits_1;                    // [6:6] RxD Pin Active Edge Interrupt Flag
  LBKDIF                 : TBits_1;                    // [7:7] LIN Break Detect Interrupt Flag
end;

TUART0_S2_bitbanded = record
  RAF                    : longWord;                   // [0:0] Receiver Active Flag
  LBKDE                  : longWord;                   // [1:1] LIN Break Detection Enable
  BRK13                  : longWord;                   // [2:2] Break Transmit Character Length
  RWUID                  : longWord;                   // [3:3] Receive Wakeup Idle Detect
  RXINV                  : longWord;                   // [4:4] Receive Data Inversion
  MSBF                   : longWord;                   // [5:5] Most Significant Bit First
  RXEDGIF                : longWord;                   // [6:6] RxD Pin Active Edge Interrupt Flag
  LBKDIF                 : longWord;                   // [7:7] LIN Break Detect Interrupt Flag
end;

TUART0_C3_bits = bitpacked record
  PEIE                   : TBits_1;                    // [0:0] Parity Error Interrupt Enable
  FEIE                   : TBits_1;                    // [1:1] Framing Error Interrupt Enable
  NEIE                   : TBits_1;                    // [2:2] Noise Error Interrupt Enable
  ORIE                   : TBits_1;                    // [3:3] Overrun Error Interrupt Enable
  TXINV                  : TBits_1;                    // [4:4] Transmit Data Inversion.
  TXDIR                  : TBits_1;                    // [5:5] Transmitter Pin Data Direction in Single-Wire mode
  T8                     : TBits_1;                    // [6:6] Transmit Bit 8
  R8                     : TBits_1;                    // [7:7] Received Bit 8
end;

TUART0_C3_bitbanded = record
  PEIE                   : longWord;                   // [0:0] Parity Error Interrupt Enable
  FEIE                   : longWord;                   // [1:1] Framing Error Interrupt Enable
  NEIE                   : longWord;                   // [2:2] Noise Error Interrupt Enable
  ORIE                   : longWord;                   // [3:3] Overrun Error Interrupt Enable
  TXINV                  : longWord;                   // [4:4] Transmit Data Inversion.
  TXDIR                  : longWord;                   // [5:5] Transmitter Pin Data Direction in Single-Wire mode
  T8                     : longWord;                   // [6:6] Transmit Bit 8
  R8                     : longWord;                   // [7:7] Received Bit 8
end;

TUART0_D_bits = bitpacked record
  RT                     : TBits_8;                    // [0:7] no description available
end;

TUART0_D_bitbanded = record
  RT                     : array[0..7] of longWord;    // [0:7] no description available
end;

TUART0_MA1_bits = bitpacked record
  MA                     : TBits_8;                    // [0:7] Match Address
end;

TUART0_MA1_bitbanded = record
  MA                     : array[0..7] of longWord;    // [0:7] Match Address
end;

TUART0_MA2_bits = bitpacked record
  MA                     : TBits_8;                    // [0:7] Match Address
end;

TUART0_MA2_bitbanded = record
  MA                     : array[0..7] of longWord;    // [0:7] Match Address
end;

TUART0_C4_bits = bitpacked record
  BRFA                   : TBits_5;                    // [0:4] Baud Rate Fine Adjust
  M10                    : TBits_1;                    // [5:5] 10-bit Mode select
  MAEN2                  : TBits_1;                    // [6:6] Match Address Mode Enable 2
  MAEN1                  : TBits_1;                    // [7:7] Match Address Mode Enable 1
end;

TUART0_C4_bitbanded = record
  BRFA                   : array[0..4] of longWord;    // [0:4] Baud Rate Fine Adjust
  M10                    : longWord;                   // [5:5] 10-bit Mode select
  MAEN2                  : longWord;                   // [6:6] Match Address Mode Enable 2
  MAEN1                  : longWord;                   // [7:7] Match Address Mode Enable 1
end;

TUART0_C5_bits = bitpacked record
  RESERVED0              : TBits_5;                    // [0:4] no description available
  RDMAS                  : TBits_1;                    // [5:5] Receiver Full DMA Select
  RESERVED1              : TBits_1;                    // [6:6] no description available
  TDMAS                  : TBits_1;                    // [7:7] Transmitter DMA Select
end;

TUART0_C5_bitbanded = record
  RESERVED0              : array[0..4] of longWord;    // [0:4] no description available
  RDMAS                  : longWord;                   // [5:5] Receiver Full DMA Select
  RESERVED1              : longWord;                   // [6:6] no description available
  TDMAS                  : longWord;                   // [7:7] Transmitter DMA Select
end;

TUART0_ED_bits = bitpacked record
  RESERVED0              : TBits_6;                    // [0:5] no description available
  PARITYE                : TBits_1;                    // [6:6] no description available
  NOISY                  : TBits_1;                    // [7:7] no description available
end;

TUART0_ED_bitbanded = record
  RESERVED0              : array[0..5] of longWord;    // [0:5] no description available
  PARITYE                : longWord;                   // [6:6] no description available
  NOISY                  : longWord;                   // [7:7] no description available
end;

TUART0_MODEM_bits = bitpacked record
  TXCTSE                 : TBits_1;                    // [0:0] Transmitter clear-to-send enable
  TXRTSE                 : TBits_1;                    // [1:1] Transmitter request-to-send enable
  TXRTSPOL               : TBits_1;                    // [2:2] Transmitter request-to-send polarity
  RXRTSE                 : TBits_1;                    // [3:3] Receiver request-to-send enable
  RESERVED0              : TBits_4;                    // [4:7] no description available
end;

TUART0_MODEM_bitbanded = record
  TXCTSE                 : longWord;                   // [0:0] Transmitter clear-to-send enable
  TXRTSE                 : longWord;                   // [1:1] Transmitter request-to-send enable
  TXRTSPOL               : longWord;                   // [2:2] Transmitter request-to-send polarity
  RXRTSE                 : longWord;                   // [3:3] Receiver request-to-send enable
  RESERVED0              : array[0..3] of longWord;    // [4:7] no description available
end;

TUART0_IR_bits = bitpacked record
  TNP                    : TBits_2;                    // [0:1] Transmitter narrow pulse
  IREN                   : TBits_1;                    // [2:2] Infrared enable
  RESERVED0              : TBits_5;                    // [3:7] no description available
end;

TUART0_IR_bitbanded = record
  TNP                    : array[0..1] of longWord;    // [0:1] Transmitter narrow pulse
  IREN                   : longWord;                   // [2:2] Infrared enable
  RESERVED0              : array[0..4] of longWord;    // [3:7] no description available
end;

TUART0_PFIFO_bits = bitpacked record
  RXFIFOSIZE             : TBits_3;                    // [0:2] Receive FIFO. Buffer Depth
  RXFE                   : TBits_1;                    // [3:3] Receive FIFO Enable
  TXFIFOSIZE             : TBits_3;                    // [4:6] Transmit FIFO. Buffer Depth
  TXFE                   : TBits_1;                    // [7:7] Transmit FIFO Enable
end;

TUART0_PFIFO_bitbanded = record
  RXFIFOSIZE             : array[0..2] of longWord;    // [0:2] Receive FIFO. Buffer Depth
  RXFE                   : longWord;                   // [3:3] Receive FIFO Enable
  TXFIFOSIZE             : array[0..2] of longWord;    // [4:6] Transmit FIFO. Buffer Depth
  TXFE                   : longWord;                   // [7:7] Transmit FIFO Enable
end;

TUART0_CFIFO_bits = bitpacked record
  RXUFE                  : TBits_1;                    // [0:0] Receive FIFO Underflow Interrupt Enable
  TXOFE                  : TBits_1;                    // [1:1] Transmit FIFO Overflow Interrupt Enable
  RESERVED0              : TBits_4;                    // [2:5] no description available
  RXFLUSH                : TBits_1;                    // [6:6] Receive FIFO/Buffer Flush
  TXFLUSH                : TBits_1;                    // [7:7] Transmit FIFO/Buffer Flush
end;

TUART0_CFIFO_bitbanded = record
  RXUFE                  : longWord;                   // [0:0] Receive FIFO Underflow Interrupt Enable
  TXOFE                  : longWord;                   // [1:1] Transmit FIFO Overflow Interrupt Enable
  RESERVED0              : array[0..3] of longWord;    // [2:5] no description available
  RXFLUSH                : longWord;                   // [6:6] Receive FIFO/Buffer Flush
  TXFLUSH                : longWord;                   // [7:7] Transmit FIFO/Buffer Flush
end;

TUART0_SFIFO_bits = bitpacked record
  RXUF                   : TBits_1;                    // [0:0] Receiver Buffer Underflow Flag
  TXOF                   : TBits_1;                    // [1:1] Transmitter Buffer Overflow Flag
  RESERVED0              : TBits_4;                    // [2:5] no description available
  RXEMPT                 : TBits_1;                    // [6:6] Receive Buffer/FIFO Empty
  TXEMPT                 : TBits_1;                    // [7:7] Transmit Buffer/FIFO Empty
end;

TUART0_SFIFO_bitbanded = record
  RXUF                   : longWord;                   // [0:0] Receiver Buffer Underflow Flag
  TXOF                   : longWord;                   // [1:1] Transmitter Buffer Overflow Flag
  RESERVED0              : array[0..3] of longWord;    // [2:5] no description available
  RXEMPT                 : longWord;                   // [6:6] Receive Buffer/FIFO Empty
  TXEMPT                 : longWord;                   // [7:7] Transmit Buffer/FIFO Empty
end;

TUART0_TWFIFO_bits = bitpacked record
  TXWATER                : TBits_8;                    // [0:7] Transmit Watermark
end;

TUART0_TWFIFO_bitbanded = record
  TXWATER                : array[0..7] of longWord;    // [0:7] Transmit Watermark
end;

TUART0_TCFIFO_bits = bitpacked record
  TXCOUNT                : TBits_8;                    // [0:7] Transmit Counter
end;

TUART0_TCFIFO_bitbanded = record
  TXCOUNT                : array[0..7] of longWord;    // [0:7] Transmit Counter
end;

TUART0_RWFIFO_bits = bitpacked record
  RXWATER                : TBits_8;                    // [0:7] Receive Watermark
end;

TUART0_RWFIFO_bitbanded = record
  RXWATER                : array[0..7] of longWord;    // [0:7] Receive Watermark
end;

TUART0_RCFIFO_bits = bitpacked record
  RXCOUNT                : TBits_8;                    // [0:7] Receive Counter
end;

TUART0_RCFIFO_bitbanded = record
  RXCOUNT                : array[0..7] of longWord;    // [0:7] Receive Counter
end;

TUART0_C7816_bits = bitpacked record
  ISO_7816E              : TBits_1;                    // [0:0] ISO-7816 Functionality Enabled
  TTYPE                  : TBits_1;                    // [1:1] Transfer Type
  INIT                   : TBits_1;                    // [2:2] Detect Initial Character
  ANACK                  : TBits_1;                    // [3:3] Generate NACK on Error
  ONACK                  : TBits_1;                    // [4:4] Generate NACK on Overflow
  RESERVED0              : TBits_3;                    // [5:7] no description available
end;

TUART0_C7816_bitbanded = record
  ISO_7816E              : longWord;                   // [0:0] ISO-7816 Functionality Enabled
  TTYPE                  : longWord;                   // [1:1] Transfer Type
  INIT                   : longWord;                   // [2:2] Detect Initial Character
  ANACK                  : longWord;                   // [3:3] Generate NACK on Error
  ONACK                  : longWord;                   // [4:4] Generate NACK on Overflow
  RESERVED0              : array[0..2] of longWord;    // [5:7] no description available
end;

TUART0_IE7816_bits = bitpacked record
  RXTE                   : TBits_1;                    // [0:0] Receive Threshold Exceeded Interrupt Enable
  TXTE                   : TBits_1;                    // [1:1] Transmit Threshold Exceeded Interrupt Enable
  GTVE                   : TBits_1;                    // [2:2] Guard Timer Violated Interrupt Enable
  RESERVED0              : TBits_1;                    // [3:3] no description available
  INITDE                 : TBits_1;                    // [4:4] Initial Character Detected Interrupt Enable
  BWTE                   : TBits_1;                    // [5:5] Block Wait Timer Interrupt Enable
  CWTE                   : TBits_1;                    // [6:6] Character Wait Timer Interrupt Enable
  WTE                    : TBits_1;                    // [7:7] Wait Timer Interrupt Enable
end;

TUART0_IE7816_bitbanded = record
  RXTE                   : longWord;                   // [0:0] Receive Threshold Exceeded Interrupt Enable
  TXTE                   : longWord;                   // [1:1] Transmit Threshold Exceeded Interrupt Enable
  GTVE                   : longWord;                   // [2:2] Guard Timer Violated Interrupt Enable
  RESERVED0              : longWord;                   // [3:3] no description available
  INITDE                 : longWord;                   // [4:4] Initial Character Detected Interrupt Enable
  BWTE                   : longWord;                   // [5:5] Block Wait Timer Interrupt Enable
  CWTE                   : longWord;                   // [6:6] Character Wait Timer Interrupt Enable
  WTE                    : longWord;                   // [7:7] Wait Timer Interrupt Enable
end;

TUART0_IS7816_bits = bitpacked record
  RXT                    : TBits_1;                    // [0:0] Receive Threshold Exceeded Interrupt
  TXT                    : TBits_1;                    // [1:1] Transmit Threshold Exceeded Interrupt
  GTV                    : TBits_1;                    // [2:2] Guard Timer Violated Interrupt
  RESERVED0              : TBits_1;                    // [3:3] no description available
  INITD                  : TBits_1;                    // [4:4] Initial Character Detected Interrupt
  BWT                    : TBits_1;                    // [5:5] Block Wait Timer Interrupt
  CWT                    : TBits_1;                    // [6:6] Character Wait Timer Interrupt
  WT                     : TBits_1;                    // [7:7] Wait Timer Interrupt
end;

TUART0_IS7816_bitbanded = record
  RXT                    : longWord;                   // [0:0] Receive Threshold Exceeded Interrupt
  TXT                    : longWord;                   // [1:1] Transmit Threshold Exceeded Interrupt
  GTV                    : longWord;                   // [2:2] Guard Timer Violated Interrupt
  RESERVED0              : longWord;                   // [3:3] no description available
  INITD                  : longWord;                   // [4:4] Initial Character Detected Interrupt
  BWT                    : longWord;                   // [5:5] Block Wait Timer Interrupt
  CWT                    : longWord;                   // [6:6] Character Wait Timer Interrupt
  WT                     : longWord;                   // [7:7] Wait Timer Interrupt
end;

TUART0_WP7816T1_bits = bitpacked record
  BWI                    : TBits_4;                    // [0:3] Block Wait Time Integer(C7816[TTYPE] = 1)
  CWI                    : TBits_4;                    // [4:7] Character Wait Time Integer (C7816[TTYPE] = 1)
end;

TUART0_WP7816T1_bitbanded = record
  BWI                    : array[0..3] of longWord;    // [0:3] Block Wait Time Integer(C7816[TTYPE] = 1)
  CWI                    : array[0..3] of longWord;    // [4:7] Character Wait Time Integer (C7816[TTYPE] = 1)
end;

TUART0_WP7816T0_bits = bitpacked record
  WI                     : TBits_8;                    // [0:7] Wait Timer Interrupt (C7816[TTYPE] = 0)
end;

TUART0_WP7816T0_bitbanded = record
  WI                     : array[0..7] of longWord;    // [0:7] Wait Timer Interrupt (C7816[TTYPE] = 0)
end;

TUART0_WN7816_bits = bitpacked record
  GTN                    : TBits_8;                    // [0:7] Guard Band N
end;

TUART0_WN7816_bitbanded = record
  GTN                    : array[0..7] of longWord;    // [0:7] Guard Band N
end;

TUART0_WF7816_bits = bitpacked record
  GTFD                   : TBits_8;                    // [0:7] FD Multiplier
end;

TUART0_WF7816_bitbanded = record
  GTFD                   : array[0..7] of longWord;    // [0:7] FD Multiplier
end;

TUART0_ET7816_bits = bitpacked record
  RXTHRESHOLD            : TBits_4;                    // [0:3] Receive NACK Threshold
  TXTHRESHOLD            : TBits_4;                    // [4:7] Transmit NACK Threshold
end;

TUART0_ET7816_bitbanded = record
  RXTHRESHOLD            : array[0..3] of longWord;    // [0:3] Receive NACK Threshold
  TXTHRESHOLD            : array[0..3] of longWord;    // [4:7] Transmit NACK Threshold
end;

TUART0_TL7816_bits = bitpacked record
  TLEN                   : TBits_8;                    // [0:7] Transmit Length
end;

TUART0_TL7816_bitbanded = record
  TLEN                   : array[0..7] of longWord;    // [0:7] Transmit Length
end;

TUART0_Registers = record
  case boolean of false: (
  BDH                    : byte;                       // 0x00 UART Baud Rate Registers:High
  BDL                    : byte;                       // 0x01 UART Baud Rate Registers: Low
  C1                     : byte;                       // 0x02 UART Control Register 1
  C2                     : byte;                       // 0x03 UART Control Register 2
  S1                     : byte;                       // 0x04 UART Status Register 1
  S2                     : byte;                       // 0x05 UART Status Register 2
  C3                     : byte;                       // 0x06 UART Control Register 3
  D                      : byte;                       // 0x07 UART Data Register
  MA1                    : byte;                       // 0x08 UART Match Address Registers 1
  MA2                    : byte;                       // 0x09 UART Match Address Registers 2
  C4                     : byte;                       // 0x0A UART Control Register 4
  C5                     : byte;                       // 0x0B UART Control Register 5
  ED                     : byte;                       // 0x0C UART Extended Data Register
  MODEM                  : byte;                       // 0x0D UART Modem Register
  IR                     : byte;                       // 0x0E UART Infrared Register
  RESERVED0              : byte;                       // 0x0F
  PFIFO                  : byte;                       // 0x10 UART FIFO Parameters
  CFIFO                  : byte;                       // 0x11 UART FIFO Control Register
  SFIFO                  : byte;                       // 0x12 UART FIFO Status Register
  TWFIFO                 : byte;                       // 0x13 UART FIFO Transmit Watermark
  TCFIFO                 : byte;                       // 0x14 UART FIFO Transmit Count
  RWFIFO                 : byte;                       // 0x15 UART FIFO Receive Watermark
  RCFIFO                 : byte;                       // 0x16 UART FIFO Receive Count
  RESERVED1              : byte;                       // 0x17
  C7816                  : byte;                       // 0x18 UART 7816 Control Register
  IE7816                 : byte;                       // 0x19 UART 7816 Interrupt Enable Register
  IS7816                 : byte;                       // 0x1A UART 7816 Interrupt Status Register
  WP7816T0               : byte;                       // 0x1B UART 7816 Wait Parameter Register
  WN7816                 : byte;                       // 0x1C UART 7816 Wait N Register
  WF7816                 : byte;                       // 0x1D UART 7816 Wait FD Register
  ET7816                 : byte;                       // 0x1E UART 7816 Error Threshold Register
  TL7816                 : byte;                       // 0x1F UART 7816 Transmit Length Register
);
true : (
BDH_bits                 : TUART0_BDH_bits;            // 0x01 UART Baud Rate Registers:High
BDL_bits                 : TUART0_BDL_bits;            // 0x02 UART Baud Rate Registers: Low
C1_bits                  : TUART0_C1_bits;             // 0x03 UART Control Register 1
C2_bits                  : TUART0_C2_bits;             // 0x04 UART Control Register 2
S1_bits                  : TUART0_S1_bits;             // 0x05 UART Status Register 1
S2_bits                  : TUART0_S2_bits;             // 0x06 UART Status Register 2
C3_bits                  : TUART0_C3_bits;             // 0x07 UART Control Register 3
D_bits                   : TUART0_D_bits;              // 0x08 UART Data Register
MA1_bits                 : TUART0_MA1_bits;            // 0x09 UART Match Address Registers 1
MA2_bits                 : TUART0_MA2_bits;            // 0x0A UART Match Address Registers 2
C4_bits                  : TUART0_C4_bits;             // 0x0B UART Control Register 4
C5_bits                  : TUART0_C5_bits;             // 0x0C UART Control Register 5
ED_bits                  : TUART0_ED_bits;             // 0x0D UART Extended Data Register
MODEM_bits               : TUART0_MODEM_bits;          // 0x0E UART Modem Register
IR_bits                  : TUART0_IR_bits;             // 0x0F UART Infrared Register
RESERVED_bits0           : byte;
PFIFO_bits               : TUART0_PFIFO_bits;          // 0x11 UART FIFO Parameters
CFIFO_bits               : TUART0_CFIFO_bits;          // 0x12 UART FIFO Control Register
SFIFO_bits               : TUART0_SFIFO_bits;          // 0x13 UART FIFO Status Register
TWFIFO_bits              : TUART0_TWFIFO_bits;         // 0x14 UART FIFO Transmit Watermark
TCFIFO_bits              : TUART0_TCFIFO_bits;         // 0x15 UART FIFO Transmit Count
RWFIFO_bits              : TUART0_RWFIFO_bits;         // 0x16 UART FIFO Receive Watermark
RCFIFO_bits              : TUART0_RCFIFO_bits;         // 0x17 UART FIFO Receive Count
RESERVED_bits1           : byte;
C7816_bits               : TUART0_C7816_bits;          // 0x19 UART 7816 Control Register
IE7816_bits              : TUART0_IE7816_bits;         // 0x1A UART 7816 Interrupt Enable Register
IS7816_bits              : TUART0_IS7816_bits;         // 0x1B UART 7816 Interrupt Status Register
WP7816T0_bits            : TUART0_WP7816T0_bits;       // 0x1C UART 7816 Wait Parameter Register
WN7816_bits              : TUART0_WN7816_bits;         // 0x1D UART 7816 Wait N Register
WF7816_bits              : TUART0_WF7816_bits;         // 0x1E UART 7816 Wait FD Register
ET7816_bits              : TUART0_ET7816_bits;         // 0x1F UART 7816 Error Threshold Register
TL7816_bits              : TUART0_TL7816_bits;         // 0x20 UART 7816 Transmit Length Register
);
end;

TUART0Registers_bitbanded = record
  BDH                    : TUART0_BDH_bitbanded;       // 0x01 UART Baud Rate Registers:High
  BDL                    : TUART0_BDL_bitbanded;       // 0x02 UART Baud Rate Registers: Low
  C1                     : TUART0_C1_bitbanded;        // 0x03 UART Control Register 1
  C2                     : TUART0_C2_bitbanded;        // 0x04 UART Control Register 2
  S1                     : TUART0_S1_bitbanded;        // 0x05 UART Status Register 1
  S2                     : TUART0_S2_bitbanded;        // 0x06 UART Status Register 2
  C3                     : TUART0_C3_bitbanded;        // 0x07 UART Control Register 3
  D                      : TUART0_D_bitbanded;         // 0x08 UART Data Register
  MA1                    : TUART0_MA1_bitbanded;       // 0x09 UART Match Address Registers 1
  MA2                    : TUART0_MA2_bitbanded;       // 0x0A UART Match Address Registers 2
  C4                     : TUART0_C4_bitbanded;        // 0x0B UART Control Register 4
  C5                     : TUART0_C5_bitbanded;        // 0x0C UART Control Register 5
  ED                     : TUART0_ED_bitbanded;        // 0x0D UART Extended Data Register
  MODEM                  : TUART0_MODEM_bitbanded;     // 0x0E UART Modem Register
  IR                     : TUART0_IR_bitbanded;        // 0x0F UART Infrared Register
  RESERVED0              : array[0..7] of longWord;
  PFIFO                  : TUART0_PFIFO_bitbanded;     // 0x11 UART FIFO Parameters
  CFIFO                  : TUART0_CFIFO_bitbanded;     // 0x12 UART FIFO Control Register
  SFIFO                  : TUART0_SFIFO_bitbanded;     // 0x13 UART FIFO Status Register
  TWFIFO                 : TUART0_TWFIFO_bitbanded;    // 0x14 UART FIFO Transmit Watermark
  TCFIFO                 : TUART0_TCFIFO_bitbanded;    // 0x15 UART FIFO Transmit Count
  RWFIFO                 : TUART0_RWFIFO_bitbanded;    // 0x16 UART FIFO Receive Watermark
  RCFIFO                 : TUART0_RCFIFO_bitbanded;    // 0x17 UART FIFO Receive Count
  RESERVED1              : array[0..7] of longWord;
  C7816                  : TUART0_C7816_bitbanded;     // 0x19 UART 7816 Control Register
  IE7816                 : TUART0_IE7816_bitbanded;    // 0x1A UART 7816 Interrupt Enable Register
  IS7816                 : TUART0_IS7816_bitbanded;    // 0x1B UART 7816 Interrupt Status Register
  WP7816T0               : TUART0_WP7816T0_bitbanded;  // 0x1C UART 7816 Wait Parameter Register
  WN7816                 : TUART0_WN7816_bitbanded;    // 0x1D UART 7816 Wait N Register
  WF7816                 : TUART0_WF7816_bitbanded;    // 0x1E UART 7816 Wait FD Register
  ET7816                 : TUART0_ET7816_bitbanded;    // 0x1F UART 7816 Error Threshold Register
  TL7816                 : TUART0_TL7816_bitbanded;    // 0x20 UART 7816 Transmit Length Register
end;

// Serial Communication Interface
TUART1_BDH_bits = bitpacked record
  SBR                    : TBits_5;                    // [0:4] UART Baud Rate Bits
  RESERVED0              : TBits_1;                    // [5:5] no description available
  RXEDGIE                : TBits_1;                    // [6:6] RxD Input Active Edge Interrupt Enable
  LBKDIE                 : TBits_1;                    // [7:7] LIN Break Detect Interrupt Enable
end;

TUART1_BDH_bitbanded = record
  SBR                    : array[0..4] of longWord;    // [0:4] UART Baud Rate Bits
  RESERVED0              : longWord;                   // [5:5] no description available
  RXEDGIE                : longWord;                   // [6:6] RxD Input Active Edge Interrupt Enable
  LBKDIE                 : longWord;                   // [7:7] LIN Break Detect Interrupt Enable
end;

TUART1_BDL_bits = bitpacked record
  SBR                    : TBits_8;                    // [0:7] UART Baud Rate Bits
end;

TUART1_BDL_bitbanded = record
  SBR                    : array[0..7] of longWord;    // [0:7] UART Baud Rate Bits
end;

TUART1_C1_bits = bitpacked record
  PT                     : TBits_1;                    // [0:0] Parity Type
  PE                     : TBits_1;                    // [1:1] Parity Enable
  ILT                    : TBits_1;                    // [2:2] Idle Line Type Select
  WAKE                   : TBits_1;                    // [3:3] Receiver Wakeup Method Select
  M                      : TBits_1;                    // [4:4] 9-bit or 8-bit Mode Select
  RSRC                   : TBits_1;                    // [5:5] Receiver Source Select
  UARTSWAI               : TBits_1;                    // [6:6] UART Stops in Wait Mode
  LOOPS                  : TBits_1;                    // [7:7] Loop Mode Select
end;

TUART1_C1_bitbanded = record
  PT                     : longWord;                   // [0:0] Parity Type
  PE                     : longWord;                   // [1:1] Parity Enable
  ILT                    : longWord;                   // [2:2] Idle Line Type Select
  WAKE                   : longWord;                   // [3:3] Receiver Wakeup Method Select
  M                      : longWord;                   // [4:4] 9-bit or 8-bit Mode Select
  RSRC                   : longWord;                   // [5:5] Receiver Source Select
  UARTSWAI               : longWord;                   // [6:6] UART Stops in Wait Mode
  LOOPS                  : longWord;                   // [7:7] Loop Mode Select
end;

TUART1_C2_bits = bitpacked record
  SBK                    : TBits_1;                    // [0:0] Send Break
  RWU                    : TBits_1;                    // [1:1] Receiver Wakeup Control
  RE                     : TBits_1;                    // [2:2] Receiver Enable
  TE                     : TBits_1;                    // [3:3] Transmitter Enable
  ILIE                   : TBits_1;                    // [4:4] Idle Line Interrupt Enable
  RIE                    : TBits_1;                    // [5:5] Receiver Full Interrupt or DMA Transfer Enable
  TCIE                   : TBits_1;                    // [6:6] Transmission Complete Interrupt Enable
  TIE                    : TBits_1;                    // [7:7] Transmitter Interrupt or DMA Transfer Enable.
end;

TUART1_C2_bitbanded = record
  SBK                    : longWord;                   // [0:0] Send Break
  RWU                    : longWord;                   // [1:1] Receiver Wakeup Control
  RE                     : longWord;                   // [2:2] Receiver Enable
  TE                     : longWord;                   // [3:3] Transmitter Enable
  ILIE                   : longWord;                   // [4:4] Idle Line Interrupt Enable
  RIE                    : longWord;                   // [5:5] Receiver Full Interrupt or DMA Transfer Enable
  TCIE                   : longWord;                   // [6:6] Transmission Complete Interrupt Enable
  TIE                    : longWord;                   // [7:7] Transmitter Interrupt or DMA Transfer Enable.
end;

TUART1_S1_bits = bitpacked record
  PF                     : TBits_1;                    // [0:0] Parity Error Flag
  FE                     : TBits_1;                    // [1:1] Framing Error Flag
  NF                     : TBits_1;                    // [2:2] Noise Flag
  &OR                    : TBits_1;                    // [3:3] Receiver Overrun Flag
  IDLE                   : TBits_1;                    // [4:4] Idle Line Flag
  RDRF                   : TBits_1;                    // [5:5] Receive Data Register Full Flag
  TC                     : TBits_1;                    // [6:6] Transmit Complete Flag
  TDRE                   : TBits_1;                    // [7:7] Transmit Data Register Empty Flag
end;

TUART1_S1_bitbanded = record
  PF                     : longWord;                   // [0:0] Parity Error Flag
  FE                     : longWord;                   // [1:1] Framing Error Flag
  NF                     : longWord;                   // [2:2] Noise Flag
  &OR                    : longWord;                   // [3:3] Receiver Overrun Flag
  IDLE                   : longWord;                   // [4:4] Idle Line Flag
  RDRF                   : longWord;                   // [5:5] Receive Data Register Full Flag
  TC                     : longWord;                   // [6:6] Transmit Complete Flag
  TDRE                   : longWord;                   // [7:7] Transmit Data Register Empty Flag
end;

TUART1_S2_bits = bitpacked record
  RAF                    : TBits_1;                    // [0:0] Receiver Active Flag
  LBKDE                  : TBits_1;                    // [1:1] LIN Break Detection Enable
  BRK13                  : TBits_1;                    // [2:2] Break Transmit Character Length
  RWUID                  : TBits_1;                    // [3:3] Receive Wakeup Idle Detect
  RXINV                  : TBits_1;                    // [4:4] Receive Data Inversion
  MSBF                   : TBits_1;                    // [5:5] Most Significant Bit First
  RXEDGIF                : TBits_1;                    // [6:6] RxD Pin Active Edge Interrupt Flag
  LBKDIF                 : TBits_1;                    // [7:7] LIN Break Detect Interrupt Flag
end;

TUART1_S2_bitbanded = record
  RAF                    : longWord;                   // [0:0] Receiver Active Flag
  LBKDE                  : longWord;                   // [1:1] LIN Break Detection Enable
  BRK13                  : longWord;                   // [2:2] Break Transmit Character Length
  RWUID                  : longWord;                   // [3:3] Receive Wakeup Idle Detect
  RXINV                  : longWord;                   // [4:4] Receive Data Inversion
  MSBF                   : longWord;                   // [5:5] Most Significant Bit First
  RXEDGIF                : longWord;                   // [6:6] RxD Pin Active Edge Interrupt Flag
  LBKDIF                 : longWord;                   // [7:7] LIN Break Detect Interrupt Flag
end;

TUART1_C3_bits = bitpacked record
  PEIE                   : TBits_1;                    // [0:0] Parity Error Interrupt Enable
  FEIE                   : TBits_1;                    // [1:1] Framing Error Interrupt Enable
  NEIE                   : TBits_1;                    // [2:2] Noise Error Interrupt Enable
  ORIE                   : TBits_1;                    // [3:3] Overrun Error Interrupt Enable
  TXINV                  : TBits_1;                    // [4:4] Transmit Data Inversion.
  TXDIR                  : TBits_1;                    // [5:5] Transmitter Pin Data Direction in Single-Wire mode
  T8                     : TBits_1;                    // [6:6] Transmit Bit 8
  R8                     : TBits_1;                    // [7:7] Received Bit 8
end;

TUART1_C3_bitbanded = record
  PEIE                   : longWord;                   // [0:0] Parity Error Interrupt Enable
  FEIE                   : longWord;                   // [1:1] Framing Error Interrupt Enable
  NEIE                   : longWord;                   // [2:2] Noise Error Interrupt Enable
  ORIE                   : longWord;                   // [3:3] Overrun Error Interrupt Enable
  TXINV                  : longWord;                   // [4:4] Transmit Data Inversion.
  TXDIR                  : longWord;                   // [5:5] Transmitter Pin Data Direction in Single-Wire mode
  T8                     : longWord;                   // [6:6] Transmit Bit 8
  R8                     : longWord;                   // [7:7] Received Bit 8
end;

TUART1_D_bits = bitpacked record
  RT                     : TBits_8;                    // [0:7] no description available
end;

TUART1_D_bitbanded = record
  RT                     : array[0..7] of longWord;    // [0:7] no description available
end;

TUART1_MA1_bits = bitpacked record
  MA                     : TBits_8;                    // [0:7] Match Address
end;

TUART1_MA1_bitbanded = record
  MA                     : array[0..7] of longWord;    // [0:7] Match Address
end;

TUART1_MA2_bits = bitpacked record
  MA                     : TBits_8;                    // [0:7] Match Address
end;

TUART1_MA2_bitbanded = record
  MA                     : array[0..7] of longWord;    // [0:7] Match Address
end;

TUART1_C4_bits = bitpacked record
  BRFA                   : TBits_5;                    // [0:4] Baud Rate Fine Adjust
  M10                    : TBits_1;                    // [5:5] 10-bit Mode select
  MAEN2                  : TBits_1;                    // [6:6] Match Address Mode Enable 2
  MAEN1                  : TBits_1;                    // [7:7] Match Address Mode Enable 1
end;

TUART1_C4_bitbanded = record
  BRFA                   : array[0..4] of longWord;    // [0:4] Baud Rate Fine Adjust
  M10                    : longWord;                   // [5:5] 10-bit Mode select
  MAEN2                  : longWord;                   // [6:6] Match Address Mode Enable 2
  MAEN1                  : longWord;                   // [7:7] Match Address Mode Enable 1
end;

TUART1_C5_bits = bitpacked record
  RESERVED0              : TBits_5;                    // [0:4] no description available
  RDMAS                  : TBits_1;                    // [5:5] Receiver Full DMA Select
  RESERVED1              : TBits_1;                    // [6:6] no description available
  TDMAS                  : TBits_1;                    // [7:7] Transmitter DMA Select
end;

TUART1_C5_bitbanded = record
  RESERVED0              : array[0..4] of longWord;    // [0:4] no description available
  RDMAS                  : longWord;                   // [5:5] Receiver Full DMA Select
  RESERVED1              : longWord;                   // [6:6] no description available
  TDMAS                  : longWord;                   // [7:7] Transmitter DMA Select
end;

TUART1_ED_bits = bitpacked record
  RESERVED0              : TBits_6;                    // [0:5] no description available
  PARITYE                : TBits_1;                    // [6:6] no description available
  NOISY                  : TBits_1;                    // [7:7] no description available
end;

TUART1_ED_bitbanded = record
  RESERVED0              : array[0..5] of longWord;    // [0:5] no description available
  PARITYE                : longWord;                   // [6:6] no description available
  NOISY                  : longWord;                   // [7:7] no description available
end;

TUART1_MODEM_bits = bitpacked record
  TXCTSE                 : TBits_1;                    // [0:0] Transmitter clear-to-send enable
  TXRTSE                 : TBits_1;                    // [1:1] Transmitter request-to-send enable
  TXRTSPOL               : TBits_1;                    // [2:2] Transmitter request-to-send polarity
  RXRTSE                 : TBits_1;                    // [3:3] Receiver request-to-send enable
  RESERVED0              : TBits_4;                    // [4:7] no description available
end;

TUART1_MODEM_bitbanded = record
  TXCTSE                 : longWord;                   // [0:0] Transmitter clear-to-send enable
  TXRTSE                 : longWord;                   // [1:1] Transmitter request-to-send enable
  TXRTSPOL               : longWord;                   // [2:2] Transmitter request-to-send polarity
  RXRTSE                 : longWord;                   // [3:3] Receiver request-to-send enable
  RESERVED0              : array[0..3] of longWord;    // [4:7] no description available
end;

TUART1_IR_bits = bitpacked record
  TNP                    : TBits_2;                    // [0:1] Transmitter narrow pulse
  IREN                   : TBits_1;                    // [2:2] Infrared enable
  RESERVED0              : TBits_5;                    // [3:7] no description available
end;

TUART1_IR_bitbanded = record
  TNP                    : array[0..1] of longWord;    // [0:1] Transmitter narrow pulse
  IREN                   : longWord;                   // [2:2] Infrared enable
  RESERVED0              : array[0..4] of longWord;    // [3:7] no description available
end;

TUART1_PFIFO_bits = bitpacked record
  RXFIFOSIZE             : TBits_3;                    // [0:2] Receive FIFO. Buffer Depth
  RXFE                   : TBits_1;                    // [3:3] Receive FIFO Enable
  TXFIFOSIZE             : TBits_3;                    // [4:6] Transmit FIFO. Buffer Depth
  TXFE                   : TBits_1;                    // [7:7] Transmit FIFO Enable
end;

TUART1_PFIFO_bitbanded = record
  RXFIFOSIZE             : array[0..2] of longWord;    // [0:2] Receive FIFO. Buffer Depth
  RXFE                   : longWord;                   // [3:3] Receive FIFO Enable
  TXFIFOSIZE             : array[0..2] of longWord;    // [4:6] Transmit FIFO. Buffer Depth
  TXFE                   : longWord;                   // [7:7] Transmit FIFO Enable
end;

TUART1_CFIFO_bits = bitpacked record
  RXUFE                  : TBits_1;                    // [0:0] Receive FIFO Underflow Interrupt Enable
  TXOFE                  : TBits_1;                    // [1:1] Transmit FIFO Overflow Interrupt Enable
  RESERVED0              : TBits_4;                    // [2:5] no description available
  RXFLUSH                : TBits_1;                    // [6:6] Receive FIFO/Buffer Flush
  TXFLUSH                : TBits_1;                    // [7:7] Transmit FIFO/Buffer Flush
end;

TUART1_CFIFO_bitbanded = record
  RXUFE                  : longWord;                   // [0:0] Receive FIFO Underflow Interrupt Enable
  TXOFE                  : longWord;                   // [1:1] Transmit FIFO Overflow Interrupt Enable
  RESERVED0              : array[0..3] of longWord;    // [2:5] no description available
  RXFLUSH                : longWord;                   // [6:6] Receive FIFO/Buffer Flush
  TXFLUSH                : longWord;                   // [7:7] Transmit FIFO/Buffer Flush
end;

TUART1_SFIFO_bits = bitpacked record
  RXUF                   : TBits_1;                    // [0:0] Receiver Buffer Underflow Flag
  TXOF                   : TBits_1;                    // [1:1] Transmitter Buffer Overflow Flag
  RESERVED0              : TBits_4;                    // [2:5] no description available
  RXEMPT                 : TBits_1;                    // [6:6] Receive Buffer/FIFO Empty
  TXEMPT                 : TBits_1;                    // [7:7] Transmit Buffer/FIFO Empty
end;

TUART1_SFIFO_bitbanded = record
  RXUF                   : longWord;                   // [0:0] Receiver Buffer Underflow Flag
  TXOF                   : longWord;                   // [1:1] Transmitter Buffer Overflow Flag
  RESERVED0              : array[0..3] of longWord;    // [2:5] no description available
  RXEMPT                 : longWord;                   // [6:6] Receive Buffer/FIFO Empty
  TXEMPT                 : longWord;                   // [7:7] Transmit Buffer/FIFO Empty
end;

TUART1_TWFIFO_bits = bitpacked record
  TXWATER                : TBits_8;                    // [0:7] Transmit Watermark
end;

TUART1_TWFIFO_bitbanded = record
  TXWATER                : array[0..7] of longWord;    // [0:7] Transmit Watermark
end;

TUART1_TCFIFO_bits = bitpacked record
  TXCOUNT                : TBits_8;                    // [0:7] Transmit Counter
end;

TUART1_TCFIFO_bitbanded = record
  TXCOUNT                : array[0..7] of longWord;    // [0:7] Transmit Counter
end;

TUART1_RWFIFO_bits = bitpacked record
  RXWATER                : TBits_8;                    // [0:7] Receive Watermark
end;

TUART1_RWFIFO_bitbanded = record
  RXWATER                : array[0..7] of longWord;    // [0:7] Receive Watermark
end;

TUART1_RCFIFO_bits = bitpacked record
  RXCOUNT                : TBits_8;                    // [0:7] Receive Counter
end;

TUART1_RCFIFO_bitbanded = record
  RXCOUNT                : array[0..7] of longWord;    // [0:7] Receive Counter
end;

TUART1_Registers = record
  case boolean of false: (
  BDH                    : byte;                       // 0x00 UART Baud Rate Registers:High
  BDL                    : byte;                       // 0x01 UART Baud Rate Registers: Low
  C1                     : byte;                       // 0x02 UART Control Register 1
  C2                     : byte;                       // 0x03 UART Control Register 2
  S1                     : byte;                       // 0x04 UART Status Register 1
  S2                     : byte;                       // 0x05 UART Status Register 2
  C3                     : byte;                       // 0x06 UART Control Register 3
  D                      : byte;                       // 0x07 UART Data Register
  MA1                    : byte;                       // 0x08 UART Match Address Registers 1
  MA2                    : byte;                       // 0x09 UART Match Address Registers 2
  C4                     : byte;                       // 0x0A UART Control Register 4
  C5                     : byte;                       // 0x0B UART Control Register 5
  ED                     : byte;                       // 0x0C UART Extended Data Register
  MODEM                  : byte;                       // 0x0D UART Modem Register
  IR                     : byte;                       // 0x0E UART Infrared Register
  RESERVED0              : byte;                       // 0x0F
  PFIFO                  : byte;                       // 0x10 UART FIFO Parameters
  CFIFO                  : byte;                       // 0x11 UART FIFO Control Register
  SFIFO                  : byte;                       // 0x12 UART FIFO Status Register
  TWFIFO                 : byte;                       // 0x13 UART FIFO Transmit Watermark
  TCFIFO                 : byte;                       // 0x14 UART FIFO Transmit Count
  RWFIFO                 : byte;                       // 0x15 UART FIFO Receive Watermark
  RCFIFO                 : byte;                       // 0x16 UART FIFO Receive Count
);
true : (
BDH_bits                 : TUART1_BDH_bits;            // 0x01 UART Baud Rate Registers:High
BDL_bits                 : TUART1_BDL_bits;            // 0x02 UART Baud Rate Registers: Low
C1_bits                  : TUART1_C1_bits;             // 0x03 UART Control Register 1
C2_bits                  : TUART1_C2_bits;             // 0x04 UART Control Register 2
S1_bits                  : TUART1_S1_bits;             // 0x05 UART Status Register 1
S2_bits                  : TUART1_S2_bits;             // 0x06 UART Status Register 2
C3_bits                  : TUART1_C3_bits;             // 0x07 UART Control Register 3
D_bits                   : TUART1_D_bits;              // 0x08 UART Data Register
MA1_bits                 : TUART1_MA1_bits;            // 0x09 UART Match Address Registers 1
MA2_bits                 : TUART1_MA2_bits;            // 0x0A UART Match Address Registers 2
C4_bits                  : TUART1_C4_bits;             // 0x0B UART Control Register 4
C5_bits                  : TUART1_C5_bits;             // 0x0C UART Control Register 5
ED_bits                  : TUART1_ED_bits;             // 0x0D UART Extended Data Register
MODEM_bits               : TUART1_MODEM_bits;          // 0x0E UART Modem Register
IR_bits                  : TUART1_IR_bits;             // 0x0F UART Infrared Register
RESERVED_bits0           : byte;
PFIFO_bits               : TUART1_PFIFO_bits;          // 0x11 UART FIFO Parameters
CFIFO_bits               : TUART1_CFIFO_bits;          // 0x12 UART FIFO Control Register
SFIFO_bits               : TUART1_SFIFO_bits;          // 0x13 UART FIFO Status Register
TWFIFO_bits              : TUART1_TWFIFO_bits;         // 0x14 UART FIFO Transmit Watermark
TCFIFO_bits              : TUART1_TCFIFO_bits;         // 0x15 UART FIFO Transmit Count
RWFIFO_bits              : TUART1_RWFIFO_bits;         // 0x16 UART FIFO Receive Watermark
RCFIFO_bits              : TUART1_RCFIFO_bits;         // 0x17 UART FIFO Receive Count
);
end;

TUART1Registers_bitbanded = record
  BDH                    : TUART1_BDH_bitbanded;       // 0x01 UART Baud Rate Registers:High
  BDL                    : TUART1_BDL_bitbanded;       // 0x02 UART Baud Rate Registers: Low
  C1                     : TUART1_C1_bitbanded;        // 0x03 UART Control Register 1
  C2                     : TUART1_C2_bitbanded;        // 0x04 UART Control Register 2
  S1                     : TUART1_S1_bitbanded;        // 0x05 UART Status Register 1
  S2                     : TUART1_S2_bitbanded;        // 0x06 UART Status Register 2
  C3                     : TUART1_C3_bitbanded;        // 0x07 UART Control Register 3
  D                      : TUART1_D_bitbanded;         // 0x08 UART Data Register
  MA1                    : TUART1_MA1_bitbanded;       // 0x09 UART Match Address Registers 1
  MA2                    : TUART1_MA2_bitbanded;       // 0x0A UART Match Address Registers 2
  C4                     : TUART1_C4_bitbanded;        // 0x0B UART Control Register 4
  C5                     : TUART1_C5_bitbanded;        // 0x0C UART Control Register 5
  ED                     : TUART1_ED_bitbanded;        // 0x0D UART Extended Data Register
  MODEM                  : TUART1_MODEM_bitbanded;     // 0x0E UART Modem Register
  IR                     : TUART1_IR_bitbanded;        // 0x0F UART Infrared Register
  RESERVED0              : array[0..7] of longWord;
  PFIFO                  : TUART1_PFIFO_bitbanded;     // 0x11 UART FIFO Parameters
  CFIFO                  : TUART1_CFIFO_bitbanded;     // 0x12 UART FIFO Control Register
  SFIFO                  : TUART1_SFIFO_bitbanded;     // 0x13 UART FIFO Status Register
  TWFIFO                 : TUART1_TWFIFO_bitbanded;    // 0x14 UART FIFO Transmit Watermark
  TCFIFO                 : TUART1_TCFIFO_bitbanded;    // 0x15 UART FIFO Transmit Count
  RWFIFO                 : TUART1_RWFIFO_bitbanded;    // 0x16 UART FIFO Receive Watermark
  RCFIFO                 : TUART1_RCFIFO_bitbanded;    // 0x17 UART FIFO Receive Count
end;

// Serial Communication Interface
TUART2_BDH_bits = bitpacked record
  SBR                    : TBits_5;                    // [0:4] UART Baud Rate Bits
  RESERVED0              : TBits_1;                    // [5:5] no description available
  RXEDGIE                : TBits_1;                    // [6:6] RxD Input Active Edge Interrupt Enable
  LBKDIE                 : TBits_1;                    // [7:7] LIN Break Detect Interrupt Enable
end;

TUART2_BDH_bitbanded = record
  SBR                    : array[0..4] of longWord;    // [0:4] UART Baud Rate Bits
  RESERVED0              : longWord;                   // [5:5] no description available
  RXEDGIE                : longWord;                   // [6:6] RxD Input Active Edge Interrupt Enable
  LBKDIE                 : longWord;                   // [7:7] LIN Break Detect Interrupt Enable
end;

TUART2_BDL_bits = bitpacked record
  SBR                    : TBits_8;                    // [0:7] UART Baud Rate Bits
end;

TUART2_BDL_bitbanded = record
  SBR                    : array[0..7] of longWord;    // [0:7] UART Baud Rate Bits
end;

TUART2_C1_bits = bitpacked record
  PT                     : TBits_1;                    // [0:0] Parity Type
  PE                     : TBits_1;                    // [1:1] Parity Enable
  ILT                    : TBits_1;                    // [2:2] Idle Line Type Select
  WAKE                   : TBits_1;                    // [3:3] Receiver Wakeup Method Select
  M                      : TBits_1;                    // [4:4] 9-bit or 8-bit Mode Select
  RSRC                   : TBits_1;                    // [5:5] Receiver Source Select
  UARTSWAI               : TBits_1;                    // [6:6] UART Stops in Wait Mode
  LOOPS                  : TBits_1;                    // [7:7] Loop Mode Select
end;

TUART2_C1_bitbanded = record
  PT                     : longWord;                   // [0:0] Parity Type
  PE                     : longWord;                   // [1:1] Parity Enable
  ILT                    : longWord;                   // [2:2] Idle Line Type Select
  WAKE                   : longWord;                   // [3:3] Receiver Wakeup Method Select
  M                      : longWord;                   // [4:4] 9-bit or 8-bit Mode Select
  RSRC                   : longWord;                   // [5:5] Receiver Source Select
  UARTSWAI               : longWord;                   // [6:6] UART Stops in Wait Mode
  LOOPS                  : longWord;                   // [7:7] Loop Mode Select
end;

TUART2_C2_bits = bitpacked record
  SBK                    : TBits_1;                    // [0:0] Send Break
  RWU                    : TBits_1;                    // [1:1] Receiver Wakeup Control
  RE                     : TBits_1;                    // [2:2] Receiver Enable
  TE                     : TBits_1;                    // [3:3] Transmitter Enable
  ILIE                   : TBits_1;                    // [4:4] Idle Line Interrupt Enable
  RIE                    : TBits_1;                    // [5:5] Receiver Full Interrupt or DMA Transfer Enable
  TCIE                   : TBits_1;                    // [6:6] Transmission Complete Interrupt Enable
  TIE                    : TBits_1;                    // [7:7] Transmitter Interrupt or DMA Transfer Enable.
end;

TUART2_C2_bitbanded = record
  SBK                    : longWord;                   // [0:0] Send Break
  RWU                    : longWord;                   // [1:1] Receiver Wakeup Control
  RE                     : longWord;                   // [2:2] Receiver Enable
  TE                     : longWord;                   // [3:3] Transmitter Enable
  ILIE                   : longWord;                   // [4:4] Idle Line Interrupt Enable
  RIE                    : longWord;                   // [5:5] Receiver Full Interrupt or DMA Transfer Enable
  TCIE                   : longWord;                   // [6:6] Transmission Complete Interrupt Enable
  TIE                    : longWord;                   // [7:7] Transmitter Interrupt or DMA Transfer Enable.
end;

TUART2_S1_bits = bitpacked record
  PF                     : TBits_1;                    // [0:0] Parity Error Flag
  FE                     : TBits_1;                    // [1:1] Framing Error Flag
  NF                     : TBits_1;                    // [2:2] Noise Flag
  &OR                    : TBits_1;                    // [3:3] Receiver Overrun Flag
  IDLE                   : TBits_1;                    // [4:4] Idle Line Flag
  RDRF                   : TBits_1;                    // [5:5] Receive Data Register Full Flag
  TC                     : TBits_1;                    // [6:6] Transmit Complete Flag
  TDRE                   : TBits_1;                    // [7:7] Transmit Data Register Empty Flag
end;

TUART2_S1_bitbanded = record
  PF                     : longWord;                   // [0:0] Parity Error Flag
  FE                     : longWord;                   // [1:1] Framing Error Flag
  NF                     : longWord;                   // [2:2] Noise Flag
  &OR                    : longWord;                   // [3:3] Receiver Overrun Flag
  IDLE                   : longWord;                   // [4:4] Idle Line Flag
  RDRF                   : longWord;                   // [5:5] Receive Data Register Full Flag
  TC                     : longWord;                   // [6:6] Transmit Complete Flag
  TDRE                   : longWord;                   // [7:7] Transmit Data Register Empty Flag
end;

TUART2_S2_bits = bitpacked record
  RAF                    : TBits_1;                    // [0:0] Receiver Active Flag
  LBKDE                  : TBits_1;                    // [1:1] LIN Break Detection Enable
  BRK13                  : TBits_1;                    // [2:2] Break Transmit Character Length
  RWUID                  : TBits_1;                    // [3:3] Receive Wakeup Idle Detect
  RXINV                  : TBits_1;                    // [4:4] Receive Data Inversion
  MSBF                   : TBits_1;                    // [5:5] Most Significant Bit First
  RXEDGIF                : TBits_1;                    // [6:6] RxD Pin Active Edge Interrupt Flag
  LBKDIF                 : TBits_1;                    // [7:7] LIN Break Detect Interrupt Flag
end;

TUART2_S2_bitbanded = record
  RAF                    : longWord;                   // [0:0] Receiver Active Flag
  LBKDE                  : longWord;                   // [1:1] LIN Break Detection Enable
  BRK13                  : longWord;                   // [2:2] Break Transmit Character Length
  RWUID                  : longWord;                   // [3:3] Receive Wakeup Idle Detect
  RXINV                  : longWord;                   // [4:4] Receive Data Inversion
  MSBF                   : longWord;                   // [5:5] Most Significant Bit First
  RXEDGIF                : longWord;                   // [6:6] RxD Pin Active Edge Interrupt Flag
  LBKDIF                 : longWord;                   // [7:7] LIN Break Detect Interrupt Flag
end;

TUART2_C3_bits = bitpacked record
  PEIE                   : TBits_1;                    // [0:0] Parity Error Interrupt Enable
  FEIE                   : TBits_1;                    // [1:1] Framing Error Interrupt Enable
  NEIE                   : TBits_1;                    // [2:2] Noise Error Interrupt Enable
  ORIE                   : TBits_1;                    // [3:3] Overrun Error Interrupt Enable
  TXINV                  : TBits_1;                    // [4:4] Transmit Data Inversion.
  TXDIR                  : TBits_1;                    // [5:5] Transmitter Pin Data Direction in Single-Wire mode
  T8                     : TBits_1;                    // [6:6] Transmit Bit 8
  R8                     : TBits_1;                    // [7:7] Received Bit 8
end;

TUART2_C3_bitbanded = record
  PEIE                   : longWord;                   // [0:0] Parity Error Interrupt Enable
  FEIE                   : longWord;                   // [1:1] Framing Error Interrupt Enable
  NEIE                   : longWord;                   // [2:2] Noise Error Interrupt Enable
  ORIE                   : longWord;                   // [3:3] Overrun Error Interrupt Enable
  TXINV                  : longWord;                   // [4:4] Transmit Data Inversion.
  TXDIR                  : longWord;                   // [5:5] Transmitter Pin Data Direction in Single-Wire mode
  T8                     : longWord;                   // [6:6] Transmit Bit 8
  R8                     : longWord;                   // [7:7] Received Bit 8
end;

TUART2_D_bits = bitpacked record
  RT                     : TBits_8;                    // [0:7] no description available
end;

TUART2_D_bitbanded = record
  RT                     : array[0..7] of longWord;    // [0:7] no description available
end;

TUART2_MA1_bits = bitpacked record
  MA                     : TBits_8;                    // [0:7] Match Address
end;

TUART2_MA1_bitbanded = record
  MA                     : array[0..7] of longWord;    // [0:7] Match Address
end;

TUART2_MA2_bits = bitpacked record
  MA                     : TBits_8;                    // [0:7] Match Address
end;

TUART2_MA2_bitbanded = record
  MA                     : array[0..7] of longWord;    // [0:7] Match Address
end;

TUART2_C4_bits = bitpacked record
  BRFA                   : TBits_5;                    // [0:4] Baud Rate Fine Adjust
  M10                    : TBits_1;                    // [5:5] 10-bit Mode select
  MAEN2                  : TBits_1;                    // [6:6] Match Address Mode Enable 2
  MAEN1                  : TBits_1;                    // [7:7] Match Address Mode Enable 1
end;

TUART2_C4_bitbanded = record
  BRFA                   : array[0..4] of longWord;    // [0:4] Baud Rate Fine Adjust
  M10                    : longWord;                   // [5:5] 10-bit Mode select
  MAEN2                  : longWord;                   // [6:6] Match Address Mode Enable 2
  MAEN1                  : longWord;                   // [7:7] Match Address Mode Enable 1
end;

TUART2_C5_bits = bitpacked record
  RESERVED0              : TBits_5;                    // [0:4] no description available
  RDMAS                  : TBits_1;                    // [5:5] Receiver Full DMA Select
  RESERVED1              : TBits_1;                    // [6:6] no description available
  TDMAS                  : TBits_1;                    // [7:7] Transmitter DMA Select
end;

TUART2_C5_bitbanded = record
  RESERVED0              : array[0..4] of longWord;    // [0:4] no description available
  RDMAS                  : longWord;                   // [5:5] Receiver Full DMA Select
  RESERVED1              : longWord;                   // [6:6] no description available
  TDMAS                  : longWord;                   // [7:7] Transmitter DMA Select
end;

TUART2_ED_bits = bitpacked record
  RESERVED0              : TBits_6;                    // [0:5] no description available
  PARITYE                : TBits_1;                    // [6:6] no description available
  NOISY                  : TBits_1;                    // [7:7] no description available
end;

TUART2_ED_bitbanded = record
  RESERVED0              : array[0..5] of longWord;    // [0:5] no description available
  PARITYE                : longWord;                   // [6:6] no description available
  NOISY                  : longWord;                   // [7:7] no description available
end;

TUART2_MODEM_bits = bitpacked record
  TXCTSE                 : TBits_1;                    // [0:0] Transmitter clear-to-send enable
  TXRTSE                 : TBits_1;                    // [1:1] Transmitter request-to-send enable
  TXRTSPOL               : TBits_1;                    // [2:2] Transmitter request-to-send polarity
  RXRTSE                 : TBits_1;                    // [3:3] Receiver request-to-send enable
  RESERVED0              : TBits_4;                    // [4:7] no description available
end;

TUART2_MODEM_bitbanded = record
  TXCTSE                 : longWord;                   // [0:0] Transmitter clear-to-send enable
  TXRTSE                 : longWord;                   // [1:1] Transmitter request-to-send enable
  TXRTSPOL               : longWord;                   // [2:2] Transmitter request-to-send polarity
  RXRTSE                 : longWord;                   // [3:3] Receiver request-to-send enable
  RESERVED0              : array[0..3] of longWord;    // [4:7] no description available
end;

TUART2_IR_bits = bitpacked record
  TNP                    : TBits_2;                    // [0:1] Transmitter narrow pulse
  IREN                   : TBits_1;                    // [2:2] Infrared enable
  RESERVED0              : TBits_5;                    // [3:7] no description available
end;

TUART2_IR_bitbanded = record
  TNP                    : array[0..1] of longWord;    // [0:1] Transmitter narrow pulse
  IREN                   : longWord;                   // [2:2] Infrared enable
  RESERVED0              : array[0..4] of longWord;    // [3:7] no description available
end;

TUART2_PFIFO_bits = bitpacked record
  RXFIFOSIZE             : TBits_3;                    // [0:2] Receive FIFO. Buffer Depth
  RXFE                   : TBits_1;                    // [3:3] Receive FIFO Enable
  TXFIFOSIZE             : TBits_3;                    // [4:6] Transmit FIFO. Buffer Depth
  TXFE                   : TBits_1;                    // [7:7] Transmit FIFO Enable
end;

TUART2_PFIFO_bitbanded = record
  RXFIFOSIZE             : array[0..2] of longWord;    // [0:2] Receive FIFO. Buffer Depth
  RXFE                   : longWord;                   // [3:3] Receive FIFO Enable
  TXFIFOSIZE             : array[0..2] of longWord;    // [4:6] Transmit FIFO. Buffer Depth
  TXFE                   : longWord;                   // [7:7] Transmit FIFO Enable
end;

TUART2_CFIFO_bits = bitpacked record
  RXUFE                  : TBits_1;                    // [0:0] Receive FIFO Underflow Interrupt Enable
  TXOFE                  : TBits_1;                    // [1:1] Transmit FIFO Overflow Interrupt Enable
  RESERVED0              : TBits_4;                    // [2:5] no description available
  RXFLUSH                : TBits_1;                    // [6:6] Receive FIFO/Buffer Flush
  TXFLUSH                : TBits_1;                    // [7:7] Transmit FIFO/Buffer Flush
end;

TUART2_CFIFO_bitbanded = record
  RXUFE                  : longWord;                   // [0:0] Receive FIFO Underflow Interrupt Enable
  TXOFE                  : longWord;                   // [1:1] Transmit FIFO Overflow Interrupt Enable
  RESERVED0              : array[0..3] of longWord;    // [2:5] no description available
  RXFLUSH                : longWord;                   // [6:6] Receive FIFO/Buffer Flush
  TXFLUSH                : longWord;                   // [7:7] Transmit FIFO/Buffer Flush
end;

TUART2_SFIFO_bits = bitpacked record
  RXUF                   : TBits_1;                    // [0:0] Receiver Buffer Underflow Flag
  TXOF                   : TBits_1;                    // [1:1] Transmitter Buffer Overflow Flag
  RESERVED0              : TBits_4;                    // [2:5] no description available
  RXEMPT                 : TBits_1;                    // [6:6] Receive Buffer/FIFO Empty
  TXEMPT                 : TBits_1;                    // [7:7] Transmit Buffer/FIFO Empty
end;

TUART2_SFIFO_bitbanded = record
  RXUF                   : longWord;                   // [0:0] Receiver Buffer Underflow Flag
  TXOF                   : longWord;                   // [1:1] Transmitter Buffer Overflow Flag
  RESERVED0              : array[0..3] of longWord;    // [2:5] no description available
  RXEMPT                 : longWord;                   // [6:6] Receive Buffer/FIFO Empty
  TXEMPT                 : longWord;                   // [7:7] Transmit Buffer/FIFO Empty
end;

TUART2_TWFIFO_bits = bitpacked record
  TXWATER                : TBits_8;                    // [0:7] Transmit Watermark
end;

TUART2_TWFIFO_bitbanded = record
  TXWATER                : array[0..7] of longWord;    // [0:7] Transmit Watermark
end;

TUART2_TCFIFO_bits = bitpacked record
  TXCOUNT                : TBits_8;                    // [0:7] Transmit Counter
end;

TUART2_TCFIFO_bitbanded = record
  TXCOUNT                : array[0..7] of longWord;    // [0:7] Transmit Counter
end;

TUART2_RWFIFO_bits = bitpacked record
  RXWATER                : TBits_8;                    // [0:7] Receive Watermark
end;

TUART2_RWFIFO_bitbanded = record
  RXWATER                : array[0..7] of longWord;    // [0:7] Receive Watermark
end;

TUART2_RCFIFO_bits = bitpacked record
  RXCOUNT                : TBits_8;                    // [0:7] Receive Counter
end;

TUART2_RCFIFO_bitbanded = record
  RXCOUNT                : array[0..7] of longWord;    // [0:7] Receive Counter
end;

TUART2_Registers = record
  case boolean of false: (
  BDH                    : byte;                       // 0x00 UART Baud Rate Registers:High
  BDL                    : byte;                       // 0x01 UART Baud Rate Registers: Low
  C1                     : byte;                       // 0x02 UART Control Register 1
  C2                     : byte;                       // 0x03 UART Control Register 2
  S1                     : byte;                       // 0x04 UART Status Register 1
  S2                     : byte;                       // 0x05 UART Status Register 2
  C3                     : byte;                       // 0x06 UART Control Register 3
  D                      : byte;                       // 0x07 UART Data Register
  MA1                    : byte;                       // 0x08 UART Match Address Registers 1
  MA2                    : byte;                       // 0x09 UART Match Address Registers 2
  C4                     : byte;                       // 0x0A UART Control Register 4
  C5                     : byte;                       // 0x0B UART Control Register 5
  ED                     : byte;                       // 0x0C UART Extended Data Register
  MODEM                  : byte;                       // 0x0D UART Modem Register
  IR                     : byte;                       // 0x0E UART Infrared Register
  RESERVED0              : byte;                       // 0x0F
  PFIFO                  : byte;                       // 0x10 UART FIFO Parameters
  CFIFO                  : byte;                       // 0x11 UART FIFO Control Register
  SFIFO                  : byte;                       // 0x12 UART FIFO Status Register
  TWFIFO                 : byte;                       // 0x13 UART FIFO Transmit Watermark
  TCFIFO                 : byte;                       // 0x14 UART FIFO Transmit Count
  RWFIFO                 : byte;                       // 0x15 UART FIFO Receive Watermark
  RCFIFO                 : byte;                       // 0x16 UART FIFO Receive Count
);
true : (
BDH_bits                 : TUART2_BDH_bits;            // 0x01 UART Baud Rate Registers:High
BDL_bits                 : TUART2_BDL_bits;            // 0x02 UART Baud Rate Registers: Low
C1_bits                  : TUART2_C1_bits;             // 0x03 UART Control Register 1
C2_bits                  : TUART2_C2_bits;             // 0x04 UART Control Register 2
S1_bits                  : TUART2_S1_bits;             // 0x05 UART Status Register 1
S2_bits                  : TUART2_S2_bits;             // 0x06 UART Status Register 2
C3_bits                  : TUART2_C3_bits;             // 0x07 UART Control Register 3
D_bits                   : TUART2_D_bits;              // 0x08 UART Data Register
MA1_bits                 : TUART2_MA1_bits;            // 0x09 UART Match Address Registers 1
MA2_bits                 : TUART2_MA2_bits;            // 0x0A UART Match Address Registers 2
C4_bits                  : TUART2_C4_bits;             // 0x0B UART Control Register 4
C5_bits                  : TUART2_C5_bits;             // 0x0C UART Control Register 5
ED_bits                  : TUART2_ED_bits;             // 0x0D UART Extended Data Register
MODEM_bits               : TUART2_MODEM_bits;          // 0x0E UART Modem Register
IR_bits                  : TUART2_IR_bits;             // 0x0F UART Infrared Register
RESERVED_bits0           : byte;
PFIFO_bits               : TUART2_PFIFO_bits;          // 0x11 UART FIFO Parameters
CFIFO_bits               : TUART2_CFIFO_bits;          // 0x12 UART FIFO Control Register
SFIFO_bits               : TUART2_SFIFO_bits;          // 0x13 UART FIFO Status Register
TWFIFO_bits              : TUART2_TWFIFO_bits;         // 0x14 UART FIFO Transmit Watermark
TCFIFO_bits              : TUART2_TCFIFO_bits;         // 0x15 UART FIFO Transmit Count
RWFIFO_bits              : TUART2_RWFIFO_bits;         // 0x16 UART FIFO Receive Watermark
RCFIFO_bits              : TUART2_RCFIFO_bits;         // 0x17 UART FIFO Receive Count
);
end;

TUART2Registers_bitbanded = record
  BDH                    : TUART2_BDH_bitbanded;       // 0x01 UART Baud Rate Registers:High
  BDL                    : TUART2_BDL_bitbanded;       // 0x02 UART Baud Rate Registers: Low
  C1                     : TUART2_C1_bitbanded;        // 0x03 UART Control Register 1
  C2                     : TUART2_C2_bitbanded;        // 0x04 UART Control Register 2
  S1                     : TUART2_S1_bitbanded;        // 0x05 UART Status Register 1
  S2                     : TUART2_S2_bitbanded;        // 0x06 UART Status Register 2
  C3                     : TUART2_C3_bitbanded;        // 0x07 UART Control Register 3
  D                      : TUART2_D_bitbanded;         // 0x08 UART Data Register
  MA1                    : TUART2_MA1_bitbanded;       // 0x09 UART Match Address Registers 1
  MA2                    : TUART2_MA2_bitbanded;       // 0x0A UART Match Address Registers 2
  C4                     : TUART2_C4_bitbanded;        // 0x0B UART Control Register 4
  C5                     : TUART2_C5_bitbanded;        // 0x0C UART Control Register 5
  ED                     : TUART2_ED_bitbanded;        // 0x0D UART Extended Data Register
  MODEM                  : TUART2_MODEM_bitbanded;     // 0x0E UART Modem Register
  IR                     : TUART2_IR_bitbanded;        // 0x0F UART Infrared Register
  RESERVED0              : array[0..7] of longWord;
  PFIFO                  : TUART2_PFIFO_bitbanded;     // 0x11 UART FIFO Parameters
  CFIFO                  : TUART2_CFIFO_bitbanded;     // 0x12 UART FIFO Control Register
  SFIFO                  : TUART2_SFIFO_bitbanded;     // 0x13 UART FIFO Status Register
  TWFIFO                 : TUART2_TWFIFO_bitbanded;    // 0x14 UART FIFO Transmit Watermark
  TCFIFO                 : TUART2_TCFIFO_bitbanded;    // 0x15 UART FIFO Transmit Count
  RWFIFO                 : TUART2_RWFIFO_bitbanded;    // 0x16 UART FIFO Receive Watermark
  RCFIFO                 : TUART2_RCFIFO_bitbanded;    // 0x17 UART FIFO Receive Count
end;

// Serial Communication Interface
TUART3_BDH_bits = bitpacked record
  SBR                    : TBits_5;                    // [0:4] UART Baud Rate Bits
  RESERVED0              : TBits_1;                    // [5:5] no description available
  RXEDGIE                : TBits_1;                    // [6:6] RxD Input Active Edge Interrupt Enable
  LBKDIE                 : TBits_1;                    // [7:7] LIN Break Detect Interrupt Enable
end;

TUART3_BDH_bitbanded = record
  SBR                    : array[0..4] of longWord;    // [0:4] UART Baud Rate Bits
  RESERVED0              : longWord;                   // [5:5] no description available
  RXEDGIE                : longWord;                   // [6:6] RxD Input Active Edge Interrupt Enable
  LBKDIE                 : longWord;                   // [7:7] LIN Break Detect Interrupt Enable
end;

TUART3_BDL_bits = bitpacked record
  SBR                    : TBits_8;                    // [0:7] UART Baud Rate Bits
end;

TUART3_BDL_bitbanded = record
  SBR                    : array[0..7] of longWord;    // [0:7] UART Baud Rate Bits
end;

TUART3_C1_bits = bitpacked record
  PT                     : TBits_1;                    // [0:0] Parity Type
  PE                     : TBits_1;                    // [1:1] Parity Enable
  ILT                    : TBits_1;                    // [2:2] Idle Line Type Select
  WAKE                   : TBits_1;                    // [3:3] Receiver Wakeup Method Select
  M                      : TBits_1;                    // [4:4] 9-bit or 8-bit Mode Select
  RSRC                   : TBits_1;                    // [5:5] Receiver Source Select
  UARTSWAI               : TBits_1;                    // [6:6] UART Stops in Wait Mode
  LOOPS                  : TBits_1;                    // [7:7] Loop Mode Select
end;

TUART3_C1_bitbanded = record
  PT                     : longWord;                   // [0:0] Parity Type
  PE                     : longWord;                   // [1:1] Parity Enable
  ILT                    : longWord;                   // [2:2] Idle Line Type Select
  WAKE                   : longWord;                   // [3:3] Receiver Wakeup Method Select
  M                      : longWord;                   // [4:4] 9-bit or 8-bit Mode Select
  RSRC                   : longWord;                   // [5:5] Receiver Source Select
  UARTSWAI               : longWord;                   // [6:6] UART Stops in Wait Mode
  LOOPS                  : longWord;                   // [7:7] Loop Mode Select
end;

TUART3_C2_bits = bitpacked record
  SBK                    : TBits_1;                    // [0:0] Send Break
  RWU                    : TBits_1;                    // [1:1] Receiver Wakeup Control
  RE                     : TBits_1;                    // [2:2] Receiver Enable
  TE                     : TBits_1;                    // [3:3] Transmitter Enable
  ILIE                   : TBits_1;                    // [4:4] Idle Line Interrupt Enable
  RIE                    : TBits_1;                    // [5:5] Receiver Full Interrupt or DMA Transfer Enable
  TCIE                   : TBits_1;                    // [6:6] Transmission Complete Interrupt Enable
  TIE                    : TBits_1;                    // [7:7] Transmitter Interrupt or DMA Transfer Enable.
end;

TUART3_C2_bitbanded = record
  SBK                    : longWord;                   // [0:0] Send Break
  RWU                    : longWord;                   // [1:1] Receiver Wakeup Control
  RE                     : longWord;                   // [2:2] Receiver Enable
  TE                     : longWord;                   // [3:3] Transmitter Enable
  ILIE                   : longWord;                   // [4:4] Idle Line Interrupt Enable
  RIE                    : longWord;                   // [5:5] Receiver Full Interrupt or DMA Transfer Enable
  TCIE                   : longWord;                   // [6:6] Transmission Complete Interrupt Enable
  TIE                    : longWord;                   // [7:7] Transmitter Interrupt or DMA Transfer Enable.
end;

TUART3_S1_bits = bitpacked record
  PF                     : TBits_1;                    // [0:0] Parity Error Flag
  FE                     : TBits_1;                    // [1:1] Framing Error Flag
  NF                     : TBits_1;                    // [2:2] Noise Flag
  &OR                    : TBits_1;                    // [3:3] Receiver Overrun Flag
  IDLE                   : TBits_1;                    // [4:4] Idle Line Flag
  RDRF                   : TBits_1;                    // [5:5] Receive Data Register Full Flag
  TC                     : TBits_1;                    // [6:6] Transmit Complete Flag
  TDRE                   : TBits_1;                    // [7:7] Transmit Data Register Empty Flag
end;

TUART3_S1_bitbanded = record
  PF                     : longWord;                   // [0:0] Parity Error Flag
  FE                     : longWord;                   // [1:1] Framing Error Flag
  NF                     : longWord;                   // [2:2] Noise Flag
  &OR                    : longWord;                   // [3:3] Receiver Overrun Flag
  IDLE                   : longWord;                   // [4:4] Idle Line Flag
  RDRF                   : longWord;                   // [5:5] Receive Data Register Full Flag
  TC                     : longWord;                   // [6:6] Transmit Complete Flag
  TDRE                   : longWord;                   // [7:7] Transmit Data Register Empty Flag
end;

TUART3_S2_bits = bitpacked record
  RAF                    : TBits_1;                    // [0:0] Receiver Active Flag
  LBKDE                  : TBits_1;                    // [1:1] LIN Break Detection Enable
  BRK13                  : TBits_1;                    // [2:2] Break Transmit Character Length
  RWUID                  : TBits_1;                    // [3:3] Receive Wakeup Idle Detect
  RXINV                  : TBits_1;                    // [4:4] Receive Data Inversion
  MSBF                   : TBits_1;                    // [5:5] Most Significant Bit First
  RXEDGIF                : TBits_1;                    // [6:6] RxD Pin Active Edge Interrupt Flag
  LBKDIF                 : TBits_1;                    // [7:7] LIN Break Detect Interrupt Flag
end;

TUART3_S2_bitbanded = record
  RAF                    : longWord;                   // [0:0] Receiver Active Flag
  LBKDE                  : longWord;                   // [1:1] LIN Break Detection Enable
  BRK13                  : longWord;                   // [2:2] Break Transmit Character Length
  RWUID                  : longWord;                   // [3:3] Receive Wakeup Idle Detect
  RXINV                  : longWord;                   // [4:4] Receive Data Inversion
  MSBF                   : longWord;                   // [5:5] Most Significant Bit First
  RXEDGIF                : longWord;                   // [6:6] RxD Pin Active Edge Interrupt Flag
  LBKDIF                 : longWord;                   // [7:7] LIN Break Detect Interrupt Flag
end;

TUART3_C3_bits = bitpacked record
  PEIE                   : TBits_1;                    // [0:0] Parity Error Interrupt Enable
  FEIE                   : TBits_1;                    // [1:1] Framing Error Interrupt Enable
  NEIE                   : TBits_1;                    // [2:2] Noise Error Interrupt Enable
  ORIE                   : TBits_1;                    // [3:3] Overrun Error Interrupt Enable
  TXINV                  : TBits_1;                    // [4:4] Transmit Data Inversion.
  TXDIR                  : TBits_1;                    // [5:5] Transmitter Pin Data Direction in Single-Wire mode
  T8                     : TBits_1;                    // [6:6] Transmit Bit 8
  R8                     : TBits_1;                    // [7:7] Received Bit 8
end;

TUART3_C3_bitbanded = record
  PEIE                   : longWord;                   // [0:0] Parity Error Interrupt Enable
  FEIE                   : longWord;                   // [1:1] Framing Error Interrupt Enable
  NEIE                   : longWord;                   // [2:2] Noise Error Interrupt Enable
  ORIE                   : longWord;                   // [3:3] Overrun Error Interrupt Enable
  TXINV                  : longWord;                   // [4:4] Transmit Data Inversion.
  TXDIR                  : longWord;                   // [5:5] Transmitter Pin Data Direction in Single-Wire mode
  T8                     : longWord;                   // [6:6] Transmit Bit 8
  R8                     : longWord;                   // [7:7] Received Bit 8
end;

TUART3_D_bits = bitpacked record
  RT                     : TBits_8;                    // [0:7] no description available
end;

TUART3_D_bitbanded = record
  RT                     : array[0..7] of longWord;    // [0:7] no description available
end;

TUART3_MA1_bits = bitpacked record
  MA                     : TBits_8;                    // [0:7] Match Address
end;

TUART3_MA1_bitbanded = record
  MA                     : array[0..7] of longWord;    // [0:7] Match Address
end;

TUART3_MA2_bits = bitpacked record
  MA                     : TBits_8;                    // [0:7] Match Address
end;

TUART3_MA2_bitbanded = record
  MA                     : array[0..7] of longWord;    // [0:7] Match Address
end;

TUART3_C4_bits = bitpacked record
  BRFA                   : TBits_5;                    // [0:4] Baud Rate Fine Adjust
  M10                    : TBits_1;                    // [5:5] 10-bit Mode select
  MAEN2                  : TBits_1;                    // [6:6] Match Address Mode Enable 2
  MAEN1                  : TBits_1;                    // [7:7] Match Address Mode Enable 1
end;

TUART3_C4_bitbanded = record
  BRFA                   : array[0..4] of longWord;    // [0:4] Baud Rate Fine Adjust
  M10                    : longWord;                   // [5:5] 10-bit Mode select
  MAEN2                  : longWord;                   // [6:6] Match Address Mode Enable 2
  MAEN1                  : longWord;                   // [7:7] Match Address Mode Enable 1
end;

TUART3_C5_bits = bitpacked record
  RESERVED0              : TBits_5;                    // [0:4] no description available
  RDMAS                  : TBits_1;                    // [5:5] Receiver Full DMA Select
  RESERVED1              : TBits_1;                    // [6:6] no description available
  TDMAS                  : TBits_1;                    // [7:7] Transmitter DMA Select
end;

TUART3_C5_bitbanded = record
  RESERVED0              : array[0..4] of longWord;    // [0:4] no description available
  RDMAS                  : longWord;                   // [5:5] Receiver Full DMA Select
  RESERVED1              : longWord;                   // [6:6] no description available
  TDMAS                  : longWord;                   // [7:7] Transmitter DMA Select
end;

TUART3_ED_bits = bitpacked record
  RESERVED0              : TBits_6;                    // [0:5] no description available
  PARITYE                : TBits_1;                    // [6:6] no description available
  NOISY                  : TBits_1;                    // [7:7] no description available
end;

TUART3_ED_bitbanded = record
  RESERVED0              : array[0..5] of longWord;    // [0:5] no description available
  PARITYE                : longWord;                   // [6:6] no description available
  NOISY                  : longWord;                   // [7:7] no description available
end;

TUART3_MODEM_bits = bitpacked record
  TXCTSE                 : TBits_1;                    // [0:0] Transmitter clear-to-send enable
  TXRTSE                 : TBits_1;                    // [1:1] Transmitter request-to-send enable
  TXRTSPOL               : TBits_1;                    // [2:2] Transmitter request-to-send polarity
  RXRTSE                 : TBits_1;                    // [3:3] Receiver request-to-send enable
  RESERVED0              : TBits_4;                    // [4:7] no description available
end;

TUART3_MODEM_bitbanded = record
  TXCTSE                 : longWord;                   // [0:0] Transmitter clear-to-send enable
  TXRTSE                 : longWord;                   // [1:1] Transmitter request-to-send enable
  TXRTSPOL               : longWord;                   // [2:2] Transmitter request-to-send polarity
  RXRTSE                 : longWord;                   // [3:3] Receiver request-to-send enable
  RESERVED0              : array[0..3] of longWord;    // [4:7] no description available
end;

TUART3_IR_bits = bitpacked record
  TNP                    : TBits_2;                    // [0:1] Transmitter narrow pulse
  IREN                   : TBits_1;                    // [2:2] Infrared enable
  RESERVED0              : TBits_5;                    // [3:7] no description available
end;

TUART3_IR_bitbanded = record
  TNP                    : array[0..1] of longWord;    // [0:1] Transmitter narrow pulse
  IREN                   : longWord;                   // [2:2] Infrared enable
  RESERVED0              : array[0..4] of longWord;    // [3:7] no description available
end;

TUART3_PFIFO_bits = bitpacked record
  RXFIFOSIZE             : TBits_3;                    // [0:2] Receive FIFO. Buffer Depth
  RXFE                   : TBits_1;                    // [3:3] Receive FIFO Enable
  TXFIFOSIZE             : TBits_3;                    // [4:6] Transmit FIFO. Buffer Depth
  TXFE                   : TBits_1;                    // [7:7] Transmit FIFO Enable
end;

TUART3_PFIFO_bitbanded = record
  RXFIFOSIZE             : array[0..2] of longWord;    // [0:2] Receive FIFO. Buffer Depth
  RXFE                   : longWord;                   // [3:3] Receive FIFO Enable
  TXFIFOSIZE             : array[0..2] of longWord;    // [4:6] Transmit FIFO. Buffer Depth
  TXFE                   : longWord;                   // [7:7] Transmit FIFO Enable
end;

TUART3_CFIFO_bits = bitpacked record
  RXUFE                  : TBits_1;                    // [0:0] Receive FIFO Underflow Interrupt Enable
  TXOFE                  : TBits_1;                    // [1:1] Transmit FIFO Overflow Interrupt Enable
  RESERVED0              : TBits_4;                    // [2:5] no description available
  RXFLUSH                : TBits_1;                    // [6:6] Receive FIFO/Buffer Flush
  TXFLUSH                : TBits_1;                    // [7:7] Transmit FIFO/Buffer Flush
end;

TUART3_CFIFO_bitbanded = record
  RXUFE                  : longWord;                   // [0:0] Receive FIFO Underflow Interrupt Enable
  TXOFE                  : longWord;                   // [1:1] Transmit FIFO Overflow Interrupt Enable
  RESERVED0              : array[0..3] of longWord;    // [2:5] no description available
  RXFLUSH                : longWord;                   // [6:6] Receive FIFO/Buffer Flush
  TXFLUSH                : longWord;                   // [7:7] Transmit FIFO/Buffer Flush
end;

TUART3_SFIFO_bits = bitpacked record
  RXUF                   : TBits_1;                    // [0:0] Receiver Buffer Underflow Flag
  TXOF                   : TBits_1;                    // [1:1] Transmitter Buffer Overflow Flag
  RESERVED0              : TBits_4;                    // [2:5] no description available
  RXEMPT                 : TBits_1;                    // [6:6] Receive Buffer/FIFO Empty
  TXEMPT                 : TBits_1;                    // [7:7] Transmit Buffer/FIFO Empty
end;

TUART3_SFIFO_bitbanded = record
  RXUF                   : longWord;                   // [0:0] Receiver Buffer Underflow Flag
  TXOF                   : longWord;                   // [1:1] Transmitter Buffer Overflow Flag
  RESERVED0              : array[0..3] of longWord;    // [2:5] no description available
  RXEMPT                 : longWord;                   // [6:6] Receive Buffer/FIFO Empty
  TXEMPT                 : longWord;                   // [7:7] Transmit Buffer/FIFO Empty
end;

TUART3_TWFIFO_bits = bitpacked record
  TXWATER                : TBits_8;                    // [0:7] Transmit Watermark
end;

TUART3_TWFIFO_bitbanded = record
  TXWATER                : array[0..7] of longWord;    // [0:7] Transmit Watermark
end;

TUART3_TCFIFO_bits = bitpacked record
  TXCOUNT                : TBits_8;                    // [0:7] Transmit Counter
end;

TUART3_TCFIFO_bitbanded = record
  TXCOUNT                : array[0..7] of longWord;    // [0:7] Transmit Counter
end;

TUART3_RWFIFO_bits = bitpacked record
  RXWATER                : TBits_8;                    // [0:7] Receive Watermark
end;

TUART3_RWFIFO_bitbanded = record
  RXWATER                : array[0..7] of longWord;    // [0:7] Receive Watermark
end;

TUART3_RCFIFO_bits = bitpacked record
  RXCOUNT                : TBits_8;                    // [0:7] Receive Counter
end;

TUART3_RCFIFO_bitbanded = record
  RXCOUNT                : array[0..7] of longWord;    // [0:7] Receive Counter
end;

TUART3_Registers = record
  case boolean of false: (
  BDH                    : byte;                       // 0x00 UART Baud Rate Registers:High
  BDL                    : byte;                       // 0x01 UART Baud Rate Registers: Low
  C1                     : byte;                       // 0x02 UART Control Register 1
  C2                     : byte;                       // 0x03 UART Control Register 2
  S1                     : byte;                       // 0x04 UART Status Register 1
  S2                     : byte;                       // 0x05 UART Status Register 2
  C3                     : byte;                       // 0x06 UART Control Register 3
  D                      : byte;                       // 0x07 UART Data Register
  MA1                    : byte;                       // 0x08 UART Match Address Registers 1
  MA2                    : byte;                       // 0x09 UART Match Address Registers 2
  C4                     : byte;                       // 0x0A UART Control Register 4
  C5                     : byte;                       // 0x0B UART Control Register 5
  ED                     : byte;                       // 0x0C UART Extended Data Register
  MODEM                  : byte;                       // 0x0D UART Modem Register
  IR                     : byte;                       // 0x0E UART Infrared Register
  RESERVED0              : byte;                       // 0x0F
  PFIFO                  : byte;                       // 0x10 UART FIFO Parameters
  CFIFO                  : byte;                       // 0x11 UART FIFO Control Register
  SFIFO                  : byte;                       // 0x12 UART FIFO Status Register
  TWFIFO                 : byte;                       // 0x13 UART FIFO Transmit Watermark
  TCFIFO                 : byte;                       // 0x14 UART FIFO Transmit Count
  RWFIFO                 : byte;                       // 0x15 UART FIFO Receive Watermark
  RCFIFO                 : byte;                       // 0x16 UART FIFO Receive Count
);
true : (
BDH_bits                 : TUART3_BDH_bits;            // 0x01 UART Baud Rate Registers:High
BDL_bits                 : TUART3_BDL_bits;            // 0x02 UART Baud Rate Registers: Low
C1_bits                  : TUART3_C1_bits;             // 0x03 UART Control Register 1
C2_bits                  : TUART3_C2_bits;             // 0x04 UART Control Register 2
S1_bits                  : TUART3_S1_bits;             // 0x05 UART Status Register 1
S2_bits                  : TUART3_S2_bits;             // 0x06 UART Status Register 2
C3_bits                  : TUART3_C3_bits;             // 0x07 UART Control Register 3
D_bits                   : TUART3_D_bits;              // 0x08 UART Data Register
MA1_bits                 : TUART3_MA1_bits;            // 0x09 UART Match Address Registers 1
MA2_bits                 : TUART3_MA2_bits;            // 0x0A UART Match Address Registers 2
C4_bits                  : TUART3_C4_bits;             // 0x0B UART Control Register 4
C5_bits                  : TUART3_C5_bits;             // 0x0C UART Control Register 5
ED_bits                  : TUART3_ED_bits;             // 0x0D UART Extended Data Register
MODEM_bits               : TUART3_MODEM_bits;          // 0x0E UART Modem Register
IR_bits                  : TUART3_IR_bits;             // 0x0F UART Infrared Register
RESERVED_bits0           : byte;
PFIFO_bits               : TUART3_PFIFO_bits;          // 0x11 UART FIFO Parameters
CFIFO_bits               : TUART3_CFIFO_bits;          // 0x12 UART FIFO Control Register
SFIFO_bits               : TUART3_SFIFO_bits;          // 0x13 UART FIFO Status Register
TWFIFO_bits              : TUART3_TWFIFO_bits;         // 0x14 UART FIFO Transmit Watermark
TCFIFO_bits              : TUART3_TCFIFO_bits;         // 0x15 UART FIFO Transmit Count
RWFIFO_bits              : TUART3_RWFIFO_bits;         // 0x16 UART FIFO Receive Watermark
RCFIFO_bits              : TUART3_RCFIFO_bits;         // 0x17 UART FIFO Receive Count
);
end;

TUART3Registers_bitbanded = record
  BDH                    : TUART3_BDH_bitbanded;       // 0x01 UART Baud Rate Registers:High
  BDL                    : TUART3_BDL_bitbanded;       // 0x02 UART Baud Rate Registers: Low
  C1                     : TUART3_C1_bitbanded;        // 0x03 UART Control Register 1
  C2                     : TUART3_C2_bitbanded;        // 0x04 UART Control Register 2
  S1                     : TUART3_S1_bitbanded;        // 0x05 UART Status Register 1
  S2                     : TUART3_S2_bitbanded;        // 0x06 UART Status Register 2
  C3                     : TUART3_C3_bitbanded;        // 0x07 UART Control Register 3
  D                      : TUART3_D_bitbanded;         // 0x08 UART Data Register
  MA1                    : TUART3_MA1_bitbanded;       // 0x09 UART Match Address Registers 1
  MA2                    : TUART3_MA2_bitbanded;       // 0x0A UART Match Address Registers 2
  C4                     : TUART3_C4_bitbanded;        // 0x0B UART Control Register 4
  C5                     : TUART3_C5_bitbanded;        // 0x0C UART Control Register 5
  ED                     : TUART3_ED_bitbanded;        // 0x0D UART Extended Data Register
  MODEM                  : TUART3_MODEM_bitbanded;     // 0x0E UART Modem Register
  IR                     : TUART3_IR_bitbanded;        // 0x0F UART Infrared Register
  RESERVED0              : array[0..7] of longWord;
  PFIFO                  : TUART3_PFIFO_bitbanded;     // 0x11 UART FIFO Parameters
  CFIFO                  : TUART3_CFIFO_bitbanded;     // 0x12 UART FIFO Control Register
  SFIFO                  : TUART3_SFIFO_bitbanded;     // 0x13 UART FIFO Status Register
  TWFIFO                 : TUART3_TWFIFO_bitbanded;    // 0x14 UART FIFO Transmit Watermark
  TCFIFO                 : TUART3_TCFIFO_bitbanded;    // 0x15 UART FIFO Transmit Count
  RWFIFO                 : TUART3_RWFIFO_bitbanded;    // 0x16 UART FIFO Receive Watermark
  RCFIFO                 : TUART3_RCFIFO_bitbanded;    // 0x17 UART FIFO Receive Count
end;

// Serial Communication Interface
TUART4_BDH_bits = bitpacked record
  SBR                    : TBits_5;                    // [0:4] UART Baud Rate Bits
  RESERVED0              : TBits_1;                    // [5:5] no description available
  RXEDGIE                : TBits_1;                    // [6:6] RxD Input Active Edge Interrupt Enable
  LBKDIE                 : TBits_1;                    // [7:7] LIN Break Detect Interrupt Enable
end;

TUART4_BDH_bitbanded = record
  SBR                    : array[0..4] of longWord;    // [0:4] UART Baud Rate Bits
  RESERVED0              : longWord;                   // [5:5] no description available
  RXEDGIE                : longWord;                   // [6:6] RxD Input Active Edge Interrupt Enable
  LBKDIE                 : longWord;                   // [7:7] LIN Break Detect Interrupt Enable
end;

TUART4_BDL_bits = bitpacked record
  SBR                    : TBits_8;                    // [0:7] UART Baud Rate Bits
end;

TUART4_BDL_bitbanded = record
  SBR                    : array[0..7] of longWord;    // [0:7] UART Baud Rate Bits
end;

TUART4_C1_bits = bitpacked record
  PT                     : TBits_1;                    // [0:0] Parity Type
  PE                     : TBits_1;                    // [1:1] Parity Enable
  ILT                    : TBits_1;                    // [2:2] Idle Line Type Select
  WAKE                   : TBits_1;                    // [3:3] Receiver Wakeup Method Select
  M                      : TBits_1;                    // [4:4] 9-bit or 8-bit Mode Select
  RSRC                   : TBits_1;                    // [5:5] Receiver Source Select
  UARTSWAI               : TBits_1;                    // [6:6] UART Stops in Wait Mode
  LOOPS                  : TBits_1;                    // [7:7] Loop Mode Select
end;

TUART4_C1_bitbanded = record
  PT                     : longWord;                   // [0:0] Parity Type
  PE                     : longWord;                   // [1:1] Parity Enable
  ILT                    : longWord;                   // [2:2] Idle Line Type Select
  WAKE                   : longWord;                   // [3:3] Receiver Wakeup Method Select
  M                      : longWord;                   // [4:4] 9-bit or 8-bit Mode Select
  RSRC                   : longWord;                   // [5:5] Receiver Source Select
  UARTSWAI               : longWord;                   // [6:6] UART Stops in Wait Mode
  LOOPS                  : longWord;                   // [7:7] Loop Mode Select
end;

TUART4_C2_bits = bitpacked record
  SBK                    : TBits_1;                    // [0:0] Send Break
  RWU                    : TBits_1;                    // [1:1] Receiver Wakeup Control
  RE                     : TBits_1;                    // [2:2] Receiver Enable
  TE                     : TBits_1;                    // [3:3] Transmitter Enable
  ILIE                   : TBits_1;                    // [4:4] Idle Line Interrupt Enable
  RIE                    : TBits_1;                    // [5:5] Receiver Full Interrupt or DMA Transfer Enable
  TCIE                   : TBits_1;                    // [6:6] Transmission Complete Interrupt Enable
  TIE                    : TBits_1;                    // [7:7] Transmitter Interrupt or DMA Transfer Enable.
end;

TUART4_C2_bitbanded = record
  SBK                    : longWord;                   // [0:0] Send Break
  RWU                    : longWord;                   // [1:1] Receiver Wakeup Control
  RE                     : longWord;                   // [2:2] Receiver Enable
  TE                     : longWord;                   // [3:3] Transmitter Enable
  ILIE                   : longWord;                   // [4:4] Idle Line Interrupt Enable
  RIE                    : longWord;                   // [5:5] Receiver Full Interrupt or DMA Transfer Enable
  TCIE                   : longWord;                   // [6:6] Transmission Complete Interrupt Enable
  TIE                    : longWord;                   // [7:7] Transmitter Interrupt or DMA Transfer Enable.
end;

TUART4_S1_bits = bitpacked record
  PF                     : TBits_1;                    // [0:0] Parity Error Flag
  FE                     : TBits_1;                    // [1:1] Framing Error Flag
  NF                     : TBits_1;                    // [2:2] Noise Flag
  &OR                    : TBits_1;                    // [3:3] Receiver Overrun Flag
  IDLE                   : TBits_1;                    // [4:4] Idle Line Flag
  RDRF                   : TBits_1;                    // [5:5] Receive Data Register Full Flag
  TC                     : TBits_1;                    // [6:6] Transmit Complete Flag
  TDRE                   : TBits_1;                    // [7:7] Transmit Data Register Empty Flag
end;

TUART4_S1_bitbanded = record
  PF                     : longWord;                   // [0:0] Parity Error Flag
  FE                     : longWord;                   // [1:1] Framing Error Flag
  NF                     : longWord;                   // [2:2] Noise Flag
  &OR                    : longWord;                   // [3:3] Receiver Overrun Flag
  IDLE                   : longWord;                   // [4:4] Idle Line Flag
  RDRF                   : longWord;                   // [5:5] Receive Data Register Full Flag
  TC                     : longWord;                   // [6:6] Transmit Complete Flag
  TDRE                   : longWord;                   // [7:7] Transmit Data Register Empty Flag
end;

TUART4_S2_bits = bitpacked record
  RAF                    : TBits_1;                    // [0:0] Receiver Active Flag
  LBKDE                  : TBits_1;                    // [1:1] LIN Break Detection Enable
  BRK13                  : TBits_1;                    // [2:2] Break Transmit Character Length
  RWUID                  : TBits_1;                    // [3:3] Receive Wakeup Idle Detect
  RXINV                  : TBits_1;                    // [4:4] Receive Data Inversion
  MSBF                   : TBits_1;                    // [5:5] Most Significant Bit First
  RXEDGIF                : TBits_1;                    // [6:6] RxD Pin Active Edge Interrupt Flag
  LBKDIF                 : TBits_1;                    // [7:7] LIN Break Detect Interrupt Flag
end;

TUART4_S2_bitbanded = record
  RAF                    : longWord;                   // [0:0] Receiver Active Flag
  LBKDE                  : longWord;                   // [1:1] LIN Break Detection Enable
  BRK13                  : longWord;                   // [2:2] Break Transmit Character Length
  RWUID                  : longWord;                   // [3:3] Receive Wakeup Idle Detect
  RXINV                  : longWord;                   // [4:4] Receive Data Inversion
  MSBF                   : longWord;                   // [5:5] Most Significant Bit First
  RXEDGIF                : longWord;                   // [6:6] RxD Pin Active Edge Interrupt Flag
  LBKDIF                 : longWord;                   // [7:7] LIN Break Detect Interrupt Flag
end;

TUART4_C3_bits = bitpacked record
  PEIE                   : TBits_1;                    // [0:0] Parity Error Interrupt Enable
  FEIE                   : TBits_1;                    // [1:1] Framing Error Interrupt Enable
  NEIE                   : TBits_1;                    // [2:2] Noise Error Interrupt Enable
  ORIE                   : TBits_1;                    // [3:3] Overrun Error Interrupt Enable
  TXINV                  : TBits_1;                    // [4:4] Transmit Data Inversion.
  TXDIR                  : TBits_1;                    // [5:5] Transmitter Pin Data Direction in Single-Wire mode
  T8                     : TBits_1;                    // [6:6] Transmit Bit 8
  R8                     : TBits_1;                    // [7:7] Received Bit 8
end;

TUART4_C3_bitbanded = record
  PEIE                   : longWord;                   // [0:0] Parity Error Interrupt Enable
  FEIE                   : longWord;                   // [1:1] Framing Error Interrupt Enable
  NEIE                   : longWord;                   // [2:2] Noise Error Interrupt Enable
  ORIE                   : longWord;                   // [3:3] Overrun Error Interrupt Enable
  TXINV                  : longWord;                   // [4:4] Transmit Data Inversion.
  TXDIR                  : longWord;                   // [5:5] Transmitter Pin Data Direction in Single-Wire mode
  T8                     : longWord;                   // [6:6] Transmit Bit 8
  R8                     : longWord;                   // [7:7] Received Bit 8
end;

TUART4_D_bits = bitpacked record
  RT                     : TBits_8;                    // [0:7] no description available
end;

TUART4_D_bitbanded = record
  RT                     : array[0..7] of longWord;    // [0:7] no description available
end;

TUART4_MA1_bits = bitpacked record
  MA                     : TBits_8;                    // [0:7] Match Address
end;

TUART4_MA1_bitbanded = record
  MA                     : array[0..7] of longWord;    // [0:7] Match Address
end;

TUART4_MA2_bits = bitpacked record
  MA                     : TBits_8;                    // [0:7] Match Address
end;

TUART4_MA2_bitbanded = record
  MA                     : array[0..7] of longWord;    // [0:7] Match Address
end;

TUART4_C4_bits = bitpacked record
  BRFA                   : TBits_5;                    // [0:4] Baud Rate Fine Adjust
  M10                    : TBits_1;                    // [5:5] 10-bit Mode select
  MAEN2                  : TBits_1;                    // [6:6] Match Address Mode Enable 2
  MAEN1                  : TBits_1;                    // [7:7] Match Address Mode Enable 1
end;

TUART4_C4_bitbanded = record
  BRFA                   : array[0..4] of longWord;    // [0:4] Baud Rate Fine Adjust
  M10                    : longWord;                   // [5:5] 10-bit Mode select
  MAEN2                  : longWord;                   // [6:6] Match Address Mode Enable 2
  MAEN1                  : longWord;                   // [7:7] Match Address Mode Enable 1
end;

TUART4_C5_bits = bitpacked record
  RESERVED0              : TBits_5;                    // [0:4] no description available
  RDMAS                  : TBits_1;                    // [5:5] Receiver Full DMA Select
  RESERVED1              : TBits_1;                    // [6:6] no description available
  TDMAS                  : TBits_1;                    // [7:7] Transmitter DMA Select
end;

TUART4_C5_bitbanded = record
  RESERVED0              : array[0..4] of longWord;    // [0:4] no description available
  RDMAS                  : longWord;                   // [5:5] Receiver Full DMA Select
  RESERVED1              : longWord;                   // [6:6] no description available
  TDMAS                  : longWord;                   // [7:7] Transmitter DMA Select
end;

TUART4_ED_bits = bitpacked record
  RESERVED0              : TBits_6;                    // [0:5] no description available
  PARITYE                : TBits_1;                    // [6:6] no description available
  NOISY                  : TBits_1;                    // [7:7] no description available
end;

TUART4_ED_bitbanded = record
  RESERVED0              : array[0..5] of longWord;    // [0:5] no description available
  PARITYE                : longWord;                   // [6:6] no description available
  NOISY                  : longWord;                   // [7:7] no description available
end;

TUART4_MODEM_bits = bitpacked record
  TXCTSE                 : TBits_1;                    // [0:0] Transmitter clear-to-send enable
  TXRTSE                 : TBits_1;                    // [1:1] Transmitter request-to-send enable
  TXRTSPOL               : TBits_1;                    // [2:2] Transmitter request-to-send polarity
  RXRTSE                 : TBits_1;                    // [3:3] Receiver request-to-send enable
  RESERVED0              : TBits_4;                    // [4:7] no description available
end;

TUART4_MODEM_bitbanded = record
  TXCTSE                 : longWord;                   // [0:0] Transmitter clear-to-send enable
  TXRTSE                 : longWord;                   // [1:1] Transmitter request-to-send enable
  TXRTSPOL               : longWord;                   // [2:2] Transmitter request-to-send polarity
  RXRTSE                 : longWord;                   // [3:3] Receiver request-to-send enable
  RESERVED0              : array[0..3] of longWord;    // [4:7] no description available
end;

TUART4_IR_bits = bitpacked record
  TNP                    : TBits_2;                    // [0:1] Transmitter narrow pulse
  IREN                   : TBits_1;                    // [2:2] Infrared enable
  RESERVED0              : TBits_5;                    // [3:7] no description available
end;

TUART4_IR_bitbanded = record
  TNP                    : array[0..1] of longWord;    // [0:1] Transmitter narrow pulse
  IREN                   : longWord;                   // [2:2] Infrared enable
  RESERVED0              : array[0..4] of longWord;    // [3:7] no description available
end;

TUART4_PFIFO_bits = bitpacked record
  RXFIFOSIZE             : TBits_3;                    // [0:2] Receive FIFO. Buffer Depth
  RXFE                   : TBits_1;                    // [3:3] Receive FIFO Enable
  TXFIFOSIZE             : TBits_3;                    // [4:6] Transmit FIFO. Buffer Depth
  TXFE                   : TBits_1;                    // [7:7] Transmit FIFO Enable
end;

TUART4_PFIFO_bitbanded = record
  RXFIFOSIZE             : array[0..2] of longWord;    // [0:2] Receive FIFO. Buffer Depth
  RXFE                   : longWord;                   // [3:3] Receive FIFO Enable
  TXFIFOSIZE             : array[0..2] of longWord;    // [4:6] Transmit FIFO. Buffer Depth
  TXFE                   : longWord;                   // [7:7] Transmit FIFO Enable
end;

TUART4_CFIFO_bits = bitpacked record
  RXUFE                  : TBits_1;                    // [0:0] Receive FIFO Underflow Interrupt Enable
  TXOFE                  : TBits_1;                    // [1:1] Transmit FIFO Overflow Interrupt Enable
  RESERVED0              : TBits_4;                    // [2:5] no description available
  RXFLUSH                : TBits_1;                    // [6:6] Receive FIFO/Buffer Flush
  TXFLUSH                : TBits_1;                    // [7:7] Transmit FIFO/Buffer Flush
end;

TUART4_CFIFO_bitbanded = record
  RXUFE                  : longWord;                   // [0:0] Receive FIFO Underflow Interrupt Enable
  TXOFE                  : longWord;                   // [1:1] Transmit FIFO Overflow Interrupt Enable
  RESERVED0              : array[0..3] of longWord;    // [2:5] no description available
  RXFLUSH                : longWord;                   // [6:6] Receive FIFO/Buffer Flush
  TXFLUSH                : longWord;                   // [7:7] Transmit FIFO/Buffer Flush
end;

TUART4_SFIFO_bits = bitpacked record
  RXUF                   : TBits_1;                    // [0:0] Receiver Buffer Underflow Flag
  TXOF                   : TBits_1;                    // [1:1] Transmitter Buffer Overflow Flag
  RESERVED0              : TBits_4;                    // [2:5] no description available
  RXEMPT                 : TBits_1;                    // [6:6] Receive Buffer/FIFO Empty
  TXEMPT                 : TBits_1;                    // [7:7] Transmit Buffer/FIFO Empty
end;

TUART4_SFIFO_bitbanded = record
  RXUF                   : longWord;                   // [0:0] Receiver Buffer Underflow Flag
  TXOF                   : longWord;                   // [1:1] Transmitter Buffer Overflow Flag
  RESERVED0              : array[0..3] of longWord;    // [2:5] no description available
  RXEMPT                 : longWord;                   // [6:6] Receive Buffer/FIFO Empty
  TXEMPT                 : longWord;                   // [7:7] Transmit Buffer/FIFO Empty
end;

TUART4_TWFIFO_bits = bitpacked record
  TXWATER                : TBits_8;                    // [0:7] Transmit Watermark
end;

TUART4_TWFIFO_bitbanded = record
  TXWATER                : array[0..7] of longWord;    // [0:7] Transmit Watermark
end;

TUART4_TCFIFO_bits = bitpacked record
  TXCOUNT                : TBits_8;                    // [0:7] Transmit Counter
end;

TUART4_TCFIFO_bitbanded = record
  TXCOUNT                : array[0..7] of longWord;    // [0:7] Transmit Counter
end;

TUART4_RWFIFO_bits = bitpacked record
  RXWATER                : TBits_8;                    // [0:7] Receive Watermark
end;

TUART4_RWFIFO_bitbanded = record
  RXWATER                : array[0..7] of longWord;    // [0:7] Receive Watermark
end;

TUART4_RCFIFO_bits = bitpacked record
  RXCOUNT                : TBits_8;                    // [0:7] Receive Counter
end;

TUART4_RCFIFO_bitbanded = record
  RXCOUNT                : array[0..7] of longWord;    // [0:7] Receive Counter
end;

TUART4_Registers = record
  case boolean of false: (
  BDH                    : byte;                       // 0x00 UART Baud Rate Registers:High
  BDL                    : byte;                       // 0x01 UART Baud Rate Registers: Low
  C1                     : byte;                       // 0x02 UART Control Register 1
  C2                     : byte;                       // 0x03 UART Control Register 2
  S1                     : byte;                       // 0x04 UART Status Register 1
  S2                     : byte;                       // 0x05 UART Status Register 2
  C3                     : byte;                       // 0x06 UART Control Register 3
  D                      : byte;                       // 0x07 UART Data Register
  MA1                    : byte;                       // 0x08 UART Match Address Registers 1
  MA2                    : byte;                       // 0x09 UART Match Address Registers 2
  C4                     : byte;                       // 0x0A UART Control Register 4
  C5                     : byte;                       // 0x0B UART Control Register 5
  ED                     : byte;                       // 0x0C UART Extended Data Register
  MODEM                  : byte;                       // 0x0D UART Modem Register
  IR                     : byte;                       // 0x0E UART Infrared Register
  RESERVED0              : byte;                       // 0x0F
  PFIFO                  : byte;                       // 0x10 UART FIFO Parameters
  CFIFO                  : byte;                       // 0x11 UART FIFO Control Register
  SFIFO                  : byte;                       // 0x12 UART FIFO Status Register
  TWFIFO                 : byte;                       // 0x13 UART FIFO Transmit Watermark
  TCFIFO                 : byte;                       // 0x14 UART FIFO Transmit Count
  RWFIFO                 : byte;                       // 0x15 UART FIFO Receive Watermark
  RCFIFO                 : byte;                       // 0x16 UART FIFO Receive Count
);
true : (
BDH_bits                 : TUART4_BDH_bits;            // 0x01 UART Baud Rate Registers:High
BDL_bits                 : TUART4_BDL_bits;            // 0x02 UART Baud Rate Registers: Low
C1_bits                  : TUART4_C1_bits;             // 0x03 UART Control Register 1
C2_bits                  : TUART4_C2_bits;             // 0x04 UART Control Register 2
S1_bits                  : TUART4_S1_bits;             // 0x05 UART Status Register 1
S2_bits                  : TUART4_S2_bits;             // 0x06 UART Status Register 2
C3_bits                  : TUART4_C3_bits;             // 0x07 UART Control Register 3
D_bits                   : TUART4_D_bits;              // 0x08 UART Data Register
MA1_bits                 : TUART4_MA1_bits;            // 0x09 UART Match Address Registers 1
MA2_bits                 : TUART4_MA2_bits;            // 0x0A UART Match Address Registers 2
C4_bits                  : TUART4_C4_bits;             // 0x0B UART Control Register 4
C5_bits                  : TUART4_C5_bits;             // 0x0C UART Control Register 5
ED_bits                  : TUART4_ED_bits;             // 0x0D UART Extended Data Register
MODEM_bits               : TUART4_MODEM_bits;          // 0x0E UART Modem Register
IR_bits                  : TUART4_IR_bits;             // 0x0F UART Infrared Register
RESERVED_bits0           : byte;
PFIFO_bits               : TUART4_PFIFO_bits;          // 0x11 UART FIFO Parameters
CFIFO_bits               : TUART4_CFIFO_bits;          // 0x12 UART FIFO Control Register
SFIFO_bits               : TUART4_SFIFO_bits;          // 0x13 UART FIFO Status Register
TWFIFO_bits              : TUART4_TWFIFO_bits;         // 0x14 UART FIFO Transmit Watermark
TCFIFO_bits              : TUART4_TCFIFO_bits;         // 0x15 UART FIFO Transmit Count
RWFIFO_bits              : TUART4_RWFIFO_bits;         // 0x16 UART FIFO Receive Watermark
RCFIFO_bits              : TUART4_RCFIFO_bits;         // 0x17 UART FIFO Receive Count
);
end;

TUART4Registers_bitbanded = record
  BDH                    : TUART4_BDH_bitbanded;       // 0x01 UART Baud Rate Registers:High
  BDL                    : TUART4_BDL_bitbanded;       // 0x02 UART Baud Rate Registers: Low
  C1                     : TUART4_C1_bitbanded;        // 0x03 UART Control Register 1
  C2                     : TUART4_C2_bitbanded;        // 0x04 UART Control Register 2
  S1                     : TUART4_S1_bitbanded;        // 0x05 UART Status Register 1
  S2                     : TUART4_S2_bitbanded;        // 0x06 UART Status Register 2
  C3                     : TUART4_C3_bitbanded;        // 0x07 UART Control Register 3
  D                      : TUART4_D_bitbanded;         // 0x08 UART Data Register
  MA1                    : TUART4_MA1_bitbanded;       // 0x09 UART Match Address Registers 1
  MA2                    : TUART4_MA2_bitbanded;       // 0x0A UART Match Address Registers 2
  C4                     : TUART4_C4_bitbanded;        // 0x0B UART Control Register 4
  C5                     : TUART4_C5_bitbanded;        // 0x0C UART Control Register 5
  ED                     : TUART4_ED_bitbanded;        // 0x0D UART Extended Data Register
  MODEM                  : TUART4_MODEM_bitbanded;     // 0x0E UART Modem Register
  IR                     : TUART4_IR_bitbanded;        // 0x0F UART Infrared Register
  RESERVED0              : array[0..7] of longWord;
  PFIFO                  : TUART4_PFIFO_bitbanded;     // 0x11 UART FIFO Parameters
  CFIFO                  : TUART4_CFIFO_bitbanded;     // 0x12 UART FIFO Control Register
  SFIFO                  : TUART4_SFIFO_bitbanded;     // 0x13 UART FIFO Status Register
  TWFIFO                 : TUART4_TWFIFO_bitbanded;    // 0x14 UART FIFO Transmit Watermark
  TCFIFO                 : TUART4_TCFIFO_bitbanded;    // 0x15 UART FIFO Transmit Count
  RWFIFO                 : TUART4_RWFIFO_bitbanded;    // 0x16 UART FIFO Receive Watermark
  RCFIFO                 : TUART4_RCFIFO_bitbanded;    // 0x17 UART FIFO Receive Count
end;

// Universal Serial Bus, OTG Capable Controller
TUSB0_PERID_bits = bitpacked record
  ID                     : TBits_6;                    // [0:5] Peripheral identification bits
  RESERVED0              : TBits_2;                    // [6:7] no description available
end;

TUSB0_PERID_bitbanded = record
  ID                     : array[0..5] of longWord;    // [0:5] Peripheral identification bits
  RESERVED0              : array[0..1] of longWord;    // [6:7] no description available
end;

TUSB0_IDCOMP_bits = bitpacked record
  NID                    : TBits_6;                    // [0:5] no description available
  RESERVED0              : TBits_2;                    // [6:7] no description available
end;

TUSB0_IDCOMP_bitbanded = record
  NID                    : array[0..5] of longWord;    // [0:5] no description available
  RESERVED0              : array[0..1] of longWord;    // [6:7] no description available
end;

TUSB0_REV_bits = bitpacked record
  REV                    : TBits_8;                    // [0:7] Revision
end;

TUSB0_REV_bitbanded = record
  REV                    : array[0..7] of longWord;    // [0:7] Revision
end;

TUSB0_ADDINFO_bits = bitpacked record
  IEHOST                 : TBits_1;                    // [0:0] no description available
  RESERVED0              : TBits_2;                    // [1:2] no description available
  IRQNUM                 : TBits_5;                    // [3:7] Assigned Interrupt Request Number
end;

TUSB0_ADDINFO_bitbanded = record
  IEHOST                 : longWord;                   // [0:0] no description available
  RESERVED0              : array[0..1] of longWord;    // [1:2] no description available
  IRQNUM                 : array[0..4] of longWord;    // [3:7] Assigned Interrupt Request Number
end;

TUSB0_OTGISTAT_bits = bitpacked record
  AVBUSCHG               : TBits_1;                    // [0:0] no description available
  RESERVED0              : TBits_1;                    // [1:1] no description available
  B_SESS_CHG             : TBits_1;                    // [2:2] no description available
  SESSVLDCHG             : TBits_1;                    // [3:3] no description available
  RESERVED1              : TBits_1;                    // [4:4] no description available
  LINE_STATE_CHG         : TBits_1;                    // [5:5] no description available
  ONEMSEC                : TBits_1;                    // [6:6] no description available
  IDCHG                  : TBits_1;                    // [7:7] no description available
end;

TUSB0_OTGISTAT_bitbanded = record
  AVBUSCHG               : longWord;                   // [0:0] no description available
  RESERVED0              : longWord;                   // [1:1] no description available
  B_SESS_CHG             : longWord;                   // [2:2] no description available
  SESSVLDCHG             : longWord;                   // [3:3] no description available
  RESERVED1              : longWord;                   // [4:4] no description available
  LINE_STATE_CHG         : longWord;                   // [5:5] no description available
  ONEMSEC                : longWord;                   // [6:6] no description available
  IDCHG                  : longWord;                   // [7:7] no description available
end;

TUSB0_OTGICR_bits = bitpacked record
  AVBUSEN                : TBits_1;                    // [0:0] A VBUS Valid interrupt enable
  RESERVED0              : TBits_1;                    // [1:1] no description available
  BSESSEN                : TBits_1;                    // [2:2] B Session END interrupt enable
  SESSVLDEN              : TBits_1;                    // [3:3] Session valid interrupt enable
  RESERVED1              : TBits_1;                    // [4:4] no description available
  LINESTATEEN            : TBits_1;                    // [5:5] Line State change interrupt enable
  ONEMSECEN              : TBits_1;                    // [6:6] 1 millisecond interrupt enable
  IDEN                   : TBits_1;                    // [7:7] ID interrupt enable
end;

TUSB0_OTGICR_bitbanded = record
  AVBUSEN                : longWord;                   // [0:0] A VBUS Valid interrupt enable
  RESERVED0              : longWord;                   // [1:1] no description available
  BSESSEN                : longWord;                   // [2:2] B Session END interrupt enable
  SESSVLDEN              : longWord;                   // [3:3] Session valid interrupt enable
  RESERVED1              : longWord;                   // [4:4] no description available
  LINESTATEEN            : longWord;                   // [5:5] Line State change interrupt enable
  ONEMSECEN              : longWord;                   // [6:6] 1 millisecond interrupt enable
  IDEN                   : longWord;                   // [7:7] ID interrupt enable
end;

TUSB0_OTGSTAT_bits = bitpacked record
  AVBUSVLD               : TBits_1;                    // [0:0] A VBUS Valid
  RESERVED0              : TBits_1;                    // [1:1] no description available
  BSESSEND               : TBits_1;                    // [2:2] B Session END
  SESS_VLD               : TBits_1;                    // [3:3] Session valid
  RESERVED1              : TBits_1;                    // [4:4] no description available
  LINESTATESTABLE        : TBits_1;                    // [5:5] no description available
  ONEMSECEN              : TBits_1;                    // [6:6] no description available
  ID                     : TBits_1;                    // [7:7] no description available
end;

TUSB0_OTGSTAT_bitbanded = record
  AVBUSVLD               : longWord;                   // [0:0] A VBUS Valid
  RESERVED0              : longWord;                   // [1:1] no description available
  BSESSEND               : longWord;                   // [2:2] B Session END
  SESS_VLD               : longWord;                   // [3:3] Session valid
  RESERVED1              : longWord;                   // [4:4] no description available
  LINESTATESTABLE        : longWord;                   // [5:5] no description available
  ONEMSECEN              : longWord;                   // [6:6] no description available
  ID                     : longWord;                   // [7:7] no description available
end;

TUSB0_OTGCTL_bits = bitpacked record
  RESERVED0              : TBits_2;                    // [0:1] no description available
  OTGEN                  : TBits_1;                    // [2:2] On-The-Go pullup/pulldown resistor enable
  RESERVED1              : TBits_1;                    // [3:3] no description available
  DMLOW                  : TBits_1;                    // [4:4] D- Data Line pull-down resistor enable
  DPLOW                  : TBits_1;                    // [5:5] D+ Data Line pull-down resistor enable
  RESERVED2              : TBits_1;                    // [6:6] no description available
  DPHIGH                 : TBits_1;                    // [7:7] D+ Data Line pullup resistor enable
end;

TUSB0_OTGCTL_bitbanded = record
  RESERVED0              : array[0..1] of longWord;    // [0:1] no description available
  OTGEN                  : longWord;                   // [2:2] On-The-Go pullup/pulldown resistor enable
  RESERVED1              : longWord;                   // [3:3] no description available
  DMLOW                  : longWord;                   // [4:4] D- Data Line pull-down resistor enable
  DPLOW                  : longWord;                   // [5:5] D+ Data Line pull-down resistor enable
  RESERVED2              : longWord;                   // [6:6] no description available
  DPHIGH                 : longWord;                   // [7:7] D+ Data Line pullup resistor enable
end;

TUSB0_ISTAT_bits = bitpacked record
  USBRST                 : TBits_1;                    // [0:0] no description available
  ERROR                  : TBits_1;                    // [1:1] no description available
  SOFTOK                 : TBits_1;                    // [2:2] no description available
  TOKDNE                 : TBits_1;                    // [3:3] no description available
  SLEEP                  : TBits_1;                    // [4:4] no description available
  RESUME                 : TBits_1;                    // [5:5] no description available
  ATTACH                 : TBits_1;                    // [6:6] Attach Interrupt
  STALL                  : TBits_1;                    // [7:7] Stall Interrupt
end;

TUSB0_ISTAT_bitbanded = record
  USBRST                 : longWord;                   // [0:0] no description available
  ERROR                  : longWord;                   // [1:1] no description available
  SOFTOK                 : longWord;                   // [2:2] no description available
  TOKDNE                 : longWord;                   // [3:3] no description available
  SLEEP                  : longWord;                   // [4:4] no description available
  RESUME                 : longWord;                   // [5:5] no description available
  ATTACH                 : longWord;                   // [6:6] Attach Interrupt
  STALL                  : longWord;                   // [7:7] Stall Interrupt
end;

TUSB0_INTEN_bits = bitpacked record
  USBRSTEN               : TBits_1;                    // [0:0] USBRST Interrupt Enable
  ERROREN                : TBits_1;                    // [1:1] ERROR Interrupt Enable
  SOFTOKEN               : TBits_1;                    // [2:2] SOFTOK Interrupt Enable
  TOKDNEEN               : TBits_1;                    // [3:3] TOKDNE Interrupt Enable
  SLEEPEN                : TBits_1;                    // [4:4] SLEEP Interrupt Enable
  RESUMEEN               : TBits_1;                    // [5:5] RESUME Interrupt Enable
  ATTACHEN               : TBits_1;                    // [6:6] ATTACH Interrupt Enable
  STALLEN                : TBits_1;                    // [7:7] STALL Interrupt Enable
end;

TUSB0_INTEN_bitbanded = record
  USBRSTEN               : longWord;                   // [0:0] USBRST Interrupt Enable
  ERROREN                : longWord;                   // [1:1] ERROR Interrupt Enable
  SOFTOKEN               : longWord;                   // [2:2] SOFTOK Interrupt Enable
  TOKDNEEN               : longWord;                   // [3:3] TOKDNE Interrupt Enable
  SLEEPEN                : longWord;                   // [4:4] SLEEP Interrupt Enable
  RESUMEEN               : longWord;                   // [5:5] RESUME Interrupt Enable
  ATTACHEN               : longWord;                   // [6:6] ATTACH Interrupt Enable
  STALLEN                : longWord;                   // [7:7] STALL Interrupt Enable
end;

TUSB0_ERRSTAT_bits = bitpacked record
  PIDERR                 : TBits_1;                    // [0:0] no description available
  CRC5EOF                : TBits_1;                    // [1:1] no description available
  CRC16                  : TBits_1;                    // [2:2] no description available
  DFN8                   : TBits_1;                    // [3:3] no description available
  BTOERR                 : TBits_1;                    // [4:4] no description available
  DMAERR                 : TBits_1;                    // [5:5] no description available
  RESERVED0              : TBits_1;                    // [6:6] no description available
  BTSERR                 : TBits_1;                    // [7:7] no description available
end;

TUSB0_ERRSTAT_bitbanded = record
  PIDERR                 : longWord;                   // [0:0] no description available
  CRC5EOF                : longWord;                   // [1:1] no description available
  CRC16                  : longWord;                   // [2:2] no description available
  DFN8                   : longWord;                   // [3:3] no description available
  BTOERR                 : longWord;                   // [4:4] no description available
  DMAERR                 : longWord;                   // [5:5] no description available
  RESERVED0              : longWord;                   // [6:6] no description available
  BTSERR                 : longWord;                   // [7:7] no description available
end;

TUSB0_ERREN_bits = bitpacked record
  PIDERREN               : TBits_1;                    // [0:0] PIDERR Interrupt Enable
  CRC5EOFEN              : TBits_1;                    // [1:1] CRC5/EOF Interrupt Enable
  CRC16EN                : TBits_1;                    // [2:2] CRC16 Interrupt Enable
  DFN8EN                 : TBits_1;                    // [3:3] DFN8 Interrupt Enable
  BTOERREN               : TBits_1;                    // [4:4] BTOERR Interrupt Enable
  DMAERREN               : TBits_1;                    // [5:5] DMAERR Interrupt Enable
  RESERVED0              : TBits_1;                    // [6:6] no description available
  BTSERREN               : TBits_1;                    // [7:7] BTSERR Interrupt Enable
end;

TUSB0_ERREN_bitbanded = record
  PIDERREN               : longWord;                   // [0:0] PIDERR Interrupt Enable
  CRC5EOFEN              : longWord;                   // [1:1] CRC5/EOF Interrupt Enable
  CRC16EN                : longWord;                   // [2:2] CRC16 Interrupt Enable
  DFN8EN                 : longWord;                   // [3:3] DFN8 Interrupt Enable
  BTOERREN               : longWord;                   // [4:4] BTOERR Interrupt Enable
  DMAERREN               : longWord;                   // [5:5] DMAERR Interrupt Enable
  RESERVED0              : longWord;                   // [6:6] no description available
  BTSERREN               : longWord;                   // [7:7] BTSERR Interrupt Enable
end;

TUSB0_STAT_bits = bitpacked record
  RESERVED0              : TBits_2;                    // [0:1] no description available
  ODD                    : TBits_1;                    // [2:2] no description available
  TX                     : TBits_1;                    // [3:3] Transmit Indicator
  ENDP                   : TBits_4;                    // [4:7] no description available
end;

TUSB0_STAT_bitbanded = record
  RESERVED0              : array[0..1] of longWord;    // [0:1] no description available
  ODD                    : longWord;                   // [2:2] no description available
  TX                     : longWord;                   // [3:3] Transmit Indicator
  ENDP                   : array[0..3] of longWord;    // [4:7] no description available
end;

TUSB0_CTL_bits = bitpacked record
  USBENSOFEN             : TBits_1;                    // [0:0] USB Enable
  ODDRST                 : TBits_1;                    // [1:1] no description available
  RESUME                 : TBits_1;                    // [2:2] no description available
  HOSTMODEEN             : TBits_1;                    // [3:3] no description available
  RESET                  : TBits_1;                    // [4:4] no description available
  TXSUSPENDTOKENBUSY     : TBits_1;                    // [5:5] no description available
  SE0                    : TBits_1;                    // [6:6] Live USB Single Ended Zero signal
  JSTATE                 : TBits_1;                    // [7:7] Live USB differential receiver JSTATE signal
end;

TUSB0_CTL_bitbanded = record
  USBENSOFEN             : longWord;                   // [0:0] USB Enable
  ODDRST                 : longWord;                   // [1:1] no description available
  RESUME                 : longWord;                   // [2:2] no description available
  HOSTMODEEN             : longWord;                   // [3:3] no description available
  RESET                  : longWord;                   // [4:4] no description available
  TXSUSPENDTOKENBUSY     : longWord;                   // [5:5] no description available
  SE0                    : longWord;                   // [6:6] Live USB Single Ended Zero signal
  JSTATE                 : longWord;                   // [7:7] Live USB differential receiver JSTATE signal
end;

TUSB0_ADDR_bits = bitpacked record
  ADDR                   : TBits_7;                    // [0:6] USB address
  LSEN                   : TBits_1;                    // [7:7] Low Speed Enable bit
end;

TUSB0_ADDR_bitbanded = record
  ADDR                   : array[0..6] of longWord;    // [0:6] USB address
  LSEN                   : longWord;                   // [7:7] Low Speed Enable bit
end;

TUSB0_BDTPAGE1_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] no description available
  BDTBA                  : TBits_7;                    // [1:7] no description available
end;

TUSB0_BDTPAGE1_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] no description available
  BDTBA                  : array[0..6] of longWord;    // [1:7] no description available
end;

TUSB0_FRMNUML_bits = bitpacked record
  FRM                    : TBits_8;                    // [0:7] no description available
end;

TUSB0_FRMNUML_bitbanded = record
  FRM                    : array[0..7] of longWord;    // [0:7] no description available
end;

TUSB0_FRMNUMH_bits = bitpacked record
  FRM                    : TBits_3;                    // [0:2] no description available
  RESERVED0              : TBits_5;                    // [3:7] no description available
end;

TUSB0_FRMNUMH_bitbanded = record
  FRM                    : array[0..2] of longWord;    // [0:2] no description available
  RESERVED0              : array[0..4] of longWord;    // [3:7] no description available
end;

TUSB0_TOKEN_bits = bitpacked record
  TOKENENDPT             : TBits_4;                    // [0:3] no description available
  TOKENPID               : TBits_4;                    // [4:7] no description available
end;

TUSB0_TOKEN_bitbanded = record
  TOKENENDPT             : array[0..3] of longWord;    // [0:3] no description available
  TOKENPID               : array[0..3] of longWord;    // [4:7] no description available
end;

TUSB0_SOFTHLD_bits = bitpacked record
  CNT                    : TBits_8;                    // [0:7] no description available
end;

TUSB0_SOFTHLD_bitbanded = record
  CNT                    : array[0..7] of longWord;    // [0:7] no description available
end;

TUSB0_BDTPAGE2_bits = bitpacked record
  BDTBA                  : TBits_8;                    // [0:7] no description available
end;

TUSB0_BDTPAGE2_bitbanded = record
  BDTBA                  : array[0..7] of longWord;    // [0:7] no description available
end;

TUSB0_BDTPAGE3_bits = bitpacked record
  BDTBA                  : TBits_8;                    // [0:7] no description available
end;

TUSB0_BDTPAGE3_bitbanded = record
  BDTBA                  : array[0..7] of longWord;    // [0:7] no description available
end;

TUSB0_ENDPT_bits = bitpacked record
  EPHSHK                 : TBits_1;                    // [0:0] no description available
  EPSTALL                : TBits_1;                    // [1:1] no description available
  EPTXEN                 : TBits_1;                    // [2:2] no description available
  EPRXEN                 : TBits_1;                    // [3:3] no description available
  EPCTLDIS               : TBits_1;                    // [4:4] no description available
  RESERVED0              : TBits_1;                    // [5:5] no description available
  RETRYDIS               : TBits_1;                    // [6:6] no description available
  HOSTWOHUB              : TBits_1;                    // [7:7] no description available
end;

TUSB0_ENDPT_bitbanded = record
  EPHSHK                 : longWord;                   // [0:0] no description available
  EPSTALL                : longWord;                   // [1:1] no description available
  EPTXEN                 : longWord;                   // [2:2] no description available
  EPRXEN                 : longWord;                   // [3:3] no description available
  EPCTLDIS               : longWord;                   // [4:4] no description available
  RESERVED0              : longWord;                   // [5:5] no description available
  RETRYDIS               : longWord;                   // [6:6] no description available
  HOSTWOHUB              : longWord;                   // [7:7] no description available
end;

TUSB0_USBCTRL_bits = bitpacked record
  RESERVED0              : TBits_6;                    // [0:5] no description available
  PDE                    : TBits_1;                    // [6:6] no description available
  SUSP                   : TBits_1;                    // [7:7] no description available
end;

TUSB0_USBCTRL_bitbanded = record
  RESERVED0              : array[0..5] of longWord;    // [0:5] no description available
  PDE                    : longWord;                   // [6:6] no description available
  SUSP                   : longWord;                   // [7:7] no description available
end;

TUSB0_OBSERVE_bits = bitpacked record
  RESERVED0              : TBits_1;                    // [0:0] no description available
  RESERVED1              : TBits_3;                    // [1:3] no description available
  DMPD                   : TBits_1;                    // [4:4] no description available
  RESERVED2              : TBits_1;                    // [5:5] no description available
  DPPD                   : TBits_1;                    // [6:6] no description available
  DPPU                   : TBits_1;                    // [7:7] no description available
end;

TUSB0_OBSERVE_bitbanded = record
  RESERVED0              : longWord;                   // [0:0] no description available
  RESERVED1              : array[0..2] of longWord;    // [1:3] no description available
  DMPD                   : longWord;                   // [4:4] no description available
  RESERVED2              : longWord;                   // [5:5] no description available
  DPPD                   : longWord;                   // [6:6] no description available
  DPPU                   : longWord;                   // [7:7] no description available
end;

TUSB0_CONTROL_bits = bitpacked record
  RESERVED0              : TBits_4;                    // [0:3] no description available
  DPPULLUPNONOTG         : TBits_1;                    // [4:4] no description available
  RESERVED1              : TBits_3;                    // [5:7] no description available
end;

TUSB0_CONTROL_bitbanded = record
  RESERVED0              : array[0..3] of longWord;    // [0:3] no description available
  DPPULLUPNONOTG         : longWord;                   // [4:4] no description available
  RESERVED1              : array[0..2] of longWord;    // [5:7] no description available
end;

TUSB0_USBTRC0_bits = bitpacked record
  USB_RESUME_INT         : TBits_1;                    // [0:0] USB Asynchronous Interrupt
  SYNC_DET               : TBits_1;                    // [1:1] Synchronous USB Interrupt Detect
  RESERVED0              : TBits_3;                    // [2:4] no description available
  USBRESMEN              : TBits_1;                    // [5:5] Asynchronous Resume Interrupt Enable
  RESERVED1              : TBits_1;                    // [6:6] no description available
  USBRESET               : TBits_1;                    // [7:7] USB reset
end;

TUSB0_USBTRC0_bitbanded = record
  USB_RESUME_INT         : longWord;                   // [0:0] USB Asynchronous Interrupt
  SYNC_DET               : longWord;                   // [1:1] Synchronous USB Interrupt Detect
  RESERVED0              : array[0..2] of longWord;    // [2:4] no description available
  USBRESMEN              : longWord;                   // [5:5] Asynchronous Resume Interrupt Enable
  RESERVED1              : longWord;                   // [6:6] no description available
  USBRESET               : longWord;                   // [7:7] USB reset
end;

TUSB0_USBFRMADJUST_bits = bitpacked record
  ADJ                    : TBits_8;                    // [0:7] Frame Adjustment
end;

TUSB0_USBFRMADJUST_bitbanded = record
  ADJ                    : array[0..7] of longWord;    // [0:7] Frame Adjustment
end;

TUSB0_Registers = record
  case boolean of false: (
  PERID                  : byte;                       // 0x00 Peripheral ID Register
  RESERVED0              : array[0..2] of byte;        // 0x01
  IDCOMP                 : byte;                       // 0x04 Peripheral ID Complement Register
  RESERVED1              : array[0..2] of byte;        // 0x05
  REV                    : byte;                       // 0x08 Peripheral Revision Register
  RESERVED2              : array[0..2] of byte;        // 0x09
  ADDINFO                : byte;                       // 0x0C Peripheral Additional Info Register
  RESERVED3              : array[0..2] of byte;        // 0x0D
  OTGISTAT               : byte;                       // 0x10 OTG Interrupt Status Register
  RESERVED4              : array[0..2] of byte;        // 0x11
  OTGICR                 : byte;                       // 0x14 OTG Interrupt Control Register
  RESERVED5              : array[0..2] of byte;        // 0x15
  OTGSTAT                : byte;                       // 0x18 OTG Status Register
  RESERVED6              : array[0..2] of byte;        // 0x19
  OTGCTL                 : byte;                       // 0x1C OTG Control Register
  RESERVED7              : array[0..98] of byte;       // 0x1D
  ISTAT                  : byte;                       // 0x80 Interrupt Status Register
  RESERVED8              : array[0..2] of byte;        // 0x81
  INTEN                  : byte;                       // 0x84 Interrupt Enable Register
  RESERVED9              : array[0..2] of byte;        // 0x85
  ERRSTAT                : byte;                       // 0x88 Error Interrupt Status Register
  RESERVED10             : array[0..2] of byte;        // 0x89
  ERREN                  : byte;                       // 0x8C Error Interrupt Enable Register
  RESERVED11             : array[0..2] of byte;        // 0x8D
  STAT                   : byte;                       // 0x90 Status Register
  RESERVED12             : array[0..2] of byte;        // 0x91
  CTL                    : byte;                       // 0x94 Control Register
  RESERVED13             : array[0..2] of byte;        // 0x95
  ADDR                   : byte;                       // 0x98 Address Register
  RESERVED14             : array[0..2] of byte;        // 0x99
  BDTPAGE1               : byte;                       // 0x9C BDT Page Register 1
  RESERVED15             : array[0..2] of byte;        // 0x9D
  FRMNUML                : byte;                       // 0xA0 Frame Number Register Low
  RESERVED16             : array[0..2] of byte;        // 0xA1
  FRMNUMH                : byte;                       // 0xA4 Frame Number Register High
  RESERVED17             : array[0..2] of byte;        // 0xA5
  TOKEN                  : byte;                       // 0xA8 Token Register
  RESERVED18             : array[0..2] of byte;        // 0xA9
  SOFTHLD                : byte;                       // 0xAC SOF Threshold Register
  RESERVED19             : array[0..2] of byte;        // 0xAD
  BDTPAGE2               : byte;                       // 0xB0 BDT Page Register 2
  RESERVED20             : array[0..2] of byte;        // 0xB1
  BDTPAGE3               : byte;                       // 0xB4 BDT Page Register 3
  RESERVED21             : array[0..10] of byte;       // 0xB5
  ENDPT0                 : byte;                       // 0xC0 Endpoint Control Register
  RESERVED22             : array[0..2] of byte;        // 0xC1
  ENDPT1                 : byte;                       // 0xC4 Endpoint Control Register
  RESERVED23             : array[0..2] of byte;        // 0xC5
  ENDPT2                 : byte;                       // 0xC8 Endpoint Control Register
  RESERVED24             : array[0..2] of byte;        // 0xC9
  ENDPT3                 : byte;                       // 0xCC Endpoint Control Register
  RESERVED25             : array[0..2] of byte;        // 0xCD
  ENDPT4                 : byte;                       // 0xD0 Endpoint Control Register
  RESERVED26             : array[0..2] of byte;        // 0xD1
  ENDPT5                 : byte;                       // 0xD4 Endpoint Control Register
  RESERVED27             : array[0..2] of byte;        // 0xD5
  ENDPT6                 : byte;                       // 0xD8 Endpoint Control Register
  RESERVED28             : array[0..2] of byte;        // 0xD9
  ENDPT7                 : byte;                       // 0xDC Endpoint Control Register
  RESERVED29             : array[0..2] of byte;        // 0xDD
  ENDPT8                 : byte;                       // 0xE0 Endpoint Control Register
  RESERVED30             : array[0..2] of byte;        // 0xE1
  ENDPT9                 : byte;                       // 0xE4 Endpoint Control Register
  RESERVED31             : array[0..2] of byte;        // 0xE5
  ENDPT10                : byte;                       // 0xE8 Endpoint Control Register
  RESERVED32             : array[0..2] of byte;        // 0xE9
  ENDPT11                : byte;                       // 0xEC Endpoint Control Register
  RESERVED33             : array[0..2] of byte;        // 0xED
  ENDPT12                : byte;                       // 0xF0 Endpoint Control Register
  RESERVED34             : array[0..2] of byte;        // 0xF1
  ENDPT13                : byte;                       // 0xF4 Endpoint Control Register
  RESERVED35             : array[0..2] of byte;        // 0xF5
  ENDPT14                : byte;                       // 0xF8 Endpoint Control Register
  RESERVED36             : array[0..2] of byte;        // 0xF9
  ENDPT15                : byte;                       // 0xFC Endpoint Control Register
  RESERVED37             : array[0..2] of byte;        // 0xFD
  USBCTRL                : byte;                       // 0x100 USB Control Register
  RESERVED38             : array[0..2] of byte;        // 0x101
  OBSERVE                : byte;                       // 0x104 USB OTG Observe Register
  RESERVED39             : array[0..2] of byte;        // 0x105
  CONTROL                : byte;                       // 0x108 USB OTG Control Register
  RESERVED40             : array[0..2] of byte;        // 0x109
  USBTRC0                : byte;                       // 0x10C USB Transceiver Control Register 0
  RESERVED41             : array[0..6] of byte;        // 0x10D
  USBFRMADJUST           : byte;                       // 0x114 Frame Adjust Register
);
true : (
PERID_bits               : TUSB0_PERID_bits;           // 0x01 Peripheral ID Register
RESERVED_bits0           : array[0..2] of byte;
IDCOMP_bits              : TUSB0_IDCOMP_bits;          // 0x05 Peripheral ID Complement Register
RESERVED_bits1           : array[0..2] of byte;
REV_bits                 : TUSB0_REV_bits;             // 0x09 Peripheral Revision Register
RESERVED_bits2           : array[0..2] of byte;
ADDINFO_bits             : TUSB0_ADDINFO_bits;         // 0x0D Peripheral Additional Info Register
RESERVED_bits3           : array[0..2] of byte;
OTGISTAT_bits            : TUSB0_OTGISTAT_bits;        // 0x11 OTG Interrupt Status Register
RESERVED_bits4           : array[0..2] of byte;
OTGICR_bits              : TUSB0_OTGICR_bits;          // 0x15 OTG Interrupt Control Register
RESERVED_bits5           : array[0..2] of byte;
OTGSTAT_bits             : TUSB0_OTGSTAT_bits;         // 0x19 OTG Status Register
RESERVED_bits6           : array[0..2] of byte;
OTGCTL_bits              : TUSB0_OTGCTL_bits;          // 0x1D OTG Control Register
RESERVED_bits7           : array[0..98] of byte;
ISTAT_bits               : TUSB0_ISTAT_bits;           // 0x81 Interrupt Status Register
RESERVED_bits8           : array[0..2] of byte;
INTEN_bits               : TUSB0_INTEN_bits;           // 0x85 Interrupt Enable Register
RESERVED_bits9           : array[0..2] of byte;
ERRSTAT_bits             : TUSB0_ERRSTAT_bits;         // 0x89 Error Interrupt Status Register
RESERVED_bits10          : array[0..2] of byte;
ERREN_bits               : TUSB0_ERREN_bits;           // 0x8D Error Interrupt Enable Register
RESERVED_bits11          : array[0..2] of byte;
STAT_bits                : TUSB0_STAT_bits;            // 0x91 Status Register
RESERVED_bits12          : array[0..2] of byte;
CTL_bits                 : TUSB0_CTL_bits;             // 0x95 Control Register
RESERVED_bits13          : array[0..2] of byte;
ADDR_bits                : TUSB0_ADDR_bits;            // 0x99 Address Register
RESERVED_bits14          : array[0..2] of byte;
BDTPAGE1_bits            : TUSB0_BDTPAGE1_bits;        // 0x9D BDT Page Register 1
RESERVED_bits15          : array[0..2] of byte;
FRMNUML_bits             : TUSB0_FRMNUML_bits;         // 0xA1 Frame Number Register Low
RESERVED_bits16          : array[0..2] of byte;
FRMNUMH_bits             : TUSB0_FRMNUMH_bits;         // 0xA5 Frame Number Register High
RESERVED_bits17          : array[0..2] of byte;
TOKEN_bits               : TUSB0_TOKEN_bits;           // 0xA9 Token Register
RESERVED_bits18          : array[0..2] of byte;
SOFTHLD_bits             : TUSB0_SOFTHLD_bits;         // 0xAD SOF Threshold Register
RESERVED_bits19          : array[0..2] of byte;
BDTPAGE2_bits            : TUSB0_BDTPAGE2_bits;        // 0xB1 BDT Page Register 2
RESERVED_bits20          : array[0..2] of byte;
BDTPAGE3_bits            : TUSB0_BDTPAGE3_bits;        // 0xB5 BDT Page Register 3
RESERVED_bits21          : array[0..10] of byte;
ENDPT0_bits              : TUSB0_ENDPT_bits;           // 0xC1 Endpoint Control Register
RESERVED_bits22          : array[0..2] of byte;
ENDPT1_bits              : TUSB0_ENDPT_bits;           // 0xC5 Endpoint Control Register
RESERVED_bits23          : array[0..2] of byte;
ENDPT2_bits              : TUSB0_ENDPT_bits;           // 0xC9 Endpoint Control Register
RESERVED_bits24          : array[0..2] of byte;
ENDPT3_bits              : TUSB0_ENDPT_bits;           // 0xCD Endpoint Control Register
RESERVED_bits25          : array[0..2] of byte;
ENDPT4_bits              : TUSB0_ENDPT_bits;           // 0xD1 Endpoint Control Register
RESERVED_bits26          : array[0..2] of byte;
ENDPT5_bits              : TUSB0_ENDPT_bits;           // 0xD5 Endpoint Control Register
RESERVED_bits27          : array[0..2] of byte;
ENDPT6_bits              : TUSB0_ENDPT_bits;           // 0xD9 Endpoint Control Register
RESERVED_bits28          : array[0..2] of byte;
ENDPT7_bits              : TUSB0_ENDPT_bits;           // 0xDD Endpoint Control Register
RESERVED_bits29          : array[0..2] of byte;
ENDPT8_bits              : TUSB0_ENDPT_bits;           // 0xE1 Endpoint Control Register
RESERVED_bits30          : array[0..2] of byte;
ENDPT9_bits              : TUSB0_ENDPT_bits;           // 0xE5 Endpoint Control Register
RESERVED_bits31          : array[0..2] of byte;
ENDPT10_bits             : TUSB0_ENDPT_bits;           // 0xE9 Endpoint Control Register
RESERVED_bits32          : array[0..2] of byte;
ENDPT11_bits             : TUSB0_ENDPT_bits;           // 0xED Endpoint Control Register
RESERVED_bits33          : array[0..2] of byte;
ENDPT12_bits             : TUSB0_ENDPT_bits;           // 0xF1 Endpoint Control Register
RESERVED_bits34          : array[0..2] of byte;
ENDPT13_bits             : TUSB0_ENDPT_bits;           // 0xF5 Endpoint Control Register
RESERVED_bits35          : array[0..2] of byte;
ENDPT14_bits             : TUSB0_ENDPT_bits;           // 0xF9 Endpoint Control Register
RESERVED_bits36          : array[0..2] of byte;
ENDPT15_bits             : TUSB0_ENDPT_bits;           // 0xFD Endpoint Control Register
RESERVED_bits37          : array[0..2] of byte;
USBCTRL_bits             : TUSB0_USBCTRL_bits;         // 0x101 USB Control Register
RESERVED_bits38          : array[0..2] of byte;
OBSERVE_bits             : TUSB0_OBSERVE_bits;         // 0x105 USB OTG Observe Register
RESERVED_bits39          : array[0..2] of byte;
CONTROL_bits             : TUSB0_CONTROL_bits;         // 0x109 USB OTG Control Register
RESERVED_bits40          : array[0..2] of byte;
USBTRC0_bits             : TUSB0_USBTRC0_bits;         // 0x10D USB Transceiver Control Register 0
RESERVED_bits41          : array[0..6] of byte;
USBFRMADJUST_bits        : TUSB0_USBFRMADJUST_bits;    // 0x115 Frame Adjust Register
);
end;

TUSB0Registers_bitbanded = record
  PERID                  : TUSB0_PERID_bitbanded;      // 0x01 Peripheral ID Register
  RESERVED0              : array[0..2] of array[0..7] of longWord;
  IDCOMP                 : TUSB0_IDCOMP_bitbanded;     // 0x05 Peripheral ID Complement Register
  RESERVED1              : array[0..2] of array[0..7] of longWord;
  REV                    : TUSB0_REV_bitbanded;        // 0x09 Peripheral Revision Register
  RESERVED2              : array[0..2] of array[0..7] of longWord;
  ADDINFO                : TUSB0_ADDINFO_bitbanded;    // 0x0D Peripheral Additional Info Register
  RESERVED3              : array[0..2] of array[0..7] of longWord;
  OTGISTAT               : TUSB0_OTGISTAT_bitbanded;   // 0x11 OTG Interrupt Status Register
  RESERVED4              : array[0..2] of array[0..7] of longWord;
  OTGICR                 : TUSB0_OTGICR_bitbanded;     // 0x15 OTG Interrupt Control Register
  RESERVED5              : array[0..2] of array[0..7] of longWord;
  OTGSTAT                : TUSB0_OTGSTAT_bitbanded;    // 0x19 OTG Status Register
  RESERVED6              : array[0..2] of array[0..7] of longWord;
  OTGCTL                 : TUSB0_OTGCTL_bitbanded;     // 0x1D OTG Control Register
  RESERVED7              : array[0..98] of array[0..7] of longWord;
  ISTAT                  : TUSB0_ISTAT_bitbanded;      // 0x81 Interrupt Status Register
  RESERVED8              : array[0..2] of array[0..7] of longWord;
  INTEN                  : TUSB0_INTEN_bitbanded;      // 0x85 Interrupt Enable Register
  RESERVED9              : array[0..2] of array[0..7] of longWord;
  ERRSTAT                : TUSB0_ERRSTAT_bitbanded;    // 0x89 Error Interrupt Status Register
  RESERVED10             : array[0..2] of array[0..7] of longWord;
  ERREN                  : TUSB0_ERREN_bitbanded;      // 0x8D Error Interrupt Enable Register
  RESERVED11             : array[0..2] of array[0..7] of longWord;
  STAT                   : TUSB0_STAT_bitbanded;       // 0x91 Status Register
  RESERVED12             : array[0..2] of array[0..7] of longWord;
  CTL                    : TUSB0_CTL_bitbanded;        // 0x95 Control Register
  RESERVED13             : array[0..2] of array[0..7] of longWord;
  ADDR                   : TUSB0_ADDR_bitbanded;       // 0x99 Address Register
  RESERVED14             : array[0..2] of array[0..7] of longWord;
  BDTPAGE1               : TUSB0_BDTPAGE1_bitbanded;   // 0x9D BDT Page Register 1
  RESERVED15             : array[0..2] of array[0..7] of longWord;
  FRMNUML                : TUSB0_FRMNUML_bitbanded;    // 0xA1 Frame Number Register Low
  RESERVED16             : array[0..2] of array[0..7] of longWord;
  FRMNUMH                : TUSB0_FRMNUMH_bitbanded;    // 0xA5 Frame Number Register High
  RESERVED17             : array[0..2] of array[0..7] of longWord;
  TOKEN                  : TUSB0_TOKEN_bitbanded;      // 0xA9 Token Register
  RESERVED18             : array[0..2] of array[0..7] of longWord;
  SOFTHLD                : TUSB0_SOFTHLD_bitbanded;    // 0xAD SOF Threshold Register
  RESERVED19             : array[0..2] of array[0..7] of longWord;
  BDTPAGE2               : TUSB0_BDTPAGE2_bitbanded;   // 0xB1 BDT Page Register 2
  RESERVED20             : array[0..2] of array[0..7] of longWord;
  BDTPAGE3               : TUSB0_BDTPAGE3_bitbanded;   // 0xB5 BDT Page Register 3
  RESERVED21             : array[0..10] of array[0..7] of longWord;
  ENDPT0                 : TUSB0_ENDPT_bitbanded;      // 0xC1 Endpoint Control Register
  RESERVED22             : array[0..2] of array[0..7] of longWord;
  ENDPT1                 : TUSB0_ENDPT_bitbanded;      // 0xC5 Endpoint Control Register
  RESERVED23             : array[0..2] of array[0..7] of longWord;
  ENDPT2                 : TUSB0_ENDPT_bitbanded;      // 0xC9 Endpoint Control Register
  RESERVED24             : array[0..2] of array[0..7] of longWord;
  ENDPT3                 : TUSB0_ENDPT_bitbanded;      // 0xCD Endpoint Control Register
  RESERVED25             : array[0..2] of array[0..7] of longWord;
  ENDPT4                 : TUSB0_ENDPT_bitbanded;      // 0xD1 Endpoint Control Register
  RESERVED26             : array[0..2] of array[0..7] of longWord;
  ENDPT5                 : TUSB0_ENDPT_bitbanded;      // 0xD5 Endpoint Control Register
  RESERVED27             : array[0..2] of array[0..7] of longWord;
  ENDPT6                 : TUSB0_ENDPT_bitbanded;      // 0xD9 Endpoint Control Register
  RESERVED28             : array[0..2] of array[0..7] of longWord;
  ENDPT7                 : TUSB0_ENDPT_bitbanded;      // 0xDD Endpoint Control Register
  RESERVED29             : array[0..2] of array[0..7] of longWord;
  ENDPT8                 : TUSB0_ENDPT_bitbanded;      // 0xE1 Endpoint Control Register
  RESERVED30             : array[0..2] of array[0..7] of longWord;
  ENDPT9                 : TUSB0_ENDPT_bitbanded;      // 0xE5 Endpoint Control Register
  RESERVED31             : array[0..2] of array[0..7] of longWord;
  ENDPT10                : TUSB0_ENDPT_bitbanded;      // 0xE9 Endpoint Control Register
  RESERVED32             : array[0..2] of array[0..7] of longWord;
  ENDPT11                : TUSB0_ENDPT_bitbanded;      // 0xED Endpoint Control Register
  RESERVED33             : array[0..2] of array[0..7] of longWord;
  ENDPT12                : TUSB0_ENDPT_bitbanded;      // 0xF1 Endpoint Control Register
  RESERVED34             : array[0..2] of array[0..7] of longWord;
  ENDPT13                : TUSB0_ENDPT_bitbanded;      // 0xF5 Endpoint Control Register
  RESERVED35             : array[0..2] of array[0..7] of longWord;
  ENDPT14                : TUSB0_ENDPT_bitbanded;      // 0xF9 Endpoint Control Register
  RESERVED36             : array[0..2] of array[0..7] of longWord;
  ENDPT15                : TUSB0_ENDPT_bitbanded;      // 0xFD Endpoint Control Register
  RESERVED37             : array[0..2] of array[0..7] of longWord;
  USBCTRL                : TUSB0_USBCTRL_bitbanded;    // 0x101 USB Control Register
  RESERVED38             : array[0..2] of array[0..7] of longWord;
  OBSERVE                : TUSB0_OBSERVE_bitbanded;    // 0x105 USB OTG Observe Register
  RESERVED39             : array[0..2] of array[0..7] of longWord;
  CONTROL                : TUSB0_CONTROL_bitbanded;    // 0x109 USB OTG Control Register
  RESERVED40             : array[0..2] of array[0..7] of longWord;
  USBTRC0                : TUSB0_USBTRC0_bitbanded;    // 0x10D USB Transceiver Control Register 0
  RESERVED41             : array[0..6] of array[0..7] of longWord;
  USBFRMADJUST           : TUSB0_USBFRMADJUST_bitbanded;// 0x115 Frame Adjust Register
end;

// USB Device Charger Detection module
TUSBDCD_CONTROL_bits = bitpacked record
  IACK                   : TBits_1;                    // [0:0] Interrupt Acknowledge
  RESERVED0              : TBits_7;                    // [1:7] no description available
  &IF                    : TBits_1;                    // [8:8] Interrupt Flag
  RESERVED1              : TBits_7;                    // [9:15] no description available
  IE                     : TBits_1;                    // [16:16] Interrupt Enable
  RESERVED2              : TBits_7;                    // [17:23] no description available
  START                  : TBits_1;                    // [24:24] Start Change Detection Sequence
  SR                     : TBits_1;                    // [25:25] Software Reset
  RESERVED3              : TBits_6;                    // [26:31] no description available
end;

TUSBDCD_CONTROL_bitbanded = record
  IACK                   : longWord;                   // [0:0] Interrupt Acknowledge
  RESERVED0              : array[0..6] of longWord;    // [1:7] no description available
  &IF                    : longWord;                   // [8:8] Interrupt Flag
  RESERVED1              : array[0..6] of longWord;    // [9:15] no description available
  IE                     : longWord;                   // [16:16] Interrupt Enable
  RESERVED2              : array[0..6] of longWord;    // [17:23] no description available
  START                  : longWord;                   // [24:24] Start Change Detection Sequence
  SR                     : longWord;                   // [25:25] Software Reset
  RESERVED3              : array[0..5] of longWord;    // [26:31] no description available
end;

TUSBDCD_CLOCK_bits = bitpacked record
  CLOCK_UNIT             : TBits_1;                    // [0:0] Unit of measurement encoding for Clock Speed
  RESERVED0              : TBits_1;                    // [1:1] no description available
  CLOCK_SPEED            : TBits_10;                   // [2:11] Numerical Value of Clock Speed in Binary
  RESERVED1              : TBits_20;                   // [12:31] no description available
end;

TUSBDCD_CLOCK_bitbanded = record
  CLOCK_UNIT             : longWord;                   // [0:0] Unit of measurement encoding for Clock Speed
  RESERVED0              : longWord;                   // [1:1] no description available
  CLOCK_SPEED            : array[0..9] of longWord;    // [2:11] Numerical Value of Clock Speed in Binary
  RESERVED1              : array[0..19] of longWord;   // [12:31] no description available
end;

TUSBDCD_STATUS_bits = bitpacked record
  RESERVED0              : TBits_16;                   // [0:15] no description available
  SEQ_RES                : TBits_2;                    // [16:17] Charger Detection Sequence Results
  SEQ_STAT               : TBits_2;                    // [18:19] Charger Detection Sequence Status
  ERR                    : TBits_1;                    // [20:20] Error Flag
  &TO                    : TBits_1;                    // [21:21] Timeout Flag
  ACTIVE                 : TBits_1;                    // [22:22] Active Status Indicator
  RESERVED1              : TBits_9;                    // [23:31] no description available
end;

TUSBDCD_STATUS_bitbanded = record
  RESERVED0              : array[0..15] of longWord;   // [0:15] no description available
  SEQ_RES                : array[0..1] of longWord;    // [16:17] Charger Detection Sequence Results
  SEQ_STAT               : array[0..1] of longWord;    // [18:19] Charger Detection Sequence Status
  ERR                    : longWord;                   // [20:20] Error Flag
  &TO                    : longWord;                   // [21:21] Timeout Flag
  ACTIVE                 : longWord;                   // [22:22] Active Status Indicator
  RESERVED1              : array[0..8] of longWord;    // [23:31] no description available
end;

TUSBDCD_TIMER0_bits = bitpacked record
  TUNITCON               : TBits_12;                   // [0:11] Unit Connection Timer Elapse (in ms)
  RESERVED0              : TBits_4;                    // [12:15] no description available
  TSEQ_INIT              : TBits_10;                   // [16:25] Sequence Initiation Time
  RESERVED1              : TBits_6;                    // [26:31] no description available
end;

TUSBDCD_TIMER0_bitbanded = record
  TUNITCON               : array[0..11] of longWord;   // [0:11] Unit Connection Timer Elapse (in ms)
  RESERVED0              : array[0..3] of longWord;    // [12:15] no description available
  TSEQ_INIT              : array[0..9] of longWord;    // [16:25] Sequence Initiation Time
  RESERVED1              : array[0..5] of longWord;    // [26:31] no description available
end;

TUSBDCD_TIMER1_bits = bitpacked record
  TVDPSRC_ON             : TBits_10;                   // [0:9] Time Period Comparator Enabled
  RESERVED0              : TBits_6;                    // [10:15] no description available
  TDCD_DBNC              : TBits_10;                   // [16:25] Time Period to Debounce D+ Signal
  RESERVED1              : TBits_6;                    // [26:31] no description available
end;

TUSBDCD_TIMER1_bitbanded = record
  TVDPSRC_ON             : array[0..9] of longWord;    // [0:9] Time Period Comparator Enabled
  RESERVED0              : array[0..5] of longWord;    // [10:15] no description available
  TDCD_DBNC              : array[0..9] of longWord;    // [16:25] Time Period to Debounce D+ Signal
  RESERVED1              : array[0..5] of longWord;    // [26:31] no description available
end;

TUSBDCD_TIMER2_bits = bitpacked record
  CHECK_DM               : TBits_4;                    // [0:3] Time Before Check of D- Line
  RESERVED0              : TBits_12;                   // [4:15] no description available
  TVDPSRC_CON            : TBits_10;                   // [16:25] Time Period Before Enabling D+ Pullup
  RESERVED1              : TBits_6;                    // [26:31] no description available
end;

TUSBDCD_TIMER2_bitbanded = record
  CHECK_DM               : array[0..3] of longWord;    // [0:3] Time Before Check of D- Line
  RESERVED0              : array[0..11] of longWord;   // [4:15] no description available
  TVDPSRC_CON            : array[0..9] of longWord;    // [16:25] Time Period Before Enabling D+ Pullup
  RESERVED1              : array[0..5] of longWord;    // [26:31] no description available
end;

TUSBDCD_Registers = record
  case boolean of false: (
  CONTROL                : longWord;                   // 0x00 Control Register
  CLOCK                  : longWord;                   // 0x04 Clock Register
  STATUS                 : longWord;                   // 0x08 Status Register
  RESERVED0              : longWord;                   // 0x0C
  TIMER0                 : longWord;                   // 0x10 TIMER0 Register
  TIMER1                 : longWord;                   // 0x14 no description available
  TIMER2                 : longWord;                   // 0x18 no description available
);
true : (
CONTROL_bits             : TUSBDCD_CONTROL_bits;       // 0x04 Control Register
CLOCK_bits               : TUSBDCD_CLOCK_bits;         // 0x08 Clock Register
STATUS_bits              : TUSBDCD_STATUS_bits;        // 0x0C Status Register
RESERVED_bits0           : longWord;
TIMER0_bits              : TUSBDCD_TIMER0_bits;        // 0x14 TIMER0 Register
TIMER1_bits              : TUSBDCD_TIMER1_bits;        // 0x18 no description available
TIMER2_bits              : TUSBDCD_TIMER2_bits;        // 0x1C no description available
);
end;

TUSBDCDRegisters_bitbanded = record
  CONTROL                : TUSBDCD_CONTROL_bitbanded;  // 0x04 Control Register
  CLOCK                  : TUSBDCD_CLOCK_bitbanded;    // 0x08 Clock Register
  STATUS                 : TUSBDCD_STATUS_bitbanded;   // 0x0C Status Register
  RESERVED0              : array[0..3] of array[0..7] of longWord;
  TIMER0                 : TUSBDCD_TIMER0_bitbanded;   // 0x14 TIMER0 Register
  TIMER1                 : TUSBDCD_TIMER1_bitbanded;   // 0x18 no description available
  TIMER2                 : TUSBDCD_TIMER2_bitbanded;   // 0x1C no description available
end;

// Voltage Reference
TVREF_TRM_bits = bitpacked record
  TRIM                   : TBits_6;                    // [0:5] Trim bits
  CHOPEN                 : TBits_1;                    // [6:6] Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized.
  RESERVED0              : TBits_1;                    // [7:7] no description available
end;

TVREF_TRM_bitbanded = record
  TRIM                   : array[0..5] of longWord;    // [0:5] Trim bits
  CHOPEN                 : longWord;                   // [6:6] Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized.
  RESERVED0              : longWord;                   // [7:7] no description available
end;

TVREF_SC_bits = bitpacked record
  MODE_LV                : TBits_2;                    // [0:1] Buffer Mode selection
  VREFST                 : TBits_1;                    // [2:2] Internal Voltage Reference stable
  RESERVED0              : TBits_1;                    // [3:3] no description available
  RESERVED1              : TBits_1;                    // [4:4] no description available
  RESERVED2              : TBits_1;                    // [5:5] no description available
  REGEN                  : TBits_1;                    // [6:6] Regulator enable
  VREFEN                 : TBits_1;                    // [7:7] Internal Voltage Reference enable
end;

TVREF_SC_bitbanded = record
  MODE_LV                : array[0..1] of longWord;    // [0:1] Buffer Mode selection
  VREFST                 : longWord;                   // [2:2] Internal Voltage Reference stable
  RESERVED0              : longWord;                   // [3:3] no description available
  RESERVED1              : longWord;                   // [4:4] no description available
  RESERVED2              : longWord;                   // [5:5] no description available
  REGEN                  : longWord;                   // [6:6] Regulator enable
  VREFEN                 : longWord;                   // [7:7] Internal Voltage Reference enable
end;

TVREF_Registers = record
  case boolean of false: (
  TRM                    : byte;                       // 0x00 VREF Trim Register
  SC                     : byte;                       // 0x01 VREF Status and Control Register
);
true : (
TRM_bits                 : TVREF_TRM_bits;             // 0x01 VREF Trim Register
SC_bits                  : TVREF_SC_bits;              // 0x02 VREF Status and Control Register
);
end;

TVREFRegisters_bitbanded = record
  TRM                    : TVREF_TRM_bitbanded;        // 0x01 VREF Trim Register
  SC                     : TVREF_SC_bitbanded;         // 0x02 VREF Status and Control Register
end;

// Generation 2008 Watchdog Timer
TWDOG_STCTRLH_bits = bitpacked record
  WDOGEN                 : TBits_1;                    // [0:0] no description available
  CLKSRC                 : TBits_1;                    // [1:1] no description available
  IRQRSTEN               : TBits_1;                    // [2:2] no description available
  WINEN                  : TBits_1;                    // [3:3] no description available
  ALLOWUPDATE            : TBits_1;                    // [4:4] no description available
  DBGEN                  : TBits_1;                    // [5:5] no description available
  STOPEN                 : TBits_1;                    // [6:6] no description available
  WAITEN                 : TBits_1;                    // [7:7] no description available
  RESERVED0              : TBits_1;                    // [8:8] no description available
  RESERVED1              : TBits_1;                    // [9:9] no description available
  TESTWDOG               : TBits_1;                    // [10:10] no description available
  TESTSEL                : TBits_1;                    // [11:11] no description available
  BYTESEL                : TBits_2;                    // [12:13] no description available
  DISTESTWDOG            : TBits_1;                    // [14:14] no description available
  RESERVED2              : TBits_1;                    // [15:15] no description available
end;

TWDOG_STCTRLH_bitbanded = record
  WDOGEN                 : longWord;                   // [0:0] no description available
  CLKSRC                 : longWord;                   // [1:1] no description available
  IRQRSTEN               : longWord;                   // [2:2] no description available
  WINEN                  : longWord;                   // [3:3] no description available
  ALLOWUPDATE            : longWord;                   // [4:4] no description available
  DBGEN                  : longWord;                   // [5:5] no description available
  STOPEN                 : longWord;                   // [6:6] no description available
  WAITEN                 : longWord;                   // [7:7] no description available
  RESERVED0              : longWord;                   // [8:8] no description available
  RESERVED1              : longWord;                   // [9:9] no description available
  TESTWDOG               : longWord;                   // [10:10] no description available
  TESTSEL                : longWord;                   // [11:11] no description available
  BYTESEL                : array[0..1] of longWord;    // [12:13] no description available
  DISTESTWDOG            : longWord;                   // [14:14] no description available
  RESERVED2              : longWord;                   // [15:15] no description available
end;

TWDOG_STCTRLL_bits = bitpacked record
  RESERVED0              : TBits_15;                   // [0:14] no description available
  INTFLG                 : TBits_1;                    // [15:15] no description available
end;

TWDOG_STCTRLL_bitbanded = record
  RESERVED0              : array[0..14] of longWord;   // [0:14] no description available
  INTFLG                 : longWord;                   // [15:15] no description available
end;

TWDOG_TOVALH_bits = bitpacked record
  TOVALHIGH              : TBits_16;                   // [0:15] no description available
end;

TWDOG_TOVALH_bitbanded = record
  TOVALHIGH              : array[0..15] of longWord;   // [0:15] no description available
end;

TWDOG_TOVALL_bits = bitpacked record
  TOVALLOW               : TBits_16;                   // [0:15] no description available
end;

TWDOG_TOVALL_bitbanded = record
  TOVALLOW               : array[0..15] of longWord;   // [0:15] no description available
end;

TWDOG_WINH_bits = bitpacked record
  WINHIGH                : TBits_16;                   // [0:15] no description available
end;

TWDOG_WINH_bitbanded = record
  WINHIGH                : array[0..15] of longWord;   // [0:15] no description available
end;

TWDOG_WINL_bits = bitpacked record
  WINLOW                 : TBits_16;                   // [0:15] no description available
end;

TWDOG_WINL_bitbanded = record
  WINLOW                 : array[0..15] of longWord;   // [0:15] no description available
end;

TWDOG_REFRESH_bits = bitpacked record
  WDOGREFRESH            : TBits_16;                   // [0:15] no description available
end;

TWDOG_REFRESH_bitbanded = record
  WDOGREFRESH            : array[0..15] of longWord;   // [0:15] no description available
end;

TWDOG_UNLOCK_bits = bitpacked record
  WDOGUNLOCK             : TBits_16;                   // [0:15] no description available
end;

TWDOG_UNLOCK_bitbanded = record
  WDOGUNLOCK             : array[0..15] of longWord;   // [0:15] no description available
end;

TWDOG_TMROUTH_bits = bitpacked record
  TIMEROUTHIGH           : TBits_16;                   // [0:15] no description available
end;

TWDOG_TMROUTH_bitbanded = record
  TIMEROUTHIGH           : array[0..15] of longWord;   // [0:15] no description available
end;

TWDOG_TMROUTL_bits = bitpacked record
  TIMEROUTLOW            : TBits_16;                   // [0:15] no description available
end;

TWDOG_TMROUTL_bitbanded = record
  TIMEROUTLOW            : array[0..15] of longWord;   // [0:15] no description available
end;

TWDOG_RSTCNT_bits = bitpacked record
  RSTCNT                 : TBits_16;                   // [0:15] no description available
end;

TWDOG_RSTCNT_bitbanded = record
  RSTCNT                 : array[0..15] of longWord;   // [0:15] no description available
end;

TWDOG_PRESC_bits = bitpacked record
  RESERVED0              : TBits_8;                    // [0:7] no description available
  PRESCVAL               : TBits_3;                    // [8:10] no description available
  RESERVED1              : TBits_5;                    // [11:15] no description available
end;

TWDOG_PRESC_bitbanded = record
  RESERVED0              : array[0..7] of longWord;    // [0:7] no description available
  PRESCVAL               : array[0..2] of longWord;    // [8:10] no description available
  RESERVED1              : array[0..4] of longWord;    // [11:15] no description available
end;

TWDOG_Registers = record
  case boolean of false: (
  STCTRLH                : word;                       // 0x00 Watchdog Status and Control Register High
  STCTRLL                : word;                       // 0x02 Watchdog Status and Control Register Low
  TOVALH                 : word;                       // 0x04 Watchdog Time-out Value Register High
  TOVALL                 : word;                       // 0x06 Watchdog Time-out Value Register Low
  WINH                   : word;                       // 0x08 Watchdog Window Register High
  WINL                   : word;                       // 0x0A Watchdog Window Register Low
  REFRESH                : word;                       // 0x0C Watchdog Refresh Register
  UNLOCK                 : word;                       // 0x0E Watchdog Unlock Register
  TMROUTH                : word;                       // 0x10 Watchdog Timer Output Register High
  TMROUTL                : word;                       // 0x12 Watchdog Timer Output Register Low
  RSTCNT                 : word;                       // 0x14 Watchdog Reset Count Register
  PRESC                  : word;                       // 0x16 Watchdog Prescaler Register
);
true : (
STCTRLH_bits             : TWDOG_STCTRLH_bits;         // 0x02 Watchdog Status and Control Register High
STCTRLL_bits             : TWDOG_STCTRLL_bits;         // 0x04 Watchdog Status and Control Register Low
TOVALH_bits              : TWDOG_TOVALH_bits;          // 0x06 Watchdog Time-out Value Register High
TOVALL_bits              : TWDOG_TOVALL_bits;          // 0x08 Watchdog Time-out Value Register Low
WINH_bits                : TWDOG_WINH_bits;            // 0x0A Watchdog Window Register High
WINL_bits                : TWDOG_WINL_bits;            // 0x0C Watchdog Window Register Low
REFRESH_bits             : TWDOG_REFRESH_bits;         // 0x0E Watchdog Refresh Register
UNLOCK_bits              : TWDOG_UNLOCK_bits;          // 0x10 Watchdog Unlock Register
TMROUTH_bits             : TWDOG_TMROUTH_bits;         // 0x12 Watchdog Timer Output Register High
TMROUTL_bits             : TWDOG_TMROUTL_bits;         // 0x14 Watchdog Timer Output Register Low
RSTCNT_bits              : TWDOG_RSTCNT_bits;          // 0x16 Watchdog Reset Count Register
PRESC_bits               : TWDOG_PRESC_bits;           // 0x18 Watchdog Prescaler Register
);
end;

TWDOGRegisters_bitbanded = record
  STCTRLH                : TWDOG_STCTRLH_bitbanded;    // 0x02 Watchdog Status and Control Register High
  STCTRLL                : TWDOG_STCTRLL_bitbanded;    // 0x04 Watchdog Status and Control Register Low
  TOVALH                 : TWDOG_TOVALH_bitbanded;     // 0x06 Watchdog Time-out Value Register High
  TOVALL                 : TWDOG_TOVALL_bitbanded;     // 0x08 Watchdog Time-out Value Register Low
  WINH                   : TWDOG_WINH_bitbanded;       // 0x0A Watchdog Window Register High
  WINL                   : TWDOG_WINL_bitbanded;       // 0x0C Watchdog Window Register Low
  REFRESH                : TWDOG_REFRESH_bitbanded;    // 0x0E Watchdog Refresh Register
  UNLOCK                 : TWDOG_UNLOCK_bitbanded;     // 0x10 Watchdog Unlock Register
  TMROUTH                : TWDOG_TMROUTH_bitbanded;    // 0x12 Watchdog Timer Output Register High
  TMROUTL                : TWDOG_TMROUTL_bitbanded;    // 0x14 Watchdog Timer Output Register Low
  RSTCNT                 : TWDOG_RSTCNT_bitbanded;     // 0x16 Watchdog Reset Count Register
  PRESC                  : TWDOG_PRESC_bitbanded;      // 0x18 Watchdog Prescaler Register
end;

const
  ADC0_BASE              = $4003B000;
  ADC0_BB_BASE           = $42760000;
  ADC1_BASE              = $400BB000;
  ADC1_BB_BASE           = $43760000;
  AIPS0_BASE             = $40000000;
  AIPS0_BB_BASE          = $42000000;
  AIPS1_BASE             = $40080000;
  AIPS1_BB_BASE          = $43000000;
  AXBS_BASE              = $40004000;
  AXBS_BB_BASE           = $42080000;
  CAN0_BASE              = $40024000;
  CAN0_BB_BASE           = $42480000;
  CMP0_BASE              = $40073000;
  CMP0_BB_BASE           = $42E60000;
  CMP1_BASE              = $40073008;
  CMP1_BB_BASE           = $42E60100;
  CMP2_BASE              = $40073010;
  CMP2_BB_BASE           = $42E60200;
  CMT_BASE               = $40062000;
  CMT_BB_BASE            = $42C40000;
  CRC_BASE               = $40032000;
  CRC_BB_BASE            = $42640000;
  DAC0_BASE              = $400CC000;
  DAC0_BB_BASE           = $43980000;
  DMA_BASE               = $40008000;
  DMA_BB_BASE            = $42100000;
  DMAMUX_BASE            = $40021000;
  DMAMUX_BB_BASE         = $42420000;
  EWM_BASE               = $40061000;
  EWM_BB_BASE            = $42C20000;
  FB_BASE                = $4000C000;
  FB_BB_BASE             = $42180000;
  FMC_BASE               = $4001F000;
  FMC_BB_BASE            = $423E0000;
  FTFL_BASE              = $40020000;
  FTFL_BB_BASE           = $42400000;
  FTFL_FlashConfig_BASE  = $00000400;
  FTM0_BASE              = $40038000;
  FTM0_BB_BASE           = $42700000;
  FTM1_BASE              = $40039000;
  FTM1_BB_BASE           = $42720000;
  FTM2_BASE              = $400B8000;
  FTM2_BB_BASE           = $43700000;
  PTA_BASE               = $400FF000;
  PTA_BB_BASE            = $43FE0000;
  PTB_BASE               = $400FF040;
  PTB_BB_BASE            = $43FE0800;
  PTC_BASE               = $400FF080;
  PTC_BB_BASE            = $43FE1000;
  PTD_BASE               = $400FF0C0;
  PTD_BB_BASE            = $43FE1800;
  PTE_BASE               = $400FF100;
  PTE_BB_BASE            = $43FE2000;
  I2C0_BASE              = $40066000;
  I2C0_BB_BASE           = $42CC0000;
  I2C1_BASE              = $40067000;
  I2C1_BB_BASE           = $42CE0000;
  I2S0_BASE              = $4002F000;
  I2S0_BB_BASE           = $425E0000;
  LLWU_BASE              = $4007C000;
  LLWU_BB_BASE           = $42F80000;
  LPTMR0_BASE            = $40040000;
  LPTMR0_BB_BASE         = $42800000;
  MCG_BASE               = $40064000;
  MCG_BB_BASE            = $42C80000;
  MCM_BASE               = $E0080000;
  NVIC_BASE              = $E000E100;
  OSC_BASE               = $40065000;
  OSC_BB_BASE            = $42CA0000;
  PDB0_BASE              = $40036000;
  PDB0_BB_BASE           = $426C0000;
  PIT_BASE               = $40037000;
  PIT_BB_BASE            = $426E0000;
  PMC_BASE               = $4007D000;
  PMC_BB_BASE            = $42FA0000;
  PORTA_BASE             = $40049000;
  PORTA_BB_BASE          = $42920000;
  PORTB_BASE             = $4004A000;
  PORTB_BB_BASE          = $42940000;
  PORTC_BASE             = $4004B000;
  PORTC_BB_BASE          = $42960000;
  PORTD_BASE             = $4004C000;
  PORTD_BB_BASE          = $42980000;
  PORTE_BASE             = $4004D000;
  PORTE_BB_BASE          = $429A0000;
  RCM_BASE               = $4007F000;
  RCM_BB_BASE            = $42FE0000;
  RFSYS_BASE             = $40041000;
  RFSYS_BB_BASE          = $42820000;
  RFVBAT_BASE            = $4003E000;
  RFVBAT_BB_BASE         = $427C0000;
  RTC_BASE               = $4003D000;
  RTC_BB_BASE            = $427A0000;
  SIM_BASE               = $40047000;
  SIM_BB_BASE            = $428E0000;
  SMC_BASE               = $4007E000;
  SMC_BB_BASE            = $42FC0000;
  SPI0_BASE              = $4002C000;
  SPI0_BB_BASE           = $42580000;
  SPI1_BASE              = $4002D000;
  SPI1_BB_BASE           = $425A0000;
  SysTick_BASE           = $E000E010;
  SystemControl_BASE     = $E000E000;
  TSI0_BASE              = $40045000;
  TSI0_BB_BASE           = $428A0000;
  UART0_BASE             = $4006A000;
  UART0_BB_BASE          = $42D40000;
  UART1_BASE             = $4006B000;
  UART1_BB_BASE          = $42D60000;
  UART2_BASE             = $4006C000;
  UART2_BB_BASE          = $42D80000;
  UART3_BASE             = $4006D000;
  UART3_BB_BASE          = $42DA0000;
  UART4_BASE             = $400EA000;
  UART4_BB_BASE          = $43D40000;
  USB0_BASE              = $40072000;
  USB0_BB_BASE           = $42E40000;
  USBDCD_BASE            = $40035000;
  USBDCD_BB_BASE         = $426A0000;
  VREF_BASE              = $40074000;
  VREF_BB_BASE           = $42E80000;
  WDOG_BASE              = $40052000;
  WDOG_BB_BASE           = $42A40000;

var
  ADC0                   : TADC0_Registers absolute ADC0_BASE;
  ADC0_bitbanded         : TADC0Registers_bitbanded absolute ADC0_BB_BASE;
  ADC1                   : TADC1_Registers absolute ADC1_BASE;
  ADC1_bitbanded         : TADC1Registers_bitbanded absolute ADC1_BB_BASE;
  AIPS0                  : TAIPS0_Registers absolute AIPS0_BASE;
  AIPS0_bitbanded        : TAIPS0Registers_bitbanded absolute AIPS0_BB_BASE;
  AIPS1                  : TAIPS1_Registers absolute AIPS1_BASE;
  AIPS1_bitbanded        : TAIPS1Registers_bitbanded absolute AIPS1_BB_BASE;
  AXBS                   : TAXBS_Registers absolute AXBS_BASE;
  AXBS_bitbanded         : TAXBSRegisters_bitbanded absolute AXBS_BB_BASE;
  CAN0                   : TCAN0_Registers absolute CAN0_BASE;
  CAN0_bitbanded         : TCAN0Registers_bitbanded absolute CAN0_BB_BASE;
  CMP0                   : TCMP0_Registers absolute CMP0_BASE;
  CMP0_bitbanded         : TCMP0Registers_bitbanded absolute CMP0_BB_BASE;
  CMP1                   : TCMP1_Registers absolute CMP1_BASE;
  CMP1_bitbanded         : TCMP1Registers_bitbanded absolute CMP1_BB_BASE;
  CMP2                   : TCMP2_Registers absolute CMP2_BASE;
  CMP2_bitbanded         : TCMP2Registers_bitbanded absolute CMP2_BB_BASE;
  CMT                    : TCMT_Registers absolute CMT_BASE;
  CMT_bitbanded          : TCMTRegisters_bitbanded absolute CMT_BB_BASE;
  CRC                    : TCRC_Registers absolute CRC_BASE;
  CRC_bitbanded          : TCRCRegisters_bitbanded absolute CRC_BB_BASE;
  DAC0                   : TDAC0_Registers absolute DAC0_BASE;
  DAC0_bitbanded         : TDAC0Registers_bitbanded absolute DAC0_BB_BASE;
  DMA                    : TDMA_Registers absolute DMA_BASE;
  DMA_bitbanded          : TDMARegisters_bitbanded absolute DMA_BB_BASE;
  DMAMUX                 : TDMAMUX_Registers absolute DMAMUX_BASE;
  DMAMUX_bitbanded       : TDMAMUXRegisters_bitbanded absolute DMAMUX_BB_BASE;
  EWM                    : TEWM_Registers absolute EWM_BASE;
  EWM_bitbanded          : TEWMRegisters_bitbanded absolute EWM_BB_BASE;
  FB                     : TFB_Registers absolute FB_BASE;
  FB_bitbanded           : TFBRegisters_bitbanded absolute FB_BB_BASE;
  FMC                    : TFMC_Registers absolute FMC_BASE;
  FMC_bitbanded          : TFMCRegisters_bitbanded absolute FMC_BB_BASE;
  FTFL                   : TFTFL_Registers absolute FTFL_BASE;
  FTFL_bitbanded         : TFTFLRegisters_bitbanded absolute FTFL_BB_BASE;
  FTFL_FlashConfig       : TFTFL_FlashConfig_Registers absolute FTFL_FlashConfig_BASE;
  FTM0                   : TFTM0_Registers absolute FTM0_BASE;
  FTM0_bitbanded         : TFTM0Registers_bitbanded absolute FTM0_BB_BASE;
  FTM1                   : TFTM1_Registers absolute FTM1_BASE;
  FTM1_bitbanded         : TFTM1Registers_bitbanded absolute FTM1_BB_BASE;
  FTM2                   : TFTM2_Registers absolute FTM2_BASE;
  FTM2_bitbanded         : TFTM2Registers_bitbanded absolute FTM2_BB_BASE;
  PTA                    : TPTA_Registers absolute PTA_BASE;
  PTA_bitbanded          : TPTARegisters_bitbanded absolute PTA_BB_BASE;
  PTB                    : TPTB_Registers absolute PTB_BASE;
  PTB_bitbanded          : TPTBRegisters_bitbanded absolute PTB_BB_BASE;
  PTC                    : TPTC_Registers absolute PTC_BASE;
  PTC_bitbanded          : TPTCRegisters_bitbanded absolute PTC_BB_BASE;
  PTD                    : TPTD_Registers absolute PTD_BASE;
  PTD_bitbanded          : TPTDRegisters_bitbanded absolute PTD_BB_BASE;
  PTE                    : TPTE_Registers absolute PTE_BASE;
  PTE_bitbanded          : TPTERegisters_bitbanded absolute PTE_BB_BASE;
  I2C0                   : TI2C0_Registers absolute I2C0_BASE;
  I2C0_bitbanded         : TI2C0Registers_bitbanded absolute I2C0_BB_BASE;
  I2C1                   : TI2C1_Registers absolute I2C1_BASE;
  I2C1_bitbanded         : TI2C1Registers_bitbanded absolute I2C1_BB_BASE;
  I2S0                   : TI2S0_Registers absolute I2S0_BASE;
  I2S0_bitbanded         : TI2S0Registers_bitbanded absolute I2S0_BB_BASE;
  LLWU                   : TLLWU_Registers absolute LLWU_BASE;
  LLWU_bitbanded         : TLLWURegisters_bitbanded absolute LLWU_BB_BASE;
  LPTMR0                 : TLPTMR0_Registers absolute LPTMR0_BASE;
  LPTMR0_bitbanded       : TLPTMR0Registers_bitbanded absolute LPTMR0_BB_BASE;
  MCG                    : TMCG_Registers absolute MCG_BASE;
  MCG_bitbanded          : TMCGRegisters_bitbanded absolute MCG_BB_BASE;
  MCM                    : TMCM_Registers absolute MCM_BASE;
  NVIC                   : TNVIC_Registers absolute NVIC_BASE;
  OSC                    : TOSC_Registers absolute OSC_BASE;
  OSC_bitbanded          : TOSCRegisters_bitbanded absolute OSC_BB_BASE;
  PDB0                   : TPDB0_Registers absolute PDB0_BASE;
  PDB0_bitbanded         : TPDB0Registers_bitbanded absolute PDB0_BB_BASE;
  PIT                    : TPIT_Registers absolute PIT_BASE;
  PIT_bitbanded          : TPITRegisters_bitbanded absolute PIT_BB_BASE;
  PMC                    : TPMC_Registers absolute PMC_BASE;
  PMC_bitbanded          : TPMCRegisters_bitbanded absolute PMC_BB_BASE;
  PORTA                  : TPORTA_Registers absolute PORTA_BASE;
  PORTA_bitbanded        : TPORTARegisters_bitbanded absolute PORTA_BB_BASE;
  PORTB                  : TPORTB_Registers absolute PORTB_BASE;
  PORTB_bitbanded        : TPORTBRegisters_bitbanded absolute PORTB_BB_BASE;
  PORTC                  : TPORTC_Registers absolute PORTC_BASE;
  PORTC_bitbanded        : TPORTCRegisters_bitbanded absolute PORTC_BB_BASE;
  PORTD                  : TPORTD_Registers absolute PORTD_BASE;
  PORTD_bitbanded        : TPORTDRegisters_bitbanded absolute PORTD_BB_BASE;
  PORTE                  : TPORTE_Registers absolute PORTE_BASE;
  PORTE_bitbanded        : TPORTERegisters_bitbanded absolute PORTE_BB_BASE;
  RCM                    : TRCM_Registers absolute RCM_BASE;
  RCM_bitbanded          : TRCMRegisters_bitbanded absolute RCM_BB_BASE;
  RFSYS                  : TRFSYS_Registers absolute RFSYS_BASE;
  RFSYS_bitbanded        : TRFSYSRegisters_bitbanded absolute RFSYS_BB_BASE;
  RFVBAT                 : TRFVBAT_Registers absolute RFVBAT_BASE;
  RFVBAT_bitbanded       : TRFVBATRegisters_bitbanded absolute RFVBAT_BB_BASE;
  RTC                    : TRTC_Registers absolute RTC_BASE;
  RTC_bitbanded          : TRTCRegisters_bitbanded absolute RTC_BB_BASE;
  SIM                    : TSIM_Registers absolute SIM_BASE;
  SIM_bitbanded          : TSIMRegisters_bitbanded absolute SIM_BB_BASE;
  SMC                    : TSMC_Registers absolute SMC_BASE;
  SMC_bitbanded          : TSMCRegisters_bitbanded absolute SMC_BB_BASE;
  SPI0                   : TSPI0_Registers absolute SPI0_BASE;
  SPI0_bitbanded         : TSPI0Registers_bitbanded absolute SPI0_BB_BASE;
  SPI1                   : TSPI1_Registers absolute SPI1_BASE;
  SPI1_bitbanded         : TSPI1Registers_bitbanded absolute SPI1_BB_BASE;
  SysTick                : TSysTick_Registers absolute SysTick_BASE;
  SystemControl          : TSystemControl_Registers absolute SystemControl_BASE;
  TSI0                   : TTSI0_Registers absolute TSI0_BASE;
  TSI0_bitbanded         : TTSI0Registers_bitbanded absolute TSI0_BB_BASE;
  UART0                  : TUART0_Registers absolute UART0_BASE;
  UART0_bitbanded        : TUART0Registers_bitbanded absolute UART0_BB_BASE;
  UART1                  : TUART1_Registers absolute UART1_BASE;
  UART1_bitbanded        : TUART1Registers_bitbanded absolute UART1_BB_BASE;
  UART2                  : TUART2_Registers absolute UART2_BASE;
  UART2_bitbanded        : TUART2Registers_bitbanded absolute UART2_BB_BASE;
  UART3                  : TUART3_Registers absolute UART3_BASE;
  UART3_bitbanded        : TUART3Registers_bitbanded absolute UART3_BB_BASE;
  UART4                  : TUART4_Registers absolute UART4_BASE;
  UART4_bitbanded        : TUART4Registers_bitbanded absolute UART4_BB_BASE;
  USB0                   : TUSB0_Registers absolute USB0_BASE;
  USB0_bitbanded         : TUSB0Registers_bitbanded absolute USB0_BB_BASE;
  USBDCD                 : TUSBDCD_Registers absolute USBDCD_BASE;
  USBDCD_bitbanded       : TUSBDCDRegisters_bitbanded absolute USBDCD_BB_BASE;
  VREF                   : TVREF_Registers absolute VREF_BASE;
  VREF_bitbanded         : TVREFRegisters_bitbanded absolute VREF_BB_BASE;
  WDOG                   : TWDOG_Registers absolute WDOG_BASE;
  WDOG_bitbanded         : TWDOGRegisters_bitbanded absolute WDOG_BB_BASE;

implementation

procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
procedure HardFault_interrupt; external name 'HardFault_interrupt';
procedure MemoryManagement_interrupt; external name 'MemoryManagement_interrupt';
procedure BusFault_interrupt; external name 'BusFault_interrupt';
procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
procedure SVC_interrupt; external name 'SVC_interrupt';
procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
procedure PendSV_interrupt; external name 'PendSV_interrupt';
procedure SysTick_interrupt; external name 'SysTick_interrupt';
procedure INT_DMA0_interrupt; external name 'INT_DMA0_interrupt';
procedure INT_DMA1_interrupt; external name 'INT_DMA1_interrupt';
procedure INT_DMA2_interrupt; external name 'INT_DMA2_interrupt';
procedure INT_DMA3_interrupt; external name 'INT_DMA3_interrupt';
procedure INT_DMA4_interrupt; external name 'INT_DMA4_interrupt';
procedure INT_DMA5_interrupt; external name 'INT_DMA5_interrupt';
procedure INT_DMA6_interrupt; external name 'INT_DMA6_interrupt';
procedure INT_DMA7_interrupt; external name 'INT_DMA7_interrupt';
procedure INT_DMA8_interrupt; external name 'INT_DMA8_interrupt';
procedure INT_DMA9_interrupt; external name 'INT_DMA9_interrupt';
procedure INT_DMA10_interrupt; external name 'INT_DMA10_interrupt';
procedure INT_DMA11_interrupt; external name 'INT_DMA11_interrupt';
procedure INT_DMA12_interrupt; external name 'INT_DMA12_interrupt';
procedure INT_DMA13_interrupt; external name 'INT_DMA13_interrupt';
procedure INT_DMA14_interrupt; external name 'INT_DMA14_interrupt';
procedure INT_DMA15_interrupt; external name 'INT_DMA15_interrupt';
procedure INT_DMA_Error_interrupt; external name 'INT_DMA_Error_interrupt';
procedure INT_FTFL_interrupt; external name 'INT_FTFL_interrupt';
procedure INT_LVD_LVW_interrupt; external name 'INT_LVD_LVW_interrupt';
procedure INT_LLW_interrupt; external name 'INT_LLW_interrupt';
procedure INT_Watchdog_interrupt; external name 'INT_Watchdog_interrupt';
procedure INT_I2C0_interrupt; external name 'INT_I2C0_interrupt';
procedure INT_I2C1_interrupt; external name 'INT_I2C1_interrupt';
procedure INT_SPI0_interrupt; external name 'INT_SPI0_interrupt';
procedure INT_SPI1_interrupt; external name 'INT_SPI1_interrupt';
procedure INT_CAN0_ORed_Message_buffer_interrupt; external name 'INT_CAN0_ORed_Message_buffer_interrupt';
procedure INT_CAN0_Bus_Off_interrupt; external name 'INT_CAN0_Bus_Off_interrupt';
procedure INT_CAN0_Error_interrupt; external name 'INT_CAN0_Error_interrupt';
procedure INT_CAN0_Tx_Warning_interrupt; external name 'INT_CAN0_Tx_Warning_interrupt';
procedure INT_CAN0_Rx_Warning_interrupt; external name 'INT_CAN0_Rx_Warning_interrupt';
procedure INT_CAN0_Wake_Up_interrupt; external name 'INT_CAN0_Wake_Up_interrupt';
procedure INT_I2S0_Tx_interrupt; external name 'INT_I2S0_Tx_interrupt';
procedure INT_I2S0_Rx_interrupt; external name 'INT_I2S0_Rx_interrupt';
procedure INT_UART0_LON_interrupt; external name 'INT_UART0_LON_interrupt';
procedure INT_UART0_RX_TX_interrupt; external name 'INT_UART0_RX_TX_interrupt';
procedure INT_UART0_ERR_interrupt; external name 'INT_UART0_ERR_interrupt';
procedure INT_UART1_RX_TX_interrupt; external name 'INT_UART1_RX_TX_interrupt';
procedure INT_UART1_ERR_interrupt; external name 'INT_UART1_ERR_interrupt';
procedure INT_UART2_RX_TX_interrupt; external name 'INT_UART2_RX_TX_interrupt';
procedure INT_UART2_ERR_interrupt; external name 'INT_UART2_ERR_interrupt';
procedure INT_UART3_RX_TX_interrupt; external name 'INT_UART3_RX_TX_interrupt';
procedure INT_UART3_ERR_interrupt; external name 'INT_UART3_ERR_interrupt';
procedure INT_UART4_RX_TX_interrupt; external name 'INT_UART4_RX_TX_interrupt';
procedure INT_UART4_ERR_interrupt; external name 'INT_UART4_ERR_interrupt';
procedure INT_ADC0_interrupt; external name 'INT_ADC0_interrupt';
procedure INT_ADC1_interrupt; external name 'INT_ADC1_interrupt';
procedure INT_CMP0_interrupt; external name 'INT_CMP0_interrupt';
procedure INT_CMP1_interrupt; external name 'INT_CMP1_interrupt';
procedure INT_CMP2_interrupt; external name 'INT_CMP2_interrupt';
procedure INT_FTM0_interrupt; external name 'INT_FTM0_interrupt';
procedure INT_FTM1_interrupt; external name 'INT_FTM1_interrupt';
procedure INT_FTM2_interrupt; external name 'INT_FTM2_interrupt';
procedure INT_CMT_interrupt; external name 'INT_CMT_interrupt';
procedure INT_RTC_interrupt; external name 'INT_RTC_interrupt';
procedure INT_RTC_Seconds_interrupt; external name 'INT_RTC_Seconds_interrupt';
procedure INT_PIT0_interrupt; external name 'INT_PIT0_interrupt';
procedure INT_PIT1_interrupt; external name 'INT_PIT1_interrupt';
procedure INT_PIT2_interrupt; external name 'INT_PIT2_interrupt';
procedure INT_PIT3_interrupt; external name 'INT_PIT3_interrupt';
procedure INT_PDB0_interrupt; external name 'INT_PDB0_interrupt';
procedure INT_USB0_interrupt; external name 'INT_USB0_interrupt';
procedure INT_USBDCD_interrupt; external name 'INT_USBDCD_interrupt';
procedure INT_Reserved95_interrupt; external name 'INT_Reserved95_interrupt';
procedure INT_DAC0_interrupt; external name 'INT_DAC0_interrupt';
procedure INT_TSI0_interrupt; external name 'INT_TSI0_interrupt';
procedure INT_LPTimer_interrupt; external name 'INT_LPTimer_interrupt';
procedure INT_PORTA_interrupt; external name 'INT_PORTA_interrupt';
procedure INT_PORTB_interrupt; external name 'INT_PORTB_interrupt';
procedure INT_PORTC_interrupt; external name 'INT_PORTC_interrupt';
procedure INT_PORTD_interrupt; external name 'INT_PORTD_interrupt';
procedure INT_PORTE_interrupt; external name 'INT_PORTE_interrupt';

{$i cortexm4f_start.inc}

  procedure FlashConfiguration; assembler; nostackframe;
  label flash_conf;
  asm
    .section ".flash_config.flash_conf"
  flash_conf:
    .byte 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF

    .text
  end;

  procedure LowLevelStartup; assembler; nostackframe;
  asm
    // Unlock watchdog
    ldr	r0, .LWDOG_BASE
    movw	r1, #50464
    strh	r1, [r0, #0xE]
    movw	r1, #55592
    strh	r1, [r0, #0xE]
    nop
    nop
    // Disable watchdog for now
    movs r1, #0
    strh r1, [r0, #0]

    b Startup

  .LWDOG_BASE:
    .long 0x40052000
  end;

  procedure Vectors; assembler; nostackframe;
  label interrupt_vectors;
  asm
    .section ".init.interrupt_vectors"
    interrupt_vectors:
    .long _stack_top
    .long LowLevelStartup                              // int -15
    .long NonMaskableInt_interrupt                     // int -14
    .long HardFault_interrupt                          // int -13
    .long MemoryManagement_interrupt                   // int -12
    .long BusFault_interrupt                           // int -11
    .long UsageFault_interrupt                         // int -10
    .long 0                                            // int -9
    .long 0                                            // int -8
    .long 0                                            // int -7
    .long 0                                            // int -6
    .long SVC_interrupt                                // int -5
    .long DebugMonitor_interrupt                       // int -4
    .long 0                                            // int -3
    .long PendSV_interrupt                             // int -2
    .long SysTick_interrupt                            // int -1
    .long 0                                            // int 0
    .long 0                                            // int 1
    .long 0                                            // int 2
    .long 0                                            // int 3
    .long 0                                            // int 4
    .long 0                                            // int 5
    .long 0                                            // int 6
    .long 0                                            // int 7
    .long 0                                            // int 8
    .long 0                                            // int 9
    .long 0                                            // int 10
    .long 0                                            // int 11
    .long 0                                            // int 12
    .long 0                                            // int 13
    .long 0                                            // int 14
    .long 0                                            // int 15
    .long INT_DMA0_interrupt                           // int 16
    .long INT_DMA1_interrupt                           // int 17
    .long INT_DMA2_interrupt                           // int 18
    .long INT_DMA3_interrupt                           // int 19
    .long INT_DMA4_interrupt                           // int 20
    .long INT_DMA5_interrupt                           // int 21
    .long INT_DMA6_interrupt                           // int 22
    .long INT_DMA7_interrupt                           // int 23
    .long INT_DMA8_interrupt                           // int 24
    .long INT_DMA9_interrupt                           // int 25
    .long INT_DMA10_interrupt                          // int 26
    .long INT_DMA11_interrupt                          // int 27
    .long INT_DMA12_interrupt                          // int 28
    .long INT_DMA13_interrupt                          // int 29
    .long INT_DMA14_interrupt                          // int 30
    .long INT_DMA15_interrupt                          // int 31
    .long INT_DMA_Error_interrupt                      // int 32
    .long 0                                            // int 33
    .long INT_FTFL_interrupt                           // int 34
    .long 0                                            // int 35
    .long INT_LVD_LVW_interrupt                        // int 36
    .long INT_LLW_interrupt                            // int 37
    .long INT_Watchdog_interrupt                       // int 38
    .long 0                                            // int 39
    .long INT_I2C0_interrupt                           // int 40
    .long INT_I2C1_interrupt                           // int 41
    .long INT_SPI0_interrupt                           // int 42
    .long INT_SPI1_interrupt                           // int 43
    .long 0                                            // int 44
    .long INT_CAN0_ORed_Message_buffer_interrupt       // int 45
    .long INT_CAN0_Bus_Off_interrupt                   // int 46
    .long INT_CAN0_Error_interrupt                     // int 47
    .long INT_CAN0_Tx_Warning_interrupt                // int 48
    .long INT_CAN0_Rx_Warning_interrupt                // int 49
    .long INT_CAN0_Wake_Up_interrupt                   // int 50
    .long INT_I2S0_Tx_interrupt                        // int 51
    .long INT_I2S0_Rx_interrupt                        // int 52
    .long 0                                            // int 53
    .long 0                                            // int 54
    .long 0                                            // int 55
    .long 0                                            // int 56
    .long 0                                            // int 57
    .long 0                                            // int 58
    .long 0                                            // int 59
    .long INT_UART0_LON_interrupt                      // int 60
    .long INT_UART0_RX_TX_interrupt                    // int 61
    .long INT_UART0_ERR_interrupt                      // int 62
    .long INT_UART1_RX_TX_interrupt                    // int 63
    .long INT_UART1_ERR_interrupt                      // int 64
    .long INT_UART2_RX_TX_interrupt                    // int 65
    .long INT_UART2_ERR_interrupt                      // int 66
    .long INT_UART3_RX_TX_interrupt                    // int 67
    .long INT_UART3_ERR_interrupt                      // int 68
    .long INT_UART4_RX_TX_interrupt                    // int 69
    .long INT_UART4_ERR_interrupt                      // int 70
    .long 0                                            // int 71
    .long 0                                            // int 72
    .long INT_ADC0_interrupt                           // int 73
    .long INT_ADC1_interrupt                           // int 74
    .long INT_CMP0_interrupt                           // int 75
    .long INT_CMP1_interrupt                           // int 76
    .long INT_CMP2_interrupt                           // int 77
    .long INT_FTM0_interrupt                           // int 78
    .long INT_FTM1_interrupt                           // int 79
    .long INT_FTM2_interrupt                           // int 80
    .long INT_CMT_interrupt                            // int 81
    .long INT_RTC_interrupt                            // int 82
    .long INT_RTC_Seconds_interrupt                    // int 83
    .long INT_PIT0_interrupt                           // int 84
    .long INT_PIT1_interrupt                           // int 85
    .long INT_PIT2_interrupt                           // int 86
    .long INT_PIT3_interrupt                           // int 87
    .long INT_PDB0_interrupt                           // int 88
    .long INT_USB0_interrupt                           // int 89
    .long INT_USBDCD_interrupt                         // int 90
    .long 0                                            // int 91
    .long 0                                            // int 92
    .long 0                                            // int 93
    .long 0                                            // int 94
    .long INT_Reserved95_interrupt                     // int 95
    .long 0                                            // int 96
    .long INT_DAC0_interrupt                           // int 97
    .long 0                                            // int 98
    .long INT_TSI0_interrupt                           // int 99
    .long 0                                            // int 100
    .long INT_LPTimer_interrupt                        // int 101
    .long 0                                            // int 102
    .long INT_PORTA_interrupt                          // int 103
    .long INT_PORTB_interrupt                          // int 104
    .long INT_PORTC_interrupt                          // int 105
    .long INT_PORTD_interrupt                          // int 106
    .long INT_PORTE_interrupt                          // int 107

    .weak NonMaskableInt_interrupt
    .weak HardFault_interrupt
    .weak MemoryManagement_interrupt
    .weak BusFault_interrupt
    .weak UsageFault_interrupt
    .weak SVC_interrupt
    .weak DebugMonitor_interrupt
    .weak PendSV_interrupt
    .weak SysTick_interrupt
    .weak INT_DMA0_interrupt
    .weak INT_DMA1_interrupt
    .weak INT_DMA2_interrupt
    .weak INT_DMA3_interrupt
    .weak INT_DMA4_interrupt
    .weak INT_DMA5_interrupt
    .weak INT_DMA6_interrupt
    .weak INT_DMA7_interrupt
    .weak INT_DMA8_interrupt
    .weak INT_DMA9_interrupt
    .weak INT_DMA10_interrupt
    .weak INT_DMA11_interrupt
    .weak INT_DMA12_interrupt
    .weak INT_DMA13_interrupt
    .weak INT_DMA14_interrupt
    .weak INT_DMA15_interrupt
    .weak INT_DMA_Error_interrupt
    .weak INT_FTFL_interrupt
    .weak INT_LVD_LVW_interrupt
    .weak INT_LLW_interrupt
    .weak INT_Watchdog_interrupt
    .weak INT_I2C0_interrupt
    .weak INT_I2C1_interrupt
    .weak INT_SPI0_interrupt
    .weak INT_SPI1_interrupt
    .weak INT_CAN0_ORed_Message_buffer_interrupt
    .weak INT_CAN0_Bus_Off_interrupt
    .weak INT_CAN0_Error_interrupt
    .weak INT_CAN0_Tx_Warning_interrupt
    .weak INT_CAN0_Rx_Warning_interrupt
    .weak INT_CAN0_Wake_Up_interrupt
    .weak INT_I2S0_Tx_interrupt
    .weak INT_I2S0_Rx_interrupt
    .weak INT_UART0_LON_interrupt
    .weak INT_UART0_RX_TX_interrupt
    .weak INT_UART0_ERR_interrupt
    .weak INT_UART1_RX_TX_interrupt
    .weak INT_UART1_ERR_interrupt
    .weak INT_UART2_RX_TX_interrupt
    .weak INT_UART2_ERR_interrupt
    .weak INT_UART3_RX_TX_interrupt
    .weak INT_UART3_ERR_interrupt
    .weak INT_UART4_RX_TX_interrupt
    .weak INT_UART4_ERR_interrupt
    .weak INT_ADC0_interrupt
    .weak INT_ADC1_interrupt
    .weak INT_CMP0_interrupt
    .weak INT_CMP1_interrupt
    .weak INT_CMP2_interrupt
    .weak INT_FTM0_interrupt
    .weak INT_FTM1_interrupt
    .weak INT_FTM2_interrupt
    .weak INT_CMT_interrupt
    .weak INT_RTC_interrupt
    .weak INT_RTC_Seconds_interrupt
    .weak INT_PIT0_interrupt
    .weak INT_PIT1_interrupt
    .weak INT_PIT2_interrupt
    .weak INT_PIT3_interrupt
    .weak INT_PDB0_interrupt
    .weak INT_USB0_interrupt
    .weak INT_USBDCD_interrupt
    .weak INT_Reserved95_interrupt
    .weak INT_DAC0_interrupt
    .weak INT_TSI0_interrupt
    .weak INT_LPTimer_interrupt
    .weak INT_PORTA_interrupt
    .weak INT_PORTB_interrupt
    .weak INT_PORTC_interrupt
    .weak INT_PORTD_interrupt
    .weak INT_PORTE_interrupt

    .set NonMaskableInt_interrupt, HaltProc
    .set HardFault_interrupt, HaltProc
    .set MemoryManagement_interrupt, HaltProc
    .set BusFault_interrupt, HaltProc
    .set UsageFault_interrupt, HaltProc
    .set SVC_interrupt, HaltProc
    .set DebugMonitor_interrupt, HaltProc
    .set PendSV_interrupt, HaltProc
    .set SysTick_interrupt, HaltProc
    .set INT_DMA0_interrupt, HaltProc
    .set INT_DMA1_interrupt, HaltProc
    .set INT_DMA2_interrupt, HaltProc
    .set INT_DMA3_interrupt, HaltProc
    .set INT_DMA4_interrupt, HaltProc
    .set INT_DMA5_interrupt, HaltProc
    .set INT_DMA6_interrupt, HaltProc
    .set INT_DMA7_interrupt, HaltProc
    .set INT_DMA8_interrupt, HaltProc
    .set INT_DMA9_interrupt, HaltProc
    .set INT_DMA10_interrupt, HaltProc
    .set INT_DMA11_interrupt, HaltProc
    .set INT_DMA12_interrupt, HaltProc
    .set INT_DMA13_interrupt, HaltProc
    .set INT_DMA14_interrupt, HaltProc
    .set INT_DMA15_interrupt, HaltProc
    .set INT_DMA_Error_interrupt, HaltProc
    .set INT_FTFL_interrupt, HaltProc
    .set INT_LVD_LVW_interrupt, HaltProc
    .set INT_LLW_interrupt, HaltProc
    .set INT_Watchdog_interrupt, HaltProc
    .set INT_I2C0_interrupt, HaltProc
    .set INT_I2C1_interrupt, HaltProc
    .set INT_SPI0_interrupt, HaltProc
    .set INT_SPI1_interrupt, HaltProc
    .set INT_CAN0_ORed_Message_buffer_interrupt, HaltProc
    .set INT_CAN0_Bus_Off_interrupt, HaltProc
    .set INT_CAN0_Error_interrupt, HaltProc
    .set INT_CAN0_Tx_Warning_interrupt, HaltProc
    .set INT_CAN0_Rx_Warning_interrupt, HaltProc
    .set INT_CAN0_Wake_Up_interrupt, HaltProc
    .set INT_I2S0_Tx_interrupt, HaltProc
    .set INT_I2S0_Rx_interrupt, HaltProc
    .set INT_UART0_LON_interrupt, HaltProc
    .set INT_UART0_RX_TX_interrupt, HaltProc
    .set INT_UART0_ERR_interrupt, HaltProc
    .set INT_UART1_RX_TX_interrupt, HaltProc
    .set INT_UART1_ERR_interrupt, HaltProc
    .set INT_UART2_RX_TX_interrupt, HaltProc
    .set INT_UART2_ERR_interrupt, HaltProc
    .set INT_UART3_RX_TX_interrupt, HaltProc
    .set INT_UART3_ERR_interrupt, HaltProc
    .set INT_UART4_RX_TX_interrupt, HaltProc
    .set INT_UART4_ERR_interrupt, HaltProc
    .set INT_ADC0_interrupt, HaltProc
    .set INT_ADC1_interrupt, HaltProc
    .set INT_CMP0_interrupt, HaltProc
    .set INT_CMP1_interrupt, HaltProc
    .set INT_CMP2_interrupt, HaltProc
    .set INT_FTM0_interrupt, HaltProc
    .set INT_FTM1_interrupt, HaltProc
    .set INT_FTM2_interrupt, HaltProc
    .set INT_CMT_interrupt, HaltProc
    .set INT_RTC_interrupt, HaltProc
    .set INT_RTC_Seconds_interrupt, HaltProc
    .set INT_PIT0_interrupt, HaltProc
    .set INT_PIT1_interrupt, HaltProc
    .set INT_PIT2_interrupt, HaltProc
    .set INT_PIT3_interrupt, HaltProc
    .set INT_PDB0_interrupt, HaltProc
    .set INT_USB0_interrupt, HaltProc
    .set INT_USBDCD_interrupt, HaltProc
    .set INT_Reserved95_interrupt, HaltProc
    .set INT_DAC0_interrupt, HaltProc
    .set INT_TSI0_interrupt, HaltProc
    .set INT_LPTimer_interrupt, HaltProc
    .set INT_PORTA_interrupt, HaltProc
    .set INT_PORTB_interrupt, HaltProc
    .set INT_PORTC_interrupt, HaltProc
    .set INT_PORTD_interrupt, HaltProc
    .set INT_PORTE_interrupt, HaltProc

    .text
  end;

end.