cgcpu.pas 218 KB

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  1. {
  2. Copyright (c) 2003 by Florian Klaempfl
  3. Member of the Free Pascal development team
  4. This unit implements the code generator for the ARM
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. unit cgcpu;
  19. {$i fpcdefs.inc}
  20. interface
  21. uses
  22. globtype,symtype,symdef,
  23. cgbase,cgutils,cgobj,
  24. aasmbase,aasmcpu,aasmtai,aasmdata,
  25. parabase,
  26. cpubase,cpuinfo,cg64f32,rgcpu;
  27. type
  28. { tbasecgarm is shared between all arm architectures }
  29. tbasecgarm = class(tcg)
  30. { true, if the next arithmetic operation should modify the flags }
  31. cgsetflags : boolean;
  32. procedure a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);override;
  33. procedure a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);override;
  34. procedure a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);override;
  35. procedure a_call_name(list : TAsmList;const s : string; weak: boolean);override;
  36. procedure a_call_reg(list : TAsmList;reg: tregister);override;
  37. { move instructions }
  38. procedure a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
  39. procedure a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
  40. function a_internal_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference):treference;
  41. function a_internal_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister):treference;
  42. { fpu move instructions }
  43. procedure a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
  44. procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
  45. procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
  46. procedure a_loadfpu_ref_cgpara(list : TAsmList;size : tcgsize;const ref : treference;const paraloc : TCGPara);override;
  47. { comparison operations }
  48. procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
  49. l : tasmlabel);override;
  50. procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
  51. procedure a_jmp_name(list : TAsmList;const s : string); override;
  52. procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
  53. procedure a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel); override;
  54. procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  55. procedure g_profilecode(list : TAsmList); override;
  56. procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
  57. procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
  58. procedure g_maybe_got_init(list : TAsmList); override;
  59. procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
  60. procedure g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);override;
  61. procedure g_concatcopy_unaligned(list : TAsmList;const source,dest : treference;len : tcgint);override;
  62. procedure g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  63. procedure g_concatcopy_internal(list : TAsmList;const source,dest : treference;len : tcgint;aligned : boolean);
  64. procedure g_overflowcheck(list: TAsmList; const l: tlocation; def: tdef); override;
  65. procedure g_overflowCheck_loc(List:TAsmList;const Loc:TLocation;def:TDef;ovloc : tlocation);override;
  66. procedure g_save_registers(list : TAsmList);override;
  67. procedure g_restore_registers(list : TAsmList);override;
  68. procedure a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  69. procedure fixref(list : TAsmList;var ref : treference);
  70. function handle_load_store(list:TAsmList;op: tasmop;oppostfix : toppostfix;reg:tregister;ref: treference):treference; virtual;
  71. procedure g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);override;
  72. procedure a_loadmm_reg_reg(list: TAsmList; fromsize, tosize : tcgsize;reg1, reg2: tregister;shuffle : pmmshuffle); override;
  73. procedure a_loadmm_ref_reg(list: TAsmList; fromsize, tosize : tcgsize;const ref: treference; reg: tregister;shuffle : pmmshuffle); override;
  74. procedure a_loadmm_reg_ref(list: TAsmList; fromsize, tosize : tcgsize;reg: tregister; const ref: treference;shuffle : pmmshuffle); override;
  75. procedure a_loadmm_intreg_reg(list: TAsmList; fromsize, tosize : tcgsize;intreg, mmreg: tregister; shuffle: pmmshuffle); override;
  76. procedure a_loadmm_reg_intreg(list: TAsmList; fromsize, tosize : tcgsize;mmreg, intreg: tregister; shuffle : pmmshuffle); override;
  77. procedure a_opmm_reg_reg(list: TAsmList; Op: TOpCG; size : tcgsize;src,dst: tregister;shuffle : pmmshuffle); override;
  78. { Transform unsupported methods into Internal errors }
  79. procedure a_bit_scan_reg_reg(list: TAsmList; reverse: boolean; size: TCGSize; src, dst: TRegister); override;
  80. { try to generate optimized 32 Bit multiplication, returns true if successful generated }
  81. function try_optimized_mul32_const_reg_reg(list: TAsmList; a: tcgint; src, dst: tregister) : boolean;
  82. { clear out potential overflow bits from 8 or 16 bit operations }
  83. { the upper 24/16 bits of a register after an operation }
  84. procedure maybeadjustresult(list: TAsmList; op: TOpCg; size: tcgsize; dst: tregister);
  85. { mla for thumb requires that none of the registers is equal to r13/r15, this method ensures this }
  86. procedure safe_mla(list: TAsmList;op1,op2,op3,op4 : TRegister);
  87. end;
  88. { tcgarm is shared between normal arm and thumb-2 }
  89. tcgarm = class(tbasecgarm)
  90. procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister); override;
  91. procedure a_op_const_ref(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; const ref: TReference); override;
  92. procedure a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister); override;
  93. procedure a_op_const_reg_reg(list: TAsmList; op: TOpCg;
  94. size: tcgsize; a: tcgint; src, dst: tregister); override;
  95. procedure a_op_reg_reg_reg(list: TAsmList; op: TOpCg;
  96. size: tcgsize; src1, src2, dst: tregister); override;
  97. procedure a_op_const_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister;setflags : boolean;var ovloc : tlocation);override;
  98. procedure a_op_reg_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister;setflags : boolean;var ovloc : tlocation);override;
  99. procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);override;
  100. procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
  101. procedure g_adjust_self_value(list:TAsmList;procdef: tprocdef;ioffset: tcgint); override;
  102. {Multiply two 32-bit registers into lo and hi 32-bit registers}
  103. procedure a_mul_reg_reg_pair(list: tasmlist; size: tcgsize; src1,src2,dstlo,dsthi: tregister); override;
  104. end;
  105. { normal arm cg }
  106. tarmcgarm = class(tcgarm)
  107. procedure init_register_allocators;override;
  108. procedure done_register_allocators;override;
  109. end;
  110. { 64 bit cg for all arm flavours }
  111. tbasecg64farm = class(tcg64f32)
  112. end;
  113. { tcg64farm is shared between normal arm and thumb-2 }
  114. tcg64farm = class(tbasecg64farm)
  115. procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  116. procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
  117. procedure a_op64_const_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64);override;
  118. procedure a_op64_reg_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64);override;
  119. procedure a_op64_const_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64;setflags : boolean;var ovloc : tlocation);override;
  120. procedure a_op64_reg_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64;setflags : boolean;var ovloc : tlocation);override;
  121. procedure a_loadmm_intreg64_reg(list: TAsmList; mmsize: tcgsize; intreg: tregister64; mmreg: tregister);override;
  122. procedure a_loadmm_reg_intreg64(list: TAsmList; mmsize: tcgsize; mmreg: tregister; intreg: tregister64);override;
  123. end;
  124. tarmcg64farm = class(tcg64farm)
  125. end;
  126. tthumbcgarm = class(tbasecgarm)
  127. procedure init_register_allocators;override;
  128. procedure done_register_allocators;override;
  129. procedure g_proc_entry(list: TAsmList; localsize: longint; nostackframe: boolean);override;
  130. procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
  131. procedure a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src,dst: TRegister);override;
  132. procedure a_op_const_reg(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; dst: tregister);override;
  133. procedure a_op_const_reg_reg(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister); override;
  134. procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  135. procedure a_load_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const Ref: treference; reg: tregister);override;
  136. procedure a_load_const_reg(list: TAsmList; size: tcgsize; a: tcgint; reg: tregister);override;
  137. procedure g_adjust_self_value(list:TAsmList;procdef: tprocdef;ioffset: tcgint); override;
  138. function handle_load_store(list: TAsmList; op: tasmop; oppostfix: toppostfix; reg: tregister; ref: treference): treference; override;
  139. procedure g_external_wrapper(list : TAsmList; procdef : tprocdef; const externalname : string); override;
  140. end;
  141. tthumbcg64farm = class(tbasecg64farm)
  142. procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  143. procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
  144. end;
  145. tthumb2cgarm = class(tcgarm)
  146. procedure init_register_allocators;override;
  147. procedure done_register_allocators;override;
  148. procedure a_call_reg(list : TAsmList;reg: tregister);override;
  149. procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);override;
  150. procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
  151. procedure a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister); override;
  152. procedure a_op_const_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister;setflags : boolean;var ovloc : tlocation);override;
  153. procedure a_op_reg_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister;setflags : boolean;var ovloc : tlocation);override;
  154. procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  155. procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
  156. procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
  157. function handle_load_store(list:TAsmList;op: tasmop;oppostfix : toppostfix;reg:tregister;ref: treference):treference; override;
  158. procedure a_loadmm_reg_reg(list: TAsmList; fromsize, tosize : tcgsize;reg1, reg2: tregister;shuffle : pmmshuffle); override;
  159. procedure a_loadmm_ref_reg(list: TAsmList; fromsize, tosize : tcgsize;const ref: treference; reg: tregister;shuffle : pmmshuffle); override;
  160. procedure a_loadmm_reg_ref(list: TAsmList; fromsize, tosize : tcgsize;reg: tregister; const ref: treference;shuffle : pmmshuffle); override;
  161. procedure a_loadmm_intreg_reg(list: TAsmList; fromsize, tosize : tcgsize;intreg, mmreg: tregister; shuffle: pmmshuffle); override;
  162. procedure a_loadmm_reg_intreg(list: TAsmList; fromsize, tosize : tcgsize;mmreg, intreg: tregister; shuffle : pmmshuffle); override;
  163. end;
  164. tthumb2cg64farm = class(tcg64farm)
  165. procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  166. end;
  167. const
  168. OpCmp2AsmCond : Array[topcmp] of TAsmCond = (C_NONE,C_EQ,C_GT,
  169. C_LT,C_GE,C_LE,C_NE,C_LS,C_CC,C_CS,C_HI);
  170. winstackpagesize = 4096;
  171. function get_fpu_postfix(def : tdef) : toppostfix;
  172. procedure create_codegen;
  173. implementation
  174. uses
  175. globals,verbose,systems,cutils,
  176. aopt,aoptcpu,
  177. fmodule,
  178. symconst,symsym,symtable,
  179. tgobj,
  180. procinfo,cpupi,
  181. paramgr;
  182. function get_fpu_postfix(def : tdef) : toppostfix;
  183. begin
  184. if def.typ=floatdef then
  185. begin
  186. case tfloatdef(def).floattype of
  187. s32real:
  188. result:=PF_S;
  189. s64real:
  190. result:=PF_D;
  191. s80real:
  192. result:=PF_E;
  193. else
  194. internalerror(200401272);
  195. end;
  196. end
  197. else
  198. internalerror(200401271);
  199. end;
  200. procedure tarmcgarm.init_register_allocators;
  201. begin
  202. inherited init_register_allocators;
  203. { currently, we always save R14, so we can use it }
  204. if (target_info.system<>system_arm_darwin) then
  205. begin
  206. if assigned(current_procinfo) and (current_procinfo.framepointer<>NR_R11) then
  207. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  208. [RS_R0,RS_R1,RS_R2,RS_R3,RS_R12,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
  209. RS_R9,RS_R10,RS_R11,RS_R14],first_int_imreg,[])
  210. else
  211. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  212. [RS_R0,RS_R1,RS_R2,RS_R3,RS_R12,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
  213. RS_R9,RS_R10,RS_R14],first_int_imreg,[])
  214. end
  215. else
  216. { r7 is not available on Darwin, it's used as frame pointer (always,
  217. for backtrace support -- also in gcc/clang -> R11 can be used).
  218. r9 is volatile }
  219. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  220. [RS_R0,RS_R1,RS_R2,RS_R3,RS_R9,RS_R12,RS_R4,RS_R5,RS_R6,RS_R8,
  221. RS_R10,RS_R11,RS_R14],first_int_imreg,[]);
  222. rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE,
  223. [RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7],first_fpu_imreg,[]);
  224. { The register allocator currently cannot deal with multiple
  225. non-overlapping subregs per register, so we can only use
  226. half the single precision registers for now (as sub registers of the
  227. double precision ones). }
  228. if current_settings.fputype=fpu_vfpv3 then
  229. rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBFD,
  230. [RS_D0,RS_D1,RS_D2,RS_D3,RS_D4,RS_D5,RS_D6,RS_D7,
  231. RS_D16,RS_D17,RS_D18,RS_D19,RS_D20,RS_D21,RS_D22,RS_D23,RS_D24,RS_D25,RS_D26,RS_D27,RS_D28,RS_D29,RS_D30,RS_D31,
  232. RS_D8,RS_D9,RS_D10,RS_D11,RS_D12,RS_D13,RS_D14,RS_D15
  233. ],first_mm_imreg,[])
  234. else
  235. rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBFD,
  236. [RS_D0,RS_D1,RS_D2,RS_D3,RS_D4,RS_D5,RS_D6,RS_D7,RS_D8,RS_D9,RS_D10,RS_D11,RS_D12,RS_D13,RS_D14,RS_D15],first_mm_imreg,[]);
  237. end;
  238. procedure tarmcgarm.done_register_allocators;
  239. begin
  240. rg[R_INTREGISTER].free;
  241. rg[R_FPUREGISTER].free;
  242. rg[R_MMREGISTER].free;
  243. inherited done_register_allocators;
  244. end;
  245. procedure tcgarm.a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);
  246. var
  247. imm_shift : byte;
  248. l : tasmlabel;
  249. hr : treference;
  250. imm1, imm2: DWord;
  251. begin
  252. if not(size in [OS_8,OS_S8,OS_16,OS_S16,OS_32,OS_S32]) then
  253. internalerror(2002090902);
  254. if is_shifter_const(a,imm_shift) then
  255. list.concat(taicpu.op_reg_const(A_MOV,reg,a))
  256. else if is_shifter_const(not(a),imm_shift) then
  257. list.concat(taicpu.op_reg_const(A_MVN,reg,not(a)))
  258. { loading of constants with mov and orr }
  259. else if (split_into_shifter_const(a,imm1, imm2)) then
  260. begin
  261. list.concat(taicpu.op_reg_const(A_MOV,reg, imm1));
  262. list.concat(taicpu.op_reg_reg_const(A_ORR,reg,reg, imm2));
  263. end
  264. { loading of constants with mvn and bic }
  265. else if (split_into_shifter_const(not(a), imm1, imm2)) then
  266. begin
  267. list.concat(taicpu.op_reg_const(A_MVN,reg, imm1));
  268. list.concat(taicpu.op_reg_reg_const(A_BIC,reg,reg, imm2));
  269. end
  270. else
  271. begin
  272. reference_reset(hr,4);
  273. current_asmdata.getjumplabel(l);
  274. cg.a_label(current_procinfo.aktlocaldata,l);
  275. hr.symboldata:=current_procinfo.aktlocaldata.last;
  276. current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(longint(a)));
  277. hr.symbol:=l;
  278. hr.base:=NR_PC;
  279. list.concat(taicpu.op_reg_ref(A_LDR,reg,hr));
  280. end;
  281. end;
  282. procedure tcgarm.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);
  283. var
  284. oppostfix:toppostfix;
  285. usedtmpref: treference;
  286. tmpreg,tmpreg2 : tregister;
  287. so : tshifterop;
  288. dir : integer;
  289. begin
  290. if (TCGSize2Size[FromSize] >= TCGSize2Size[ToSize]) then
  291. FromSize := ToSize;
  292. case FromSize of
  293. { signed integer registers }
  294. OS_8:
  295. oppostfix:=PF_B;
  296. OS_S8:
  297. oppostfix:=PF_SB;
  298. OS_16:
  299. oppostfix:=PF_H;
  300. OS_S16:
  301. oppostfix:=PF_SH;
  302. OS_32,
  303. OS_S32:
  304. oppostfix:=PF_None;
  305. else
  306. InternalError(200308297);
  307. end;
  308. if (ref.alignment in [1,2]) and (ref.alignment<tcgsize2size[fromsize]) then
  309. begin
  310. if target_info.endian=endian_big then
  311. dir:=-1
  312. else
  313. dir:=1;
  314. case FromSize of
  315. OS_16,OS_S16:
  316. begin
  317. { only complicated references need an extra loadaddr }
  318. if assigned(ref.symbol) or
  319. (ref.index<>NR_NO) or
  320. (ref.offset<-4095) or
  321. (ref.offset>4094) or
  322. { sometimes the compiler reused registers }
  323. (reg=ref.index) or
  324. (reg=ref.base) then
  325. begin
  326. tmpreg2:=getintregister(list,OS_INT);
  327. a_loadaddr_ref_reg(list,ref,tmpreg2);
  328. reference_reset_base(usedtmpref,tmpreg2,0,ref.alignment);
  329. end
  330. else
  331. usedtmpref:=ref;
  332. if target_info.endian=endian_big then
  333. inc(usedtmpref.offset,1);
  334. shifterop_reset(so);so.shiftmode:=SM_LSL;so.shiftimm:=8;
  335. tmpreg:=getintregister(list,OS_INT);
  336. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,reg);
  337. inc(usedtmpref.offset,dir);
  338. if FromSize=OS_16 then
  339. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg)
  340. else
  341. a_internal_load_ref_reg(list,OS_S8,OS_S8,usedtmpref,tmpreg);
  342. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,reg,tmpreg,so));
  343. end;
  344. OS_32,OS_S32:
  345. begin
  346. tmpreg:=getintregister(list,OS_INT);
  347. { only complicated references need an extra loadaddr }
  348. if assigned(ref.symbol) or
  349. (ref.index<>NR_NO) or
  350. (ref.offset<-4095) or
  351. (ref.offset>4092) or
  352. { sometimes the compiler reused registers }
  353. (reg=ref.index) or
  354. (reg=ref.base) then
  355. begin
  356. tmpreg2:=getintregister(list,OS_INT);
  357. a_loadaddr_ref_reg(list,ref,tmpreg2);
  358. reference_reset_base(usedtmpref,tmpreg2,0,ref.alignment);
  359. end
  360. else
  361. usedtmpref:=ref;
  362. shifterop_reset(so);so.shiftmode:=SM_LSL;
  363. if ref.alignment=2 then
  364. begin
  365. if target_info.endian=endian_big then
  366. inc(usedtmpref.offset,2);
  367. a_internal_load_ref_reg(list,OS_16,OS_16,usedtmpref,reg);
  368. inc(usedtmpref.offset,dir*2);
  369. a_internal_load_ref_reg(list,OS_16,OS_16,usedtmpref,tmpreg);
  370. so.shiftimm:=16;
  371. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,reg,tmpreg,so));
  372. end
  373. else
  374. begin
  375. tmpreg2:=getintregister(list,OS_INT);
  376. if target_info.endian=endian_big then
  377. inc(usedtmpref.offset,3);
  378. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,reg);
  379. inc(usedtmpref.offset,dir);
  380. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
  381. inc(usedtmpref.offset,dir);
  382. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg2);
  383. so.shiftimm:=8;
  384. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,reg,tmpreg,so));
  385. inc(usedtmpref.offset,dir);
  386. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
  387. so.shiftimm:=16;
  388. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,reg,tmpreg2,so));
  389. so.shiftimm:=24;
  390. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,reg,tmpreg,so));
  391. end;
  392. end
  393. else
  394. handle_load_store(list,A_LDR,oppostfix,reg,ref);
  395. end;
  396. end
  397. else
  398. handle_load_store(list,A_LDR,oppostfix,reg,ref);
  399. if (fromsize=OS_S8) and (tosize = OS_16) then
  400. a_load_reg_reg(list,OS_16,OS_32,reg,reg);
  401. end;
  402. procedure tcgarm.g_adjust_self_value(list:TAsmList;procdef: tprocdef;ioffset: tcgint);
  403. var
  404. hsym : tsym;
  405. href : treference;
  406. paraloc : Pcgparalocation;
  407. shift : byte;
  408. begin
  409. { calculate the parameter info for the procdef }
  410. procdef.init_paraloc_info(callerside);
  411. hsym:=tsym(procdef.parast.Find('self'));
  412. if not(assigned(hsym) and
  413. (hsym.typ=paravarsym)) then
  414. internalerror(200305251);
  415. paraloc:=tparavarsym(hsym).paraloc[callerside].location;
  416. while paraloc<>nil do
  417. with paraloc^ do
  418. begin
  419. case loc of
  420. LOC_REGISTER:
  421. begin
  422. if is_shifter_const(ioffset,shift) then
  423. a_op_const_reg(list,OP_SUB,size,ioffset,register)
  424. else
  425. begin
  426. a_load_const_reg(list,OS_ADDR,ioffset,NR_R12);
  427. a_op_reg_reg(list,OP_SUB,size,NR_R12,register);
  428. end;
  429. end;
  430. LOC_REFERENCE:
  431. begin
  432. { offset in the wrapper needs to be adjusted for the stored
  433. return address }
  434. reference_reset_base(href,reference.index,reference.offset+sizeof(aint),sizeof(pint));
  435. if is_shifter_const(ioffset,shift) then
  436. a_op_const_ref(list,OP_SUB,size,ioffset,href)
  437. else
  438. begin
  439. a_load_const_reg(list,OS_ADDR,ioffset,NR_R12);
  440. a_op_reg_ref(list,OP_SUB,size,NR_R12,href);
  441. end;
  442. end
  443. else
  444. internalerror(200309189);
  445. end;
  446. paraloc:=next;
  447. end;
  448. end;
  449. procedure tbasecgarm.a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);
  450. var
  451. ref: treference;
  452. begin
  453. paraloc.check_simple_location;
  454. paramanager.allocparaloc(list,paraloc.location);
  455. case paraloc.location^.loc of
  456. LOC_REGISTER,LOC_CREGISTER:
  457. a_load_const_reg(list,size,a,paraloc.location^.register);
  458. LOC_REFERENCE:
  459. begin
  460. reference_reset(ref,paraloc.alignment);
  461. ref.base:=paraloc.location^.reference.index;
  462. ref.offset:=paraloc.location^.reference.offset;
  463. a_load_const_ref(list,size,a,ref);
  464. end;
  465. else
  466. internalerror(2002081101);
  467. end;
  468. end;
  469. procedure tbasecgarm.a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);
  470. var
  471. tmpref, ref: treference;
  472. location: pcgparalocation;
  473. sizeleft: aint;
  474. begin
  475. location := paraloc.location;
  476. tmpref := r;
  477. sizeleft := paraloc.intsize;
  478. while assigned(location) do
  479. begin
  480. paramanager.allocparaloc(list,location);
  481. case location^.loc of
  482. LOC_REGISTER,LOC_CREGISTER:
  483. a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
  484. LOC_REFERENCE:
  485. begin
  486. reference_reset_base(ref,location^.reference.index,location^.reference.offset,paraloc.alignment);
  487. { doubles in softemu mode have a strange order of registers and references }
  488. if location^.size=OS_32 then
  489. g_concatcopy(list,tmpref,ref,4)
  490. else
  491. begin
  492. g_concatcopy(list,tmpref,ref,sizeleft);
  493. if assigned(location^.next) then
  494. internalerror(2005010710);
  495. end;
  496. end;
  497. LOC_FPUREGISTER,LOC_CFPUREGISTER:
  498. case location^.size of
  499. OS_F32, OS_F64:
  500. a_loadfpu_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
  501. else
  502. internalerror(2002072801);
  503. end;
  504. LOC_VOID:
  505. begin
  506. // nothing to do
  507. end;
  508. else
  509. internalerror(2002081103);
  510. end;
  511. inc(tmpref.offset,tcgsize2size[location^.size]);
  512. dec(sizeleft,tcgsize2size[location^.size]);
  513. location := location^.next;
  514. end;
  515. end;
  516. procedure tbasecgarm.a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);
  517. var
  518. ref: treference;
  519. tmpreg: tregister;
  520. begin
  521. paraloc.check_simple_location;
  522. paramanager.allocparaloc(list,paraloc.location);
  523. case paraloc.location^.loc of
  524. LOC_REGISTER,LOC_CREGISTER:
  525. a_loadaddr_ref_reg(list,r,paraloc.location^.register);
  526. LOC_REFERENCE:
  527. begin
  528. reference_reset(ref,paraloc.alignment);
  529. ref.base := paraloc.location^.reference.index;
  530. ref.offset := paraloc.location^.reference.offset;
  531. tmpreg := getintregister(list,OS_ADDR);
  532. a_loadaddr_ref_reg(list,r,tmpreg);
  533. a_load_reg_ref(list,OS_ADDR,OS_ADDR,tmpreg,ref);
  534. end;
  535. else
  536. internalerror(2002080701);
  537. end;
  538. end;
  539. procedure tbasecgarm.a_call_name(list : TAsmList;const s : string; weak: boolean);
  540. var
  541. branchopcode: tasmop;
  542. r : treference;
  543. sym : TAsmSymbol;
  544. begin
  545. { check not really correct: should only be used for non-Thumb cpus }
  546. if CPUARM_HAS_BLX_LABEL in cpu_capabilities[current_settings.cputype] then
  547. branchopcode:=A_BLX
  548. else
  549. branchopcode:=A_BL;
  550. if not(weak) then
  551. sym:=current_asmdata.RefAsmSymbol(s)
  552. else
  553. sym:=current_asmdata.WeakRefAsmSymbol(s);
  554. reference_reset_symbol(r,sym,0,sizeof(pint));
  555. if (tf_pic_uses_got in target_info.flags) and
  556. (cs_create_pic in current_settings.moduleswitches) then
  557. begin
  558. include(current_procinfo.flags,pi_needs_got);
  559. r.refaddr:=addr_pic
  560. end
  561. else
  562. r.refaddr:=addr_full;
  563. list.concat(taicpu.op_ref(branchopcode,r));
  564. {
  565. the compiler does not properly set this flag anymore in pass 1, and
  566. for now we only need it after pass 2 (I hope) (JM)
  567. if not(pi_do_call in current_procinfo.flags) then
  568. internalerror(2003060703);
  569. }
  570. include(current_procinfo.flags,pi_do_call);
  571. end;
  572. procedure tbasecgarm.a_call_reg(list : TAsmList;reg: tregister);
  573. begin
  574. { check not really correct: should only be used for non-Thumb cpus }
  575. if not(CPUARM_HAS_BLX in cpu_capabilities[current_settings.cputype]) then
  576. begin
  577. list.concat(taicpu.op_reg_reg(A_MOV,NR_R14,NR_PC));
  578. list.concat(taicpu.op_reg_reg(A_MOV,NR_PC,reg));
  579. end
  580. else
  581. list.concat(taicpu.op_reg(A_BLX, reg));
  582. {
  583. the compiler does not properly set this flag anymore in pass 1, and
  584. for now we only need it after pass 2 (I hope) (JM)
  585. if not(pi_do_call in current_procinfo.flags) then
  586. internalerror(2003060703);
  587. }
  588. include(current_procinfo.flags,pi_do_call);
  589. end;
  590. procedure tcgarm.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister);
  591. begin
  592. a_op_const_reg_reg(list,op,size,a,reg,reg);
  593. end;
  594. procedure tcgarm.a_op_const_ref(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; const ref: TReference);
  595. var
  596. tmpreg,tmpresreg : tregister;
  597. tmpref : treference;
  598. begin
  599. tmpreg:=getintregister(list,size);
  600. tmpresreg:=getintregister(list,size);
  601. tmpref:=a_internal_load_ref_reg(list,size,size,ref,tmpreg);
  602. a_op_const_reg_reg(list,op,size,a,tmpreg,tmpresreg);
  603. a_load_reg_ref(list,size,size,tmpresreg,tmpref);
  604. end;
  605. procedure tcgarm.a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister);
  606. var
  607. so : tshifterop;
  608. begin
  609. if op = OP_NEG then
  610. begin
  611. list.concat(taicpu.op_reg_reg_const(A_RSB,dst,src,0));
  612. maybeadjustresult(list,OP_NEG,size,dst);
  613. end
  614. else if op = OP_NOT then
  615. begin
  616. if size in [OS_8, OS_16, OS_S8, OS_S16] then
  617. begin
  618. shifterop_reset(so);
  619. so.shiftmode:=SM_LSL;
  620. if size in [OS_8, OS_S8] then
  621. so.shiftimm:=24
  622. else
  623. so.shiftimm:=16;
  624. list.concat(taicpu.op_reg_reg_shifterop(A_MVN,dst,src,so));
  625. {Using a shift here allows this to be folded into another instruction}
  626. if size in [OS_S8, OS_S16] then
  627. so.shiftmode:=SM_ASR
  628. else
  629. so.shiftmode:=SM_LSR;
  630. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,dst,so));
  631. end
  632. else
  633. list.concat(taicpu.op_reg_reg(A_MVN,dst,src));
  634. end
  635. else
  636. a_op_reg_reg_reg(list,op,size,src,dst,dst);
  637. end;
  638. const
  639. op_reg_reg_opcg2asmop: array[TOpCG] of tasmop =
  640. (A_NONE,A_MOV,A_ADD,A_AND,A_NONE,A_NONE,A_MUL,A_MUL,A_NONE,A_NONE,A_ORR,
  641. A_NONE,A_NONE,A_NONE,A_SUB,A_EOR,A_NONE,A_NONE);
  642. op_reg_opcg2asmop: array[TOpCG] of tasmop =
  643. (A_NONE,A_MOV,A_ADD,A_AND,A_NONE,A_NONE,A_MUL,A_MUL,A_NONE,A_NONE,A_ORR,
  644. A_ASR,A_LSL,A_LSR,A_SUB,A_EOR,A_NONE,A_ROR);
  645. op_reg_postfix: array[TOpCG] of TOpPostfix =
  646. (PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,
  647. PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None);
  648. procedure tcgarm.a_op_const_reg_reg(list: TAsmList; op: TOpCg;
  649. size: tcgsize; a: tcgint; src, dst: tregister);
  650. var
  651. ovloc : tlocation;
  652. begin
  653. a_op_const_reg_reg_checkoverflow(list,op,size,a,src,dst,false,ovloc);
  654. end;
  655. procedure tcgarm.a_op_reg_reg_reg(list: TAsmList; op: TOpCg;
  656. size: tcgsize; src1, src2, dst: tregister);
  657. var
  658. ovloc : tlocation;
  659. begin
  660. a_op_reg_reg_reg_checkoverflow(list,op,size,src1,src2,dst,false,ovloc);
  661. end;
  662. function opshift2shiftmode(op: TOpCg): tshiftmode;
  663. begin
  664. case op of
  665. OP_SHL: Result:=SM_LSL;
  666. OP_SHR: Result:=SM_LSR;
  667. OP_ROR: Result:=SM_ROR;
  668. OP_ROL: Result:=SM_ROR;
  669. OP_SAR: Result:=SM_ASR;
  670. else internalerror(2012070501);
  671. end
  672. end;
  673. function tbasecgarm.try_optimized_mul32_const_reg_reg(list: TAsmList; a: tcgint; src, dst: tregister) : boolean;
  674. var
  675. multiplier : dword;
  676. power : longint;
  677. shifterop : tshifterop;
  678. bitsset : byte;
  679. negative : boolean;
  680. first : boolean;
  681. b,
  682. cycles : byte;
  683. maxeffort : byte;
  684. begin
  685. result:=true;
  686. cycles:=0;
  687. negative:=a<0;
  688. shifterop.rs:=NR_NO;
  689. shifterop.shiftmode:=SM_LSL;
  690. if negative then
  691. inc(cycles);
  692. multiplier:=dword(abs(a));
  693. bitsset:=popcnt(multiplier and $fffffffe);
  694. { heuristics to estimate how much instructions are reasonable to replace the mul,
  695. this is currently based on XScale timings }
  696. { in the simplest case, we need a mov to load the constant and a mul to carry out the
  697. actual multiplication, this requires min. 1+4 cycles
  698. because the first shift imm. might cause a stall and because we need more instructions
  699. when replacing the mul we generate max. 3 instructions to replace this mul }
  700. maxeffort:=3;
  701. { if the constant is not a shifter op, we need either some mov/mvn/bic/or sequence or
  702. a ldr, so generating one more operation to replace this is beneficial }
  703. if not(is_shifter_const(dword(a),b)) and not(is_shifter_const(not(dword(a)),b)) then
  704. inc(maxeffort);
  705. { if the upper 5 bits are all set or clear, mul is one cycle faster }
  706. if ((dword(a) and $f8000000)=0) or ((dword(a) and $f8000000)=$f8000000) then
  707. dec(maxeffort);
  708. { if the upper 17 bits are all set or clear, mul is another cycle faster }
  709. if ((dword(a) and $ffff8000)=0) or ((dword(a) and $ffff8000)=$ffff8000) then
  710. dec(maxeffort);
  711. { most simple cases }
  712. if a=1 then
  713. a_load_reg_reg(list,OS_32,OS_32,src,dst)
  714. else if a=0 then
  715. a_load_const_reg(list,OS_32,0,dst)
  716. else if a=-1 then
  717. a_op_reg_reg(list,OP_NEG,OS_32,src,dst)
  718. { add up ?
  719. basically, one add is needed for each bit being set in the constant factor
  720. however, the least significant bit is for free, it can be hidden in the initial
  721. instruction
  722. }
  723. else if (bitsset+cycles<=maxeffort) and
  724. (bitsset<=popcnt(dword(nextpowerof2(multiplier,power)-multiplier) and $fffffffe)) then
  725. begin
  726. first:=true;
  727. while multiplier<>0 do
  728. begin
  729. shifterop.shiftimm:=BsrDWord(multiplier);
  730. if odd(multiplier) then
  731. begin
  732. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,dst,src,src,shifterop));
  733. dec(multiplier);
  734. end
  735. else
  736. if first then
  737. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,shifterop))
  738. else
  739. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,dst,dst,src,shifterop));
  740. first:=false;
  741. dec(multiplier,1 shl shifterop.shiftimm);
  742. end;
  743. if negative then
  744. list.concat(taicpu.op_reg_reg_const(A_RSB,dst,dst,0));
  745. end
  746. { subtract from the next greater power of two? }
  747. else if popcnt(dword(nextpowerof2(multiplier,power)-multiplier) and $fffffffe)+cycles+1<=maxeffort then
  748. begin
  749. first:=true;
  750. while multiplier<>0 do
  751. begin
  752. if first then
  753. begin
  754. multiplier:=(1 shl power)-multiplier;
  755. shifterop.shiftimm:=power;
  756. end
  757. else
  758. shifterop.shiftimm:=BsrDWord(multiplier);
  759. if odd(multiplier) then
  760. begin
  761. list.concat(taicpu.op_reg_reg_reg_shifterop(A_RSB,dst,src,src,shifterop));
  762. dec(multiplier);
  763. end
  764. else
  765. if first then
  766. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,shifterop))
  767. else
  768. begin
  769. list.concat(taicpu.op_reg_reg_reg_shifterop(A_SUB,dst,dst,src,shifterop));
  770. dec(multiplier,1 shl shifterop.shiftimm);
  771. end;
  772. first:=false;
  773. end;
  774. if negative then
  775. list.concat(taicpu.op_reg_reg_const(A_RSB,dst,dst,0));
  776. end
  777. else
  778. result:=false;
  779. end;
  780. procedure tcgarm.a_op_const_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister;setflags : boolean;var ovloc : tlocation);
  781. var
  782. shift, lsb, width : byte;
  783. tmpreg : tregister;
  784. so : tshifterop;
  785. l1 : longint;
  786. imm1, imm2: DWord;
  787. begin
  788. optimize_op_const(size, op, a);
  789. case op of
  790. OP_NONE:
  791. begin
  792. if src <> dst then
  793. a_load_reg_reg(list, size, size, src, dst);
  794. exit;
  795. end;
  796. OP_MOVE:
  797. begin
  798. a_load_const_reg(list, size, a, dst);
  799. exit;
  800. end;
  801. end;
  802. ovloc.loc:=LOC_VOID;
  803. if {$ifopt R+}(a<>-2147483648) and{$endif} not setflags and is_shifter_const(-a,shift) then
  804. case op of
  805. OP_ADD:
  806. begin
  807. op:=OP_SUB;
  808. a:=aint(dword(-a));
  809. end;
  810. OP_SUB:
  811. begin
  812. op:=OP_ADD;
  813. a:=aint(dword(-a));
  814. end
  815. end;
  816. if is_shifter_const(a,shift) and not(op in [OP_IMUL,OP_MUL]) then
  817. case op of
  818. OP_NEG,OP_NOT:
  819. internalerror(200308281);
  820. OP_SHL,
  821. OP_SHR,
  822. OP_ROL,
  823. OP_ROR,
  824. OP_SAR:
  825. begin
  826. if a>32 then
  827. internalerror(200308294);
  828. shifterop_reset(so);
  829. so.shiftmode:=opshift2shiftmode(op);
  830. if op = OP_ROL then
  831. so.shiftimm:=32-a
  832. else
  833. so.shiftimm:=a;
  834. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,so));
  835. end;
  836. else
  837. {if (op in [OP_SUB, OP_ADD]) and
  838. ((a < 0) or
  839. (a > 4095)) then
  840. begin
  841. tmpreg:=getintregister(list,size);
  842. list.concat(taicpu.op_reg_const(A_MOVT, tmpreg, (a shr 16) and $FFFF));
  843. list.concat(taicpu.op_reg_const(A_MOV, tmpreg, a and $FFFF));
  844. list.concat(setoppostfix(taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmop[op],dst,src,tmpreg),toppostfix(ord(cgsetflags or setflags)*ord(PF_S))
  845. ));
  846. end
  847. else}
  848. begin
  849. if cgsetflags or setflags then
  850. a_reg_alloc(list,NR_DEFAULTFLAGS);
  851. list.concat(setoppostfix(
  852. taicpu.op_reg_reg_const(op_reg_reg_opcg2asmop[op],dst,src,a),toppostfix(ord(cgsetflags or setflags)*ord(PF_S))));
  853. end;
  854. if (cgsetflags or setflags) and (size in [OS_8,OS_16,OS_32]) then
  855. begin
  856. ovloc.loc:=LOC_FLAGS;
  857. case op of
  858. OP_ADD:
  859. ovloc.resflags:=F_CS;
  860. OP_SUB:
  861. ovloc.resflags:=F_CC;
  862. end;
  863. end;
  864. end
  865. else
  866. begin
  867. { there could be added some more sophisticated optimizations }
  868. if (op in [OP_IMUL,OP_IDIV]) and (a=-1) then
  869. a_op_reg_reg(list,OP_NEG,size,src,dst)
  870. { we do this here instead in the peephole optimizer because
  871. it saves us a register }
  872. else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a,l1) and not(cgsetflags or setflags) then
  873. a_op_const_reg_reg(list,OP_SHL,size,l1,src,dst)
  874. { for example : b=a*5 -> b=a*4+a with add instruction and shl }
  875. else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a-1,l1) and not(cgsetflags or setflags) then
  876. begin
  877. if l1>32 then{roozbeh does this ever happen?}
  878. internalerror(200308296);
  879. shifterop_reset(so);
  880. so.shiftmode:=SM_LSL;
  881. so.shiftimm:=l1;
  882. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,dst,src,src,so));
  883. end
  884. { for example : b=a*7 -> b=a*8-a with rsb instruction and shl }
  885. else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a+1,l1) and not(cgsetflags or setflags) then
  886. begin
  887. if l1>32 then{does this ever happen?}
  888. internalerror(201205181);
  889. shifterop_reset(so);
  890. so.shiftmode:=SM_LSL;
  891. so.shiftimm:=l1;
  892. list.concat(taicpu.op_reg_reg_reg_shifterop(A_RSB,dst,src,src,so));
  893. end
  894. else if (op in [OP_MUL,OP_IMUL]) and not(cgsetflags or setflags) and try_optimized_mul32_const_reg_reg(list,a,src,dst) then
  895. begin
  896. { nothing to do on success }
  897. end
  898. { BIC clears the specified bits, while AND keeps them, using BIC allows to use a
  899. broader range of shifterconstants.}
  900. else if (op = OP_AND) and is_shifter_const(not(dword(a)),shift) then
  901. list.concat(taicpu.op_reg_reg_const(A_BIC,dst,src,not(dword(a))))
  902. { Doing two shifts instead of two bics might allow the peephole optimizer to fold the second shift
  903. into the following instruction}
  904. else if (op = OP_AND) and
  905. is_continuous_mask(a, lsb, width) and
  906. ((lsb = 0) or ((lsb + width) = 32)) then
  907. begin
  908. shifterop_reset(so);
  909. if (width = 16) and
  910. (lsb = 0) and
  911. (current_settings.cputype >= cpu_armv6) then
  912. list.concat(taicpu.op_reg_reg(A_UXTH,dst,src))
  913. else if (width = 8) and
  914. (lsb = 0) and
  915. (current_settings.cputype >= cpu_armv6) then
  916. list.concat(taicpu.op_reg_reg(A_UXTB,dst,src))
  917. else if lsb = 0 then
  918. begin
  919. so.shiftmode:=SM_LSL;
  920. so.shiftimm:=32-width;
  921. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,so));
  922. so.shiftmode:=SM_LSR;
  923. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,dst,so));
  924. end
  925. else
  926. begin
  927. so.shiftmode:=SM_LSR;
  928. so.shiftimm:=lsb;
  929. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,so));
  930. so.shiftmode:=SM_LSL;
  931. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,dst,so));
  932. end;
  933. end
  934. else if (op = OP_AND) and split_into_shifter_const(not(dword(a)), imm1, imm2) then
  935. begin
  936. list.concat(taicpu.op_reg_reg_const(A_BIC,dst,src,imm1));
  937. list.concat(taicpu.op_reg_reg_const(A_BIC,dst,dst,imm2));
  938. end
  939. else if (op in [OP_ADD, OP_SUB, OP_OR, OP_XOR]) and
  940. not(cgsetflags or setflags) and
  941. split_into_shifter_const(a, imm1, imm2) then
  942. begin
  943. list.concat(taicpu.op_reg_reg_const(op_reg_reg_opcg2asmop[op],dst,src,imm1));
  944. list.concat(taicpu.op_reg_reg_const(op_reg_reg_opcg2asmop[op],dst,dst,imm2));
  945. end
  946. else
  947. begin
  948. tmpreg:=getintregister(list,size);
  949. a_load_const_reg(list,size,a,tmpreg);
  950. a_op_reg_reg_reg_checkoverflow(list,op,size,tmpreg,src,dst,setflags,ovloc);
  951. end;
  952. end;
  953. maybeadjustresult(list,op,size,dst);
  954. end;
  955. procedure tcgarm.a_op_reg_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister;setflags : boolean;var ovloc : tlocation);
  956. var
  957. so : tshifterop;
  958. tmpreg,overflowreg : tregister;
  959. asmop : tasmop;
  960. begin
  961. ovloc.loc:=LOC_VOID;
  962. case op of
  963. OP_NEG,OP_NOT,
  964. OP_DIV,OP_IDIV:
  965. internalerror(200308283);
  966. OP_SHL,
  967. OP_SHR,
  968. OP_SAR,
  969. OP_ROR:
  970. begin
  971. if (op = OP_ROR) and not(size in [OS_32,OS_S32]) then
  972. internalerror(2008072801);
  973. shifterop_reset(so);
  974. so.rs:=src1;
  975. so.shiftmode:=opshift2shiftmode(op);
  976. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src2,so));
  977. end;
  978. OP_ROL:
  979. begin
  980. if not(size in [OS_32,OS_S32]) then
  981. internalerror(2008072801);
  982. { simulate ROL by ror'ing 32-value }
  983. tmpreg:=getintregister(list,OS_32);
  984. list.concat(taicpu.op_reg_reg_const(A_RSB,tmpreg,src1, 32));
  985. shifterop_reset(so);
  986. so.rs:=tmpreg;
  987. so.shiftmode:=SM_ROR;
  988. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src2,so));
  989. end;
  990. OP_IMUL,
  991. OP_MUL:
  992. begin
  993. if cgsetflags or setflags then
  994. begin
  995. overflowreg:=getintregister(list,size);
  996. if op=OP_IMUL then
  997. asmop:=A_SMULL
  998. else
  999. asmop:=A_UMULL;
  1000. { the arm doesn't allow that rd and rm are the same }
  1001. if dst=src2 then
  1002. begin
  1003. if dst<>src1 then
  1004. list.concat(taicpu.op_reg_reg_reg_reg(asmop,dst,overflowreg,src1,src2))
  1005. else
  1006. begin
  1007. tmpreg:=getintregister(list,size);
  1008. a_load_reg_reg(list,size,size,src2,dst);
  1009. list.concat(taicpu.op_reg_reg_reg_reg(asmop,dst,overflowreg,tmpreg,src1));
  1010. end;
  1011. end
  1012. else
  1013. list.concat(taicpu.op_reg_reg_reg_reg(asmop,dst,overflowreg,src2,src1));
  1014. a_reg_alloc(list,NR_DEFAULTFLAGS);
  1015. if op=OP_IMUL then
  1016. begin
  1017. shifterop_reset(so);
  1018. so.shiftmode:=SM_ASR;
  1019. so.shiftimm:=31;
  1020. list.concat(taicpu.op_reg_reg_shifterop(A_CMP,overflowreg,dst,so));
  1021. end
  1022. else
  1023. list.concat(taicpu.op_reg_const(A_CMP,overflowreg,0));
  1024. ovloc.loc:=LOC_FLAGS;
  1025. ovloc.resflags:=F_NE;
  1026. end
  1027. else
  1028. begin
  1029. { the arm doesn't allow that rd and rm are the same }
  1030. if dst=src2 then
  1031. begin
  1032. if dst<>src1 then
  1033. list.concat(taicpu.op_reg_reg_reg(A_MUL,dst,src1,src2))
  1034. else
  1035. begin
  1036. tmpreg:=getintregister(list,size);
  1037. a_load_reg_reg(list,size,size,src2,dst);
  1038. list.concat(taicpu.op_reg_reg_reg(A_MUL,dst,tmpreg,src1));
  1039. end;
  1040. end
  1041. else
  1042. list.concat(taicpu.op_reg_reg_reg(A_MUL,dst,src2,src1));
  1043. end;
  1044. end;
  1045. else
  1046. begin
  1047. if cgsetflags or setflags then
  1048. a_reg_alloc(list,NR_DEFAULTFLAGS);
  1049. list.concat(setoppostfix(
  1050. taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmop[op],dst,src2,src1),toppostfix(ord(cgsetflags or setflags)*ord(PF_S))));
  1051. end;
  1052. end;
  1053. maybeadjustresult(list,op,size,dst);
  1054. end;
  1055. procedure tcgarm.a_mul_reg_reg_pair(list: tasmlist; size: tcgsize; src1,src2,dstlo,dsthi: tregister);
  1056. var
  1057. asmop: tasmop;
  1058. begin
  1059. list.concat(tai_comment.create(strpnew('tcgarm.a_mul_reg_reg_pair called')));
  1060. case size of
  1061. OS_32: asmop:=A_UMULL;
  1062. OS_S32: asmop:=A_SMULL;
  1063. else
  1064. InternalError(2014060802);
  1065. end;
  1066. { The caller might omit dstlo or dsthi, when he is not interested in it, we still
  1067. need valid registers everywhere. In case of dsthi = NR_NO we could fall back to
  1068. 32x32=32 bit multiplication}
  1069. if (dstlo = NR_NO) then
  1070. dstlo:=getintregister(list,size);
  1071. if (dsthi = NR_NO) then
  1072. dsthi:=getintregister(list,size);
  1073. list.concat(taicpu.op_reg_reg_reg_reg(asmop, dstlo, dsthi, src1,src2));
  1074. end;
  1075. function tbasecgarm.handle_load_store(list:TAsmList;op: tasmop;oppostfix : toppostfix;reg:tregister;ref: treference):treference;
  1076. var
  1077. tmpreg1,tmpreg2 : tregister;
  1078. tmpref : treference;
  1079. l : tasmlabel;
  1080. begin
  1081. tmpreg1:=NR_NO;
  1082. { Be sure to have a base register }
  1083. if (ref.base=NR_NO) then
  1084. begin
  1085. if ref.shiftmode<>SM_None then
  1086. internalerror(2014020701);
  1087. ref.base:=ref.index;
  1088. ref.index:=NR_NO;
  1089. end;
  1090. { absolute symbols can't be handled directly, we've to store the symbol reference
  1091. in the text segment and access it pc relative
  1092. For now, we assume that references where base or index equals to PC are already
  1093. relative, all other references are assumed to be absolute and thus they need
  1094. to be handled extra.
  1095. A proper solution would be to change refoptions to a set and store the information
  1096. if the symbol is absolute or relative there.
  1097. }
  1098. if (assigned(ref.symbol) and
  1099. not(is_pc(ref.base)) and
  1100. not(is_pc(ref.index))
  1101. ) or
  1102. { [#xxx] isn't a valid address operand }
  1103. ((ref.base=NR_NO) and (ref.index=NR_NO)) or
  1104. (ref.offset<-4095) or
  1105. (ref.offset>4095) or
  1106. ((oppostfix in [PF_SB,PF_H,PF_SH]) and
  1107. ((ref.offset<-255) or
  1108. (ref.offset>255)
  1109. )
  1110. ) or
  1111. (((op in [A_LDF,A_STF,A_FLDS,A_FLDD,A_FSTS,A_FSTD]) or (op=A_VSTR) or (op=A_VLDR)) and
  1112. ((ref.offset<-1020) or
  1113. (ref.offset>1020) or
  1114. ((abs(ref.offset) mod 4)<>0)
  1115. )
  1116. ) or
  1117. ((GenerateThumbCode) and
  1118. (((oppostfix in [PF_SB,PF_SH]) and (ref.offset<>0)) or
  1119. ((oppostfix=PF_None) and ((ref.offset<0) or ((ref.base<>NR_STACK_POINTER_REG) and (ref.offset>124)) or
  1120. ((ref.base=NR_STACK_POINTER_REG) and (ref.offset>1020)) or ((ref.offset mod 4)<>0))) or
  1121. ((oppostfix=PF_H) and ((ref.offset<0) or (ref.offset>62) or ((ref.offset mod 2)<>0) or ((getsupreg(ref.base) in [RS_R8..RS_R15]) and (ref.offset<>0)))) or
  1122. ((oppostfix=PF_B) and ((ref.offset<0) or (ref.offset>31) or ((getsupreg(ref.base) in [RS_R8..RS_R15]) and (ref.offset<>0))))
  1123. )
  1124. ) then
  1125. begin
  1126. fixref(list,ref);
  1127. end;
  1128. if GenerateThumbCode then
  1129. begin
  1130. { certain thumb load require base and index }
  1131. if (oppostfix in [PF_SB,PF_SH]) and
  1132. (ref.base<>NR_NO) and (ref.index=NR_NO) then
  1133. begin
  1134. tmpreg1:=getintregister(list,OS_ADDR);
  1135. a_load_const_reg(list,OS_ADDR,0,tmpreg1);
  1136. ref.index:=tmpreg1;
  1137. end;
  1138. { "hi" registers cannot be used as base or index }
  1139. if (getsupreg(ref.base) in [RS_R8..RS_R12,RS_R14]) or
  1140. ((ref.base=NR_R13) and (ref.index<>NR_NO)) then
  1141. begin
  1142. tmpreg1:=getintregister(list,OS_ADDR);
  1143. a_load_reg_reg(list,OS_ADDR,OS_ADDR,ref.base,tmpreg1);
  1144. ref.base:=tmpreg1;
  1145. end;
  1146. if getsupreg(ref.index) in [RS_R8..RS_R14] then
  1147. begin
  1148. tmpreg1:=getintregister(list,OS_ADDR);
  1149. a_load_reg_reg(list,OS_ADDR,OS_ADDR,ref.index,tmpreg1);
  1150. ref.index:=tmpreg1;
  1151. end;
  1152. end;
  1153. { fold if there is base, index and offset, however, don't fold
  1154. for vfp memory instructions because we later fold the index }
  1155. if not((op in [A_FLDS,A_FLDD,A_FSTS,A_FSTD]) or (op=A_VSTR) or (op=A_VLDR)) and
  1156. (ref.base<>NR_NO) and (ref.index<>NR_NO) and (ref.offset<>0) then
  1157. begin
  1158. if tmpreg1<>NR_NO then
  1159. begin
  1160. tmpreg2:=getintregister(list,OS_ADDR);
  1161. a_op_const_reg_reg(list,OP_ADD,OS_ADDR,ref.offset,tmpreg1,tmpreg2);
  1162. tmpreg1:=tmpreg2;
  1163. end
  1164. else
  1165. begin
  1166. tmpreg1:=getintregister(list,OS_ADDR);
  1167. a_op_const_reg_reg(list,OP_ADD,OS_ADDR,ref.offset,ref.base,tmpreg1);
  1168. ref.base:=tmpreg1;
  1169. end;
  1170. ref.offset:=0;
  1171. end;
  1172. { floating point operations have only limited references
  1173. we expect here, that a base is already set }
  1174. if ((op in [A_LDF,A_STF,A_FLDS,A_FLDD,A_FSTS,A_FSTD]) or (op=A_VSTR) or (op=A_VLDR)) and (ref.index<>NR_NO) then
  1175. begin
  1176. if ref.shiftmode<>SM_none then
  1177. internalerror(200309121);
  1178. if tmpreg1<>NR_NO then
  1179. begin
  1180. if ref.base=tmpreg1 then
  1181. begin
  1182. if ref.signindex<0 then
  1183. list.concat(taicpu.op_reg_reg_reg(A_SUB,tmpreg1,tmpreg1,ref.index))
  1184. else
  1185. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg1,tmpreg1,ref.index));
  1186. ref.index:=NR_NO;
  1187. end
  1188. else
  1189. begin
  1190. if ref.index<>tmpreg1 then
  1191. internalerror(200403161);
  1192. if ref.signindex<0 then
  1193. list.concat(taicpu.op_reg_reg_reg(A_SUB,tmpreg1,ref.base,tmpreg1))
  1194. else
  1195. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg1,ref.base,tmpreg1));
  1196. ref.base:=tmpreg1;
  1197. ref.index:=NR_NO;
  1198. end;
  1199. end
  1200. else
  1201. begin
  1202. tmpreg1:=getintregister(list,OS_ADDR);
  1203. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg1,ref.base,ref.index));
  1204. ref.base:=tmpreg1;
  1205. ref.index:=NR_NO;
  1206. end;
  1207. end;
  1208. list.concat(setoppostfix(taicpu.op_reg_ref(op,reg,ref),oppostfix));
  1209. Result := ref;
  1210. end;
  1211. procedure tbasecgarm.a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);
  1212. var
  1213. oppostfix:toppostfix;
  1214. usedtmpref: treference;
  1215. tmpreg : tregister;
  1216. dir : integer;
  1217. begin
  1218. if (TCGSize2Size[FromSize] >= TCGSize2Size[ToSize]) then
  1219. FromSize := ToSize;
  1220. case ToSize of
  1221. { signed integer registers }
  1222. OS_8,
  1223. OS_S8:
  1224. oppostfix:=PF_B;
  1225. OS_16,
  1226. OS_S16:
  1227. oppostfix:=PF_H;
  1228. OS_32,
  1229. OS_S32,
  1230. { for vfp value stored in integer register }
  1231. OS_F32:
  1232. oppostfix:=PF_None;
  1233. else
  1234. InternalError(200308299);
  1235. end;
  1236. if (ref.alignment in [1,2]) and (ref.alignment<tcgsize2size[tosize]) then
  1237. begin
  1238. if target_info.endian=endian_big then
  1239. dir:=-1
  1240. else
  1241. dir:=1;
  1242. case FromSize of
  1243. OS_16,OS_S16:
  1244. begin
  1245. tmpreg:=getintregister(list,OS_INT);
  1246. usedtmpref:=ref;
  1247. if target_info.endian=endian_big then
  1248. inc(usedtmpref.offset,1);
  1249. usedtmpref:=a_internal_load_reg_ref(list,OS_8,OS_8,reg,usedtmpref);
  1250. inc(usedtmpref.offset,dir);
  1251. a_op_const_reg_reg(list,OP_SHR,OS_INT,8,reg,tmpreg);
  1252. a_internal_load_reg_ref(list,OS_8,OS_8,tmpreg,usedtmpref);
  1253. end;
  1254. OS_32,OS_S32:
  1255. begin
  1256. tmpreg:=getintregister(list,OS_INT);
  1257. usedtmpref:=ref;
  1258. if ref.alignment=2 then
  1259. begin
  1260. if target_info.endian=endian_big then
  1261. inc(usedtmpref.offset,2);
  1262. usedtmpref:=a_internal_load_reg_ref(list,OS_16,OS_16,reg,usedtmpref);
  1263. a_op_const_reg_reg(list,OP_SHR,OS_INT,16,reg,tmpreg);
  1264. inc(usedtmpref.offset,dir*2);
  1265. a_internal_load_reg_ref(list,OS_16,OS_16,tmpreg,usedtmpref);
  1266. end
  1267. else
  1268. begin
  1269. if target_info.endian=endian_big then
  1270. inc(usedtmpref.offset,3);
  1271. usedtmpref:=a_internal_load_reg_ref(list,OS_8,OS_8,reg,usedtmpref);
  1272. a_op_const_reg_reg(list,OP_SHR,OS_INT,8,reg,tmpreg);
  1273. inc(usedtmpref.offset,dir);
  1274. a_internal_load_reg_ref(list,OS_8,OS_8,tmpreg,usedtmpref);
  1275. a_op_const_reg(list,OP_SHR,OS_INT,8,tmpreg);
  1276. inc(usedtmpref.offset,dir);
  1277. a_internal_load_reg_ref(list,OS_8,OS_8,tmpreg,usedtmpref);
  1278. a_op_const_reg(list,OP_SHR,OS_INT,8,tmpreg);
  1279. inc(usedtmpref.offset,dir);
  1280. a_internal_load_reg_ref(list,OS_8,OS_8,tmpreg,usedtmpref);
  1281. end;
  1282. end
  1283. else
  1284. handle_load_store(list,A_STR,oppostfix,reg,ref);
  1285. end;
  1286. end
  1287. else
  1288. handle_load_store(list,A_STR,oppostfix,reg,ref);
  1289. end;
  1290. function tbasecgarm.a_internal_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference):treference;
  1291. var
  1292. oppostfix:toppostfix;
  1293. begin
  1294. case ToSize of
  1295. { signed integer registers }
  1296. OS_8,
  1297. OS_S8:
  1298. oppostfix:=PF_B;
  1299. OS_16,
  1300. OS_S16:
  1301. oppostfix:=PF_H;
  1302. OS_32,
  1303. OS_S32:
  1304. oppostfix:=PF_None;
  1305. else
  1306. InternalError(2003082910);
  1307. end;
  1308. result:=handle_load_store(list,A_STR,oppostfix,reg,ref);
  1309. end;
  1310. function tbasecgarm.a_internal_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister):treference;
  1311. var
  1312. oppostfix:toppostfix;
  1313. begin
  1314. case FromSize of
  1315. { signed integer registers }
  1316. OS_8:
  1317. oppostfix:=PF_B;
  1318. OS_S8:
  1319. oppostfix:=PF_SB;
  1320. OS_16:
  1321. oppostfix:=PF_H;
  1322. OS_S16:
  1323. oppostfix:=PF_SH;
  1324. OS_32,
  1325. OS_S32:
  1326. oppostfix:=PF_None;
  1327. else
  1328. InternalError(200308291);
  1329. end;
  1330. result:=handle_load_store(list,A_LDR,oppostfix,reg,ref);
  1331. end;
  1332. procedure tbasecgarm.a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);
  1333. var
  1334. so : tshifterop;
  1335. procedure do_shift(shiftmode : tshiftmode; shiftimm : byte; reg : tregister);
  1336. begin
  1337. if GenerateThumbCode then
  1338. begin
  1339. case shiftmode of
  1340. SM_ASR:
  1341. a_op_const_reg_reg(list,OP_SAR,OS_32,shiftimm,reg,reg2);
  1342. SM_LSR:
  1343. a_op_const_reg_reg(list,OP_SHR,OS_32,shiftimm,reg,reg2);
  1344. SM_LSL:
  1345. a_op_const_reg_reg(list,OP_SHL,OS_32,shiftimm,reg,reg2);
  1346. else
  1347. internalerror(2013090301);
  1348. end;
  1349. end
  1350. else
  1351. begin
  1352. so.shiftmode:=shiftmode;
  1353. so.shiftimm:=shiftimm;
  1354. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,reg2,reg,so));
  1355. end;
  1356. end;
  1357. var
  1358. instr: taicpu;
  1359. conv_done: boolean;
  1360. begin
  1361. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  1362. internalerror(2002090901);
  1363. conv_done:=false;
  1364. if tosize<>fromsize then
  1365. begin
  1366. shifterop_reset(so);
  1367. conv_done:=true;
  1368. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  1369. fromsize:=tosize;
  1370. if current_settings.cputype<cpu_armv6 then
  1371. case fromsize of
  1372. OS_8:
  1373. if GenerateThumbCode then
  1374. a_op_const_reg_reg(list,OP_AND,OS_32,$ff,reg1,reg2)
  1375. else
  1376. list.concat(taicpu.op_reg_reg_const(A_AND,reg2,reg1,$ff));
  1377. OS_S8:
  1378. begin
  1379. do_shift(SM_LSL,24,reg1);
  1380. if tosize=OS_16 then
  1381. begin
  1382. do_shift(SM_ASR,8,reg2);
  1383. do_shift(SM_LSR,16,reg2);
  1384. end
  1385. else
  1386. do_shift(SM_ASR,24,reg2);
  1387. end;
  1388. OS_16:
  1389. begin
  1390. do_shift(SM_LSL,16,reg1);
  1391. do_shift(SM_LSR,16,reg2);
  1392. end;
  1393. OS_S16:
  1394. begin
  1395. do_shift(SM_LSL,16,reg1);
  1396. do_shift(SM_ASR,16,reg2)
  1397. end;
  1398. else
  1399. conv_done:=false;
  1400. end
  1401. else
  1402. case fromsize of
  1403. OS_8:
  1404. if GenerateThumbCode then
  1405. list.concat(taicpu.op_reg_reg(A_UXTB,reg2,reg1))
  1406. else
  1407. list.concat(taicpu.op_reg_reg_const(A_AND,reg2,reg1,$ff));
  1408. OS_S8:
  1409. begin
  1410. if tosize=OS_16 then
  1411. begin
  1412. so.shiftmode:=SM_ROR;
  1413. so.shiftimm:=16;
  1414. list.concat(taicpu.op_reg_reg_shifterop(A_SXTB16,reg2,reg1,so));
  1415. do_shift(SM_LSR,16,reg2);
  1416. end
  1417. else
  1418. list.concat(taicpu.op_reg_reg(A_SXTB,reg2,reg1));
  1419. end;
  1420. OS_16:
  1421. list.concat(taicpu.op_reg_reg(A_UXTH,reg2,reg1));
  1422. OS_S16:
  1423. list.concat(taicpu.op_reg_reg(A_SXTH,reg2,reg1));
  1424. else
  1425. conv_done:=false;
  1426. end
  1427. end;
  1428. if not conv_done and (reg1<>reg2) then
  1429. begin
  1430. { same size, only a register mov required }
  1431. instr:=taicpu.op_reg_reg(A_MOV,reg2,reg1);
  1432. list.Concat(instr);
  1433. { Notify the register allocator that we have written a move instruction so
  1434. it can try to eliminate it. }
  1435. add_move_instruction(instr);
  1436. end;
  1437. end;
  1438. procedure tbasecgarm.a_loadfpu_ref_cgpara(list : TAsmList;size : tcgsize;const ref : treference;const paraloc : TCGPara);
  1439. var
  1440. href,href2 : treference;
  1441. hloc : pcgparalocation;
  1442. begin
  1443. href:=ref;
  1444. hloc:=paraloc.location;
  1445. while assigned(hloc) do
  1446. begin
  1447. case hloc^.loc of
  1448. LOC_FPUREGISTER,LOC_CFPUREGISTER:
  1449. begin
  1450. paramanager.allocparaloc(list,paraloc.location);
  1451. a_loadfpu_ref_reg(list,size,size,ref,hloc^.register);
  1452. end;
  1453. LOC_REGISTER :
  1454. case hloc^.size of
  1455. OS_32,
  1456. OS_F32:
  1457. begin
  1458. paramanager.allocparaloc(list,paraloc.location);
  1459. a_load_ref_reg(list,OS_32,OS_32,href,hloc^.register);
  1460. end;
  1461. OS_64,
  1462. OS_F64:
  1463. cg64.a_load64_ref_cgpara(list,href,paraloc);
  1464. else
  1465. a_load_ref_reg(list,hloc^.size,hloc^.size,href,hloc^.register);
  1466. end;
  1467. LOC_REFERENCE :
  1468. begin
  1469. reference_reset_base(href2,hloc^.reference.index,hloc^.reference.offset,paraloc.alignment);
  1470. { concatcopy should choose the best way to copy the data }
  1471. g_concatcopy(list,href,href2,tcgsize2size[hloc^.size]);
  1472. end;
  1473. else
  1474. internalerror(200408241);
  1475. end;
  1476. inc(href.offset,tcgsize2size[hloc^.size]);
  1477. hloc:=hloc^.next;
  1478. end;
  1479. end;
  1480. procedure tbasecgarm.a_loadfpu_reg_reg(list: TAsmList; fromsize,tosize: tcgsize; reg1, reg2: tregister);
  1481. begin
  1482. list.concat(setoppostfix(taicpu.op_reg_reg(A_MVF,reg2,reg1),cgsize2fpuoppostfix[tosize]));
  1483. end;
  1484. procedure tbasecgarm.a_loadfpu_ref_reg(list: TAsmList; fromsize,tosize: tcgsize; const ref: treference; reg: tregister);
  1485. var
  1486. oppostfix:toppostfix;
  1487. begin
  1488. case fromsize of
  1489. OS_32,
  1490. OS_F32:
  1491. oppostfix:=PF_S;
  1492. OS_64,
  1493. OS_F64:
  1494. oppostfix:=PF_D;
  1495. OS_F80:
  1496. oppostfix:=PF_E;
  1497. else
  1498. InternalError(200309021);
  1499. end;
  1500. handle_load_store(list,A_LDF,oppostfix,reg,ref);
  1501. if fromsize<>tosize then
  1502. a_loadfpu_reg_reg(list,fromsize,tosize,reg,reg);
  1503. end;
  1504. procedure tbasecgarm.a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference);
  1505. var
  1506. oppostfix:toppostfix;
  1507. begin
  1508. case tosize of
  1509. OS_F32:
  1510. oppostfix:=PF_S;
  1511. OS_F64:
  1512. oppostfix:=PF_D;
  1513. OS_F80:
  1514. oppostfix:=PF_E;
  1515. else
  1516. InternalError(200309022);
  1517. end;
  1518. handle_load_store(list,A_STF,oppostfix,reg,ref);
  1519. end;
  1520. { comparison operations }
  1521. procedure tbasecgarm.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
  1522. l : tasmlabel);
  1523. var
  1524. tmpreg : tregister;
  1525. b : byte;
  1526. begin
  1527. a_reg_alloc(list,NR_DEFAULTFLAGS);
  1528. if (not(GenerateThumbCode) and is_shifter_const(a,b)) or
  1529. ((GenerateThumbCode) and is_thumb_imm(a)) then
  1530. list.concat(taicpu.op_reg_const(A_CMP,reg,a))
  1531. { CMN reg,0 and CMN reg,$80000000 are different from CMP reg,$ffffffff
  1532. and CMP reg,$7fffffff regarding the flags according to the ARM manual }
  1533. else if (a<>$7fffffff) and (a<>-1) and not(GenerateThumbCode) and is_shifter_const(-a,b) then
  1534. list.concat(taicpu.op_reg_const(A_CMN,reg,-a))
  1535. else
  1536. begin
  1537. tmpreg:=getintregister(list,size);
  1538. a_load_const_reg(list,size,a,tmpreg);
  1539. list.concat(taicpu.op_reg_reg(A_CMP,reg,tmpreg));
  1540. end;
  1541. a_jmp_cond(list,cmp_op,l);
  1542. a_reg_dealloc(list,NR_DEFAULTFLAGS);
  1543. end;
  1544. procedure tbasecgarm.a_bit_scan_reg_reg(list: TAsmList; reverse: boolean; size: TCGSize; src, dst: TRegister);
  1545. begin
  1546. if reverse then
  1547. begin
  1548. list.Concat(taicpu.op_reg_reg(A_CLZ,dst,src));
  1549. list.Concat(taicpu.op_reg_reg_const(A_RSB,dst,dst,31));
  1550. list.Concat(taicpu.op_reg_reg_const(A_AND,dst,dst,255));
  1551. end
  1552. { it is decided during the compilation of the system unit if this code is used or not
  1553. so no additional check for rbit is needed }
  1554. else
  1555. begin
  1556. list.Concat(taicpu.op_reg_reg(A_RBIT,dst,src));
  1557. list.Concat(taicpu.op_reg_reg(A_CLZ,dst,dst));
  1558. a_reg_alloc(list,NR_DEFAULTFLAGS);
  1559. list.Concat(taicpu.op_reg_const(A_CMP,dst,32));
  1560. if GenerateThumb2Code then
  1561. list.Concat(taicpu.op_cond(A_IT, C_EQ));
  1562. list.Concat(setcondition(taicpu.op_reg_const(A_MOV,dst,$ff),C_EQ));
  1563. a_reg_dealloc(list,NR_DEFAULTFLAGS);
  1564. end;
  1565. end;
  1566. procedure tbasecgarm.a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
  1567. begin
  1568. a_reg_alloc(list,NR_DEFAULTFLAGS);
  1569. list.concat(taicpu.op_reg_reg(A_CMP,reg2,reg1));
  1570. a_jmp_cond(list,cmp_op,l);
  1571. a_reg_dealloc(list,NR_DEFAULTFLAGS);
  1572. end;
  1573. procedure tbasecgarm.a_jmp_name(list : TAsmList;const s : string);
  1574. var
  1575. ai : taicpu;
  1576. begin
  1577. { generate far jump, leave it to the optimizer to get rid of it }
  1578. if GenerateThumbCode then
  1579. ai:=taicpu.op_sym(A_BL,current_asmdata.RefAsmSymbol(s))
  1580. else
  1581. ai:=taicpu.op_sym(A_B,current_asmdata.RefAsmSymbol(s));
  1582. ai.is_jmp:=true;
  1583. list.concat(ai);
  1584. end;
  1585. procedure tbasecgarm.a_jmp_always(list : TAsmList;l: tasmlabel);
  1586. var
  1587. ai : taicpu;
  1588. begin
  1589. { generate far jump, leave it to the optimizer to get rid of it }
  1590. if GenerateThumbCode then
  1591. ai:=taicpu.op_sym(A_BL,l)
  1592. else
  1593. ai:=taicpu.op_sym(A_B,l);
  1594. ai.is_jmp:=true;
  1595. list.concat(ai);
  1596. end;
  1597. procedure tbasecgarm.a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel);
  1598. var
  1599. ai : taicpu;
  1600. inv_flags : TResFlags;
  1601. hlabel : TAsmLabel;
  1602. begin
  1603. if GenerateThumbCode then
  1604. begin
  1605. inv_flags:=f;
  1606. inverse_flags(inv_flags);
  1607. { the optimizer has to fix this if jump range is sufficient short }
  1608. current_asmdata.getjumplabel(hlabel);
  1609. ai:=setcondition(taicpu.op_sym(A_B,hlabel),flags_to_cond(inv_flags));
  1610. ai.is_jmp:=true;
  1611. list.concat(ai);
  1612. a_jmp_always(list,l);
  1613. a_label(list,hlabel);
  1614. end
  1615. else
  1616. begin
  1617. ai:=setcondition(taicpu.op_sym(A_B,l),flags_to_cond(f));
  1618. ai.is_jmp:=true;
  1619. list.concat(ai);
  1620. end;
  1621. end;
  1622. procedure tbasecgarm.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
  1623. begin
  1624. list.concat(setcondition(taicpu.op_reg_const(A_MOV,reg,1),flags_to_cond(f)));
  1625. list.concat(setcondition(taicpu.op_reg_const(A_MOV,reg,0),inverse_cond(flags_to_cond(f))));
  1626. end;
  1627. procedure tbasecgarm.g_profilecode(list : TAsmList);
  1628. begin
  1629. if target_info.system = system_arm_linux then
  1630. begin
  1631. list.concat(taicpu.op_regset(A_PUSH,R_INTREGISTER,R_SUBWHOLE,[RS_R14]));
  1632. a_call_name(list,'__gnu_mcount_nc',false);
  1633. end
  1634. else
  1635. internalerror(2014091201);
  1636. end;
  1637. procedure tbasecgarm.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
  1638. var
  1639. ref : treference;
  1640. shift : byte;
  1641. firstfloatreg,lastfloatreg,
  1642. r : byte;
  1643. mmregs,
  1644. regs, saveregs : tcpuregisterset;
  1645. registerarea,
  1646. r7offset,
  1647. stackmisalignment : pint;
  1648. postfix: toppostfix;
  1649. imm1, imm2: DWord;
  1650. stack_parameters : Boolean;
  1651. begin
  1652. LocalSize:=align(LocalSize,4);
  1653. stack_parameters:=current_procinfo.procdef.stack_tainting_parameter(calleeside);
  1654. { call instruction does not put anything on the stack }
  1655. registerarea:=0;
  1656. tarmprocinfo(current_procinfo).stackpaddingreg:=High(TSuperRegister);
  1657. lastfloatreg:=RS_NO;
  1658. if not(nostackframe) then
  1659. begin
  1660. firstfloatreg:=RS_NO;
  1661. mmregs:=[];
  1662. case current_settings.fputype of
  1663. fpu_fpa,
  1664. fpu_fpa10,
  1665. fpu_fpa11:
  1666. begin
  1667. { save floating point registers? }
  1668. regs:=rg[R_FPUREGISTER].used_in_proc-paramanager.get_volatile_registers_fpu(pocall_stdcall);
  1669. for r:=RS_F0 to RS_F7 do
  1670. if r in regs then
  1671. begin
  1672. if firstfloatreg=RS_NO then
  1673. firstfloatreg:=r;
  1674. lastfloatreg:=r;
  1675. inc(registerarea,12);
  1676. end;
  1677. end;
  1678. fpu_vfpv2,
  1679. fpu_vfpv3,
  1680. fpu_vfpv3_d16:
  1681. begin;
  1682. mmregs:=rg[R_MMREGISTER].used_in_proc-paramanager.get_volatile_registers_mm(pocall_stdcall);
  1683. end;
  1684. end;
  1685. a_reg_alloc(list,NR_STACK_POINTER_REG);
  1686. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1687. a_reg_alloc(list,NR_FRAME_POINTER_REG);
  1688. { save int registers }
  1689. reference_reset(ref,4);
  1690. ref.index:=NR_STACK_POINTER_REG;
  1691. ref.addressmode:=AM_PREINDEXED;
  1692. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1693. if not(target_info.system in systems_darwin) then
  1694. begin
  1695. a_reg_alloc(list,NR_STACK_POINTER_REG);
  1696. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1697. begin
  1698. a_reg_alloc(list,NR_R12);
  1699. list.concat(taicpu.op_reg_reg(A_MOV,NR_R12,NR_STACK_POINTER_REG));
  1700. end;
  1701. { the (old) ARM APCS requires saving both the stack pointer (to
  1702. crawl the stack) and the PC (to identify the function this
  1703. stack frame belongs to) -> also save R12 (= copy of R13 on entry)
  1704. and R15 -- still needs updating for EABI and Darwin, they don't
  1705. need that }
  1706. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1707. regs:=regs+[RS_FRAME_POINTER_REG,RS_R12,RS_R14,RS_R15]
  1708. else
  1709. if (regs<>[]) or (pi_do_call in current_procinfo.flags) then
  1710. include(regs,RS_R14);
  1711. if regs<>[] then
  1712. begin
  1713. for r:=RS_R0 to RS_R15 do
  1714. if r in regs then
  1715. inc(registerarea,4);
  1716. { if the stack is not 8 byte aligned, try to add an extra register,
  1717. so we can avoid the extra sub/add ...,#4 later (KB) }
  1718. if ((registerarea mod current_settings.alignment.localalignmax) <> 0) then
  1719. for r:=RS_R3 downto RS_R0 do
  1720. if not(r in regs) then
  1721. begin
  1722. regs:=regs+[r];
  1723. inc(registerarea,4);
  1724. tarmprocinfo(current_procinfo).stackpaddingreg:=r;
  1725. break;
  1726. end;
  1727. list.concat(setoppostfix(taicpu.op_ref_regset(A_STM,ref,R_INTREGISTER,R_SUBWHOLE,regs),PF_FD));
  1728. end;
  1729. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1730. begin
  1731. { the framepointer now points to the saved R15, so the saved
  1732. framepointer is at R11-12 (for get_caller_frame) }
  1733. list.concat(taicpu.op_reg_reg_const(A_SUB,NR_FRAME_POINTER_REG,NR_R12,4));
  1734. a_reg_dealloc(list,NR_R12);
  1735. end;
  1736. end
  1737. else
  1738. begin
  1739. { always save r14 if we use r7 as the framepointer, because
  1740. the parameter offsets are hardcoded in advance and always
  1741. assume that r14 sits on the stack right behind the saved r7
  1742. }
  1743. if current_procinfo.framepointer=NR_FRAME_POINTER_REG then
  1744. include(regs,RS_FRAME_POINTER_REG);
  1745. if (regs<>[]) or (pi_do_call in current_procinfo.flags) then
  1746. include(regs,RS_R14);
  1747. if regs<>[] then
  1748. begin
  1749. { on Darwin, you first have to save [r4-r7,lr], and then
  1750. [r8,r10,r11] and make r7 point to the previously saved
  1751. r7 so that you can perform a stack crawl based on it
  1752. ([r7] is previous stack frame, [r7+4] is return address
  1753. }
  1754. include(regs,RS_FRAME_POINTER_REG);
  1755. saveregs:=regs-[RS_R8,RS_R10,RS_R11];
  1756. r7offset:=0;
  1757. for r:=RS_R0 to RS_R15 do
  1758. if r in saveregs then
  1759. begin
  1760. inc(registerarea,4);
  1761. if r<RS_FRAME_POINTER_REG then
  1762. inc(r7offset,4);
  1763. end;
  1764. { save the registers }
  1765. list.concat(setoppostfix(taicpu.op_ref_regset(A_STM,ref,R_INTREGISTER,R_SUBWHOLE,saveregs),PF_FD));
  1766. { make r7 point to the saved r7 (regardless of whether this
  1767. frame uses the framepointer, for backtrace purposes) }
  1768. if r7offset<>0 then
  1769. list.concat(taicpu.op_reg_reg_const(A_ADD,NR_FRAME_POINTER_REG,NR_R13,r7offset))
  1770. else
  1771. list.concat(taicpu.op_reg_reg(A_MOV,NR_R7,NR_R13));
  1772. { now save the rest (if any) }
  1773. saveregs:=regs-saveregs;
  1774. if saveregs<>[] then
  1775. begin
  1776. for r:=RS_R8 to RS_R11 do
  1777. if r in saveregs then
  1778. inc(registerarea,4);
  1779. list.concat(setoppostfix(taicpu.op_ref_regset(A_STM,ref,R_INTREGISTER,R_SUBWHOLE,saveregs),PF_FD));
  1780. end;
  1781. end;
  1782. end;
  1783. stackmisalignment:=registerarea mod current_settings.alignment.localalignmax;
  1784. if (LocalSize<>0) or
  1785. ((stackmisalignment<>0) and
  1786. ((pi_do_call in current_procinfo.flags) or
  1787. (po_assembler in current_procinfo.procdef.procoptions))) then
  1788. begin
  1789. localsize:=align(localsize+stackmisalignment,current_settings.alignment.localalignmax)-stackmisalignment;
  1790. if stack_parameters and (pi_estimatestacksize in current_procinfo.flags) then
  1791. begin
  1792. if localsize>tarmprocinfo(current_procinfo).stackframesize then
  1793. internalerror(2014030901)
  1794. else
  1795. localsize:=tarmprocinfo(current_procinfo).stackframesize-registerarea;
  1796. end;
  1797. if is_shifter_const(localsize,shift) then
  1798. begin
  1799. a_reg_dealloc(list,NR_R12);
  1800. list.concat(taicpu.op_reg_reg_const(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,LocalSize));
  1801. end
  1802. else if split_into_shifter_const(localsize, imm1, imm2) then
  1803. begin
  1804. a_reg_dealloc(list,NR_R12);
  1805. list.concat(taicpu.op_reg_reg_const(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,imm1));
  1806. list.concat(taicpu.op_reg_reg_const(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,imm2));
  1807. end
  1808. else
  1809. begin
  1810. if current_procinfo.framepointer=NR_STACK_POINTER_REG then
  1811. a_reg_alloc(list,NR_R12);
  1812. a_load_const_reg(list,OS_ADDR,LocalSize,NR_R12);
  1813. list.concat(taicpu.op_reg_reg_reg(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,NR_R12));
  1814. a_reg_dealloc(list,NR_R12);
  1815. end;
  1816. end;
  1817. if (mmregs<>[]) or
  1818. (firstfloatreg<>RS_NO) then
  1819. begin
  1820. reference_reset(ref,4);
  1821. if (tg.direction*tarmprocinfo(current_procinfo).floatregstart>=1023) or
  1822. (current_settings.fputype in [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16]) then
  1823. begin
  1824. if not is_shifter_const(tarmprocinfo(current_procinfo).floatregstart,shift) then
  1825. begin
  1826. a_reg_alloc(list,NR_R12);
  1827. a_load_const_reg(list,OS_ADDR,-tarmprocinfo(current_procinfo).floatregstart,NR_R12);
  1828. list.concat(taicpu.op_reg_reg_reg(A_SUB,NR_R12,current_procinfo.framepointer,NR_R12));
  1829. a_reg_dealloc(list,NR_R12);
  1830. end
  1831. else
  1832. list.concat(taicpu.op_reg_reg_const(A_SUB,NR_R12,current_procinfo.framepointer,-tarmprocinfo(current_procinfo).floatregstart));
  1833. ref.base:=NR_R12;
  1834. end
  1835. else
  1836. begin
  1837. ref.base:=current_procinfo.framepointer;
  1838. ref.offset:=tarmprocinfo(current_procinfo).floatregstart;
  1839. end;
  1840. case current_settings.fputype of
  1841. fpu_fpa,
  1842. fpu_fpa10,
  1843. fpu_fpa11:
  1844. begin
  1845. list.concat(taicpu.op_reg_const_ref(A_SFM,newreg(R_FPUREGISTER,firstfloatreg,R_SUBWHOLE),
  1846. lastfloatreg-firstfloatreg+1,ref));
  1847. end;
  1848. fpu_vfpv2,
  1849. fpu_vfpv3,
  1850. fpu_vfpv3_d16:
  1851. begin
  1852. ref.index:=ref.base;
  1853. ref.base:=NR_NO;
  1854. { FSTMX is deprecated on ARMv6 and later }
  1855. if (current_settings.cputype<cpu_armv6) then
  1856. postfix:=PF_IAX
  1857. else
  1858. postfix:=PF_IAD;
  1859. list.concat(setoppostfix(taicpu.op_ref_regset(A_FSTM,ref,R_MMREGISTER,R_SUBFD,mmregs),postfix));
  1860. end;
  1861. end;
  1862. end;
  1863. end;
  1864. end;
  1865. procedure tbasecgarm.g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean);
  1866. var
  1867. ref : treference;
  1868. LocalSize : longint;
  1869. firstfloatreg,lastfloatreg,
  1870. r,
  1871. shift : byte;
  1872. mmregs,
  1873. saveregs,
  1874. regs : tcpuregisterset;
  1875. registerarea,
  1876. stackmisalignment: pint;
  1877. paddingreg: TSuperRegister;
  1878. mmpostfix: toppostfix;
  1879. imm1, imm2: DWord;
  1880. begin
  1881. if not(nostackframe) then
  1882. begin
  1883. registerarea:=0;
  1884. firstfloatreg:=RS_NO;
  1885. lastfloatreg:=RS_NO;
  1886. mmregs:=[];
  1887. saveregs:=[];
  1888. case current_settings.fputype of
  1889. fpu_fpa,
  1890. fpu_fpa10,
  1891. fpu_fpa11:
  1892. begin
  1893. { restore floating point registers? }
  1894. regs:=rg[R_FPUREGISTER].used_in_proc-paramanager.get_volatile_registers_fpu(pocall_stdcall);
  1895. for r:=RS_F0 to RS_F7 do
  1896. if r in regs then
  1897. begin
  1898. if firstfloatreg=RS_NO then
  1899. firstfloatreg:=r;
  1900. lastfloatreg:=r;
  1901. { floating point register space is already included in
  1902. localsize below by calc_stackframe_size
  1903. inc(registerarea,12);
  1904. }
  1905. end;
  1906. end;
  1907. fpu_vfpv2,
  1908. fpu_vfpv3,
  1909. fpu_vfpv3_d16:
  1910. begin;
  1911. { restore vfp registers? }
  1912. mmregs:=rg[R_MMREGISTER].used_in_proc-paramanager.get_volatile_registers_mm(pocall_stdcall);
  1913. end;
  1914. end;
  1915. if (firstfloatreg<>RS_NO) or
  1916. (mmregs<>[]) then
  1917. begin
  1918. reference_reset(ref,4);
  1919. if (tg.direction*tarmprocinfo(current_procinfo).floatregstart>=1023) or
  1920. (current_settings.fputype in [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16]) then
  1921. begin
  1922. if not is_shifter_const(tarmprocinfo(current_procinfo).floatregstart,shift) then
  1923. begin
  1924. a_reg_alloc(list,NR_R12);
  1925. a_load_const_reg(list,OS_ADDR,-tarmprocinfo(current_procinfo).floatregstart,NR_R12);
  1926. list.concat(taicpu.op_reg_reg_reg(A_SUB,NR_R12,current_procinfo.framepointer,NR_R12));
  1927. a_reg_dealloc(list,NR_R12);
  1928. end
  1929. else
  1930. list.concat(taicpu.op_reg_reg_const(A_SUB,NR_R12,current_procinfo.framepointer,-tarmprocinfo(current_procinfo).floatregstart));
  1931. ref.base:=NR_R12;
  1932. end
  1933. else
  1934. begin
  1935. ref.base:=current_procinfo.framepointer;
  1936. ref.offset:=tarmprocinfo(current_procinfo).floatregstart;
  1937. end;
  1938. case current_settings.fputype of
  1939. fpu_fpa,
  1940. fpu_fpa10,
  1941. fpu_fpa11:
  1942. begin
  1943. list.concat(taicpu.op_reg_const_ref(A_LFM,newreg(R_FPUREGISTER,firstfloatreg,R_SUBWHOLE),
  1944. lastfloatreg-firstfloatreg+1,ref));
  1945. end;
  1946. fpu_vfpv2,
  1947. fpu_vfpv3,
  1948. fpu_vfpv3_d16:
  1949. begin
  1950. ref.index:=ref.base;
  1951. ref.base:=NR_NO;
  1952. { FLDMX is deprecated on ARMv6 and later }
  1953. if (current_settings.cputype<cpu_armv6) then
  1954. mmpostfix:=PF_IAX
  1955. else
  1956. mmpostfix:=PF_IAD;
  1957. list.concat(setoppostfix(taicpu.op_ref_regset(A_FLDM,ref,R_MMREGISTER,R_SUBFD,mmregs),mmpostfix));
  1958. end;
  1959. end;
  1960. end;
  1961. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1962. if (pi_do_call in current_procinfo.flags) or
  1963. (regs<>[]) or
  1964. ((target_info.system in systems_darwin) and
  1965. (current_procinfo.framepointer<>NR_STACK_POINTER_REG)) then
  1966. begin
  1967. exclude(regs,RS_R14);
  1968. include(regs,RS_R15);
  1969. if (target_info.system in systems_darwin) then
  1970. include(regs,RS_FRAME_POINTER_REG);
  1971. end;
  1972. if not(target_info.system in systems_darwin) then
  1973. begin
  1974. { restore saved stack pointer to SP (R13) and saved lr to PC (R15).
  1975. The saved PC came after that but is discarded, since we restore
  1976. the stack pointer }
  1977. if (current_procinfo.framepointer<>NR_STACK_POINTER_REG) then
  1978. regs:=regs+[RS_FRAME_POINTER_REG,RS_R13,RS_R15];
  1979. end
  1980. else
  1981. begin
  1982. { restore R8-R11 already if necessary (they've been stored
  1983. before the others) }
  1984. saveregs:=regs*[RS_R8,RS_R10,RS_R11];
  1985. if saveregs<>[] then
  1986. begin
  1987. reference_reset(ref,4);
  1988. ref.index:=NR_STACK_POINTER_REG;
  1989. ref.addressmode:=AM_PREINDEXED;
  1990. for r:=RS_R8 to RS_R11 do
  1991. if r in saveregs then
  1992. inc(registerarea,4);
  1993. regs:=regs-saveregs;
  1994. end;
  1995. end;
  1996. for r:=RS_R0 to RS_R15 do
  1997. if r in regs then
  1998. inc(registerarea,4);
  1999. { reapply the stack padding reg, in case there was one, see the complimentary
  2000. comment in g_proc_entry() (KB) }
  2001. paddingreg:=tarmprocinfo(current_procinfo).stackpaddingreg;
  2002. if paddingreg < RS_R4 then
  2003. if paddingreg in regs then
  2004. internalerror(201306190)
  2005. else
  2006. begin
  2007. regs:=regs+[paddingreg];
  2008. inc(registerarea,4);
  2009. end;
  2010. stackmisalignment:=registerarea mod current_settings.alignment.localalignmax;
  2011. if (current_procinfo.framepointer=NR_STACK_POINTER_REG) or
  2012. (target_info.system in systems_darwin) then
  2013. begin
  2014. LocalSize:=current_procinfo.calc_stackframe_size;
  2015. if (LocalSize<>0) or
  2016. ((stackmisalignment<>0) and
  2017. ((pi_do_call in current_procinfo.flags) or
  2018. (po_assembler in current_procinfo.procdef.procoptions))) then
  2019. begin
  2020. if pi_estimatestacksize in current_procinfo.flags then
  2021. LocalSize:=tarmprocinfo(current_procinfo).stackframesize-registerarea
  2022. else
  2023. localsize:=align(localsize+stackmisalignment,current_settings.alignment.localalignmax)-stackmisalignment;
  2024. if is_shifter_const(LocalSize,shift) then
  2025. list.concat(taicpu.op_reg_reg_const(A_ADD,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,LocalSize))
  2026. else if split_into_shifter_const(localsize, imm1, imm2) then
  2027. begin
  2028. list.concat(taicpu.op_reg_reg_const(A_ADD,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,imm1));
  2029. list.concat(taicpu.op_reg_reg_const(A_ADD,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,imm2));
  2030. end
  2031. else
  2032. begin
  2033. a_reg_alloc(list,NR_R12);
  2034. a_load_const_reg(list,OS_ADDR,LocalSize,NR_R12);
  2035. list.concat(taicpu.op_reg_reg_reg(A_ADD,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,NR_R12));
  2036. a_reg_dealloc(list,NR_R12);
  2037. end;
  2038. end;
  2039. if (target_info.system in systems_darwin) and
  2040. (saveregs<>[]) then
  2041. list.concat(setoppostfix(taicpu.op_ref_regset(A_LDM,ref,R_INTREGISTER,R_SUBWHOLE,saveregs),PF_FD));
  2042. if regs=[] then
  2043. begin
  2044. if not(CPUARM_HAS_BX in cpu_capabilities[current_settings.cputype]) then
  2045. list.concat(taicpu.op_reg_reg(A_MOV,NR_PC,NR_R14))
  2046. else
  2047. list.concat(taicpu.op_reg(A_BX,NR_R14))
  2048. end
  2049. else
  2050. begin
  2051. reference_reset(ref,4);
  2052. ref.index:=NR_STACK_POINTER_REG;
  2053. ref.addressmode:=AM_PREINDEXED;
  2054. list.concat(setoppostfix(taicpu.op_ref_regset(A_LDM,ref,R_INTREGISTER,R_SUBWHOLE,regs),PF_FD));
  2055. end;
  2056. end
  2057. else
  2058. begin
  2059. { restore int registers and return }
  2060. reference_reset(ref,4);
  2061. ref.index:=NR_FRAME_POINTER_REG;
  2062. list.concat(setoppostfix(taicpu.op_ref_regset(A_LDM,ref,R_INTREGISTER,R_SUBWHOLE,regs),PF_EA));
  2063. end;
  2064. end
  2065. else if not(CPUARM_HAS_BX in cpu_capabilities[current_settings.cputype]) then
  2066. list.concat(taicpu.op_reg_reg(A_MOV,NR_PC,NR_R14))
  2067. else
  2068. list.concat(taicpu.op_reg(A_BX,NR_R14))
  2069. end;
  2070. procedure tbasecgarm.g_maybe_got_init(list : TAsmList);
  2071. var
  2072. ref : treference;
  2073. l : TAsmLabel;
  2074. begin
  2075. if (cs_create_pic in current_settings.moduleswitches) and
  2076. (pi_needs_got in current_procinfo.flags) and
  2077. (tf_pic_uses_got in target_info.flags) then
  2078. begin
  2079. reference_reset(ref,4);
  2080. current_asmdata.getdatalabel(l);
  2081. cg.a_label(current_procinfo.aktlocaldata,l);
  2082. ref.symbol:=l;
  2083. ref.base:=NR_PC;
  2084. ref.symboldata:=current_procinfo.aktlocaldata.last;
  2085. list.concat(Taicpu.op_reg_ref(A_LDR,current_procinfo.got,ref));
  2086. current_asmdata.getaddrlabel(l);
  2087. current_procinfo.aktlocaldata.concat(tai_const.Create_rel_sym_offset(aitconst_32bit,l,current_asmdata.RefAsmSymbol('_GLOBAL_OFFSET_TABLE_'),-8));
  2088. cg.a_label(list,l);
  2089. list.concat(Taicpu.op_reg_reg_reg(A_ADD,current_procinfo.got,NR_PC,current_procinfo.got));
  2090. end;
  2091. end;
  2092. procedure tbasecgarm.a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);
  2093. var
  2094. b : byte;
  2095. tmpref : treference;
  2096. instr : taicpu;
  2097. begin
  2098. if ref.addressmode<>AM_OFFSET then
  2099. internalerror(200309071);
  2100. tmpref:=ref;
  2101. { Be sure to have a base register }
  2102. if (tmpref.base=NR_NO) then
  2103. begin
  2104. if tmpref.shiftmode<>SM_None then
  2105. internalerror(2014020702);
  2106. if tmpref.signindex<0 then
  2107. internalerror(200312023);
  2108. tmpref.base:=tmpref.index;
  2109. tmpref.index:=NR_NO;
  2110. end;
  2111. if assigned(tmpref.symbol) or
  2112. not((is_shifter_const(tmpref.offset,b)) or
  2113. (is_shifter_const(-tmpref.offset,b))
  2114. ) then
  2115. fixref(list,tmpref);
  2116. { expect a base here if there is an index }
  2117. if (tmpref.base=NR_NO) and (tmpref.index<>NR_NO) then
  2118. internalerror(200312022);
  2119. if tmpref.index<>NR_NO then
  2120. begin
  2121. if tmpref.shiftmode<>SM_None then
  2122. internalerror(200312021);
  2123. if tmpref.signindex<0 then
  2124. a_op_reg_reg_reg(list,OP_SUB,OS_ADDR,tmpref.base,tmpref.index,r)
  2125. else
  2126. a_op_reg_reg_reg(list,OP_ADD,OS_ADDR,tmpref.base,tmpref.index,r);
  2127. if tmpref.offset<>0 then
  2128. a_op_const_reg_reg(list,OP_ADD,OS_ADDR,tmpref.offset,r,r);
  2129. end
  2130. else
  2131. begin
  2132. if tmpref.base=NR_NO then
  2133. a_load_const_reg(list,OS_ADDR,tmpref.offset,r)
  2134. else
  2135. if tmpref.offset<>0 then
  2136. a_op_const_reg_reg(list,OP_ADD,OS_ADDR,tmpref.offset,tmpref.base,r)
  2137. else
  2138. begin
  2139. instr:=taicpu.op_reg_reg(A_MOV,r,tmpref.base);
  2140. list.concat(instr);
  2141. add_move_instruction(instr);
  2142. end;
  2143. end;
  2144. end;
  2145. procedure tbasecgarm.fixref(list : TAsmList;var ref : treference);
  2146. var
  2147. tmpreg, tmpreg2 : tregister;
  2148. tmpref : treference;
  2149. l, piclabel : tasmlabel;
  2150. indirection_done : boolean;
  2151. begin
  2152. { absolute symbols can't be handled directly, we've to store the symbol reference
  2153. in the text segment and access it pc relative
  2154. For now, we assume that references where base or index equals to PC are already
  2155. relative, all other references are assumed to be absolute and thus they need
  2156. to be handled extra.
  2157. A proper solution would be to change refoptions to a set and store the information
  2158. if the symbol is absolute or relative there.
  2159. }
  2160. { create consts entry }
  2161. reference_reset(tmpref,4);
  2162. current_asmdata.getjumplabel(l);
  2163. cg.a_label(current_procinfo.aktlocaldata,l);
  2164. tmpref.symboldata:=current_procinfo.aktlocaldata.last;
  2165. piclabel:=nil;
  2166. tmpreg:=NR_NO;
  2167. indirection_done:=false;
  2168. if assigned(ref.symbol) then
  2169. begin
  2170. if (target_info.system=system_arm_darwin) and
  2171. (ref.symbol.bind in [AB_EXTERNAL,AB_WEAK_EXTERNAL,AB_PRIVATE_EXTERN,AB_COMMON]) then
  2172. begin
  2173. tmpreg:=g_indirect_sym_load(list,ref.symbol.name,asmsym2indsymflags(ref.symbol));
  2174. if ref.offset<>0 then
  2175. a_op_const_reg(list,OP_ADD,OS_ADDR,ref.offset,tmpreg);
  2176. indirection_done:=true;
  2177. end
  2178. else if (cs_create_pic in current_settings.moduleswitches) then
  2179. if (tf_pic_uses_got in target_info.flags) then
  2180. current_procinfo.aktlocaldata.concat(tai_const.Create_type_sym_offset(aitconst_got,ref.symbol,ref.offset))
  2181. else
  2182. begin
  2183. { ideally, we would want to generate
  2184. ldr r1, LPICConstPool
  2185. LPICLocal:
  2186. ldr/str r2,[pc,r1]
  2187. ...
  2188. LPICConstPool:
  2189. .long _globsym-(LPICLocal+8)
  2190. However, we cannot be sure that the ldr/str will follow
  2191. right after the call to fixref, so we have to load the
  2192. complete address already in a register.
  2193. }
  2194. current_asmdata.getaddrlabel(piclabel);
  2195. current_procinfo.aktlocaldata.concat(tai_const.Create_rel_sym_offset(aitconst_ptr,piclabel,ref.symbol,ref.offset-8));
  2196. end
  2197. else
  2198. current_procinfo.aktlocaldata.concat(tai_const.create_sym_offset(ref.symbol,ref.offset))
  2199. end
  2200. else
  2201. current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(ref.offset));
  2202. { load consts entry }
  2203. if not indirection_done then
  2204. begin
  2205. tmpreg:=getintregister(list,OS_INT);
  2206. tmpref.symbol:=l;
  2207. tmpref.base:=NR_PC;
  2208. list.concat(taicpu.op_reg_ref(A_LDR,tmpreg,tmpref));
  2209. if (cs_create_pic in current_settings.moduleswitches) and
  2210. (tf_pic_uses_got in target_info.flags) and
  2211. assigned(ref.symbol) then
  2212. begin
  2213. reference_reset(tmpref,4);
  2214. tmpref.base:=current_procinfo.got;
  2215. tmpref.index:=tmpreg;
  2216. list.concat(taicpu.op_reg_ref(A_LDR,tmpreg,tmpref));
  2217. end;
  2218. end;
  2219. if assigned(piclabel) then
  2220. begin
  2221. cg.a_label(list,piclabel);
  2222. tmpreg2:=getaddressregister(list);
  2223. a_op_reg_reg_reg(list,OP_ADD,OS_ADDR,tmpreg,NR_PC,tmpreg2);
  2224. tmpreg:=tmpreg2
  2225. end;
  2226. { This routine can be called with PC as base/index in case the offset
  2227. was too large to encode in a load/store. In that case, the entire
  2228. absolute expression has been re-encoded in a new constpool entry, and
  2229. we have to remove the use of PC from the original reference (the code
  2230. above made everything relative to the value loaded from the new
  2231. constpool entry) }
  2232. if is_pc(ref.base) then
  2233. ref.base:=NR_NO;
  2234. if is_pc(ref.index) then
  2235. ref.index:=NR_NO;
  2236. if (ref.base<>NR_NO) then
  2237. begin
  2238. if ref.index<>NR_NO then
  2239. begin
  2240. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,tmpreg));
  2241. ref.base:=tmpreg;
  2242. end
  2243. else
  2244. if ref.base<>NR_PC then
  2245. begin
  2246. ref.index:=tmpreg;
  2247. ref.shiftimm:=0;
  2248. ref.signindex:=1;
  2249. ref.shiftmode:=SM_None;
  2250. end
  2251. else
  2252. ref.base:=tmpreg;
  2253. end
  2254. else
  2255. ref.base:=tmpreg;
  2256. ref.offset:=0;
  2257. ref.symbol:=nil;
  2258. end;
  2259. procedure tbasecgarm.g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  2260. var
  2261. paraloc1,paraloc2,paraloc3 : TCGPara;
  2262. pd : tprocdef;
  2263. begin
  2264. pd:=search_system_proc('MOVE');
  2265. paraloc1.init;
  2266. paraloc2.init;
  2267. paraloc3.init;
  2268. paramanager.getintparaloc(pd,1,paraloc1);
  2269. paramanager.getintparaloc(pd,2,paraloc2);
  2270. paramanager.getintparaloc(pd,3,paraloc3);
  2271. a_load_const_cgpara(list,OS_SINT,len,paraloc3);
  2272. a_loadaddr_ref_cgpara(list,dest,paraloc2);
  2273. a_loadaddr_ref_cgpara(list,source,paraloc1);
  2274. paramanager.freecgpara(list,paraloc3);
  2275. paramanager.freecgpara(list,paraloc2);
  2276. paramanager.freecgpara(list,paraloc1);
  2277. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  2278. alloccpuregisters(list,R_FPUREGISTER,paramanager.get_volatile_registers_fpu(pocall_default));
  2279. a_call_name(list,'FPC_MOVE',false);
  2280. dealloccpuregisters(list,R_FPUREGISTER,paramanager.get_volatile_registers_fpu(pocall_default));
  2281. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  2282. paraloc3.done;
  2283. paraloc2.done;
  2284. paraloc1.done;
  2285. end;
  2286. procedure tbasecgarm.g_concatcopy_internal(list : TAsmList;const source,dest : treference;len : tcgint;aligned : boolean);
  2287. const
  2288. maxtmpreg_arm = 10; {roozbeh: can be reduced to 8 or lower if might conflick with reserved ones,also +2 is used becouse of regs required for referencing}
  2289. maxtmpreg_thumb = 5;
  2290. var
  2291. srcref,dstref,usedtmpref,usedtmpref2:treference;
  2292. srcreg,destreg,countreg,r,tmpreg:tregister;
  2293. helpsize:aint;
  2294. copysize:byte;
  2295. cgsize:Tcgsize;
  2296. tmpregisters:array[1..maxtmpreg_arm] of tregister;
  2297. maxtmpreg,
  2298. tmpregi,tmpregi2:byte;
  2299. { will never be called with count<=4 }
  2300. procedure genloop(count : aword;size : byte);
  2301. const
  2302. size2opsize : array[1..4] of tcgsize = (OS_8,OS_16,OS_NO,OS_32);
  2303. var
  2304. l : tasmlabel;
  2305. begin
  2306. current_asmdata.getjumplabel(l);
  2307. if count<size then size:=1;
  2308. a_load_const_reg(list,OS_INT,count div size,countreg);
  2309. cg.a_label(list,l);
  2310. srcref.addressmode:=AM_POSTINDEXED;
  2311. dstref.addressmode:=AM_POSTINDEXED;
  2312. srcref.offset:=size;
  2313. dstref.offset:=size;
  2314. r:=getintregister(list,size2opsize[size]);
  2315. a_load_ref_reg(list,size2opsize[size],size2opsize[size],srcref,r);
  2316. a_reg_alloc(list,NR_DEFAULTFLAGS);
  2317. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_SUB,countreg,countreg,1),PF_S));
  2318. a_load_reg_ref(list,size2opsize[size],size2opsize[size],r,dstref);
  2319. a_jmp_flags(list,F_NE,l);
  2320. a_reg_dealloc(list,NR_DEFAULTFLAGS);
  2321. srcref.offset:=1;
  2322. dstref.offset:=1;
  2323. case count mod size of
  2324. 1:
  2325. begin
  2326. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  2327. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  2328. end;
  2329. 2:
  2330. if aligned then
  2331. begin
  2332. a_load_ref_reg(list,OS_16,OS_16,srcref,r);
  2333. a_load_reg_ref(list,OS_16,OS_16,r,dstref);
  2334. end
  2335. else
  2336. begin
  2337. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  2338. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  2339. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  2340. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  2341. end;
  2342. 3:
  2343. if aligned then
  2344. begin
  2345. srcref.offset:=2;
  2346. dstref.offset:=2;
  2347. a_load_ref_reg(list,OS_16,OS_16,srcref,r);
  2348. a_load_reg_ref(list,OS_16,OS_16,r,dstref);
  2349. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  2350. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  2351. end
  2352. else
  2353. begin
  2354. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  2355. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  2356. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  2357. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  2358. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  2359. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  2360. end;
  2361. end;
  2362. { keep the registers alive }
  2363. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  2364. list.concat(taicpu.op_reg_reg(A_MOV,srcreg,srcreg));
  2365. list.concat(taicpu.op_reg_reg(A_MOV,destreg,destreg));
  2366. end;
  2367. { will never be called with count<=4 }
  2368. procedure genloop_thumb(count : aword;size : byte);
  2369. procedure refincofs(const ref : treference;const value : longint = 1);
  2370. begin
  2371. a_op_const_reg(list,OP_ADD,OS_ADDR,value,ref.base);
  2372. end;
  2373. const
  2374. size2opsize : array[1..4] of tcgsize = (OS_8,OS_16,OS_NO,OS_32);
  2375. var
  2376. l : tasmlabel;
  2377. begin
  2378. current_asmdata.getjumplabel(l);
  2379. if count<size then size:=1;
  2380. a_load_const_reg(list,OS_INT,count div size,countreg);
  2381. cg.a_label(list,l);
  2382. r:=getintregister(list,size2opsize[size]);
  2383. a_load_ref_reg(list,size2opsize[size],size2opsize[size],srcref,r);
  2384. refincofs(srcref);
  2385. a_load_reg_ref(list,size2opsize[size],size2opsize[size],r,dstref);
  2386. refincofs(dstref);
  2387. a_reg_alloc(list,NR_DEFAULTFLAGS);
  2388. list.concat(taicpu.op_reg_reg_const(A_SUB,countreg,countreg,1));
  2389. a_jmp_flags(list,F_NE,l);
  2390. a_reg_dealloc(list,NR_DEFAULTFLAGS);
  2391. case count mod size of
  2392. 1:
  2393. begin
  2394. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  2395. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  2396. end;
  2397. 2:
  2398. if aligned then
  2399. begin
  2400. a_load_ref_reg(list,OS_16,OS_16,srcref,r);
  2401. a_load_reg_ref(list,OS_16,OS_16,r,dstref);
  2402. end
  2403. else
  2404. begin
  2405. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  2406. refincofs(srcref);
  2407. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  2408. refincofs(dstref);
  2409. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  2410. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  2411. end;
  2412. 3:
  2413. if aligned then
  2414. begin
  2415. a_load_ref_reg(list,OS_16,OS_16,srcref,r);
  2416. refincofs(srcref,2);
  2417. a_load_reg_ref(list,OS_16,OS_16,r,dstref);
  2418. refincofs(dstref,2);
  2419. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  2420. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  2421. end
  2422. else
  2423. begin
  2424. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  2425. refincofs(srcref);
  2426. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  2427. refincofs(dstref);
  2428. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  2429. refincofs(srcref);
  2430. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  2431. refincofs(dstref);
  2432. a_load_ref_reg(list,OS_8,OS_8,srcref,r);
  2433. a_load_reg_ref(list,OS_8,OS_8,r,dstref);
  2434. end;
  2435. end;
  2436. { keep the registers alive }
  2437. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  2438. list.concat(taicpu.op_reg_reg(A_MOV,srcreg,srcreg));
  2439. list.concat(taicpu.op_reg_reg(A_MOV,destreg,destreg));
  2440. end;
  2441. begin
  2442. if len=0 then
  2443. exit;
  2444. if GenerateThumbCode then
  2445. maxtmpreg:=maxtmpreg_thumb
  2446. else
  2447. maxtmpreg:=maxtmpreg_arm;
  2448. helpsize:=12+maxtmpreg*4;//52 with maxtmpreg=10
  2449. dstref:=dest;
  2450. srcref:=source;
  2451. if cs_opt_size in current_settings.optimizerswitches then
  2452. helpsize:=8;
  2453. if aligned and (len=4) then
  2454. begin
  2455. tmpreg:=getintregister(list,OS_32);
  2456. a_load_ref_reg(list,OS_32,OS_32,source,tmpreg);
  2457. a_load_reg_ref(list,OS_32,OS_32,tmpreg,dest);
  2458. end
  2459. else if aligned and (len=2) then
  2460. begin
  2461. tmpreg:=getintregister(list,OS_16);
  2462. a_load_ref_reg(list,OS_16,OS_16,source,tmpreg);
  2463. a_load_reg_ref(list,OS_16,OS_16,tmpreg,dest);
  2464. end
  2465. else if (len<=helpsize) and aligned then
  2466. begin
  2467. tmpregi:=0;
  2468. srcreg:=getintregister(list,OS_ADDR);
  2469. { explicit pc relative addressing, could be
  2470. e.g. a floating point constant }
  2471. if source.base=NR_PC then
  2472. begin
  2473. { ... then we don't need a loadaddr }
  2474. srcref:=source;
  2475. end
  2476. else
  2477. begin
  2478. a_loadaddr_ref_reg(list,source,srcreg);
  2479. reference_reset_base(srcref,srcreg,0,source.alignment);
  2480. end;
  2481. while (len div 4 <> 0) and (tmpregi<maxtmpreg) do
  2482. begin
  2483. inc(tmpregi);
  2484. tmpregisters[tmpregi]:=getintregister(list,OS_32);
  2485. a_load_ref_reg(list,OS_32,OS_32,srcref,tmpregisters[tmpregi]);
  2486. inc(srcref.offset,4);
  2487. dec(len,4);
  2488. end;
  2489. destreg:=getintregister(list,OS_ADDR);
  2490. a_loadaddr_ref_reg(list,dest,destreg);
  2491. reference_reset_base(dstref,destreg,0,dest.alignment);
  2492. tmpregi2:=1;
  2493. while (tmpregi2<=tmpregi) do
  2494. begin
  2495. a_load_reg_ref(list,OS_32,OS_32,tmpregisters[tmpregi2],dstref);
  2496. inc(dstref.offset,4);
  2497. inc(tmpregi2);
  2498. end;
  2499. copysize:=4;
  2500. cgsize:=OS_32;
  2501. while len<>0 do
  2502. begin
  2503. if len<2 then
  2504. begin
  2505. copysize:=1;
  2506. cgsize:=OS_8;
  2507. end
  2508. else if len<4 then
  2509. begin
  2510. copysize:=2;
  2511. cgsize:=OS_16;
  2512. end;
  2513. dec(len,copysize);
  2514. r:=getintregister(list,cgsize);
  2515. a_load_ref_reg(list,cgsize,cgsize,srcref,r);
  2516. a_load_reg_ref(list,cgsize,cgsize,r,dstref);
  2517. inc(srcref.offset,copysize);
  2518. inc(dstref.offset,copysize);
  2519. end;{end of while}
  2520. end
  2521. else
  2522. begin
  2523. cgsize:=OS_32;
  2524. if (len<=4) then{len<=4 and not aligned}
  2525. begin
  2526. r:=getintregister(list,cgsize);
  2527. usedtmpref:=a_internal_load_ref_reg(list,OS_8,OS_8,srcref,r);
  2528. if Len=1 then
  2529. a_load_reg_ref(list,OS_8,OS_8,r,dstref)
  2530. else
  2531. begin
  2532. tmpreg:=getintregister(list,cgsize);
  2533. usedtmpref2:=a_internal_load_reg_ref(list,OS_8,OS_8,r,dstref);
  2534. inc(usedtmpref.offset,1);
  2535. a_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
  2536. inc(usedtmpref2.offset,1);
  2537. a_load_reg_ref(list,OS_8,OS_8,tmpreg,usedtmpref2);
  2538. if len>2 then
  2539. begin
  2540. inc(usedtmpref.offset,1);
  2541. a_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
  2542. inc(usedtmpref2.offset,1);
  2543. a_load_reg_ref(list,OS_8,OS_8,tmpreg,usedtmpref2);
  2544. if len>3 then
  2545. begin
  2546. inc(usedtmpref.offset,1);
  2547. a_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
  2548. inc(usedtmpref2.offset,1);
  2549. a_load_reg_ref(list,OS_8,OS_8,tmpreg,usedtmpref2);
  2550. end;
  2551. end;
  2552. end;
  2553. end{end of if len<=4}
  2554. else
  2555. begin{unaligned & 4<len<helpsize **or** aligned/unaligned & len>helpsize}
  2556. destreg:=getintregister(list,OS_ADDR);
  2557. a_loadaddr_ref_reg(list,dest,destreg);
  2558. reference_reset_base(dstref,destreg,0,dest.alignment);
  2559. srcreg:=getintregister(list,OS_ADDR);
  2560. a_loadaddr_ref_reg(list,source,srcreg);
  2561. reference_reset_base(srcref,srcreg,0,source.alignment);
  2562. countreg:=getintregister(list,OS_32);
  2563. // if cs_opt_size in current_settings.optimizerswitches then
  2564. { roozbeh : it seems loading 1 byte is faster becouse of caching/fetching(?) }
  2565. {if aligned then
  2566. genloop(len,4)
  2567. else}
  2568. if GenerateThumbCode then
  2569. genloop_thumb(len,1)
  2570. else
  2571. genloop(len,1);
  2572. end;
  2573. end;
  2574. end;
  2575. procedure tbasecgarm.g_concatcopy_unaligned(list : TAsmList;const source,dest : treference;len : tcgint);
  2576. begin
  2577. g_concatcopy_internal(list,source,dest,len,false);
  2578. end;
  2579. procedure tbasecgarm.g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);
  2580. begin
  2581. if (source.alignment in [1,3]) or
  2582. (dest.alignment in [1,3]) then
  2583. g_concatcopy_internal(list,source,dest,len,false)
  2584. else
  2585. g_concatcopy_internal(list,source,dest,len,true);
  2586. end;
  2587. procedure tbasecgarm.g_overflowCheck(list : TAsmList;const l : tlocation;def : tdef);
  2588. var
  2589. ovloc : tlocation;
  2590. begin
  2591. ovloc.loc:=LOC_VOID;
  2592. g_overflowCheck_loc(list,l,def,ovloc);
  2593. end;
  2594. procedure tbasecgarm.g_overflowCheck_loc(List:TAsmList;const Loc:TLocation;def:TDef;ovloc : tlocation);
  2595. var
  2596. hl : tasmlabel;
  2597. ai:TAiCpu;
  2598. hflags : tresflags;
  2599. begin
  2600. if not(cs_check_overflow in current_settings.localswitches) then
  2601. exit;
  2602. current_asmdata.getjumplabel(hl);
  2603. case ovloc.loc of
  2604. LOC_VOID:
  2605. begin
  2606. ai:=taicpu.op_sym(A_B,hl);
  2607. ai.is_jmp:=true;
  2608. if not((def.typ=pointerdef) or
  2609. ((def.typ=orddef) and
  2610. (torddef(def).ordtype in [u64bit,u16bit,u32bit,u8bit,uchar,
  2611. pasbool8,pasbool16,pasbool32,pasbool64]))) then
  2612. ai.SetCondition(C_VC)
  2613. else
  2614. if TAiCpu(List.Last).opcode in [A_RSB,A_RSC,A_SBC,A_SUB] then
  2615. ai.SetCondition(C_CS)
  2616. else
  2617. ai.SetCondition(C_CC);
  2618. list.concat(ai);
  2619. end;
  2620. LOC_FLAGS:
  2621. begin
  2622. hflags:=ovloc.resflags;
  2623. inverse_flags(hflags);
  2624. cg.a_jmp_flags(list,hflags,hl);
  2625. cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
  2626. end;
  2627. else
  2628. internalerror(200409281);
  2629. end;
  2630. a_call_name(list,'FPC_OVERFLOW',false);
  2631. a_label(list,hl);
  2632. end;
  2633. procedure tbasecgarm.g_save_registers(list : TAsmList);
  2634. begin
  2635. { this work is done in g_proc_entry }
  2636. end;
  2637. procedure tbasecgarm.g_restore_registers(list : TAsmList);
  2638. begin
  2639. { this work is done in g_proc_exit }
  2640. end;
  2641. procedure tbasecgarm.a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  2642. var
  2643. ai : taicpu;
  2644. hlabel : TAsmLabel;
  2645. begin
  2646. if GenerateThumbCode then
  2647. begin
  2648. { the optimizer has to fix this if jump range is sufficient short }
  2649. current_asmdata.getjumplabel(hlabel);
  2650. ai:=Taicpu.Op_sym(A_B,hlabel);
  2651. ai.SetCondition(inverse_cond(OpCmp2AsmCond[cond]));
  2652. ai.is_jmp:=true;
  2653. list.concat(ai);
  2654. a_jmp_always(list,l);
  2655. a_label(list,hlabel);
  2656. end
  2657. else
  2658. begin
  2659. ai:=Taicpu.Op_sym(A_B,l);
  2660. ai.SetCondition(OpCmp2AsmCond[cond]);
  2661. ai.is_jmp:=true;
  2662. list.concat(ai);
  2663. end;
  2664. end;
  2665. function get_scalar_mm_op(fromsize,tosize : tcgsize) : tasmop;
  2666. const
  2667. convertop : array[OS_F32..OS_F128,OS_F32..OS_F128] of tasmop = (
  2668. (A_FCPYS,A_FCVTSD,A_NONE,A_NONE,A_NONE),
  2669. (A_FCVTDS,A_FCPYD,A_NONE,A_NONE,A_NONE),
  2670. (A_NONE,A_NONE,A_NONE,A_NONE,A_NONE),
  2671. (A_NONE,A_NONE,A_NONE,A_NONE,A_NONE),
  2672. (A_NONE,A_NONE,A_NONE,A_NONE,A_NONE));
  2673. begin
  2674. result:=convertop[fromsize,tosize];
  2675. if result=A_NONE then
  2676. internalerror(200312205);
  2677. end;
  2678. procedure tbasecgarm.a_loadmm_reg_reg(list: tasmlist; fromsize,tosize: tcgsize; reg1,reg2: tregister; shuffle: pmmshuffle);
  2679. var
  2680. instr: taicpu;
  2681. begin
  2682. if shuffle=nil then
  2683. begin
  2684. if fromsize=tosize then
  2685. { needs correct size in case of spilling }
  2686. case fromsize of
  2687. OS_F32:
  2688. instr:=taicpu.op_reg_reg(A_FCPYS,reg2,reg1);
  2689. OS_F64:
  2690. instr:=taicpu.op_reg_reg(A_FCPYD,reg2,reg1);
  2691. else
  2692. internalerror(2009112405);
  2693. end
  2694. else
  2695. internalerror(2009112406);
  2696. end
  2697. else if shufflescalar(shuffle) then
  2698. instr:=taicpu.op_reg_reg(get_scalar_mm_op(tosize,fromsize),reg2,reg1)
  2699. else
  2700. internalerror(2009112407);
  2701. list.concat(instr);
  2702. case instr.opcode of
  2703. A_FCPYS,
  2704. A_FCPYD:
  2705. add_move_instruction(instr);
  2706. end;
  2707. end;
  2708. procedure tbasecgarm.a_loadmm_ref_reg(list: tasmlist; fromsize,tosize: tcgsize; const ref: treference; reg: tregister; shuffle: pmmshuffle);
  2709. var
  2710. intreg,
  2711. tmpmmreg : tregister;
  2712. reg64 : tregister64;
  2713. op : tasmop;
  2714. begin
  2715. if assigned(shuffle) and
  2716. not(shufflescalar(shuffle)) then
  2717. internalerror(2009112413);
  2718. case fromsize of
  2719. OS_32,OS_S32:
  2720. begin
  2721. fromsize:=OS_F32;
  2722. { since we are loading an integer, no conversion may be required }
  2723. if (fromsize<>tosize) then
  2724. internalerror(2009112801);
  2725. end;
  2726. OS_64,OS_S64:
  2727. begin
  2728. fromsize:=OS_F64;
  2729. { since we are loading an integer, no conversion may be required }
  2730. if (fromsize<>tosize) then
  2731. internalerror(2009112901);
  2732. end;
  2733. end;
  2734. if (fromsize<>tosize) then
  2735. tmpmmreg:=getmmregister(list,fromsize)
  2736. else
  2737. tmpmmreg:=reg;
  2738. if (ref.alignment in [1,2]) then
  2739. begin
  2740. case fromsize of
  2741. OS_F32:
  2742. begin
  2743. intreg:=getintregister(list,OS_32);
  2744. a_load_ref_reg(list,OS_32,OS_32,ref,intreg);
  2745. a_loadmm_intreg_reg(list,OS_32,OS_F32,intreg,tmpmmreg,mms_movescalar);
  2746. end;
  2747. OS_F64:
  2748. begin
  2749. reg64.reglo:=getintregister(list,OS_32);
  2750. reg64.reghi:=getintregister(list,OS_32);
  2751. cg64.a_load64_ref_reg(list,ref,reg64);
  2752. cg64.a_loadmm_intreg64_reg(list,OS_F64,reg64,tmpmmreg);
  2753. end;
  2754. else
  2755. internalerror(2009112412);
  2756. end;
  2757. end
  2758. else
  2759. begin
  2760. case fromsize of
  2761. OS_F32:
  2762. op:=A_FLDS;
  2763. OS_F64:
  2764. op:=A_FLDD;
  2765. else
  2766. internalerror(2009112415);
  2767. end;
  2768. handle_load_store(list,op,PF_None,tmpmmreg,ref);
  2769. end;
  2770. if (tmpmmreg<>reg) then
  2771. a_loadmm_reg_reg(list,fromsize,tosize,tmpmmreg,reg,shuffle);
  2772. end;
  2773. procedure tbasecgarm.a_loadmm_reg_ref(list: tasmlist; fromsize,tosize: tcgsize; reg: tregister; const ref: treference; shuffle: pmmshuffle);
  2774. var
  2775. intreg,
  2776. tmpmmreg : tregister;
  2777. reg64 : tregister64;
  2778. op : tasmop;
  2779. begin
  2780. if assigned(shuffle) and
  2781. not(shufflescalar(shuffle)) then
  2782. internalerror(2009112416);
  2783. case tosize of
  2784. OS_32,OS_S32:
  2785. begin
  2786. tosize:=OS_F32;
  2787. { since we are loading an integer, no conversion may be required }
  2788. if (fromsize<>tosize) then
  2789. internalerror(2009112801);
  2790. end;
  2791. OS_64,OS_S64:
  2792. begin
  2793. tosize:=OS_F64;
  2794. { since we are loading an integer, no conversion may be required }
  2795. if (fromsize<>tosize) then
  2796. internalerror(2009112901);
  2797. end;
  2798. end;
  2799. if (fromsize<>tosize) then
  2800. begin
  2801. tmpmmreg:=getmmregister(list,tosize);
  2802. a_loadmm_reg_reg(list,fromsize,tosize,reg,tmpmmreg,shuffle);
  2803. end
  2804. else
  2805. tmpmmreg:=reg;
  2806. if (ref.alignment in [1,2]) then
  2807. begin
  2808. case tosize of
  2809. OS_F32:
  2810. begin
  2811. intreg:=getintregister(list,OS_32);
  2812. a_loadmm_reg_intreg(list,OS_F32,OS_32,tmpmmreg,intreg,shuffle);
  2813. a_load_reg_ref(list,OS_32,OS_32,intreg,ref);
  2814. end;
  2815. OS_F64:
  2816. begin
  2817. reg64.reglo:=getintregister(list,OS_32);
  2818. reg64.reghi:=getintregister(list,OS_32);
  2819. cg64.a_loadmm_reg_intreg64(list,OS_F64,tmpmmreg,reg64);
  2820. cg64.a_load64_reg_ref(list,reg64,ref);
  2821. end;
  2822. else
  2823. internalerror(2009112417);
  2824. end;
  2825. end
  2826. else
  2827. begin
  2828. case fromsize of
  2829. OS_F32:
  2830. op:=A_FSTS;
  2831. OS_F64:
  2832. op:=A_FSTD;
  2833. else
  2834. internalerror(2009112418);
  2835. end;
  2836. handle_load_store(list,op,PF_None,tmpmmreg,ref);
  2837. end;
  2838. end;
  2839. procedure tbasecgarm.a_loadmm_intreg_reg(list: TAsmList; fromsize, tosize : tcgsize; intreg, mmreg: tregister; shuffle: pmmshuffle);
  2840. begin
  2841. { this code can only be used to transfer raw data, not to perform
  2842. conversions }
  2843. if (tosize<>OS_F32) then
  2844. internalerror(2009112419);
  2845. if not(fromsize in [OS_32,OS_S32]) then
  2846. internalerror(2009112420);
  2847. if assigned(shuffle) and
  2848. not shufflescalar(shuffle) then
  2849. internalerror(2009112516);
  2850. list.concat(taicpu.op_reg_reg(A_FMSR,mmreg,intreg));
  2851. end;
  2852. procedure tbasecgarm.a_loadmm_reg_intreg(list: TAsmList; fromsize, tosize : tcgsize; mmreg, intreg: tregister;shuffle : pmmshuffle);
  2853. begin
  2854. { this code can only be used to transfer raw data, not to perform
  2855. conversions }
  2856. if (fromsize<>OS_F32) then
  2857. internalerror(2009112430);
  2858. if not(tosize in [OS_32,OS_S32]) then
  2859. internalerror(2009112420);
  2860. if assigned(shuffle) and
  2861. not shufflescalar(shuffle) then
  2862. internalerror(2009112514);
  2863. list.concat(taicpu.op_reg_reg(A_FMRS,intreg,mmreg));
  2864. end;
  2865. procedure tbasecgarm.a_opmm_reg_reg(list: tasmlist; op: topcg; size: tcgsize; src, dst: tregister; shuffle: pmmshuffle);
  2866. var
  2867. tmpreg: tregister;
  2868. begin
  2869. { the vfp doesn't support xor nor any other logical operation, but
  2870. this routine is used to initialise global mm regvars. We can
  2871. easily initialise an mm reg with 0 though. }
  2872. case op of
  2873. OP_XOR:
  2874. begin
  2875. if (src<>dst) or
  2876. (reg_cgsize(src)<>size) or
  2877. assigned(shuffle) then
  2878. internalerror(2009112907);
  2879. tmpreg:=getintregister(list,OS_32);
  2880. a_load_const_reg(list,OS_32,0,tmpreg);
  2881. case size of
  2882. OS_F32:
  2883. list.concat(taicpu.op_reg_reg(A_FMSR,dst,tmpreg));
  2884. OS_F64:
  2885. list.concat(taicpu.op_reg_reg_reg(A_FMDRR,dst,tmpreg,tmpreg));
  2886. else
  2887. internalerror(2009112908);
  2888. end;
  2889. end
  2890. else
  2891. internalerror(2009112906);
  2892. end;
  2893. end;
  2894. procedure tbasecgarm.g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);
  2895. procedure loadvmttor12;
  2896. var
  2897. tmpref,
  2898. href : treference;
  2899. extrareg : boolean;
  2900. l : TAsmLabel;
  2901. begin
  2902. reference_reset_base(href,NR_R0,0,sizeof(pint));
  2903. if GenerateThumbCode then
  2904. begin
  2905. if (href.offset in [0..124]) and ((href.offset mod 4)=0) then
  2906. begin
  2907. list.concat(taicpu.op_regset(A_PUSH,R_INTREGISTER,R_SUBWHOLE,[RS_R0]));
  2908. cg.a_load_ref_reg(list,OS_ADDR,OS_ADDR,href,NR_R0);
  2909. list.concat(taicpu.op_reg_reg(A_MOV,NR_R12,NR_R0));
  2910. list.concat(taicpu.op_regset(A_POP,R_INTREGISTER,R_SUBWHOLE,[RS_R0]));
  2911. end
  2912. else
  2913. begin
  2914. list.concat(taicpu.op_regset(A_PUSH,R_INTREGISTER,R_SUBWHOLE,[RS_R0,RS_R1]));
  2915. { create consts entry }
  2916. reference_reset(tmpref,4);
  2917. current_asmdata.getjumplabel(l);
  2918. current_procinfo.aktlocaldata.Concat(tai_align.Create(4));
  2919. cg.a_label(current_procinfo.aktlocaldata,l);
  2920. tmpref.symboldata:=current_procinfo.aktlocaldata.last;
  2921. current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(href.offset));
  2922. tmpref.symbol:=l;
  2923. tmpref.base:=NR_PC;
  2924. list.concat(taicpu.op_reg_ref(A_LDR,NR_R1,tmpref));
  2925. href.offset:=0;
  2926. href.index:=NR_R1;
  2927. cg.a_load_ref_reg(list,OS_ADDR,OS_ADDR,href,NR_R0);
  2928. list.concat(taicpu.op_reg_reg(A_MOV,NR_R12,NR_R0));
  2929. list.concat(taicpu.op_regset(A_POP,R_INTREGISTER,R_SUBWHOLE,[RS_R0,RS_R1]));
  2930. end;
  2931. end
  2932. else
  2933. cg.a_load_ref_reg(list,OS_ADDR,OS_ADDR,href,NR_R12);
  2934. end;
  2935. procedure op_onr12methodaddr;
  2936. var
  2937. tmpref,
  2938. href : treference;
  2939. l : TAsmLabel;
  2940. begin
  2941. if (procdef.extnumber=$ffff) then
  2942. Internalerror(200006139);
  2943. if GenerateThumbCode then
  2944. begin
  2945. reference_reset_base(href,NR_R0,tobjectdef(procdef.struct).vmtmethodoffset(procdef.extnumber),sizeof(pint));
  2946. if (href.offset in [0..124]) and ((href.offset mod 4)=0) then
  2947. begin
  2948. list.concat(taicpu.op_regset(A_PUSH,R_INTREGISTER,R_SUBWHOLE,[RS_R0]));
  2949. list.concat(taicpu.op_reg_reg(A_MOV,NR_R0,NR_R12));
  2950. cg.a_load_ref_reg(list,OS_ADDR,OS_ADDR,href,NR_R0);
  2951. list.concat(taicpu.op_reg_reg(A_MOV,NR_R12,NR_R0));
  2952. list.concat(taicpu.op_regset(A_POP,R_INTREGISTER,R_SUBWHOLE,[RS_R0]));
  2953. end
  2954. else
  2955. begin
  2956. list.concat(taicpu.op_regset(A_PUSH,R_INTREGISTER,R_SUBWHOLE,[RS_R0,RS_R1]));
  2957. { create consts entry }
  2958. reference_reset(tmpref,4);
  2959. current_asmdata.getjumplabel(l);
  2960. current_procinfo.aktlocaldata.Concat(tai_align.Create(4));
  2961. cg.a_label(current_procinfo.aktlocaldata,l);
  2962. tmpref.symboldata:=current_procinfo.aktlocaldata.last;
  2963. current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(href.offset));
  2964. tmpref.symbol:=l;
  2965. tmpref.base:=NR_PC;
  2966. list.concat(taicpu.op_reg_ref(A_LDR,NR_R1,tmpref));
  2967. list.concat(taicpu.op_reg_reg(A_MOV,NR_R0,NR_R12));
  2968. href.offset:=0;
  2969. href.base:=NR_R0;
  2970. href.index:=NR_R1;
  2971. cg.a_load_ref_reg(list,OS_ADDR,OS_ADDR,href,NR_R0);
  2972. list.concat(taicpu.op_reg_reg(A_MOV,NR_R12,NR_R0));
  2973. list.concat(taicpu.op_regset(A_POP,R_INTREGISTER,R_SUBWHOLE,[RS_R0,RS_R1]));
  2974. end;
  2975. end
  2976. else
  2977. begin
  2978. reference_reset_base(href,NR_R12,tobjectdef(procdef.struct).vmtmethodoffset(procdef.extnumber),sizeof(pint));
  2979. cg.a_load_ref_reg(list,OS_ADDR,OS_ADDR,href,NR_R12);
  2980. end;
  2981. list.concat(taicpu.op_reg(A_BX,NR_R12));
  2982. end;
  2983. var
  2984. make_global : boolean;
  2985. tmpref : treference;
  2986. l : TAsmLabel;
  2987. begin
  2988. if not(procdef.proctypeoption in [potype_function,potype_procedure]) then
  2989. Internalerror(200006137);
  2990. if not assigned(procdef.struct) or
  2991. (procdef.procoptions*[po_classmethod, po_staticmethod,
  2992. po_methodpointer, po_interrupt, po_iocheck]<>[]) then
  2993. Internalerror(200006138);
  2994. if procdef.owner.symtabletype<>ObjectSymtable then
  2995. Internalerror(200109191);
  2996. if GenerateThumbCode or GenerateThumb2Code then
  2997. list.concat(tai_thumb_func.create);
  2998. make_global:=false;
  2999. if (not current_module.is_unit) or
  3000. create_smartlink or
  3001. (procdef.owner.defowner.owner.symtabletype=globalsymtable) then
  3002. make_global:=true;
  3003. if make_global then
  3004. list.concat(Tai_symbol.Createname_global(labelname,AT_FUNCTION,0))
  3005. else
  3006. list.concat(Tai_symbol.Createname(labelname,AT_FUNCTION,0));
  3007. { the wrapper might need aktlocaldata for the additional data to
  3008. load the constant }
  3009. current_procinfo:=cprocinfo.create(nil);
  3010. { set param1 interface to self }
  3011. g_adjust_self_value(list,procdef,ioffset);
  3012. { case 4 }
  3013. if (po_virtualmethod in procdef.procoptions) and
  3014. not is_objectpascal_helper(procdef.struct) then
  3015. begin
  3016. loadvmttor12;
  3017. op_onr12methodaddr;
  3018. end
  3019. { case 0 }
  3020. else if GenerateThumbCode then
  3021. begin
  3022. { bl cannot be used here because it destroys lr }
  3023. list.concat(taicpu.op_regset(A_PUSH,R_INTREGISTER,R_SUBWHOLE,[RS_R0]));
  3024. { create consts entry }
  3025. reference_reset(tmpref,4);
  3026. current_asmdata.getjumplabel(l);
  3027. current_procinfo.aktlocaldata.Concat(tai_align.Create(4));
  3028. cg.a_label(current_procinfo.aktlocaldata,l);
  3029. tmpref.symboldata:=current_procinfo.aktlocaldata.last;
  3030. current_procinfo.aktlocaldata.concat(tai_const.Create_sym(current_asmdata.RefAsmSymbol(procdef.mangledname)));
  3031. tmpref.symbol:=l;
  3032. tmpref.base:=NR_PC;
  3033. cg.a_load_ref_reg(list,OS_ADDR,OS_ADDR,tmpref,NR_R0);
  3034. list.concat(taicpu.op_reg_reg(A_MOV,NR_R12,NR_R0));
  3035. list.concat(taicpu.op_regset(A_POP,R_INTREGISTER,R_SUBWHOLE,[RS_R0]));
  3036. list.concat(taicpu.op_reg(A_BX,NR_R12));
  3037. end
  3038. else
  3039. list.concat(taicpu.op_sym(A_B,current_asmdata.RefAsmSymbol(procdef.mangledname)));
  3040. list.concatlist(current_procinfo.aktlocaldata);
  3041. current_procinfo.Free;
  3042. current_procinfo:=nil;
  3043. list.concat(Tai_symbol_end.Createname(labelname));
  3044. end;
  3045. procedure tbasecgarm.maybeadjustresult(list: TAsmList; op: TOpCg; size: tcgsize; dst: tregister);
  3046. const
  3047. overflowops = [OP_MUL,OP_SHL,OP_ADD,OP_SUB,OP_NEG];
  3048. begin
  3049. if (op in overflowops) and
  3050. (size in [OS_8,OS_S8,OS_16,OS_S16]) then
  3051. a_load_reg_reg(list,OS_32,size,dst,dst);
  3052. end;
  3053. procedure tbasecgarm.safe_mla(list : TAsmList; op1,op2,op3,op4 : TRegister);
  3054. procedure checkreg(var reg : TRegister);
  3055. var
  3056. tmpreg : TRegister;
  3057. begin
  3058. if ((GenerateThumbCode or GenerateThumb2Code) and (getsupreg(reg)=RS_R13)) or
  3059. (getsupreg(reg)=RS_R15) then
  3060. begin
  3061. tmpreg:=getintregister(list,OS_INT);
  3062. a_load_reg_reg(list,OS_INT,OS_INT,reg,tmpreg);
  3063. reg:=tmpreg;
  3064. end;
  3065. end;
  3066. begin
  3067. checkreg(op1);
  3068. checkreg(op2);
  3069. checkreg(op3);
  3070. checkreg(op4);
  3071. list.concat(taicpu.op_reg_reg_reg_reg(A_MLA,op1,op2,op3,op4));
  3072. end;
  3073. procedure tcg64farm.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
  3074. begin
  3075. case op of
  3076. OP_NEG:
  3077. begin
  3078. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  3079. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_RSB,regdst.reglo,regsrc.reglo,0),PF_S));
  3080. list.concat(taicpu.op_reg_reg_const(A_RSC,regdst.reghi,regsrc.reghi,0));
  3081. cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
  3082. end;
  3083. OP_NOT:
  3084. begin
  3085. cg.a_op_reg_reg(list,OP_NOT,OS_INT,regsrc.reglo,regdst.reglo);
  3086. cg.a_op_reg_reg(list,OP_NOT,OS_INT,regsrc.reghi,regdst.reghi);
  3087. end;
  3088. else
  3089. a_op64_reg_reg_reg(list,op,size,regsrc,regdst,regdst);
  3090. end;
  3091. end;
  3092. procedure tcg64farm.a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);
  3093. begin
  3094. a_op64_const_reg_reg(list,op,size,value,reg,reg);
  3095. end;
  3096. procedure tcg64farm.a_op64_const_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64);
  3097. var
  3098. ovloc : tlocation;
  3099. begin
  3100. a_op64_const_reg_reg_checkoverflow(list,op,size,value,regsrc,regdst,false,ovloc);
  3101. end;
  3102. procedure tcg64farm.a_op64_reg_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64);
  3103. var
  3104. ovloc : tlocation;
  3105. begin
  3106. a_op64_reg_reg_reg_checkoverflow(list,op,size,regsrc1,regsrc2,regdst,false,ovloc);
  3107. end;
  3108. procedure tcg64farm.a_loadmm_intreg64_reg(list: TAsmList; mmsize: tcgsize; intreg: tregister64; mmreg: tregister);
  3109. begin
  3110. { this code can only be used to transfer raw data, not to perform
  3111. conversions }
  3112. if (mmsize<>OS_F64) then
  3113. internalerror(2009112405);
  3114. list.concat(taicpu.op_reg_reg_reg(A_FMDRR,mmreg,intreg.reglo,intreg.reghi));
  3115. end;
  3116. procedure tcg64farm.a_loadmm_reg_intreg64(list: TAsmList; mmsize: tcgsize; mmreg: tregister; intreg: tregister64);
  3117. begin
  3118. { this code can only be used to transfer raw data, not to perform
  3119. conversions }
  3120. if (mmsize<>OS_F64) then
  3121. internalerror(2009112406);
  3122. list.concat(taicpu.op_reg_reg_reg(A_FMRRD,intreg.reglo,intreg.reghi,mmreg));
  3123. end;
  3124. procedure tcg64farm.a_op64_const_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64;setflags : boolean;var ovloc : tlocation);
  3125. var
  3126. tmpreg : tregister;
  3127. b : byte;
  3128. begin
  3129. ovloc.loc:=LOC_VOID;
  3130. case op of
  3131. OP_NEG,
  3132. OP_NOT :
  3133. internalerror(2012022501);
  3134. end;
  3135. if (setflags or tbasecgarm(cg).cgsetflags) and (op in [OP_ADD,OP_SUB]) then
  3136. begin
  3137. case op of
  3138. OP_ADD:
  3139. begin
  3140. if is_shifter_const(lo(value),b) then
  3141. begin
  3142. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  3143. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_ADD,regdst.reglo,regsrc.reglo,lo(value)),PF_S))
  3144. end
  3145. else
  3146. begin
  3147. tmpreg:=cg.getintregister(list,OS_32);
  3148. cg.a_load_const_reg(list,OS_32,lo(value),tmpreg);
  3149. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  3150. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADD,regdst.reglo,regsrc.reglo,tmpreg),PF_S));
  3151. end;
  3152. if is_shifter_const(hi(value),b) then
  3153. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_ADC,regdst.reghi,regsrc.reghi,hi(value)),PF_S))
  3154. else
  3155. begin
  3156. tmpreg:=cg.getintregister(list,OS_32);
  3157. cg.a_load_const_reg(list,OS_32,hi(value),tmpreg);
  3158. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADC,regdst.reghi,regsrc.reghi,tmpreg),PF_S));
  3159. end;
  3160. end;
  3161. OP_SUB:
  3162. begin
  3163. if is_shifter_const(lo(value),b) then
  3164. begin
  3165. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  3166. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_SUB,regdst.reglo,regsrc.reglo,lo(value)),PF_S))
  3167. end
  3168. else
  3169. begin
  3170. tmpreg:=cg.getintregister(list,OS_32);
  3171. cg.a_load_const_reg(list,OS_32,lo(value),tmpreg);
  3172. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  3173. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SUB,regdst.reglo,regsrc.reglo,tmpreg),PF_S));
  3174. end;
  3175. if is_shifter_const(hi(value),b) then
  3176. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_SBC,regdst.reghi,regsrc.reghi,aint(hi(value))),PF_S))
  3177. else
  3178. begin
  3179. tmpreg:=cg.getintregister(list,OS_32);
  3180. cg.a_load_const_reg(list,OS_32,hi(value),tmpreg);
  3181. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SBC,regdst.reghi,regsrc.reghi,tmpreg),PF_S));
  3182. end;
  3183. end;
  3184. else
  3185. internalerror(200502131);
  3186. end;
  3187. if size=OS_64 then
  3188. begin
  3189. { the arm has an weired opinion how flags for SUB/ADD are handled }
  3190. ovloc.loc:=LOC_FLAGS;
  3191. case op of
  3192. OP_ADD:
  3193. ovloc.resflags:=F_CS;
  3194. OP_SUB:
  3195. ovloc.resflags:=F_CC;
  3196. end;
  3197. end;
  3198. end
  3199. else
  3200. begin
  3201. case op of
  3202. OP_AND,OP_OR,OP_XOR:
  3203. begin
  3204. cg.a_op_const_reg_reg(list,op,OS_32,aint(lo(value)),regsrc.reglo,regdst.reglo);
  3205. cg.a_op_const_reg_reg(list,op,OS_32,aint(hi(value)),regsrc.reghi,regdst.reghi);
  3206. end;
  3207. OP_ADD:
  3208. begin
  3209. if is_shifter_const(aint(lo(value)),b) then
  3210. begin
  3211. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  3212. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_ADD,regdst.reglo,regsrc.reglo,aint(lo(value))),PF_S))
  3213. end
  3214. else
  3215. begin
  3216. tmpreg:=cg.getintregister(list,OS_32);
  3217. cg.a_load_const_reg(list,OS_32,aint(lo(value)),tmpreg);
  3218. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  3219. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADD,regdst.reglo,regsrc.reglo,tmpreg),PF_S));
  3220. end;
  3221. if is_shifter_const(aint(hi(value)),b) then
  3222. list.concat(taicpu.op_reg_reg_const(A_ADC,regdst.reghi,regsrc.reghi,aint(hi(value))))
  3223. else
  3224. begin
  3225. tmpreg:=cg.getintregister(list,OS_32);
  3226. cg.a_load_const_reg(list,OS_32,aint(hi(value)),tmpreg);
  3227. list.concat(taicpu.op_reg_reg_reg(A_ADC,regdst.reghi,regsrc.reghi,tmpreg));
  3228. end;
  3229. end;
  3230. OP_SUB:
  3231. begin
  3232. if is_shifter_const(aint(lo(value)),b) then
  3233. begin
  3234. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  3235. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_SUB,regdst.reglo,regsrc.reglo,aint(lo(value))),PF_S))
  3236. end
  3237. else
  3238. begin
  3239. tmpreg:=cg.getintregister(list,OS_32);
  3240. cg.a_load_const_reg(list,OS_32,aint(lo(value)),tmpreg);
  3241. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  3242. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SUB,regdst.reglo,regsrc.reglo,tmpreg),PF_S));
  3243. end;
  3244. if is_shifter_const(aint(hi(value)),b) then
  3245. list.concat(taicpu.op_reg_reg_const(A_SBC,regdst.reghi,regsrc.reghi,aint(hi(value))))
  3246. else
  3247. begin
  3248. tmpreg:=cg.getintregister(list,OS_32);
  3249. cg.a_load_const_reg(list,OS_32,hi(value),tmpreg);
  3250. list.concat(taicpu.op_reg_reg_reg(A_SBC,regdst.reghi,regsrc.reghi,tmpreg));
  3251. end;
  3252. end;
  3253. else
  3254. internalerror(2003083101);
  3255. end;
  3256. end;
  3257. end;
  3258. procedure tcg64farm.a_op64_reg_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64;setflags : boolean;var ovloc : tlocation);
  3259. begin
  3260. ovloc.loc:=LOC_VOID;
  3261. case op of
  3262. OP_NEG,
  3263. OP_NOT :
  3264. internalerror(2012022502);
  3265. end;
  3266. if (setflags or tbasecgarm(cg).cgsetflags) and (op in [OP_ADD,OP_SUB]) then
  3267. begin
  3268. case op of
  3269. OP_ADD:
  3270. begin
  3271. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  3272. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADD,regdst.reglo,regsrc1.reglo,regsrc2.reglo),PF_S));
  3273. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADC,regdst.reghi,regsrc1.reghi,regsrc2.reghi),PF_S));
  3274. end;
  3275. OP_SUB:
  3276. begin
  3277. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  3278. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SUB,regdst.reglo,regsrc2.reglo,regsrc1.reglo),PF_S));
  3279. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SBC,regdst.reghi,regsrc2.reghi,regsrc1.reghi),PF_S));
  3280. end;
  3281. else
  3282. internalerror(2003083101);
  3283. end;
  3284. if size=OS_64 then
  3285. begin
  3286. { the arm has an weired opinion how flags for SUB/ADD are handled }
  3287. ovloc.loc:=LOC_FLAGS;
  3288. case op of
  3289. OP_ADD:
  3290. ovloc.resflags:=F_CS;
  3291. OP_SUB:
  3292. ovloc.resflags:=F_CC;
  3293. end;
  3294. end;
  3295. end
  3296. else
  3297. begin
  3298. case op of
  3299. OP_AND,OP_OR,OP_XOR:
  3300. begin
  3301. cg.a_op_reg_reg_reg(list,op,OS_32,regsrc1.reglo,regsrc2.reglo,regdst.reglo);
  3302. cg.a_op_reg_reg_reg(list,op,OS_32,regsrc1.reghi,regsrc2.reghi,regdst.reghi);
  3303. end;
  3304. OP_ADD:
  3305. begin
  3306. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  3307. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ADD,regdst.reglo,regsrc1.reglo,regsrc2.reglo),PF_S));
  3308. list.concat(taicpu.op_reg_reg_reg(A_ADC,regdst.reghi,regsrc1.reghi,regsrc2.reghi));
  3309. cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
  3310. end;
  3311. OP_SUB:
  3312. begin
  3313. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  3314. list.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SUB,regdst.reglo,regsrc2.reglo,regsrc1.reglo),PF_S));
  3315. list.concat(taicpu.op_reg_reg_reg(A_SBC,regdst.reghi,regsrc2.reghi,regsrc1.reghi));
  3316. cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
  3317. end;
  3318. else
  3319. internalerror(2003083101);
  3320. end;
  3321. end;
  3322. end;
  3323. procedure tthumbcgarm.init_register_allocators;
  3324. begin
  3325. inherited init_register_allocators;
  3326. if assigned(current_procinfo) and (current_procinfo.framepointer=NR_R7) then
  3327. rg[R_INTREGISTER]:=trgintcputhumb.create(R_INTREGISTER,R_SUBWHOLE,
  3328. [RS_R0,RS_R1,RS_R2,RS_R3,RS_R4,RS_R5,RS_R6],first_int_imreg,[])
  3329. else
  3330. rg[R_INTREGISTER]:=trgintcputhumb.create(R_INTREGISTER,R_SUBWHOLE,
  3331. [RS_R0,RS_R1,RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7],first_int_imreg,[]);
  3332. end;
  3333. procedure tthumbcgarm.done_register_allocators;
  3334. begin
  3335. rg[R_INTREGISTER].free;
  3336. rg[R_FPUREGISTER].free;
  3337. rg[R_MMREGISTER].free;
  3338. inherited done_register_allocators;
  3339. end;
  3340. procedure tthumbcgarm.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
  3341. var
  3342. ref : treference;
  3343. shift : byte;
  3344. r : byte;
  3345. regs, saveregs : tcpuregisterset;
  3346. r7offset,
  3347. stackmisalignment : pint;
  3348. postfix: toppostfix;
  3349. registerarea,
  3350. imm1, imm2: DWord;
  3351. stack_parameters: Boolean;
  3352. begin
  3353. stack_parameters:=current_procinfo.procdef.stack_tainting_parameter(calleeside);
  3354. LocalSize:=align(LocalSize,4);
  3355. { call instruction does not put anything on the stack }
  3356. stackmisalignment:=0;
  3357. if not(nostackframe) then
  3358. begin
  3359. a_reg_alloc(list,NR_STACK_POINTER_REG);
  3360. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  3361. a_reg_alloc(list,NR_FRAME_POINTER_REG);
  3362. { save int registers }
  3363. reference_reset(ref,4);
  3364. ref.index:=NR_STACK_POINTER_REG;
  3365. ref.addressmode:=AM_PREINDEXED;
  3366. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  3367. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  3368. begin
  3369. //!!!! a_reg_alloc(list,NR_R12);
  3370. //!!!! list.concat(taicpu.op_reg_reg(A_MOV,NR_R12,NR_STACK_POINTER_REG));
  3371. end;
  3372. { the (old) ARM APCS requires saving both the stack pointer (to
  3373. crawl the stack) and the PC (to identify the function this
  3374. stack frame belongs to) -> also save R12 (= copy of R13 on entry)
  3375. and R15 -- still needs updating for EABI and Darwin, they don't
  3376. need that }
  3377. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  3378. regs:=regs+[RS_R7,RS_R14]
  3379. else
  3380. // if (regs<>[]) or (pi_do_call in current_procinfo.flags) then
  3381. include(regs,RS_R14);
  3382. { safely estimate stack size }
  3383. if localsize+current_settings.alignment.localalignmax+4>508 then
  3384. begin
  3385. include(rg[R_INTREGISTER].used_in_proc,RS_R4);
  3386. include(regs,RS_R4);
  3387. end;
  3388. registerarea:=0;
  3389. if regs<>[] then
  3390. begin
  3391. for r:=RS_R0 to RS_R15 do
  3392. if r in regs then
  3393. inc(registerarea,4);
  3394. list.concat(taicpu.op_regset(A_PUSH,R_INTREGISTER,R_SUBWHOLE,regs));
  3395. end;
  3396. stackmisalignment:=registerarea mod current_settings.alignment.localalignmax;
  3397. if stack_parameters or (LocalSize<>0) or
  3398. ((stackmisalignment<>0) and
  3399. ((pi_do_call in current_procinfo.flags) or
  3400. (po_assembler in current_procinfo.procdef.procoptions))) then
  3401. begin
  3402. { do we access stack parameters?
  3403. if yes, the previously estimated stacksize must be used }
  3404. if stack_parameters then
  3405. begin
  3406. if localsize>tarmprocinfo(current_procinfo).stackframesize then
  3407. begin
  3408. writeln(localsize);
  3409. writeln(tarmprocinfo(current_procinfo).stackframesize);
  3410. internalerror(2013040601);
  3411. end
  3412. else
  3413. localsize:=tarmprocinfo(current_procinfo).stackframesize-registerarea;
  3414. end
  3415. else
  3416. localsize:=align(localsize+stackmisalignment,current_settings.alignment.localalignmax)-stackmisalignment;
  3417. if localsize<508 then
  3418. begin
  3419. list.concat(taicpu.op_reg_reg_const(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,LocalSize));
  3420. end
  3421. else if localsize<=1016 then
  3422. begin
  3423. list.concat(taicpu.op_reg_reg_const(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,508));
  3424. list.concat(taicpu.op_reg_reg_const(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,LocalSize-508));
  3425. end
  3426. else
  3427. begin
  3428. a_load_const_reg(list,OS_ADDR,-localsize,NR_R4);
  3429. list.concat(taicpu.op_reg_reg_reg(A_ADD,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,NR_R4));
  3430. include(regs,RS_R4);
  3431. //!!!! if current_procinfo.framepointer=NR_STACK_POINTER_REG then
  3432. //!!!! a_reg_alloc(list,NR_R12);
  3433. //!!!! a_load_const_reg(list,OS_ADDR,LocalSize,NR_R12);
  3434. //!!!! list.concat(taicpu.op_reg_reg_reg(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,NR_R12));
  3435. //!!!! a_reg_dealloc(list,NR_R12);
  3436. end;
  3437. end;
  3438. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  3439. begin
  3440. list.concat(taicpu.op_reg_reg_const(A_ADD,current_procinfo.framepointer,NR_STACK_POINTER_REG,0));
  3441. end;
  3442. end;
  3443. end;
  3444. procedure tthumbcgarm.g_proc_exit(list: TAsmList; parasize: longint; nostackframe: boolean);
  3445. var
  3446. ref : treference;
  3447. LocalSize : longint;
  3448. r,
  3449. shift : byte;
  3450. saveregs,
  3451. regs : tcpuregisterset;
  3452. registerarea : DWord;
  3453. stackmisalignment: pint;
  3454. imm1, imm2: DWord;
  3455. stack_parameters : Boolean;
  3456. begin
  3457. if not(nostackframe) then
  3458. begin
  3459. stack_parameters:=current_procinfo.procdef.stack_tainting_parameter(calleeside);
  3460. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  3461. include(regs,RS_R15);
  3462. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  3463. include(regs,getsupreg(current_procinfo.framepointer));
  3464. registerarea:=0;
  3465. for r:=RS_R0 to RS_R15 do
  3466. if r in regs then
  3467. inc(registerarea,4);
  3468. stackmisalignment:=registerarea mod current_settings.alignment.localalignmax;
  3469. LocalSize:=current_procinfo.calc_stackframe_size;
  3470. if stack_parameters then
  3471. localsize:=tarmprocinfo(current_procinfo).stackframesize-registerarea
  3472. else
  3473. localsize:=align(localsize+stackmisalignment,current_settings.alignment.localalignmax)-stackmisalignment;
  3474. if (current_procinfo.framepointer=NR_STACK_POINTER_REG) or
  3475. (target_info.system in systems_darwin) then
  3476. begin
  3477. if (LocalSize<>0) or
  3478. ((stackmisalignment<>0) and
  3479. ((pi_do_call in current_procinfo.flags) or
  3480. (po_assembler in current_procinfo.procdef.procoptions))) then
  3481. begin
  3482. if LocalSize=0 then
  3483. else if LocalSize<=508 then
  3484. list.concat(taicpu.op_reg_reg_const(A_ADD,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,LocalSize))
  3485. else if LocalSize<=1016 then
  3486. begin
  3487. list.concat(taicpu.op_reg_reg_const(A_ADD,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,508));
  3488. list.concat(taicpu.op_reg_reg_const(A_ADD,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,localsize-508));
  3489. end
  3490. else
  3491. begin
  3492. a_reg_alloc(list,NR_R3);
  3493. a_load_const_reg(list,OS_ADDR,LocalSize,NR_R3);
  3494. list.concat(taicpu.op_reg_reg_reg(A_ADD,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,NR_R3));
  3495. a_reg_dealloc(list,NR_R3);
  3496. end;
  3497. end;
  3498. if regs=[] then
  3499. begin
  3500. if not(CPUARM_HAS_BX in cpu_capabilities[current_settings.cputype]) then
  3501. list.concat(taicpu.op_reg_reg(A_MOV,NR_PC,NR_R14))
  3502. else
  3503. list.concat(taicpu.op_reg(A_BX,NR_R14))
  3504. end
  3505. else
  3506. list.concat(taicpu.op_regset(A_POP,R_INTREGISTER,R_SUBWHOLE,regs));
  3507. end;
  3508. end
  3509. else if not(CPUARM_HAS_BX in cpu_capabilities[current_settings.cputype]) then
  3510. list.concat(taicpu.op_reg_reg(A_MOV,NR_PC,NR_R14))
  3511. else
  3512. list.concat(taicpu.op_reg(A_BX,NR_R14))
  3513. end;
  3514. procedure tthumbcgarm.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);
  3515. var
  3516. oppostfix:toppostfix;
  3517. usedtmpref: treference;
  3518. tmpreg,tmpreg2 : tregister;
  3519. dir : integer;
  3520. begin
  3521. if (TCGSize2Size[FromSize] >= TCGSize2Size[ToSize]) then
  3522. FromSize := ToSize;
  3523. case FromSize of
  3524. { signed integer registers }
  3525. OS_8:
  3526. oppostfix:=PF_B;
  3527. OS_S8:
  3528. oppostfix:=PF_SB;
  3529. OS_16:
  3530. oppostfix:=PF_H;
  3531. OS_S16:
  3532. oppostfix:=PF_SH;
  3533. OS_32,
  3534. OS_S32:
  3535. oppostfix:=PF_None;
  3536. else
  3537. InternalError(200308298);
  3538. end;
  3539. if (ref.alignment in [1,2]) and (ref.alignment<tcgsize2size[fromsize]) then
  3540. begin
  3541. if target_info.endian=endian_big then
  3542. dir:=-1
  3543. else
  3544. dir:=1;
  3545. case FromSize of
  3546. OS_16,OS_S16:
  3547. begin
  3548. { only complicated references need an extra loadaddr }
  3549. if assigned(ref.symbol) or
  3550. (ref.index<>NR_NO) or
  3551. (ref.offset<-124) or
  3552. (ref.offset>124) or
  3553. { sometimes the compiler reused registers }
  3554. (reg=ref.index) or
  3555. (reg=ref.base) then
  3556. begin
  3557. tmpreg2:=getintregister(list,OS_INT);
  3558. a_loadaddr_ref_reg(list,ref,tmpreg2);
  3559. reference_reset_base(usedtmpref,tmpreg2,0,ref.alignment);
  3560. end
  3561. else
  3562. usedtmpref:=ref;
  3563. if target_info.endian=endian_big then
  3564. inc(usedtmpref.offset,1);
  3565. tmpreg:=getintregister(list,OS_INT);
  3566. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,reg);
  3567. inc(usedtmpref.offset,dir);
  3568. if FromSize=OS_16 then
  3569. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg)
  3570. else
  3571. a_internal_load_ref_reg(list,OS_S8,OS_S8,usedtmpref,tmpreg);
  3572. list.concat(taicpu.op_reg_const(A_LSL,tmpreg,8));
  3573. list.concat(taicpu.op_reg_reg(A_ORR,reg,tmpreg));
  3574. end;
  3575. OS_32,OS_S32:
  3576. begin
  3577. tmpreg:=getintregister(list,OS_INT);
  3578. { only complicated references need an extra loadaddr }
  3579. if assigned(ref.symbol) or
  3580. (ref.index<>NR_NO) or
  3581. (ref.offset<-124) or
  3582. (ref.offset>124) or
  3583. { sometimes the compiler reused registers }
  3584. (reg=ref.index) or
  3585. (reg=ref.base) then
  3586. begin
  3587. tmpreg2:=getintregister(list,OS_INT);
  3588. a_loadaddr_ref_reg(list,ref,tmpreg2);
  3589. reference_reset_base(usedtmpref,tmpreg2,0,ref.alignment);
  3590. end
  3591. else
  3592. usedtmpref:=ref;
  3593. if ref.alignment=2 then
  3594. begin
  3595. if target_info.endian=endian_big then
  3596. inc(usedtmpref.offset,2);
  3597. a_internal_load_ref_reg(list,OS_16,OS_16,usedtmpref,reg);
  3598. inc(usedtmpref.offset,dir*2);
  3599. a_internal_load_ref_reg(list,OS_16,OS_16,usedtmpref,tmpreg);
  3600. list.concat(taicpu.op_reg_const(A_LSL,tmpreg,16));
  3601. list.concat(taicpu.op_reg_reg(A_ORR,reg,tmpreg));
  3602. end
  3603. else
  3604. begin
  3605. if target_info.endian=endian_big then
  3606. inc(usedtmpref.offset,3);
  3607. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,reg);
  3608. inc(usedtmpref.offset,dir);
  3609. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
  3610. list.concat(taicpu.op_reg_const(A_LSL,tmpreg,8));
  3611. list.concat(taicpu.op_reg_reg(A_ORR,reg,tmpreg));
  3612. inc(usedtmpref.offset,dir);
  3613. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
  3614. list.concat(taicpu.op_reg_const(A_LSL,tmpreg,16));
  3615. list.concat(taicpu.op_reg_reg(A_ORR,reg,tmpreg));
  3616. inc(usedtmpref.offset,dir);
  3617. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
  3618. list.concat(taicpu.op_reg_const(A_LSL,tmpreg,24));
  3619. list.concat(taicpu.op_reg_reg(A_ORR,reg,tmpreg));
  3620. end;
  3621. end
  3622. else
  3623. handle_load_store(list,A_LDR,oppostfix,reg,ref);
  3624. end;
  3625. end
  3626. else
  3627. handle_load_store(list,A_LDR,oppostfix,reg,ref);
  3628. if (fromsize=OS_S8) and (tosize = OS_16) then
  3629. a_load_reg_reg(list,OS_16,OS_32,reg,reg);
  3630. end;
  3631. procedure tthumbcgarm.a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);
  3632. var
  3633. imm_shift : byte;
  3634. l : tasmlabel;
  3635. hr : treference;
  3636. begin
  3637. if not(size in [OS_8,OS_S8,OS_16,OS_S16,OS_32,OS_S32]) then
  3638. internalerror(2002090902);
  3639. if is_thumb_imm(a) then
  3640. list.concat(taicpu.op_reg_const(A_MOV,reg,a))
  3641. else
  3642. begin
  3643. reference_reset(hr,4);
  3644. current_asmdata.getjumplabel(l);
  3645. cg.a_label(current_procinfo.aktlocaldata,l);
  3646. hr.symboldata:=current_procinfo.aktlocaldata.last;
  3647. current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(longint(a)));
  3648. hr.symbol:=l;
  3649. hr.base:=NR_PC;
  3650. list.concat(taicpu.op_reg_ref(A_LDR,reg,hr));
  3651. end;
  3652. end;
  3653. procedure tthumbcgarm.g_adjust_self_value(list:TAsmList;procdef: tprocdef;ioffset: tcgint);
  3654. var
  3655. hsym : tsym;
  3656. href,
  3657. tmpref : treference;
  3658. paraloc : Pcgparalocation;
  3659. l : TAsmLabel;
  3660. begin
  3661. { calculate the parameter info for the procdef }
  3662. procdef.init_paraloc_info(callerside);
  3663. hsym:=tsym(procdef.parast.Find('self'));
  3664. if not(assigned(hsym) and
  3665. (hsym.typ=paravarsym)) then
  3666. internalerror(200305251);
  3667. paraloc:=tparavarsym(hsym).paraloc[callerside].location;
  3668. while paraloc<>nil do
  3669. with paraloc^ do
  3670. begin
  3671. case loc of
  3672. LOC_REGISTER:
  3673. begin
  3674. if is_thumb_imm(ioffset) then
  3675. a_op_const_reg(list,OP_SUB,size,ioffset,register)
  3676. else
  3677. begin
  3678. list.concat(taicpu.op_regset(A_PUSH,R_INTREGISTER,R_SUBWHOLE,[RS_R4]));
  3679. reference_reset(tmpref,4);
  3680. current_asmdata.getjumplabel(l);
  3681. current_procinfo.aktlocaldata.Concat(tai_align.Create(4));
  3682. cg.a_label(current_procinfo.aktlocaldata,l);
  3683. tmpref.symboldata:=current_procinfo.aktlocaldata.last;
  3684. current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(ioffset));
  3685. tmpref.symbol:=l;
  3686. tmpref.base:=NR_PC;
  3687. list.concat(taicpu.op_reg_ref(A_LDR,NR_R4,tmpref));
  3688. a_op_reg_reg(list,OP_SUB,size,NR_R4,register);
  3689. list.concat(taicpu.op_regset(A_POP,R_INTREGISTER,R_SUBWHOLE,[RS_R4]));
  3690. end;
  3691. end;
  3692. LOC_REFERENCE:
  3693. begin
  3694. { offset in the wrapper needs to be adjusted for the stored
  3695. return address }
  3696. reference_reset_base(href,reference.index,reference.offset+sizeof(aint),sizeof(pint));
  3697. if is_thumb_imm(ioffset) then
  3698. a_op_const_ref(list,OP_SUB,size,ioffset,href)
  3699. else
  3700. begin
  3701. list.concat(taicpu.op_regset(A_PUSH,R_INTREGISTER,R_SUBWHOLE,[RS_R4]));
  3702. reference_reset(tmpref,4);
  3703. current_asmdata.getjumplabel(l);
  3704. current_procinfo.aktlocaldata.Concat(tai_align.Create(4));
  3705. cg.a_label(current_procinfo.aktlocaldata,l);
  3706. tmpref.symboldata:=current_procinfo.aktlocaldata.last;
  3707. current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(ioffset));
  3708. tmpref.symbol:=l;
  3709. tmpref.base:=NR_PC;
  3710. list.concat(taicpu.op_reg_ref(A_LDR,NR_R4,tmpref));
  3711. a_op_reg_ref(list,OP_SUB,size,NR_R4,href);
  3712. list.concat(taicpu.op_regset(A_POP,R_INTREGISTER,R_SUBWHOLE,[RS_R4]));
  3713. end;
  3714. end
  3715. else
  3716. internalerror(200309189);
  3717. end;
  3718. paraloc:=next;
  3719. end;
  3720. end;
  3721. function tthumbcgarm.handle_load_store(list: TAsmList; op: tasmop; oppostfix: toppostfix; reg: tregister; ref: treference): treference;
  3722. var
  3723. href : treference;
  3724. tmpreg : TRegister;
  3725. begin
  3726. href:=ref;
  3727. if { LDR/STR limitations }
  3728. (
  3729. (((op=A_LDR) and (oppostfix=PF_None)) or
  3730. ((op=A_STR) and (oppostfix=PF_None))) and
  3731. (ref.base<>NR_STACK_POINTER_REG) and
  3732. (abs(ref.offset)>124)
  3733. ) or
  3734. { LDRB/STRB limitations }
  3735. (
  3736. (((op=A_LDR) and (oppostfix=PF_B)) or
  3737. ((op=A_LDRB) and (oppostfix=PF_None)) or
  3738. ((op=A_STR) and (oppostfix=PF_B)) or
  3739. ((op=A_STRB) and (oppostfix=PF_None))) and
  3740. ((ref.base=NR_STACK_POINTER_REG) or
  3741. (ref.index=NR_STACK_POINTER_REG) or
  3742. (abs(ref.offset)>31)
  3743. )
  3744. ) or
  3745. { LDRH/STRH limitations }
  3746. (
  3747. (((op=A_LDR) and (oppostfix=PF_H)) or
  3748. ((op=A_LDRH) and (oppostfix=PF_None)) or
  3749. ((op=A_STR) and (oppostfix=PF_H)) or
  3750. ((op=A_STRH) and (oppostfix=PF_None))) and
  3751. ((ref.base=NR_STACK_POINTER_REG) or
  3752. (ref.index=NR_STACK_POINTER_REG) or
  3753. (abs(ref.offset)>62) or
  3754. ((abs(ref.offset) mod 2)<>0)
  3755. )
  3756. ) then
  3757. begin
  3758. tmpreg:=getintregister(list,OS_ADDR);
  3759. a_loadaddr_ref_reg(list,ref,tmpreg);
  3760. reference_reset_base(href,tmpreg,0,ref.alignment);
  3761. end
  3762. else if (op=A_LDR) and
  3763. (oppostfix in [PF_None]) and
  3764. (ref.base=NR_STACK_POINTER_REG) and
  3765. (abs(ref.offset)>1020) then
  3766. begin
  3767. tmpreg:=getintregister(list,OS_ADDR);
  3768. a_loadaddr_ref_reg(list,ref,tmpreg);
  3769. reference_reset_base(href,tmpreg,0,ref.alignment);
  3770. end
  3771. else if (op=A_LDR) and
  3772. ((oppostfix in [PF_SH,PF_SB]) or
  3773. (abs(ref.offset)>124)) then
  3774. begin
  3775. tmpreg:=getintregister(list,OS_ADDR);
  3776. a_loadaddr_ref_reg(list,ref,tmpreg);
  3777. reference_reset_base(href,tmpreg,0,ref.alignment);
  3778. end;
  3779. Result:=inherited handle_load_store(list, op, oppostfix, reg, href);
  3780. end;
  3781. procedure tthumbcgarm.a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister);
  3782. var
  3783. tmpreg,overflowreg : tregister;
  3784. asmop : tasmop;
  3785. begin
  3786. case op of
  3787. OP_NEG:
  3788. list.concat(taicpu.op_reg_reg(A_NEG,dst,src));
  3789. OP_NOT:
  3790. list.concat(taicpu.op_reg_reg(A_MVN,dst,src));
  3791. OP_DIV,OP_IDIV:
  3792. internalerror(200308284);
  3793. OP_ROL:
  3794. begin
  3795. if not(size in [OS_32,OS_S32]) then
  3796. internalerror(2008072801);
  3797. { simulate ROL by ror'ing 32-value }
  3798. tmpreg:=getintregister(list,OS_32);
  3799. a_load_const_reg(list,OS_32,32,tmpreg);
  3800. list.concat(taicpu.op_reg_reg(A_SUB,tmpreg,src));
  3801. list.concat(taicpu.op_reg_reg(A_ROR,dst,src));
  3802. end;
  3803. else
  3804. begin
  3805. a_reg_alloc(list,NR_DEFAULTFLAGS);
  3806. list.concat(setoppostfix(
  3807. taicpu.op_reg_reg(op_reg_opcg2asmop[op],dst,src),op_reg_postfix[op]));
  3808. end;
  3809. end;
  3810. maybeadjustresult(list,op,size,dst);
  3811. end;
  3812. procedure tthumbcgarm.a_op_const_reg(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; dst: tregister);
  3813. var
  3814. tmpreg : tregister;
  3815. so : tshifterop;
  3816. l1 : longint;
  3817. imm1, imm2: DWord;
  3818. begin
  3819. //!!! ovloc.loc:=LOC_VOID;
  3820. if {$ifopt R+}(a<>-2147483648) and{$endif} {!!!!!! not setflags and } is_thumb_imm(-a) then
  3821. case op of
  3822. OP_ADD:
  3823. begin
  3824. op:=OP_SUB;
  3825. a:=aint(dword(-a));
  3826. end;
  3827. OP_SUB:
  3828. begin
  3829. op:=OP_ADD;
  3830. a:=aint(dword(-a));
  3831. end
  3832. end;
  3833. if is_thumb_imm(a) and (op in [OP_ADD,OP_SUB]) then
  3834. begin
  3835. // if cgsetflags or setflags then
  3836. a_reg_alloc(list,NR_DEFAULTFLAGS);
  3837. list.concat(setoppostfix(
  3838. taicpu.op_reg_const(op_reg_opcg2asmop[op],dst,a),op_reg_postfix[op]));
  3839. if (cgsetflags {!!! or setflags }) and (size in [OS_8,OS_16,OS_32]) then
  3840. begin
  3841. //!!! ovloc.loc:=LOC_FLAGS;
  3842. case op of
  3843. OP_ADD:
  3844. //!!! ovloc.resflags:=F_CS;
  3845. ;
  3846. OP_SUB:
  3847. //!!! ovloc.resflags:=F_CC;
  3848. ;
  3849. end;
  3850. end;
  3851. end
  3852. else
  3853. begin
  3854. { there could be added some more sophisticated optimizations }
  3855. if (op in [OP_MUL,OP_IMUL,OP_DIV,OP_IDIV]) and (a=1) then
  3856. a_load_reg_reg(list,size,size,dst,dst)
  3857. else if (op in [OP_MUL,OP_IMUL]) and (a=0) then
  3858. a_load_const_reg(list,size,0,dst)
  3859. else if (op in [OP_IMUL,OP_IDIV]) and (a=-1) then
  3860. a_op_reg_reg(list,OP_NEG,size,dst,dst)
  3861. { we do this here instead in the peephole optimizer because
  3862. it saves us a register }
  3863. {$ifdef DUMMY}
  3864. else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a,l1) and not(cgsetflags or setflags) then
  3865. a_op_const_reg_reg(list,OP_SHL,size,l1,dst,dst)
  3866. { for example : b=a*5 -> b=a*4+a with add instruction and shl }
  3867. else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a-1,l1) and not(cgsetflags or setflags) then
  3868. begin
  3869. if l1>32 then{roozbeh does this ever happen?}
  3870. internalerror(200308296);
  3871. shifterop_reset(so);
  3872. so.shiftmode:=SM_LSL;
  3873. so.shiftimm:=l1;
  3874. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,dst,dst,dst,so));
  3875. end
  3876. { for example : b=a*7 -> b=a*8-a with rsb instruction and shl }
  3877. else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a+1,l1) and not(cgsetflags or setflags) then
  3878. begin
  3879. if l1>32 then{does this ever happen?}
  3880. internalerror(201205181);
  3881. shifterop_reset(so);
  3882. so.shiftmode:=SM_LSL;
  3883. so.shiftimm:=l1;
  3884. list.concat(taicpu.op_reg_reg_reg_shifterop(A_RSB,dst,dst,dst,so));
  3885. end
  3886. else if (op in [OP_MUL,OP_IMUL]) and not(cgsetflags or setflags) and try_optimized_mul32_const_reg_reg(list,a,dst,dst) then
  3887. begin
  3888. { nothing to do on success }
  3889. end
  3890. {$endif DUMMY}
  3891. { x := y and 0; just clears a register, this sometimes gets generated on 64bit ops.
  3892. Just using mov x, #0 might allow some easier optimizations down the line. }
  3893. else if (op = OP_AND) and (dword(a)=0) then
  3894. list.concat(taicpu.op_reg_const(A_MOV,dst,0))
  3895. { x := y AND $FFFFFFFF just copies the register, so use mov for better optimizations }
  3896. else if (op = OP_AND) and (not(dword(a))=0) then
  3897. // do nothing
  3898. { BIC clears the specified bits, while AND keeps them, using BIC allows to use a
  3899. broader range of shifterconstants.}
  3900. {$ifdef DUMMY}
  3901. else if (op = OP_AND) and is_shifter_const(not(dword(a)),shift) then
  3902. list.concat(taicpu.op_reg_reg_const(A_BIC,dst,dst,not(dword(a))))
  3903. else if (op = OP_AND) and split_into_shifter_const(not(dword(a)), imm1, imm2) then
  3904. begin
  3905. list.concat(taicpu.op_reg_reg_const(A_BIC,dst,dst,imm1));
  3906. list.concat(taicpu.op_reg_reg_const(A_BIC,dst,dst,imm2));
  3907. end
  3908. else if (op in [OP_ADD, OP_SUB, OP_OR]) and
  3909. not(cgsetflags or setflags) and
  3910. split_into_shifter_const(a, imm1, imm2) then
  3911. begin
  3912. list.concat(taicpu.op_reg_reg_const(op_reg_reg_opcg2asmop[op],dst,dst,imm1));
  3913. list.concat(taicpu.op_reg_reg_const(op_reg_reg_opcg2asmop[op],dst,dst,imm2));
  3914. end
  3915. {$endif DUMMY}
  3916. else if (op in [OP_SHL, OP_SHR, OP_SAR]) then
  3917. begin
  3918. list.concat(taicpu.op_reg_reg_const(op_reg_opcg2asmop[op],dst,dst,a));
  3919. end
  3920. else
  3921. begin
  3922. tmpreg:=getintregister(list,size);
  3923. a_load_const_reg(list,size,a,tmpreg);
  3924. a_op_reg_reg(list,op,size,tmpreg,dst);
  3925. end;
  3926. end;
  3927. maybeadjustresult(list,op,size,dst);
  3928. end;
  3929. procedure tthumbcgarm.a_op_const_reg_reg(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister);
  3930. begin
  3931. if (op=OP_ADD) and (src=NR_R13) and (dst<>NR_R13) and ((a mod 4)=0) and (a>0) and (a<=1020) then
  3932. list.concat(taicpu.op_reg_reg_const(A_ADD,dst,src,a))
  3933. else
  3934. inherited a_op_const_reg_reg(list,op,size,a,src,dst);
  3935. end;
  3936. procedure tthumbcgarm.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
  3937. var
  3938. l1,l2 : tasmlabel;
  3939. ai : taicpu;
  3940. begin
  3941. current_asmdata.getjumplabel(l1);
  3942. current_asmdata.getjumplabel(l2);
  3943. ai:=setcondition(taicpu.op_sym(A_B,l1),flags_to_cond(f));
  3944. ai.is_jmp:=true;
  3945. list.concat(ai);
  3946. list.concat(taicpu.op_reg_const(A_MOV,reg,0));
  3947. list.concat(taicpu.op_sym(A_B,l2));
  3948. cg.a_label(list,l1);
  3949. list.concat(taicpu.op_reg_const(A_MOV,reg,1));
  3950. a_reg_dealloc(list,NR_DEFAULTFLAGS);
  3951. cg.a_label(list,l2);
  3952. end;
  3953. procedure tthumbcgarm.g_external_wrapper(list: TAsmList; procdef: tprocdef; const externalname: string);
  3954. var
  3955. tmpref : treference;
  3956. l : tasmlabel;
  3957. begin
  3958. { there is no branch instruction on thumb which allows big distances and which leaves LR as it is
  3959. and which allows to switch the instruction set }
  3960. { create const entry }
  3961. reference_reset(tmpref,4);
  3962. current_asmdata.getjumplabel(l);
  3963. tmpref.symbol:=l;
  3964. tmpref.base:=NR_PC;
  3965. list.concat(taicpu.op_regset(A_PUSH,R_INTREGISTER,R_SUBWHOLE,[RS_R0]));
  3966. list.concat(taicpu.op_reg_ref(A_LDR,NR_R0,tmpref));
  3967. list.concat(taicpu.op_reg_reg(A_MOV,NR_R12,NR_R0));
  3968. list.concat(taicpu.op_regset(A_POP,R_INTREGISTER,R_SUBWHOLE,[RS_R0]));
  3969. list.concat(taicpu.op_reg(A_BX,NR_R12));
  3970. { append const entry }
  3971. list.Concat(tai_align.Create(4));
  3972. list.Concat(tai_label.create(l));
  3973. list.concat(tai_const.Create_sym(current_asmdata.RefAsmSymbol(externalname)));
  3974. end;
  3975. procedure tthumb2cgarm.init_register_allocators;
  3976. begin
  3977. inherited init_register_allocators;
  3978. { currently, we save R14 always, so we can use it }
  3979. if (target_info.system<>system_arm_darwin) then
  3980. rg[R_INTREGISTER]:=trgintcputhumb2.create(R_INTREGISTER,R_SUBWHOLE,
  3981. [RS_R0,RS_R1,RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
  3982. RS_R9,RS_R10,RS_R12,RS_R14],first_int_imreg,[])
  3983. else
  3984. { r9 is not available on Darwin according to the llvm code generator }
  3985. rg[R_INTREGISTER]:=trgintcputhumb2.create(R_INTREGISTER,R_SUBWHOLE,
  3986. [RS_R0,RS_R1,RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
  3987. RS_R10,RS_R12,RS_R14],first_int_imreg,[]);
  3988. rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE,
  3989. [RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7],first_fpu_imreg,[]);
  3990. if current_settings.fputype in [fpu_fpv4_s16,fpu_vfpv3_d16] then
  3991. rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBFD,
  3992. [RS_D0,RS_D1,RS_D2,RS_D3,RS_D4,RS_D5,RS_D6,RS_D7,
  3993. RS_D8,RS_D9,RS_D10,RS_D11,RS_D12,RS_D13,RS_D14,RS_D15
  3994. ],first_mm_imreg,[])
  3995. else
  3996. rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBNONE,
  3997. [RS_S0,RS_S1,RS_R2,RS_R3,RS_R4,RS_S31],first_mm_imreg,[]);
  3998. end;
  3999. procedure tthumb2cgarm.done_register_allocators;
  4000. begin
  4001. rg[R_INTREGISTER].free;
  4002. rg[R_FPUREGISTER].free;
  4003. rg[R_MMREGISTER].free;
  4004. inherited done_register_allocators;
  4005. end;
  4006. procedure tthumb2cgarm.a_call_reg(list : TAsmList;reg: tregister);
  4007. begin
  4008. list.concat(taicpu.op_reg(A_BLX, reg));
  4009. {
  4010. the compiler does not properly set this flag anymore in pass 1, and
  4011. for now we only need it after pass 2 (I hope) (JM)
  4012. if not(pi_do_call in current_procinfo.flags) then
  4013. internalerror(2003060703);
  4014. }
  4015. include(current_procinfo.flags,pi_do_call);
  4016. end;
  4017. procedure tthumb2cgarm.a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);
  4018. var
  4019. imm_shift : byte;
  4020. l : tasmlabel;
  4021. hr : treference;
  4022. begin
  4023. if not(size in [OS_8,OS_S8,OS_16,OS_S16,OS_32,OS_S32]) then
  4024. internalerror(2002090902);
  4025. if is_thumb32_imm(a) then
  4026. list.concat(taicpu.op_reg_const(A_MOV,reg,a))
  4027. else if is_thumb32_imm(not(a)) then
  4028. list.concat(taicpu.op_reg_const(A_MVN,reg,not(a)))
  4029. else if (a and $FFFF)=a then
  4030. list.concat(taicpu.op_reg_const(A_MOVW,reg,a))
  4031. else
  4032. begin
  4033. reference_reset(hr,4);
  4034. current_asmdata.getjumplabel(l);
  4035. cg.a_label(current_procinfo.aktlocaldata,l);
  4036. hr.symboldata:=current_procinfo.aktlocaldata.last;
  4037. current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(longint(a)));
  4038. hr.symbol:=l;
  4039. hr.base:=NR_PC;
  4040. list.concat(taicpu.op_reg_ref(A_LDR,reg,hr));
  4041. end;
  4042. end;
  4043. procedure tthumb2cgarm.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);
  4044. var
  4045. oppostfix:toppostfix;
  4046. usedtmpref: treference;
  4047. tmpreg,tmpreg2 : tregister;
  4048. so : tshifterop;
  4049. dir : integer;
  4050. begin
  4051. if (TCGSize2Size[FromSize] >= TCGSize2Size[ToSize]) then
  4052. FromSize := ToSize;
  4053. case FromSize of
  4054. { signed integer registers }
  4055. OS_8:
  4056. oppostfix:=PF_B;
  4057. OS_S8:
  4058. oppostfix:=PF_SB;
  4059. OS_16:
  4060. oppostfix:=PF_H;
  4061. OS_S16:
  4062. oppostfix:=PF_SH;
  4063. OS_32,
  4064. OS_S32:
  4065. oppostfix:=PF_None;
  4066. else
  4067. InternalError(200308299);
  4068. end;
  4069. if (ref.alignment in [1,2]) and (ref.alignment<tcgsize2size[fromsize]) then
  4070. begin
  4071. if target_info.endian=endian_big then
  4072. dir:=-1
  4073. else
  4074. dir:=1;
  4075. case FromSize of
  4076. OS_16,OS_S16:
  4077. begin
  4078. { only complicated references need an extra loadaddr }
  4079. if assigned(ref.symbol) or
  4080. (ref.index<>NR_NO) or
  4081. (ref.offset<-255) or
  4082. (ref.offset>4094) or
  4083. { sometimes the compiler reused registers }
  4084. (reg=ref.index) or
  4085. (reg=ref.base) then
  4086. begin
  4087. tmpreg2:=getintregister(list,OS_INT);
  4088. a_loadaddr_ref_reg(list,ref,tmpreg2);
  4089. reference_reset_base(usedtmpref,tmpreg2,0,ref.alignment);
  4090. end
  4091. else
  4092. usedtmpref:=ref;
  4093. if target_info.endian=endian_big then
  4094. inc(usedtmpref.offset,1);
  4095. shifterop_reset(so);so.shiftmode:=SM_LSL;so.shiftimm:=8;
  4096. tmpreg:=getintregister(list,OS_INT);
  4097. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,reg);
  4098. inc(usedtmpref.offset,dir);
  4099. if FromSize=OS_16 then
  4100. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg)
  4101. else
  4102. a_internal_load_ref_reg(list,OS_S8,OS_S8,usedtmpref,tmpreg);
  4103. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,reg,tmpreg,so));
  4104. end;
  4105. OS_32,OS_S32:
  4106. begin
  4107. tmpreg:=getintregister(list,OS_INT);
  4108. { only complicated references need an extra loadaddr }
  4109. if assigned(ref.symbol) or
  4110. (ref.index<>NR_NO) or
  4111. (ref.offset<-255) or
  4112. (ref.offset>4092) or
  4113. { sometimes the compiler reused registers }
  4114. (reg=ref.index) or
  4115. (reg=ref.base) then
  4116. begin
  4117. tmpreg2:=getintregister(list,OS_INT);
  4118. a_loadaddr_ref_reg(list,ref,tmpreg2);
  4119. reference_reset_base(usedtmpref,tmpreg2,0,ref.alignment);
  4120. end
  4121. else
  4122. usedtmpref:=ref;
  4123. shifterop_reset(so);so.shiftmode:=SM_LSL;
  4124. if ref.alignment=2 then
  4125. begin
  4126. if target_info.endian=endian_big then
  4127. inc(usedtmpref.offset,2);
  4128. a_internal_load_ref_reg(list,OS_16,OS_16,usedtmpref,reg);
  4129. inc(usedtmpref.offset,dir*2);
  4130. a_internal_load_ref_reg(list,OS_16,OS_16,usedtmpref,tmpreg);
  4131. so.shiftimm:=16;
  4132. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,reg,tmpreg,so));
  4133. end
  4134. else
  4135. begin
  4136. if target_info.endian=endian_big then
  4137. inc(usedtmpref.offset,3);
  4138. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,reg);
  4139. inc(usedtmpref.offset,dir);
  4140. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
  4141. so.shiftimm:=8;
  4142. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,reg,tmpreg,so));
  4143. inc(usedtmpref.offset,dir);
  4144. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
  4145. so.shiftimm:=16;
  4146. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,reg,tmpreg,so));
  4147. inc(usedtmpref.offset,dir);
  4148. a_internal_load_ref_reg(list,OS_8,OS_8,usedtmpref,tmpreg);
  4149. so.shiftimm:=24;
  4150. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,reg,reg,tmpreg,so));
  4151. end;
  4152. end
  4153. else
  4154. handle_load_store(list,A_LDR,oppostfix,reg,ref);
  4155. end;
  4156. end
  4157. else
  4158. handle_load_store(list,A_LDR,oppostfix,reg,ref);
  4159. if (fromsize=OS_S8) and (tosize = OS_16) then
  4160. a_load_reg_reg(list,OS_16,OS_32,reg,reg);
  4161. end;
  4162. procedure tthumb2cgarm.a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister);
  4163. begin
  4164. if op = OP_NOT then
  4165. begin
  4166. list.concat(taicpu.op_reg_reg(A_MVN,dst,src));
  4167. case size of
  4168. OS_8: list.concat(taicpu.op_reg_reg(A_UXTB,dst,dst));
  4169. OS_S8: list.concat(taicpu.op_reg_reg(A_SXTB,dst,dst));
  4170. OS_16: list.concat(taicpu.op_reg_reg(A_UXTH,dst,dst));
  4171. OS_S16: list.concat(taicpu.op_reg_reg(A_SXTH,dst,dst));
  4172. end;
  4173. end
  4174. else
  4175. inherited a_op_reg_reg(list, op, size, src, dst);
  4176. end;
  4177. procedure tthumb2cgarm.a_op_const_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister;setflags : boolean;var ovloc : tlocation);
  4178. var
  4179. shift, width : byte;
  4180. tmpreg : tregister;
  4181. so : tshifterop;
  4182. l1 : longint;
  4183. begin
  4184. ovloc.loc:=LOC_VOID;
  4185. if {$ifopt R+}(a<>-2147483648) and{$endif} is_shifter_const(-a,shift) then
  4186. case op of
  4187. OP_ADD:
  4188. begin
  4189. op:=OP_SUB;
  4190. a:=aint(dword(-a));
  4191. end;
  4192. OP_SUB:
  4193. begin
  4194. op:=OP_ADD;
  4195. a:=aint(dword(-a));
  4196. end
  4197. end;
  4198. if is_shifter_const(a,shift) and not(op in [OP_IMUL,OP_MUL]) then
  4199. case op of
  4200. OP_NEG,OP_NOT,
  4201. OP_DIV,OP_IDIV:
  4202. internalerror(200308285);
  4203. OP_SHL:
  4204. begin
  4205. if a>32 then
  4206. internalerror(2014020703);
  4207. if a<>0 then
  4208. begin
  4209. shifterop_reset(so);
  4210. so.shiftmode:=SM_LSL;
  4211. so.shiftimm:=a;
  4212. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,so));
  4213. end
  4214. else
  4215. list.concat(taicpu.op_reg_reg(A_MOV,dst,src));
  4216. end;
  4217. OP_ROL:
  4218. begin
  4219. if a>32 then
  4220. internalerror(2014020704);
  4221. if a<>0 then
  4222. begin
  4223. shifterop_reset(so);
  4224. so.shiftmode:=SM_ROR;
  4225. so.shiftimm:=32-a;
  4226. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,so));
  4227. end
  4228. else
  4229. list.concat(taicpu.op_reg_reg(A_MOV,dst,src));
  4230. end;
  4231. OP_ROR:
  4232. begin
  4233. if a>32 then
  4234. internalerror(2014020705);
  4235. if a<>0 then
  4236. begin
  4237. shifterop_reset(so);
  4238. so.shiftmode:=SM_ROR;
  4239. so.shiftimm:=a;
  4240. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,so));
  4241. end
  4242. else
  4243. list.concat(taicpu.op_reg_reg(A_MOV,dst,src));
  4244. end;
  4245. OP_SHR:
  4246. begin
  4247. if a>32 then
  4248. internalerror(200308292);
  4249. shifterop_reset(so);
  4250. if a<>0 then
  4251. begin
  4252. so.shiftmode:=SM_LSR;
  4253. so.shiftimm:=a;
  4254. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,so));
  4255. end
  4256. else
  4257. list.concat(taicpu.op_reg_reg(A_MOV,dst,src));
  4258. end;
  4259. OP_SAR:
  4260. begin
  4261. if a>32 then
  4262. internalerror(200308295);
  4263. if a<>0 then
  4264. begin
  4265. shifterop_reset(so);
  4266. so.shiftmode:=SM_ASR;
  4267. so.shiftimm:=a;
  4268. list.concat(taicpu.op_reg_reg_shifterop(A_MOV,dst,src,so));
  4269. end
  4270. else
  4271. list.concat(taicpu.op_reg_reg(A_MOV,dst,src));
  4272. end;
  4273. else
  4274. if (op in [OP_SUB, OP_ADD]) and
  4275. ((a < 0) or
  4276. (a > 4095)) then
  4277. begin
  4278. tmpreg:=getintregister(list,size);
  4279. a_load_const_reg(list, size, a, tmpreg);
  4280. if cgsetflags or setflags then
  4281. a_reg_alloc(list,NR_DEFAULTFLAGS);
  4282. list.concat(setoppostfix(
  4283. taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmop[op],dst,src,tmpreg),toppostfix(ord(cgsetflags or setflags)*ord(PF_S))));
  4284. end
  4285. else
  4286. begin
  4287. if cgsetflags or setflags then
  4288. a_reg_alloc(list,NR_DEFAULTFLAGS);
  4289. list.concat(setoppostfix(
  4290. taicpu.op_reg_reg_const(op_reg_reg_opcg2asmop[op],dst,src,a),toppostfix(ord(cgsetflags or setflags)*ord(PF_S))));
  4291. end;
  4292. if (cgsetflags or setflags) and (size in [OS_8,OS_16,OS_32]) then
  4293. begin
  4294. ovloc.loc:=LOC_FLAGS;
  4295. case op of
  4296. OP_ADD:
  4297. ovloc.resflags:=F_CS;
  4298. OP_SUB:
  4299. ovloc.resflags:=F_CC;
  4300. end;
  4301. end;
  4302. end
  4303. else
  4304. begin
  4305. { there could be added some more sophisticated optimizations }
  4306. if (op in [OP_MUL,OP_IMUL]) and (a=1) then
  4307. a_load_reg_reg(list,size,size,src,dst)
  4308. else if (op in [OP_MUL,OP_IMUL]) and (a=0) then
  4309. a_load_const_reg(list,size,0,dst)
  4310. else if (op in [OP_IMUL]) and (a=-1) then
  4311. a_op_reg_reg(list,OP_NEG,size,src,dst)
  4312. { we do this here instead in the peephole optimizer because
  4313. it saves us a register }
  4314. else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a,l1) and not(cgsetflags or setflags) then
  4315. a_op_const_reg_reg(list,OP_SHL,size,l1,src,dst)
  4316. { for example : b=a*5 -> b=a*4+a with add instruction and shl }
  4317. else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a-1,l1) and not(cgsetflags or setflags) then
  4318. begin
  4319. if l1>32 then{roozbeh does this ever happen?}
  4320. internalerror(200308296);
  4321. shifterop_reset(so);
  4322. so.shiftmode:=SM_LSL;
  4323. so.shiftimm:=l1;
  4324. list.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,dst,src,src,so));
  4325. end
  4326. { for example : b=a*7 -> b=a*8-a with rsb instruction and shl }
  4327. else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a+1,l1) and not(cgsetflags or setflags) then
  4328. begin
  4329. if l1>32 then{does this ever happen?}
  4330. internalerror(201205181);
  4331. shifterop_reset(so);
  4332. so.shiftmode:=SM_LSL;
  4333. so.shiftimm:=l1;
  4334. list.concat(taicpu.op_reg_reg_reg_shifterop(A_RSB,dst,src,src,so));
  4335. end
  4336. else if (op in [OP_MUL,OP_IMUL]) and not(cgsetflags or setflags) and try_optimized_mul32_const_reg_reg(list,a,src,dst) then
  4337. begin
  4338. { nothing to do on success }
  4339. end
  4340. { x := y and 0; just clears a register, this sometimes gets generated on 64bit ops.
  4341. Just using mov x, #0 might allow some easier optimizations down the line. }
  4342. else if (op = OP_AND) and (dword(a)=0) then
  4343. list.concat(taicpu.op_reg_const(A_MOV,dst,0))
  4344. { x := y AND $FFFFFFFF just copies the register, so use mov for better optimizations }
  4345. else if (op = OP_AND) and (not(dword(a))=0) then
  4346. list.concat(taicpu.op_reg_reg(A_MOV,dst,src))
  4347. { BIC clears the specified bits, while AND keeps them, using BIC allows to use a
  4348. broader range of shifterconstants.}
  4349. {else if (op = OP_AND) and is_shifter_const(not(dword(a)),shift) then
  4350. list.concat(taicpu.op_reg_reg_const(A_BIC,dst,src,not(dword(a))))}
  4351. else if (op = OP_AND) and is_thumb32_imm(a) then
  4352. list.concat(taicpu.op_reg_reg_const(A_AND,dst,src,dword(a)))
  4353. else if (op = OP_AND) and (a = $FFFF) then
  4354. list.concat(taicpu.op_reg_reg(A_UXTH,dst,src))
  4355. else if (op = OP_AND) and is_thumb32_imm(not(dword(a))) then
  4356. list.concat(taicpu.op_reg_reg_const(A_BIC,dst,src,not(dword(a))))
  4357. else if (op = OP_AND) and is_continuous_mask(not(a), shift, width) then
  4358. begin
  4359. a_load_reg_reg(list,size,size,src,dst);
  4360. list.concat(taicpu.op_reg_const_const(A_BFC,dst,shift,width))
  4361. end
  4362. else
  4363. begin
  4364. tmpreg:=getintregister(list,size);
  4365. a_load_const_reg(list,size,a,tmpreg);
  4366. a_op_reg_reg_reg_checkoverflow(list,op,size,tmpreg,src,dst,setflags,ovloc);
  4367. end;
  4368. end;
  4369. maybeadjustresult(list,op,size,dst);
  4370. end;
  4371. const
  4372. op_reg_reg_opcg2asmopThumb2: array[TOpCG] of tasmop =
  4373. (A_NONE,A_MOV,A_ADD,A_AND,A_UDIV,A_SDIV,A_MUL,A_MUL,A_NONE,A_MVN,A_ORR,
  4374. A_ASR,A_LSL,A_LSR,A_SUB,A_EOR,A_NONE,A_ROR);
  4375. procedure tthumb2cgarm.a_op_reg_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister;setflags : boolean;var ovloc : tlocation);
  4376. var
  4377. so : tshifterop;
  4378. tmpreg,overflowreg : tregister;
  4379. asmop : tasmop;
  4380. begin
  4381. ovloc.loc:=LOC_VOID;
  4382. case op of
  4383. OP_NEG,OP_NOT:
  4384. internalerror(200308286);
  4385. OP_ROL:
  4386. begin
  4387. if not(size in [OS_32,OS_S32]) then
  4388. internalerror(2008072801);
  4389. { simulate ROL by ror'ing 32-value }
  4390. tmpreg:=getintregister(list,OS_32);
  4391. list.concat(taicpu.op_reg_const(A_MOV,tmpreg,32));
  4392. list.concat(taicpu.op_reg_reg_reg(A_SUB,src1,tmpreg,src1));
  4393. list.concat(taicpu.op_reg_reg_reg(A_ROR, dst, src2, src1));
  4394. end;
  4395. OP_ROR:
  4396. begin
  4397. if not(size in [OS_32,OS_S32]) then
  4398. internalerror(2008072802);
  4399. list.concat(taicpu.op_reg_reg_reg(A_ROR, dst, src2, src1));
  4400. end;
  4401. OP_IMUL,
  4402. OP_MUL:
  4403. begin
  4404. if cgsetflags or setflags then
  4405. begin
  4406. overflowreg:=getintregister(list,size);
  4407. if op=OP_IMUL then
  4408. asmop:=A_SMULL
  4409. else
  4410. asmop:=A_UMULL;
  4411. { the arm doesn't allow that rd and rm are the same }
  4412. if dst=src2 then
  4413. begin
  4414. if dst<>src1 then
  4415. list.concat(taicpu.op_reg_reg_reg_reg(asmop,dst,overflowreg,src1,src2))
  4416. else
  4417. begin
  4418. tmpreg:=getintregister(list,size);
  4419. a_load_reg_reg(list,size,size,src2,dst);
  4420. list.concat(taicpu.op_reg_reg_reg_reg(asmop,dst,overflowreg,tmpreg,src1));
  4421. end;
  4422. end
  4423. else
  4424. list.concat(taicpu.op_reg_reg_reg_reg(asmop,dst,overflowreg,src2,src1));
  4425. a_reg_alloc(list,NR_DEFAULTFLAGS);
  4426. if op=OP_IMUL then
  4427. begin
  4428. shifterop_reset(so);
  4429. so.shiftmode:=SM_ASR;
  4430. so.shiftimm:=31;
  4431. list.concat(taicpu.op_reg_reg_shifterop(A_CMP,overflowreg,dst,so));
  4432. end
  4433. else
  4434. list.concat(taicpu.op_reg_const(A_CMP,overflowreg,0));
  4435. ovloc.loc:=LOC_FLAGS;
  4436. ovloc.resflags:=F_NE;
  4437. end
  4438. else
  4439. begin
  4440. { the arm doesn't allow that rd and rm are the same }
  4441. if dst=src2 then
  4442. begin
  4443. if dst<>src1 then
  4444. list.concat(taicpu.op_reg_reg_reg(A_MUL,dst,src1,src2))
  4445. else
  4446. begin
  4447. tmpreg:=getintregister(list,size);
  4448. a_load_reg_reg(list,size,size,src2,dst);
  4449. list.concat(taicpu.op_reg_reg_reg(A_MUL,dst,tmpreg,src1));
  4450. end;
  4451. end
  4452. else
  4453. list.concat(taicpu.op_reg_reg_reg(A_MUL,dst,src2,src1));
  4454. end;
  4455. end;
  4456. else
  4457. begin
  4458. if cgsetflags or setflags then
  4459. a_reg_alloc(list,NR_DEFAULTFLAGS);
  4460. {$ifdef dummy}
  4461. { R13 is not allowed for certain instruction operands }
  4462. if op_reg_reg_opcg2asmopThumb2[op] in [A_ADD,A_SUB,A_AND,A_BIC,A_EOR] then
  4463. begin
  4464. if getsupreg(dst)=RS_R13 then
  4465. begin
  4466. tmpreg:=getintregister(list,OS_INT);
  4467. a_load_reg_reg(list,OS_INT,OS_INT,dst,tmpreg);
  4468. dst:=tmpreg;
  4469. end;
  4470. if getsupreg(src1)=RS_R13 then
  4471. begin
  4472. tmpreg:=getintregister(list,OS_INT);
  4473. a_load_reg_reg(list,OS_INT,OS_INT,src1,tmpreg);
  4474. src1:=tmpreg;
  4475. end;
  4476. end;
  4477. {$endif}
  4478. list.concat(setoppostfix(
  4479. taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmopThumb2[op],dst,src2,src1),toppostfix(ord(cgsetflags or setflags)*ord(PF_S))));
  4480. end;
  4481. end;
  4482. maybeadjustresult(list,op,size,dst);
  4483. end;
  4484. procedure tthumb2cgarm.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
  4485. var item: taicpu;
  4486. begin
  4487. list.concat(taicpu.op_cond(A_ITE, flags_to_cond(f)));
  4488. list.concat(setcondition(taicpu.op_reg_const(A_MOV,reg,1),flags_to_cond(f)));
  4489. list.concat(setcondition(taicpu.op_reg_const(A_MOV,reg,0),inverse_cond(flags_to_cond(f))));
  4490. end;
  4491. procedure tthumb2cgarm.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
  4492. var
  4493. ref : treference;
  4494. shift : byte;
  4495. firstfloatreg,lastfloatreg,
  4496. r : byte;
  4497. regs : tcpuregisterset;
  4498. stackmisalignment: pint;
  4499. begin
  4500. LocalSize:=align(LocalSize,4);
  4501. { call instruction does not put anything on the stack }
  4502. stackmisalignment:=0;
  4503. if not(nostackframe) then
  4504. begin
  4505. firstfloatreg:=RS_NO;
  4506. lastfloatreg:=RS_NO;
  4507. { save floating point registers? }
  4508. for r:=RS_F0 to RS_F7 do
  4509. if r in rg[R_FPUREGISTER].used_in_proc-paramanager.get_volatile_registers_fpu(pocall_stdcall) then
  4510. begin
  4511. if firstfloatreg=RS_NO then
  4512. firstfloatreg:=r;
  4513. lastfloatreg:=r;
  4514. inc(stackmisalignment,12);
  4515. end;
  4516. a_reg_alloc(list,NR_STACK_POINTER_REG);
  4517. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  4518. begin
  4519. a_reg_alloc(list,NR_FRAME_POINTER_REG);
  4520. a_reg_alloc(list,NR_R12);
  4521. list.concat(taicpu.op_reg_reg(A_MOV,NR_R12,NR_STACK_POINTER_REG));
  4522. end;
  4523. { save int registers }
  4524. reference_reset(ref,4);
  4525. ref.index:=NR_STACK_POINTER_REG;
  4526. ref.addressmode:=AM_PREINDEXED;
  4527. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  4528. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  4529. regs:=regs+[RS_FRAME_POINTER_REG,RS_R14]
  4530. else if (regs<>[]) or (pi_do_call in current_procinfo.flags) then
  4531. include(regs,RS_R14);
  4532. if regs<>[] then
  4533. begin
  4534. for r:=RS_R0 to RS_R15 do
  4535. if (r in regs) then
  4536. inc(stackmisalignment,4);
  4537. list.concat(setoppostfix(taicpu.op_ref_regset(A_STM,ref,R_INTREGISTER,R_SUBWHOLE,regs),PF_FD));
  4538. end;
  4539. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  4540. begin
  4541. { the framepointer now points to the saved R15, so the saved
  4542. framepointer is at R11-12 (for get_caller_frame) }
  4543. list.concat(taicpu.op_reg_reg_const(A_SUB,NR_FRAME_POINTER_REG,NR_R12,4));
  4544. a_reg_dealloc(list,NR_R12);
  4545. end;
  4546. stackmisalignment:=stackmisalignment mod current_settings.alignment.localalignmax;
  4547. if (LocalSize<>0) or
  4548. ((stackmisalignment<>0) and
  4549. ((pi_do_call in current_procinfo.flags) or
  4550. (po_assembler in current_procinfo.procdef.procoptions))) then
  4551. begin
  4552. localsize:=align(localsize+stackmisalignment,current_settings.alignment.localalignmax)-stackmisalignment;
  4553. if not(is_shifter_const(localsize,shift)) then
  4554. begin
  4555. if current_procinfo.framepointer=NR_STACK_POINTER_REG then
  4556. a_reg_alloc(list,NR_R12);
  4557. a_load_const_reg(list,OS_ADDR,LocalSize,NR_R12);
  4558. list.concat(taicpu.op_reg_reg_reg(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,NR_R12));
  4559. a_reg_dealloc(list,NR_R12);
  4560. end
  4561. else
  4562. begin
  4563. a_reg_dealloc(list,NR_R12);
  4564. list.concat(taicpu.op_reg_reg_const(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,LocalSize));
  4565. end;
  4566. end;
  4567. if firstfloatreg<>RS_NO then
  4568. begin
  4569. reference_reset(ref,4);
  4570. if tg.direction*tarmprocinfo(current_procinfo).floatregstart>=1023 then
  4571. begin
  4572. a_load_const_reg(list,OS_ADDR,-tarmprocinfo(current_procinfo).floatregstart,NR_R12);
  4573. list.concat(taicpu.op_reg_reg_reg(A_SUB,NR_R12,current_procinfo.framepointer,NR_R12));
  4574. ref.base:=NR_R12;
  4575. end
  4576. else
  4577. begin
  4578. ref.base:=current_procinfo.framepointer;
  4579. ref.offset:=tarmprocinfo(current_procinfo).floatregstart;
  4580. end;
  4581. list.concat(taicpu.op_reg_const_ref(A_SFM,newreg(R_FPUREGISTER,firstfloatreg,R_SUBWHOLE),
  4582. lastfloatreg-firstfloatreg+1,ref));
  4583. end;
  4584. end;
  4585. end;
  4586. procedure tthumb2cgarm.g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean);
  4587. var
  4588. ref : treference;
  4589. firstfloatreg,lastfloatreg,
  4590. r : byte;
  4591. shift : byte;
  4592. regs : tcpuregisterset;
  4593. LocalSize : longint;
  4594. stackmisalignment: pint;
  4595. begin
  4596. if not(nostackframe) then
  4597. begin
  4598. stackmisalignment:=0;
  4599. { restore floating point register }
  4600. firstfloatreg:=RS_NO;
  4601. lastfloatreg:=RS_NO;
  4602. { save floating point registers? }
  4603. for r:=RS_F0 to RS_F7 do
  4604. if r in rg[R_FPUREGISTER].used_in_proc-paramanager.get_volatile_registers_fpu(pocall_stdcall) then
  4605. begin
  4606. if firstfloatreg=RS_NO then
  4607. firstfloatreg:=r;
  4608. lastfloatreg:=r;
  4609. { floating point register space is already included in
  4610. localsize below by calc_stackframe_size
  4611. inc(stackmisalignment,12);
  4612. }
  4613. end;
  4614. if firstfloatreg<>RS_NO then
  4615. begin
  4616. reference_reset(ref,4);
  4617. if tg.direction*tarmprocinfo(current_procinfo).floatregstart>=1023 then
  4618. begin
  4619. a_load_const_reg(list,OS_ADDR,-tarmprocinfo(current_procinfo).floatregstart,NR_R12);
  4620. list.concat(taicpu.op_reg_reg_reg(A_SUB,NR_R12,current_procinfo.framepointer,NR_R12));
  4621. ref.base:=NR_R12;
  4622. end
  4623. else
  4624. begin
  4625. ref.base:=current_procinfo.framepointer;
  4626. ref.offset:=tarmprocinfo(current_procinfo).floatregstart;
  4627. end;
  4628. list.concat(taicpu.op_reg_const_ref(A_LFM,newreg(R_FPUREGISTER,firstfloatreg,R_SUBWHOLE),
  4629. lastfloatreg-firstfloatreg+1,ref));
  4630. end;
  4631. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  4632. if (pi_do_call in current_procinfo.flags) or (regs<>[]) then
  4633. begin
  4634. exclude(regs,RS_R14);
  4635. include(regs,RS_R15);
  4636. end;
  4637. if (current_procinfo.framepointer<>NR_STACK_POINTER_REG) then
  4638. regs:=regs+[RS_FRAME_POINTER_REG,RS_R15];
  4639. for r:=RS_R0 to RS_R15 do
  4640. if (r in regs) then
  4641. inc(stackmisalignment,4);
  4642. stackmisalignment:=stackmisalignment mod current_settings.alignment.localalignmax;
  4643. LocalSize:=current_procinfo.calc_stackframe_size;
  4644. if (LocalSize<>0) or
  4645. ((stackmisalignment<>0) and
  4646. ((pi_do_call in current_procinfo.flags) or
  4647. (po_assembler in current_procinfo.procdef.procoptions))) then
  4648. begin
  4649. localsize:=align(localsize+stackmisalignment,current_settings.alignment.localalignmax)-stackmisalignment;
  4650. if not(is_shifter_const(LocalSize,shift)) then
  4651. begin
  4652. a_reg_alloc(list,NR_R12);
  4653. a_load_const_reg(list,OS_ADDR,LocalSize,NR_R12);
  4654. list.concat(taicpu.op_reg_reg(A_ADD,NR_STACK_POINTER_REG,NR_R12));
  4655. a_reg_dealloc(list,NR_R12);
  4656. end
  4657. else
  4658. begin
  4659. a_reg_dealloc(list,NR_R12);
  4660. list.concat(taicpu.op_reg_const(A_ADD,NR_STACK_POINTER_REG,LocalSize));
  4661. end;
  4662. end;
  4663. if regs=[] then
  4664. list.concat(taicpu.op_reg_reg(A_MOV,NR_R15,NR_R14))
  4665. else
  4666. begin
  4667. reference_reset(ref,4);
  4668. ref.index:=NR_STACK_POINTER_REG;
  4669. ref.addressmode:=AM_PREINDEXED;
  4670. list.concat(setoppostfix(taicpu.op_ref_regset(A_LDM,ref,R_INTREGISTER,R_SUBWHOLE,regs),PF_FD));
  4671. end;
  4672. end
  4673. else
  4674. list.concat(taicpu.op_reg_reg(A_MOV,NR_PC,NR_R14));
  4675. end;
  4676. function tthumb2cgarm.handle_load_store(list:TAsmList;op: tasmop;oppostfix : toppostfix;reg:tregister;ref: treference):treference;
  4677. var
  4678. tmpreg : tregister;
  4679. tmpref : treference;
  4680. l : tasmlabel;
  4681. so: tshifterop;
  4682. begin
  4683. tmpreg:=NR_NO;
  4684. { Be sure to have a base register }
  4685. if (ref.base=NR_NO) then
  4686. begin
  4687. if ref.shiftmode<>SM_None then
  4688. internalerror(2014020706);
  4689. ref.base:=ref.index;
  4690. ref.index:=NR_NO;
  4691. end;
  4692. { absolute symbols can't be handled directly, we've to store the symbol reference
  4693. in the text segment and access it pc relative
  4694. For now, we assume that references where base or index equals to PC are already
  4695. relative, all other references are assumed to be absolute and thus they need
  4696. to be handled extra.
  4697. A proper solution would be to change refoptions to a set and store the information
  4698. if the symbol is absolute or relative there.
  4699. }
  4700. if (assigned(ref.symbol) and
  4701. not(is_pc(ref.base)) and
  4702. not(is_pc(ref.index))
  4703. ) or
  4704. { [#xxx] isn't a valid address operand }
  4705. ((ref.base=NR_NO) and (ref.index=NR_NO)) or
  4706. //(ref.offset<-4095) or
  4707. (ref.offset<-255) or
  4708. (ref.offset>4095) or
  4709. ((oppostfix in [PF_SB,PF_H,PF_SH]) and
  4710. ((ref.offset<-255) or
  4711. (ref.offset>255)
  4712. )
  4713. ) or
  4714. (((op in [A_LDF,A_STF,A_FLDS,A_FLDD,A_FSTS,A_FSTD]) or (op=A_VSTR) or (op=A_VLDR)) and
  4715. ((ref.offset<-1020) or
  4716. (ref.offset>1020) or
  4717. ((abs(ref.offset) mod 4)<>0) or
  4718. { the usual pc relative symbol handling assumes possible offsets of +/- 4095 }
  4719. assigned(ref.symbol)
  4720. )
  4721. ) then
  4722. begin
  4723. reference_reset(tmpref,4);
  4724. { load symbol }
  4725. tmpreg:=getintregister(list,OS_INT);
  4726. if assigned(ref.symbol) then
  4727. begin
  4728. current_asmdata.getjumplabel(l);
  4729. cg.a_label(current_procinfo.aktlocaldata,l);
  4730. tmpref.symboldata:=current_procinfo.aktlocaldata.last;
  4731. current_procinfo.aktlocaldata.concat(tai_const.create_sym_offset(ref.symbol,ref.offset));
  4732. { load consts entry }
  4733. tmpref.symbol:=l;
  4734. tmpref.base:=NR_R15;
  4735. list.concat(taicpu.op_reg_ref(A_LDR,tmpreg,tmpref));
  4736. { in case of LDF/STF, we got rid of the NR_R15 }
  4737. if is_pc(ref.base) then
  4738. ref.base:=NR_NO;
  4739. if is_pc(ref.index) then
  4740. ref.index:=NR_NO;
  4741. end
  4742. else
  4743. a_load_const_reg(list,OS_ADDR,ref.offset,tmpreg);
  4744. if (ref.base<>NR_NO) then
  4745. begin
  4746. if ref.index<>NR_NO then
  4747. begin
  4748. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,tmpreg));
  4749. ref.base:=tmpreg;
  4750. end
  4751. else
  4752. begin
  4753. ref.index:=tmpreg;
  4754. ref.shiftimm:=0;
  4755. ref.signindex:=1;
  4756. ref.shiftmode:=SM_None;
  4757. end;
  4758. end
  4759. else
  4760. ref.base:=tmpreg;
  4761. ref.offset:=0;
  4762. ref.symbol:=nil;
  4763. end;
  4764. if (ref.base<>NR_NO) and (ref.index<>NR_NO) and (ref.offset<>0) then
  4765. begin
  4766. if tmpreg<>NR_NO then
  4767. a_op_const_reg_reg(list,OP_ADD,OS_ADDR,ref.offset,tmpreg,tmpreg)
  4768. else
  4769. begin
  4770. tmpreg:=getintregister(list,OS_ADDR);
  4771. a_op_const_reg_reg(list,OP_ADD,OS_ADDR,ref.offset,ref.base,tmpreg);
  4772. ref.base:=tmpreg;
  4773. end;
  4774. ref.offset:=0;
  4775. end;
  4776. { Hack? Thumb2 doesn't allow PC indexed addressing modes(although it does in the specification) }
  4777. if (ref.base=NR_R15) and (ref.index<>NR_NO) and (ref.shiftmode <> sm_none) then
  4778. begin
  4779. tmpreg:=getintregister(list,OS_ADDR);
  4780. list.concat(taicpu.op_reg_reg(A_MOV, tmpreg, NR_R15));
  4781. ref.base := tmpreg;
  4782. end;
  4783. { floating point operations have only limited references
  4784. we expect here, that a base is already set }
  4785. if ((op in [A_LDF,A_STF,A_FLDS,A_FLDD,A_FSTS,A_FSTD]) or (op=A_VSTR) or (op=A_VLDR)) and (ref.index<>NR_NO) then
  4786. begin
  4787. if ref.shiftmode<>SM_none then
  4788. internalerror(200309121);
  4789. if tmpreg<>NR_NO then
  4790. begin
  4791. if ref.base=tmpreg then
  4792. begin
  4793. if ref.signindex<0 then
  4794. list.concat(taicpu.op_reg_reg_reg(A_SUB,tmpreg,tmpreg,ref.index))
  4795. else
  4796. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,tmpreg,ref.index));
  4797. ref.index:=NR_NO;
  4798. end
  4799. else
  4800. begin
  4801. if ref.index<>tmpreg then
  4802. internalerror(200403161);
  4803. if ref.signindex<0 then
  4804. list.concat(taicpu.op_reg_reg_reg(A_SUB,tmpreg,ref.base,tmpreg))
  4805. else
  4806. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,tmpreg));
  4807. ref.base:=tmpreg;
  4808. ref.index:=NR_NO;
  4809. end;
  4810. end
  4811. else
  4812. begin
  4813. tmpreg:=getintregister(list,OS_ADDR);
  4814. list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,ref.index));
  4815. ref.base:=tmpreg;
  4816. ref.index:=NR_NO;
  4817. end;
  4818. end;
  4819. list.concat(setoppostfix(taicpu.op_reg_ref(op,reg,ref),oppostfix));
  4820. Result := ref;
  4821. end;
  4822. procedure tthumb2cgarm.a_loadmm_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister; shuffle: pmmshuffle);
  4823. var
  4824. instr: taicpu;
  4825. begin
  4826. if (fromsize=OS_F32) and
  4827. (tosize=OS_F32) then
  4828. begin
  4829. instr:=setoppostfix(taicpu.op_reg_reg(A_VMOV,reg2,reg1), PF_F32);
  4830. list.Concat(instr);
  4831. add_move_instruction(instr);
  4832. end
  4833. else if (fromsize=OS_F64) and
  4834. (tosize=OS_F64) then
  4835. begin
  4836. //list.Concat(setoppostfix(taicpu.op_reg_reg(A_VMOV,tregister(longint(reg2)+1),tregister(longint(reg1)+1)), PF_F32));
  4837. //list.Concat(setoppostfix(taicpu.op_reg_reg(A_VMOV,reg2,reg1), PF_F32));
  4838. end
  4839. else if (fromsize=OS_F32) and
  4840. (tosize=OS_F64) then
  4841. //list.Concat(setoppostfix(taicpu.op_reg_reg(A_VCVT,reg2,reg1), PF_F32))
  4842. begin
  4843. //list.concat(nil);
  4844. end;
  4845. end;
  4846. procedure tthumb2cgarm.a_loadmm_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister; shuffle: pmmshuffle);
  4847. begin
  4848. if fromsize=OS_F32 then
  4849. handle_load_store(list,A_VLDR,PF_F32,reg,ref)
  4850. else
  4851. handle_load_store(list,A_VLDR,PF_F64,reg,ref);
  4852. end;
  4853. procedure tthumb2cgarm.a_loadmm_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference; shuffle: pmmshuffle);
  4854. begin
  4855. if fromsize=OS_F32 then
  4856. handle_load_store(list,A_VSTR,PF_F32,reg,ref)
  4857. else
  4858. handle_load_store(list,A_VSTR,PF_F64,reg,ref);
  4859. end;
  4860. procedure tthumb2cgarm.a_loadmm_intreg_reg(list: TAsmList; fromsize, tosize: tcgsize; intreg, mmreg: tregister; shuffle: pmmshuffle);
  4861. begin
  4862. if //(shuffle=nil) and
  4863. (tosize=OS_F32) then
  4864. list.Concat(taicpu.op_reg_reg(A_VMOV,mmreg,intreg))
  4865. else
  4866. internalerror(2012100813);
  4867. end;
  4868. procedure tthumb2cgarm.a_loadmm_reg_intreg(list: TAsmList; fromsize, tosize: tcgsize; mmreg, intreg: tregister; shuffle: pmmshuffle);
  4869. begin
  4870. if //(shuffle=nil) and
  4871. (fromsize=OS_F32) then
  4872. list.Concat(taicpu.op_reg_reg(A_VMOV,intreg,mmreg))
  4873. else
  4874. internalerror(2012100814);
  4875. end;
  4876. procedure tthumb2cg64farm.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
  4877. var tmpreg: tregister;
  4878. begin
  4879. case op of
  4880. OP_NEG:
  4881. begin
  4882. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  4883. list.concat(setoppostfix(taicpu.op_reg_reg_const(A_RSB,regdst.reglo,regsrc.reglo,0),PF_S));
  4884. tmpreg:=cg.getintregister(list,OS_32);
  4885. list.concat(taicpu.op_reg_const(A_MOV,tmpreg,0));
  4886. list.concat(taicpu.op_reg_reg_reg(A_SBC,regdst.reghi,tmpreg,regsrc.reghi));
  4887. cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
  4888. end;
  4889. else
  4890. inherited a_op64_reg_reg(list, op, size, regsrc, regdst);
  4891. end;
  4892. end;
  4893. procedure tthumbcg64farm.a_op64_reg_reg(list: TAsmList; op: TOpCG; size: tcgsize; regsrc, regdst: tregister64);
  4894. begin
  4895. case op of
  4896. OP_NEG:
  4897. begin
  4898. list.concat(taicpu.op_reg_const(A_MOV,regdst.reglo,0));
  4899. list.concat(taicpu.op_reg_const(A_MOV,regdst.reghi,0));
  4900. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  4901. list.concat(taicpu.op_reg_reg(A_SUB,regdst.reglo,regsrc.reglo));
  4902. list.concat(taicpu.op_reg_reg(A_SBC,regdst.reghi,regsrc.reghi));
  4903. cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
  4904. end;
  4905. OP_NOT:
  4906. begin
  4907. cg.a_op_reg_reg(list,OP_NOT,OS_INT,regsrc.reglo,regdst.reglo);
  4908. cg.a_op_reg_reg(list,OP_NOT,OS_INT,regsrc.reghi,regdst.reghi);
  4909. end;
  4910. OP_AND,OP_OR,OP_XOR:
  4911. begin
  4912. cg.a_op_reg_reg(list,op,OS_32,regsrc.reglo,regdst.reglo);
  4913. cg.a_op_reg_reg(list,op,OS_32,regsrc.reghi,regdst.reghi);
  4914. end;
  4915. OP_ADD:
  4916. begin
  4917. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  4918. list.concat(taicpu.op_reg_reg(A_ADD,regdst.reglo,regsrc.reglo));
  4919. list.concat(taicpu.op_reg_reg(A_ADC,regdst.reghi,regsrc.reghi));
  4920. end;
  4921. OP_SUB:
  4922. begin
  4923. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  4924. list.concat(taicpu.op_reg_reg(A_SUB,regdst.reglo,regsrc.reglo));
  4925. list.concat(taicpu.op_reg_reg(A_SBC,regdst.reghi,regsrc.reghi));
  4926. end;
  4927. else
  4928. internalerror(2003083101);
  4929. end;
  4930. end;
  4931. procedure tthumbcg64farm.a_op64_const_reg(list: TAsmList; op: TOpCG; size: tcgsize; value: int64; reg: tregister64);
  4932. var
  4933. tmpreg : tregister;
  4934. b : byte;
  4935. begin
  4936. case op of
  4937. OP_AND,OP_OR,OP_XOR:
  4938. begin
  4939. cg.a_op_const_reg(list,op,OS_32,aint(lo(value)),reg.reglo);
  4940. cg.a_op_const_reg(list,op,OS_32,aint(hi(value)),reg.reghi);
  4941. end;
  4942. OP_ADD:
  4943. begin
  4944. if (aint(lo(value))>=0) and (aint(lo(value))<=255) then
  4945. begin
  4946. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  4947. list.concat(taicpu.op_reg_const(A_ADD,reg.reglo,aint(lo(value))));
  4948. end
  4949. else
  4950. begin
  4951. tmpreg:=cg.getintregister(list,OS_32);
  4952. cg.a_load_const_reg(list,OS_32,aint(lo(value)),tmpreg);
  4953. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  4954. list.concat(taicpu.op_reg_reg(A_ADD,reg.reglo,tmpreg));
  4955. end;
  4956. tmpreg:=cg.getintregister(list,OS_32);
  4957. cg.a_load_const_reg(list,OS_32,aint(hi(value)),tmpreg);
  4958. list.concat(taicpu.op_reg_reg(A_ADC,reg.reghi,tmpreg));
  4959. end;
  4960. OP_SUB:
  4961. begin
  4962. if (aint(lo(value))>=0) and (aint(lo(value))<=255) then
  4963. begin
  4964. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  4965. list.concat(taicpu.op_reg_const(A_SUB,reg.reglo,aint(lo(value))))
  4966. end
  4967. else
  4968. begin
  4969. tmpreg:=cg.getintregister(list,OS_32);
  4970. cg.a_load_const_reg(list,OS_32,aint(lo(value)),tmpreg);
  4971. cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
  4972. list.concat(taicpu.op_reg_reg(A_SUB,reg.reglo,tmpreg));
  4973. end;
  4974. tmpreg:=cg.getintregister(list,OS_32);
  4975. cg.a_load_const_reg(list,OS_32,hi(value),tmpreg);
  4976. list.concat(taicpu.op_reg_reg(A_SBC,reg.reghi,tmpreg));
  4977. end;
  4978. else
  4979. internalerror(2003083101);
  4980. end;
  4981. end;
  4982. procedure create_codegen;
  4983. begin
  4984. if GenerateThumb2Code then
  4985. begin
  4986. cg:=tthumb2cgarm.create;
  4987. cg64:=tthumb2cg64farm.create;
  4988. casmoptimizer:=TCpuThumb2AsmOptimizer;
  4989. end
  4990. else if GenerateThumbCode then
  4991. begin
  4992. cg:=tthumbcgarm.create;
  4993. cg64:=tthumbcg64farm.create;
  4994. // casmoptimizer:=TCpuThumbAsmOptimizer;
  4995. end
  4996. else
  4997. begin
  4998. cg:=tarmcgarm.create;
  4999. cg64:=tarmcg64farm.create;
  5000. casmoptimizer:=TCpuAsmOptimizer;
  5001. end;
  5002. end;
  5003. end.