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aoptcpu.pas
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02c3f328a2
- RISC-V: Share optimizations between 32 and 64-bit.
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пре 5 година |
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aoptcpub.pas
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9b0ff05ee8
- get rid of MaxOps, it is redundant with max_operands
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пре 6 година |
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aoptcpuc.pas
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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пре 7 година |
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aoptcpud.pas
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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пре 7 година |
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cgcpu.pas
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159d97e864
* Risc-V: make use of sext.h instruction if available
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пре 1 година |
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cpuinfo.pas
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0b49fba637
+ more RiscV extensions
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пре 9 месеци |
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cpunode.pas
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c86e7b43b4
Add insert_init_final_table method
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пре 1 година |
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cpupara.pas
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49aa141703
* major parts of the RiscV paramgr unified, improves code generation and less failures in RiscV32 regression tests
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пре 8 месеци |
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cpupi.pas
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281b3ad276
* fix case completeness and unreachable code warnings in compiler that would
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пре 6 година |
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cputarg.pas
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bedd4edc72
+ first work for esp32-c3 support
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пре 2 година |
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hlcgcpu.pas
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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пре 7 година |
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nrv32add.pas
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c83e6c34a9
riscv32: Fix 64bit comparisons
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пре 2 година |
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nrv32cal.pas
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44150f43ac
* RISC-V 32 compilation fixed
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пре 7 година |
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nrv32cnv.pas
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281b3ad276
* fix case completeness and unreachable code warnings in compiler that would
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пре 6 година |
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nrv32mat.pas
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6d157b5bf0
+ Risc-V 32: optimize QWord(1) shl ...
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пре 1 година |
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nrv32util.pas
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57da25581e
+ write .option pic directive if needed
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пре 8 месеци |
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rrv32con.inc
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8d0bdf2f16
+ RiscV: vector registers
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пре 8 месеци |
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rrv32dwa.inc
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8d0bdf2f16
+ RiscV: vector registers
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пре 8 месеци |
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rrv32nor.inc
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8d0bdf2f16
+ RiscV: vector registers
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пре 8 месеци |
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rrv32num.inc
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8d0bdf2f16
+ RiscV: vector registers
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пре 8 месеци |
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rrv32rni.inc
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8d0bdf2f16
+ RiscV: vector registers
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пре 8 месеци |
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rrv32sri.inc
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8d0bdf2f16
+ RiscV: vector registers
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пре 8 месеци |
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rrv32sta.inc
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8d0bdf2f16
+ RiscV: vector registers
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пре 8 месеци |
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rrv32std.inc
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8d0bdf2f16
+ RiscV: vector registers
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пре 8 месеци |
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rrv32sup.inc
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8d0bdf2f16
+ RiscV: vector registers
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пре 8 месеци |
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symcpu.pas
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ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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пре 7 година |
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tripletcpu.pas
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eb7ba1690e
* mark all external assemblers using an LLVM tool using af_llvm
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пре 5 година |
florian
57da25581e
+ write .option pic directive if needed