cgcpu.pas 66 KB

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  1. {
  2. Copyright (c) 2008 by Florian Klaempfl
  3. Member of the Free Pascal development team
  4. This unit implements the code generator for the AVR
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. unit cgcpu;
  19. {$i fpcdefs.inc}
  20. interface
  21. uses
  22. globtype,symtype,symdef,
  23. cgbase,cgutils,cgobj,
  24. aasmbase,aasmcpu,aasmtai,aasmdata,
  25. parabase,
  26. cpubase,cpuinfo,node,cg64f32,rgcpu;
  27. type
  28. { tcgavr }
  29. tcgavr = class(tcg)
  30. { true, if the next arithmetic operation should modify the flags }
  31. cgsetflags : boolean;
  32. procedure init_register_allocators;override;
  33. procedure done_register_allocators;override;
  34. function getintregister(list:TAsmList;size:Tcgsize):Tregister;override;
  35. function getaddressregister(list:TAsmList):TRegister;override;
  36. procedure a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);override;
  37. procedure a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);override;
  38. procedure a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);override;
  39. procedure a_load_reg_cgpara(list : TAsmList; size : tcgsize;r : tregister; const cgpara : tcgpara);override;
  40. procedure a_call_name(list : TAsmList;const s : string; weak: boolean);override;
  41. procedure a_call_reg(list : TAsmList;reg: tregister);override;
  42. procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister); override;
  43. procedure a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src, dst : TRegister); override;
  44. { move instructions }
  45. procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);override;
  46. procedure a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
  47. procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
  48. procedure a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
  49. { fpu move instructions }
  50. procedure a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
  51. procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
  52. procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
  53. { comparison operations }
  54. procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
  55. l : tasmlabel);override;
  56. procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
  57. procedure a_jmp_name(list : TAsmList;const s : string); override;
  58. procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
  59. procedure a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel); override;
  60. procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  61. procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
  62. procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
  63. procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
  64. procedure g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);override;
  65. procedure g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  66. procedure g_overflowcheck(list: TAsmList; const l: tlocation; def: tdef); override;
  67. procedure g_save_registers(list : TAsmList);override;
  68. procedure g_restore_registers(list : TAsmList);override;
  69. procedure a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  70. procedure fixref(list : TAsmList;var ref : treference);
  71. function normalize_ref(list : TAsmList;ref : treference;
  72. tmpreg : tregister) : treference;
  73. procedure emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  74. procedure a_adjust_sp(list: TAsmList; value: longint);
  75. function GetLoad(const ref : treference) : tasmop;
  76. function GetStore(const ref: treference): tasmop;
  77. protected
  78. procedure a_op_reg_reg_internal(list: TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
  79. procedure a_op_const_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg, reghi: TRegister);
  80. end;
  81. tcg64favr = class(tcg64f32)
  82. procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  83. procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
  84. end;
  85. procedure create_codegen;
  86. const
  87. TOpCG2AsmOp: Array[topcg] of TAsmOp = (A_NONE,A_MOV,A_ADD,A_AND,A_NONE,
  88. A_NONE,A_MUL,A_MULS,A_NEG,A_COM,A_OR,
  89. A_ASR,A_LSL,A_LSR,A_SUB,A_EOR,A_ROL,A_ROR);
  90. implementation
  91. uses
  92. globals,verbose,systems,cutils,
  93. fmodule,
  94. symconst,symsym,symtable,
  95. tgobj,rgobj,
  96. procinfo,cpupi,
  97. paramgr;
  98. procedure tcgavr.init_register_allocators;
  99. begin
  100. inherited init_register_allocators;
  101. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  102. [RS_R8,RS_R9,
  103. RS_R10,RS_R11,RS_R12,RS_R13,RS_R14,RS_R15,RS_R16,RS_R17,RS_R18,RS_R19,
  104. RS_R20,RS_R21,RS_R22,RS_R23,RS_R24,RS_R25,
  105. RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7],first_int_imreg,[]);
  106. { rg[R_ADDRESSREGISTER]:=trgintcpu.create(R_ADDRESSREGISTER,R_SUBWHOLE,
  107. [RS_R26,RS_R30],first_int_imreg,[]); }
  108. end;
  109. procedure tcgavr.done_register_allocators;
  110. begin
  111. rg[R_INTREGISTER].free;
  112. // rg[R_ADDRESSREGISTER].free;
  113. inherited done_register_allocators;
  114. end;
  115. function tcgavr.getintregister(list: TAsmList; size: Tcgsize): Tregister;
  116. var
  117. tmp1,tmp2,tmp3 : TRegister;
  118. begin
  119. case size of
  120. OS_8,OS_S8:
  121. Result:=inherited getintregister(list, size);
  122. OS_16,OS_S16:
  123. begin
  124. Result:=inherited getintregister(list, OS_8);
  125. { ensure that the high register can be retrieved by
  126. GetNextReg
  127. }
  128. if inherited getintregister(list, OS_8)<>GetNextReg(Result) then
  129. internalerror(2011021331);
  130. end;
  131. OS_32,OS_S32:
  132. begin
  133. Result:=inherited getintregister(list, OS_8);
  134. tmp1:=inherited getintregister(list, OS_8);
  135. { ensure that the high register can be retrieved by
  136. GetNextReg
  137. }
  138. if tmp1<>GetNextReg(Result) then
  139. internalerror(2011021332);
  140. tmp2:=inherited getintregister(list, OS_8);
  141. { ensure that the upper register can be retrieved by
  142. GetNextReg
  143. }
  144. if tmp2<>GetNextReg(tmp1) then
  145. internalerror(2011021333);
  146. tmp3:=inherited getintregister(list, OS_8);
  147. { ensure that the upper register can be retrieved by
  148. GetNextReg
  149. }
  150. if tmp3<>GetNextReg(tmp2) then
  151. internalerror(2011021334);
  152. end;
  153. else
  154. internalerror(2011021330);
  155. end;
  156. end;
  157. function tcgavr.getaddressregister(list: TAsmList): TRegister;
  158. begin
  159. Result:=getintregister(list,OS_ADDR);
  160. end;
  161. procedure tcgavr.a_load_reg_cgpara(list : TAsmList;size : tcgsize;r : tregister;const cgpara : tcgpara);
  162. procedure load_para_loc(r : TRegister;paraloc : PCGParaLocation);
  163. var
  164. ref : treference;
  165. begin
  166. paramanager.allocparaloc(list,paraloc);
  167. case paraloc^.loc of
  168. LOC_REGISTER,LOC_CREGISTER:
  169. a_load_reg_reg(list,paraloc^.size,paraloc^.size,r,paraloc^.register);
  170. LOC_REFERENCE,LOC_CREFERENCE:
  171. begin
  172. reference_reset_base(ref,paraloc^.reference.index,paraloc^.reference.offset,2);
  173. a_load_reg_ref(list,paraloc^.size,paraloc^.size,r,ref);
  174. end;
  175. else
  176. internalerror(2002071004);
  177. end;
  178. end;
  179. var
  180. i, i2 : longint;
  181. hp : PCGParaLocation;
  182. begin
  183. { if use_push(cgpara) then
  184. begin
  185. if tcgsize2size[cgpara.Size] > 2 then
  186. begin
  187. if tcgsize2size[cgpara.Size] <> 4 then
  188. internalerror(2013031101);
  189. if cgpara.location^.Next = nil then
  190. begin
  191. if tcgsize2size[cgpara.location^.size] <> 4 then
  192. internalerror(2013031101);
  193. end
  194. else
  195. begin
  196. if tcgsize2size[cgpara.location^.size] <> 2 then
  197. internalerror(2013031101);
  198. if tcgsize2size[cgpara.location^.Next^.size] <> 2 then
  199. internalerror(2013031101);
  200. if cgpara.location^.Next^.Next <> nil then
  201. internalerror(2013031101);
  202. end;
  203. if tcgsize2size[cgpara.size]>cgpara.alignment then
  204. pushsize:=cgpara.size
  205. else
  206. pushsize:=int_cgsize(cgpara.alignment);
  207. pushsize2 := int_cgsize(tcgsize2size[pushsize] - 2);
  208. list.concat(taicpu.op_reg(A_PUSH,TCgsize2opsize[pushsize2],makeregsize(list,GetNextReg(r),pushsize2)));
  209. list.concat(taicpu.op_reg(A_PUSH,S_W,makeregsize(list,r,OS_16)));
  210. end
  211. else
  212. begin
  213. cgpara.check_simple_location;
  214. if tcgsize2size[cgpara.location^.size]>cgpara.alignment then
  215. pushsize:=cgpara.location^.size
  216. else
  217. pushsize:=int_cgsize(cgpara.alignment);
  218. list.concat(taicpu.op_reg(A_PUSH,TCgsize2opsize[pushsize],makeregsize(list,r,pushsize)));
  219. end;
  220. end
  221. else }
  222. begin
  223. if not(tcgsize2size[cgpara.Size] in [1..4]) then
  224. internalerror(2014011101);
  225. hp:=cgpara.location;
  226. i:=0;
  227. while i<tcgsize2size[cgpara.Size] do
  228. begin
  229. if not(assigned(hp)) then
  230. internalerror(2014011102);
  231. inc(i, tcgsize2size[hp^.Size]);
  232. if hp^.Loc=LOC_REGISTER then
  233. begin
  234. load_para_loc(r,hp);
  235. hp:=hp^.Next;
  236. r:=GetNextReg(r);
  237. end
  238. else
  239. begin
  240. load_para_loc(r,hp);
  241. for i2:=1 to tcgsize2size[hp^.Size] do
  242. r:=GetNextReg(r);
  243. hp:=hp^.Next;
  244. end;
  245. end;
  246. if assigned(hp) then
  247. internalerror(2014011103);
  248. end;
  249. end;
  250. procedure tcgavr.a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);
  251. var
  252. i : longint;
  253. hp : PCGParaLocation;
  254. begin
  255. if not(tcgsize2size[paraloc.Size] in [1..4]) then
  256. internalerror(2014011101);
  257. hp:=paraloc.location;
  258. for i:=1 to tcgsize2size[paraloc.Size] do
  259. begin
  260. if not(assigned(hp)) or
  261. (tcgsize2size[hp^.size]<>1) or
  262. (hp^.shiftval<>0) then
  263. internalerror(2014011105);
  264. case hp^.loc of
  265. LOC_REGISTER,LOC_CREGISTER:
  266. a_load_const_reg(list,hp^.size,(a shr (i-1)) and $ff,hp^.register);
  267. LOC_REFERENCE,LOC_CREFERENCE:
  268. begin
  269. list.concat(taicpu.op_const(A_PUSH,(a shr (i-1)) and $ff));
  270. end;
  271. else
  272. internalerror(2002071004);
  273. end;
  274. hp:=hp^.Next;
  275. end;
  276. if assigned(hp) then
  277. internalerror(2014011104);
  278. end;
  279. procedure tcgavr.a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);
  280. var
  281. tmpref, ref: treference;
  282. location: pcgparalocation;
  283. sizeleft: tcgint;
  284. begin
  285. location := paraloc.location;
  286. tmpref := r;
  287. sizeleft := paraloc.intsize;
  288. while assigned(location) do
  289. begin
  290. paramanager.allocparaloc(list,location);
  291. case location^.loc of
  292. LOC_REGISTER,LOC_CREGISTER:
  293. a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
  294. LOC_REFERENCE:
  295. begin
  296. reference_reset_base(ref,location^.reference.index,location^.reference.offset,paraloc.alignment);
  297. { doubles in softemu mode have a strange order of registers and references }
  298. if location^.size=OS_32 then
  299. g_concatcopy(list,tmpref,ref,4)
  300. else
  301. begin
  302. g_concatcopy(list,tmpref,ref,sizeleft);
  303. if assigned(location^.next) then
  304. internalerror(2005010710);
  305. end;
  306. end;
  307. LOC_VOID:
  308. begin
  309. // nothing to do
  310. end;
  311. else
  312. internalerror(2002081103);
  313. end;
  314. inc(tmpref.offset,tcgsize2size[location^.size]);
  315. dec(sizeleft,tcgsize2size[location^.size]);
  316. location := location^.next;
  317. end;
  318. end;
  319. procedure tcgavr.a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);
  320. var
  321. tmpreg: tregister;
  322. begin
  323. tmpreg:=getaddressregister(list);
  324. a_loadaddr_ref_reg(list,r,tmpreg);
  325. a_load_reg_cgpara(list,OS_ADDR,tmpreg,paraloc);
  326. end;
  327. procedure tcgavr.a_call_name(list : TAsmList;const s : string; weak: boolean);
  328. begin
  329. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  330. list.concat(taicpu.op_sym(A_CALL,current_asmdata.RefAsmSymbol(s)))
  331. else
  332. list.concat(taicpu.op_sym(A_RCALL,current_asmdata.RefAsmSymbol(s)));
  333. include(current_procinfo.flags,pi_do_call);
  334. end;
  335. procedure tcgavr.a_call_reg(list : TAsmList;reg: tregister);
  336. begin
  337. a_reg_alloc(list,NR_ZLO);
  338. a_reg_alloc(list,NR_ZHI);
  339. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZLO,reg));
  340. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZHI,GetHigh(reg)));
  341. list.concat(taicpu.op_none(A_ICALL));
  342. a_reg_dealloc(list,NR_ZLO);
  343. a_reg_dealloc(list,NR_ZHI);
  344. include(current_procinfo.flags,pi_do_call);
  345. end;
  346. procedure tcgavr.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister);
  347. begin
  348. if not(size in [OS_S8,OS_8,OS_S16,OS_16,OS_S32,OS_32]) then
  349. internalerror(2012102403);
  350. a_op_const_reg_internal(list,Op,size,a,reg,NR_NO);
  351. end;
  352. procedure tcgavr.a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src, dst : TRegister);
  353. begin
  354. if not(size in [OS_S8,OS_8,OS_S16,OS_16,OS_S32,OS_32]) then
  355. internalerror(2012102401);
  356. a_op_reg_reg_internal(list,Op,size,src,NR_NO,dst,NR_NO);
  357. end;
  358. procedure tcgavr.a_op_reg_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
  359. var
  360. countreg,
  361. tmpreg: tregister;
  362. i : integer;
  363. instr : taicpu;
  364. paraloc1,paraloc2,paraloc3 : TCGPara;
  365. l1,l2 : tasmlabel;
  366. pd : tprocdef;
  367. procedure NextSrcDst;
  368. begin
  369. if i=5 then
  370. begin
  371. dst:=dsthi;
  372. src:=srchi;
  373. end
  374. else
  375. begin
  376. dst:=GetNextReg(dst);
  377. src:=GetNextReg(src);
  378. end;
  379. end;
  380. { iterates TmpReg through all registers of dst }
  381. procedure NextTmp;
  382. begin
  383. if i=5 then
  384. tmpreg:=dsthi
  385. else
  386. tmpreg:=GetNextReg(tmpreg);
  387. end;
  388. begin
  389. case op of
  390. OP_ADD:
  391. begin
  392. list.concat(taicpu.op_reg_reg(A_ADD,dst,src));
  393. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  394. begin
  395. for i:=2 to tcgsize2size[size] do
  396. begin
  397. NextSrcDst;
  398. list.concat(taicpu.op_reg_reg(A_ADC,dst,src));
  399. end;
  400. end;
  401. end;
  402. OP_SUB:
  403. begin
  404. list.concat(taicpu.op_reg_reg(A_SUB,dst,src));
  405. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  406. begin
  407. for i:=2 to tcgsize2size[size] do
  408. begin
  409. NextSrcDst;
  410. list.concat(taicpu.op_reg_reg(A_SBC,dst,src));
  411. end;
  412. end;
  413. end;
  414. OP_NEG:
  415. begin
  416. if src<>dst then
  417. begin
  418. if size in [OS_S64,OS_64] then
  419. begin
  420. a_load_reg_reg(list,OS_32,OS_32,src,dst);
  421. a_load_reg_reg(list,OS_32,OS_32,srchi,dsthi);
  422. end
  423. else
  424. a_load_reg_reg(list,size,size,src,dst);
  425. end;
  426. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  427. begin
  428. tmpreg:=GetNextReg(dst);
  429. for i:=2 to tcgsize2size[size] do
  430. begin
  431. list.concat(taicpu.op_reg(A_COM,tmpreg));
  432. NextTmp;
  433. end;
  434. list.concat(taicpu.op_reg(A_NEG,dst));
  435. tmpreg:=GetNextReg(dst);
  436. for i:=2 to tcgsize2size[size] do
  437. begin
  438. list.concat(taicpu.op_reg_const(A_SBCI,tmpreg,-1));
  439. NextTmp;
  440. end;
  441. end;
  442. end;
  443. OP_NOT:
  444. begin
  445. for i:=1 to tcgsize2size[size] do
  446. begin
  447. if src<>dst then
  448. a_load_reg_reg(list,OS_8,OS_8,src,dst);
  449. list.concat(taicpu.op_reg(A_COM,dst));
  450. NextSrcDst;
  451. end;
  452. end;
  453. OP_MUL,OP_IMUL:
  454. begin
  455. if size in [OS_8,OS_S8] then
  456. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src))
  457. else if size=OS_16 then
  458. begin
  459. pd:=search_system_proc('fpc_mul_word');
  460. paraloc1.init;
  461. paraloc2.init;
  462. paraloc3.init;
  463. paramanager.getintparaloc(pd,1,paraloc1);
  464. paramanager.getintparaloc(pd,2,paraloc2);
  465. paramanager.getintparaloc(pd,3,paraloc3);
  466. a_load_const_cgpara(list,OS_8,0,paraloc3);
  467. a_load_reg_cgpara(list,OS_16,src,paraloc2);
  468. a_load_reg_cgpara(list,OS_16,dst,paraloc1);
  469. paramanager.freecgpara(list,paraloc3);
  470. paramanager.freecgpara(list,paraloc2);
  471. paramanager.freecgpara(list,paraloc1);
  472. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  473. a_call_name(list,'FPC_MUL_WORD',false);
  474. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  475. cg.a_reg_alloc(list,NR_FUNCTION_RESULT_REG);
  476. cg.a_load_reg_reg(list,OS_16,OS_16,NR_FUNCTION_RESULT_REG,dst);
  477. paraloc3.done;
  478. paraloc2.done;
  479. paraloc1.done;
  480. end
  481. else
  482. internalerror(2011022002);
  483. end;
  484. OP_DIV,OP_IDIV:
  485. { special stuff, needs separate handling inside code }
  486. { generator }
  487. internalerror(2011022001);
  488. OP_SHR,OP_SHL,OP_SAR,OP_ROL,OP_ROR:
  489. begin
  490. current_asmdata.getjumplabel(l1);
  491. current_asmdata.getjumplabel(l2);
  492. countreg:=getintregister(list,OS_8);
  493. a_load_reg_reg(list,size,OS_8,src,countreg);
  494. list.concat(taicpu.op_reg_const(A_CPI,countreg,0));
  495. a_jmp_flags(list,F_EQ,l2);
  496. cg.a_label(list,l1);
  497. case op of
  498. OP_SHR:
  499. list.concat(taicpu.op_reg(A_LSR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  500. OP_SHL:
  501. list.concat(taicpu.op_reg(A_LSL,dst));
  502. OP_SAR:
  503. list.concat(taicpu.op_reg(A_ASR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  504. OP_ROR:
  505. begin
  506. { load carry? }
  507. if not(size in [OS_8,OS_S8]) then
  508. begin
  509. list.concat(taicpu.op_none(A_CLC));
  510. list.concat(taicpu.op_reg_const(A_SBRC,src,0));
  511. list.concat(taicpu.op_none(A_SEC));
  512. end;
  513. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  514. end;
  515. OP_ROL:
  516. begin
  517. { load carry? }
  518. if not(size in [OS_8,OS_S8]) then
  519. begin
  520. list.concat(taicpu.op_none(A_CLC));
  521. list.concat(taicpu.op_reg_const(A_SBRC,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1),7));
  522. list.concat(taicpu.op_none(A_SEC));
  523. end;
  524. list.concat(taicpu.op_reg(A_ROL,dst))
  525. end;
  526. else
  527. internalerror(2011030901);
  528. end;
  529. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  530. begin
  531. for i:=2 to tcgsize2size[size] do
  532. begin
  533. case op of
  534. OP_ROR,
  535. OP_SHR:
  536. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  537. OP_ROL,
  538. OP_SHL:
  539. list.concat(taicpu.op_reg(A_ROL,GetOffsetReg64(dst,dsthi,i-1)));
  540. OP_SAR:
  541. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  542. else
  543. internalerror(2011030902);
  544. end;
  545. end;
  546. end;
  547. a_op_const_reg(list,OP_SUB,OS_8,1,countreg);
  548. a_jmp_flags(list,F_NE,l1);
  549. // keep registers alive
  550. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  551. cg.a_label(list,l2);
  552. end;
  553. OP_AND,OP_OR,OP_XOR:
  554. begin
  555. for i:=1 to tcgsize2size[size] do
  556. begin
  557. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src));
  558. NextSrcDst;
  559. end;
  560. end;
  561. else
  562. internalerror(2011022004);
  563. end;
  564. end;
  565. procedure tcgavr.a_op_const_reg_internal(list: TAsmList; Op: TOpCG;
  566. size: TCGSize; a: tcgint; reg, reghi: TRegister);
  567. var
  568. mask : qword;
  569. shift : byte;
  570. i : byte;
  571. tmpreg : tregister;
  572. tmpreg64 : tregister64;
  573. procedure NextReg;
  574. begin
  575. if i=5 then
  576. reg:=reghi
  577. else
  578. reg:=GetNextReg(reg);
  579. end;
  580. begin
  581. mask:=$ff;
  582. shift:=0;
  583. case op of
  584. OP_OR:
  585. begin
  586. for i:=1 to tcgsize2size[size] do
  587. begin
  588. list.concat(taicpu.op_reg_const(A_ORI,reg,(a and mask) shr shift));
  589. NextReg;
  590. mask:=mask shl 8;
  591. inc(shift,8);
  592. end;
  593. end;
  594. OP_AND:
  595. begin
  596. for i:=1 to tcgsize2size[size] do
  597. begin
  598. list.concat(taicpu.op_reg_const(A_ANDI,reg,(a and mask) shr shift));
  599. NextReg;
  600. mask:=mask shl 8;
  601. inc(shift,8);
  602. end;
  603. end;
  604. OP_SUB:
  605. begin
  606. list.concat(taicpu.op_reg_const(A_SUBI,reg,a and mask));
  607. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  608. begin
  609. for i:=2 to tcgsize2size[size] do
  610. begin
  611. NextReg;
  612. mask:=mask shl 8;
  613. inc(shift,8);
  614. list.concat(taicpu.op_reg_const(A_SBCI,reg,(a and mask) shr shift));
  615. end;
  616. end;
  617. end;
  618. {OP_ADD:
  619. begin
  620. list.concat(taicpu.op_reg_const(A_SUBI,reg,(-a) and mask));
  621. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  622. begin
  623. for i:=2 to tcgsize2size[size] do
  624. begin
  625. NextReg;
  626. mask:=mask shl 8;
  627. inc(shift,8);
  628. list.concat(taicpu.op_reg_const(A_ADC,reg,(a and mask) shr shift));
  629. end;
  630. end;
  631. end; }
  632. else
  633. begin
  634. if size in [OS_64,OS_S64] then
  635. begin
  636. tmpreg64.reglo:=getintregister(list,OS_32);
  637. tmpreg64.reghi:=getintregister(list,OS_32);
  638. cg64.a_load64_const_reg(list,a,tmpreg64);
  639. cg64.a_op64_reg_reg(list,op,size,tmpreg64,joinreg64(reg,reghi));
  640. end
  641. else
  642. begin
  643. tmpreg:=getintregister(list,size);
  644. a_load_const_reg(list,size,a,tmpreg);
  645. a_op_reg_reg(list,op,size,tmpreg,reg);
  646. end;
  647. end;
  648. end;
  649. end;
  650. procedure tcgavr.a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);
  651. var
  652. mask : qword;
  653. shift : byte;
  654. i : byte;
  655. begin
  656. mask:=$ff;
  657. shift:=0;
  658. for i:=1 to tcgsize2size[size] do
  659. begin
  660. if ((qword(a) and mask) shr shift)=0 then
  661. emit_mov(list,reg,NR_R1)
  662. else
  663. list.concat(taicpu.op_reg_const(A_LDI,reg,(qword(a) and mask) shr shift));
  664. mask:=mask shl 8;
  665. inc(shift,8);
  666. reg:=GetNextReg(reg);
  667. end;
  668. end;
  669. function tcgavr.normalize_ref(list:TAsmList;ref: treference;tmpreg : tregister) : treference;
  670. procedure maybegetcpuregister(list:tasmlist;reg : tregister);
  671. begin
  672. { allocate the register only, if a cpu register is passed }
  673. if getsupreg(reg)<first_int_imreg then
  674. getcpuregister(list,reg);
  675. end;
  676. var
  677. tmpref : treference;
  678. l : tasmlabel;
  679. begin
  680. Result:=ref;
  681. if ref.addressmode<>AM_UNCHANGED then
  682. internalerror(2011021701);
  683. { Be sure to have a base register }
  684. if (ref.base=NR_NO) then
  685. begin
  686. { only symbol+offset? }
  687. if ref.index=NR_NO then
  688. exit;
  689. ref.base:=ref.index;
  690. ref.index:=NR_NO;
  691. end;
  692. if assigned(ref.symbol) or (ref.offset<>0) then
  693. begin
  694. reference_reset(tmpref,0);
  695. tmpref.symbol:=ref.symbol;
  696. tmpref.offset:=ref.offset;
  697. tmpref.refaddr:=addr_lo8;
  698. maybegetcpuregister(list,tmpreg);
  699. list.concat(taicpu.op_reg_ref(A_LDI,tmpreg,tmpref));
  700. tmpref.refaddr:=addr_hi8;
  701. maybegetcpuregister(list,GetNextReg(tmpreg));
  702. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(tmpreg),tmpref));
  703. if (ref.base<>NR_NO) then
  704. begin
  705. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
  706. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
  707. end;
  708. if (ref.index<>NR_NO) then
  709. begin
  710. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  711. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  712. end;
  713. ref.symbol:=nil;
  714. ref.offset:=0;
  715. ref.base:=tmpreg;
  716. ref.index:=NR_NO;
  717. end
  718. else if (ref.base<>NR_NO) and (ref.index<>NR_NO) then
  719. begin
  720. maybegetcpuregister(list,tmpreg);
  721. emit_mov(list,tmpreg,ref.base);
  722. maybegetcpuregister(list,GetNextReg(tmpreg));
  723. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  724. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  725. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  726. ref.base:=tmpreg;
  727. ref.index:=NR_NO;
  728. end
  729. else if (ref.base<>NR_NO) then
  730. begin
  731. maybegetcpuregister(list,tmpreg);
  732. emit_mov(list,tmpreg,ref.base);
  733. maybegetcpuregister(list,GetNextReg(tmpreg));
  734. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  735. ref.base:=tmpreg;
  736. ref.index:=NR_NO;
  737. end
  738. else if (ref.index<>NR_NO) then
  739. begin
  740. maybegetcpuregister(list,tmpreg);
  741. emit_mov(list,tmpreg,ref.index);
  742. maybegetcpuregister(list,GetNextReg(tmpreg));
  743. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
  744. ref.base:=tmpreg;
  745. ref.index:=NR_NO;
  746. end;
  747. Result:=ref;
  748. end;
  749. procedure tcgavr.a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);
  750. var
  751. href : treference;
  752. conv_done: boolean;
  753. tmpreg : tregister;
  754. i : integer;
  755. QuickRef : Boolean;
  756. begin
  757. QuickRef:=false;
  758. if not((Ref.addressmode=AM_UNCHANGED) and
  759. (Ref.symbol=nil) and
  760. ((Ref.base=NR_R28) or
  761. (Ref.base=NR_R29)) and
  762. (Ref.Index=NR_No) and
  763. (Ref.Offset in [0..64-tcgsize2size[tosize]])) and
  764. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  765. href:=normalize_ref(list,Ref,NR_R30)
  766. else
  767. begin
  768. QuickRef:=true;
  769. href:=Ref;
  770. end;
  771. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  772. internalerror(2011021307);
  773. conv_done:=false;
  774. if tosize<>fromsize then
  775. begin
  776. conv_done:=true;
  777. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  778. fromsize:=tosize;
  779. case fromsize of
  780. OS_8:
  781. begin
  782. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  783. href.addressmode:=AM_POSTINCREMENT;
  784. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  785. for i:=2 to tcgsize2size[tosize] do
  786. begin
  787. if QuickRef then
  788. inc(href.offset);
  789. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  790. href.addressmode:=AM_POSTINCREMENT
  791. else
  792. href.addressmode:=AM_UNCHANGED;
  793. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  794. end;
  795. end;
  796. OS_S8:
  797. begin
  798. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  799. href.addressmode:=AM_POSTINCREMENT;
  800. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  801. if tcgsize2size[tosize]>1 then
  802. begin
  803. tmpreg:=getintregister(list,OS_8);
  804. list.concat(taicpu.op_reg(A_CLR,tmpreg));
  805. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  806. list.concat(taicpu.op_reg(A_COM,tmpreg));
  807. for i:=2 to tcgsize2size[tosize] do
  808. begin
  809. if QuickRef then
  810. inc(href.offset);
  811. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  812. href.addressmode:=AM_POSTINCREMENT
  813. else
  814. href.addressmode:=AM_UNCHANGED;
  815. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  816. end;
  817. end;
  818. end;
  819. OS_16:
  820. begin
  821. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  822. href.addressmode:=AM_POSTINCREMENT;
  823. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  824. if QuickRef then
  825. inc(href.offset)
  826. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  827. href.addressmode:=AM_POSTINCREMENT
  828. else
  829. href.addressmode:=AM_UNCHANGED;
  830. reg:=GetNextReg(reg);
  831. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  832. for i:=3 to tcgsize2size[tosize] do
  833. begin
  834. if QuickRef then
  835. inc(href.offset);
  836. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  837. href.addressmode:=AM_POSTINCREMENT
  838. else
  839. href.addressmode:=AM_UNCHANGED;
  840. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  841. end;
  842. end;
  843. OS_S16:
  844. begin
  845. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  846. href.addressmode:=AM_POSTINCREMENT;
  847. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  848. if QuickRef then
  849. inc(href.offset)
  850. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  851. href.addressmode:=AM_POSTINCREMENT
  852. else
  853. href.addressmode:=AM_UNCHANGED;
  854. reg:=GetNextReg(reg);
  855. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  856. if tcgsize2size[tosize]>2 then
  857. begin
  858. tmpreg:=getintregister(list,OS_8);
  859. list.concat(taicpu.op_reg(A_CLR,tmpreg));
  860. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  861. list.concat(taicpu.op_reg(A_COM,tmpreg));
  862. for i:=3 to tcgsize2size[tosize] do
  863. begin
  864. if QuickRef then
  865. inc(href.offset);
  866. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  867. href.addressmode:=AM_POSTINCREMENT
  868. else
  869. href.addressmode:=AM_UNCHANGED;
  870. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  871. end;
  872. end;
  873. end;
  874. else
  875. conv_done:=false;
  876. end;
  877. end;
  878. if not conv_done then
  879. begin
  880. for i:=1 to tcgsize2size[fromsize] do
  881. begin
  882. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  883. href.addressmode:=AM_POSTINCREMENT
  884. else
  885. href.addressmode:=AM_UNCHANGED;
  886. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  887. if QuickRef then
  888. inc(href.offset);
  889. reg:=GetNextReg(reg);
  890. end;
  891. end;
  892. if not(QuickRef) then
  893. begin
  894. ungetcpuregister(list,href.base);
  895. ungetcpuregister(list,GetNextReg(href.base));
  896. end;
  897. end;
  898. procedure tcgavr.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;
  899. const Ref : treference;reg : tregister);
  900. var
  901. href : treference;
  902. conv_done: boolean;
  903. tmpreg : tregister;
  904. i : integer;
  905. QuickRef : boolean;
  906. begin
  907. QuickRef:=false;
  908. if not((Ref.addressmode=AM_UNCHANGED) and
  909. (Ref.symbol=nil) and
  910. ((Ref.base=NR_R28) or
  911. (Ref.base=NR_R29)) and
  912. (Ref.Index=NR_No) and
  913. (Ref.Offset in [0..64-tcgsize2size[fromsize]])) and
  914. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  915. href:=normalize_ref(list,Ref,NR_R30)
  916. else
  917. begin
  918. QuickRef:=true;
  919. href:=Ref;
  920. end;
  921. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  922. internalerror(2011021307);
  923. conv_done:=false;
  924. if tosize<>fromsize then
  925. begin
  926. conv_done:=true;
  927. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  928. fromsize:=tosize;
  929. case fromsize of
  930. OS_8:
  931. begin
  932. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  933. for i:=2 to tcgsize2size[tosize] do
  934. begin
  935. reg:=GetNextReg(reg);
  936. list.concat(taicpu.op_reg(A_CLR,reg));
  937. end;
  938. end;
  939. OS_S8:
  940. begin
  941. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  942. tmpreg:=reg;
  943. if tcgsize2size[tosize]>1 then
  944. begin
  945. reg:=GetNextReg(reg);
  946. list.concat(taicpu.op_reg(A_CLR,reg));
  947. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  948. list.concat(taicpu.op_reg(A_COM,reg));
  949. tmpreg:=reg;
  950. for i:=3 to tcgsize2size[tosize] do
  951. begin
  952. reg:=GetNextReg(reg);
  953. emit_mov(list,reg,tmpreg);
  954. end;
  955. end;
  956. end;
  957. OS_16:
  958. begin
  959. if not(QuickRef) then
  960. href.addressmode:=AM_POSTINCREMENT;
  961. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  962. if QuickRef then
  963. inc(href.offset);
  964. href.addressmode:=AM_UNCHANGED;
  965. reg:=GetNextReg(reg);
  966. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  967. for i:=3 to tcgsize2size[tosize] do
  968. begin
  969. reg:=GetNextReg(reg);
  970. list.concat(taicpu.op_reg(A_CLR,reg));
  971. end;
  972. end;
  973. OS_S16:
  974. begin
  975. if not(QuickRef) then
  976. href.addressmode:=AM_POSTINCREMENT;
  977. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  978. if QuickRef then
  979. inc(href.offset);
  980. href.addressmode:=AM_UNCHANGED;
  981. reg:=GetNextReg(reg);
  982. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  983. tmpreg:=reg;
  984. reg:=GetNextReg(reg);
  985. list.concat(taicpu.op_reg(A_CLR,reg));
  986. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  987. list.concat(taicpu.op_reg(A_COM,reg));
  988. tmpreg:=reg;
  989. for i:=4 to tcgsize2size[tosize] do
  990. begin
  991. reg:=GetNextReg(reg);
  992. emit_mov(list,reg,tmpreg);
  993. end;
  994. end;
  995. else
  996. conv_done:=false;
  997. end;
  998. end;
  999. if not conv_done then
  1000. begin
  1001. for i:=1 to tcgsize2size[fromsize] do
  1002. begin
  1003. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  1004. href.addressmode:=AM_POSTINCREMENT
  1005. else
  1006. href.addressmode:=AM_UNCHANGED;
  1007. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1008. if QuickRef then
  1009. inc(href.offset);
  1010. reg:=GetNextReg(reg);
  1011. end;
  1012. end;
  1013. if not(QuickRef) then
  1014. begin
  1015. ungetcpuregister(list,href.base);
  1016. ungetcpuregister(list,GetNextReg(href.base));
  1017. end;
  1018. end;
  1019. procedure tcgavr.a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);
  1020. var
  1021. conv_done: boolean;
  1022. tmpreg : tregister;
  1023. i : integer;
  1024. begin
  1025. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  1026. internalerror(2011021310);
  1027. conv_done:=false;
  1028. if tosize<>fromsize then
  1029. begin
  1030. conv_done:=true;
  1031. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  1032. fromsize:=tosize;
  1033. case fromsize of
  1034. OS_8:
  1035. begin
  1036. emit_mov(list,reg2,reg1);
  1037. for i:=2 to tcgsize2size[tosize] do
  1038. begin
  1039. reg2:=GetNextReg(reg2);
  1040. list.concat(taicpu.op_reg(A_CLR,reg2));
  1041. end;
  1042. end;
  1043. OS_S8:
  1044. begin
  1045. emit_mov(list,reg2,reg1);
  1046. if tcgsize2size[tosize]>1 then
  1047. begin
  1048. reg2:=GetNextReg(reg2);
  1049. list.concat(taicpu.op_reg(A_CLR,reg2));
  1050. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  1051. list.concat(taicpu.op_reg(A_COM,reg2));
  1052. tmpreg:=reg2;
  1053. for i:=3 to tcgsize2size[tosize] do
  1054. begin
  1055. reg2:=GetNextReg(reg2);
  1056. emit_mov(list,reg2,tmpreg);
  1057. end;
  1058. end;
  1059. end;
  1060. OS_16:
  1061. begin
  1062. emit_mov(list,reg2,reg1);
  1063. reg1:=GetNextReg(reg1);
  1064. reg2:=GetNextReg(reg2);
  1065. emit_mov(list,reg2,reg1);
  1066. for i:=3 to tcgsize2size[tosize] do
  1067. begin
  1068. reg2:=GetNextReg(reg2);
  1069. list.concat(taicpu.op_reg(A_CLR,reg2));
  1070. end;
  1071. end;
  1072. OS_S16:
  1073. begin
  1074. emit_mov(list,reg2,reg1);
  1075. reg1:=GetNextReg(reg1);
  1076. reg2:=GetNextReg(reg2);
  1077. emit_mov(list,reg2,reg1);
  1078. if tcgsize2size[tosize]>2 then
  1079. begin
  1080. reg2:=GetNextReg(reg2);
  1081. list.concat(taicpu.op_reg(A_CLR,reg2));
  1082. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  1083. list.concat(taicpu.op_reg(A_COM,reg2));
  1084. tmpreg:=reg2;
  1085. for i:=4 to tcgsize2size[tosize] do
  1086. begin
  1087. reg2:=GetNextReg(reg2);
  1088. emit_mov(list,reg2,tmpreg);
  1089. end;
  1090. end;
  1091. end;
  1092. else
  1093. conv_done:=false;
  1094. end;
  1095. end;
  1096. if not conv_done and (reg1<>reg2) then
  1097. begin
  1098. for i:=1 to tcgsize2size[fromsize] do
  1099. begin
  1100. emit_mov(list,reg2,reg1);
  1101. reg1:=GetNextReg(reg1);
  1102. reg2:=GetNextReg(reg2);
  1103. end;
  1104. end;
  1105. end;
  1106. procedure tcgavr.a_loadfpu_reg_reg(list: TAsmList; fromsize,tosize: tcgsize; reg1, reg2: tregister);
  1107. begin
  1108. internalerror(2012010702);
  1109. end;
  1110. procedure tcgavr.a_loadfpu_ref_reg(list: TAsmList; fromsize,tosize: tcgsize; const ref: treference; reg: tregister);
  1111. begin
  1112. internalerror(2012010703);
  1113. end;
  1114. procedure tcgavr.a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference);
  1115. begin
  1116. internalerror(2012010704);
  1117. end;
  1118. { comparison operations }
  1119. procedure tcgavr.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;
  1120. cmp_op : topcmp;a : tcgint;reg : tregister;l : tasmlabel);
  1121. var
  1122. swapped : boolean;
  1123. tmpreg : tregister;
  1124. i : byte;
  1125. begin
  1126. if a=0 then
  1127. begin
  1128. swapped:=false;
  1129. { swap parameters? }
  1130. case cmp_op of
  1131. OC_GT:
  1132. begin
  1133. swapped:=true;
  1134. cmp_op:=OC_LT;
  1135. end;
  1136. OC_LTE:
  1137. begin
  1138. swapped:=true;
  1139. cmp_op:=OC_GTE;
  1140. end;
  1141. OC_BE:
  1142. begin
  1143. swapped:=true;
  1144. cmp_op:=OC_AE;
  1145. end;
  1146. OC_A:
  1147. begin
  1148. swapped:=true;
  1149. cmp_op:=OC_B;
  1150. end;
  1151. end;
  1152. if swapped then
  1153. list.concat(taicpu.op_reg_reg(A_CP,reg,NR_R1))
  1154. else
  1155. list.concat(taicpu.op_reg_reg(A_CP,NR_R1,reg));
  1156. for i:=2 to tcgsize2size[size] do
  1157. begin
  1158. reg:=GetNextReg(reg);
  1159. if swapped then
  1160. list.concat(taicpu.op_reg_reg(A_CPC,reg,NR_R1))
  1161. else
  1162. list.concat(taicpu.op_reg_reg(A_CPC,NR_R1,reg));
  1163. end;
  1164. a_jmp_cond(list,cmp_op,l);
  1165. end
  1166. else
  1167. inherited a_cmp_const_reg_label(list,size,cmp_op,a,reg,l);
  1168. end;
  1169. procedure tcgavr.a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;
  1170. cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
  1171. var
  1172. swapped : boolean;
  1173. tmpreg : tregister;
  1174. i : byte;
  1175. begin
  1176. swapped:=false;
  1177. { swap parameters? }
  1178. case cmp_op of
  1179. OC_GT:
  1180. begin
  1181. swapped:=true;
  1182. cmp_op:=OC_LT;
  1183. end;
  1184. OC_LTE:
  1185. begin
  1186. swapped:=true;
  1187. cmp_op:=OC_GTE;
  1188. end;
  1189. OC_BE:
  1190. begin
  1191. swapped:=true;
  1192. cmp_op:=OC_AE;
  1193. end;
  1194. OC_A:
  1195. begin
  1196. swapped:=true;
  1197. cmp_op:=OC_B;
  1198. end;
  1199. end;
  1200. if swapped then
  1201. begin
  1202. tmpreg:=reg1;
  1203. reg1:=reg2;
  1204. reg2:=tmpreg;
  1205. end;
  1206. list.concat(taicpu.op_reg_reg(A_CP,reg2,reg1));
  1207. for i:=2 to tcgsize2size[size] do
  1208. begin
  1209. reg1:=GetNextReg(reg1);
  1210. reg2:=GetNextReg(reg2);
  1211. list.concat(taicpu.op_reg_reg(A_CPC,reg2,reg1));
  1212. end;
  1213. a_jmp_cond(list,cmp_op,l);
  1214. end;
  1215. procedure tcgavr.a_jmp_name(list : TAsmList;const s : string);
  1216. var
  1217. ai : taicpu;
  1218. begin
  1219. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  1220. ai:=taicpu.op_sym(A_JMP,current_asmdata.RefAsmSymbol(s))
  1221. else
  1222. ai:=taicpu.op_sym(A_RJMP,current_asmdata.RefAsmSymbol(s));
  1223. ai.is_jmp:=true;
  1224. list.concat(ai);
  1225. end;
  1226. procedure tcgavr.a_jmp_always(list : TAsmList;l: tasmlabel);
  1227. var
  1228. ai : taicpu;
  1229. begin
  1230. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  1231. ai:=taicpu.op_sym(A_JMP,l)
  1232. else
  1233. ai:=taicpu.op_sym(A_RJMP,l);
  1234. ai.is_jmp:=true;
  1235. list.concat(ai);
  1236. end;
  1237. procedure tcgavr.a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel);
  1238. var
  1239. ai : taicpu;
  1240. begin
  1241. ai:=setcondition(taicpu.op_sym(A_BRxx,l),flags_to_cond(f));
  1242. ai.is_jmp:=true;
  1243. list.concat(ai);
  1244. end;
  1245. procedure tcgavr.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
  1246. var
  1247. l : TAsmLabel;
  1248. tmpflags : TResFlags;
  1249. begin
  1250. current_asmdata.getjumplabel(l);
  1251. {
  1252. if flags_to_cond(f) then
  1253. begin
  1254. tmpflags:=f;
  1255. inverse_flags(tmpflags);
  1256. list.concat(taicpu.op_reg(A_CLR,reg));
  1257. a_jmp_flags(list,tmpflags,l);
  1258. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1259. end
  1260. else
  1261. }
  1262. begin
  1263. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1264. a_jmp_flags(list,f,l);
  1265. list.concat(taicpu.op_reg(A_CLR,reg));
  1266. end;
  1267. cg.a_label(list,l);
  1268. end;
  1269. procedure tcgavr.a_adjust_sp(list : TAsmList; value : longint);
  1270. var
  1271. i : integer;
  1272. begin
  1273. case value of
  1274. 0:
  1275. ;
  1276. {-14..-1:
  1277. begin
  1278. if ((-value) mod 2)<>0 then
  1279. list.concat(taicpu.op_reg(A_PUSH,NR_R0));
  1280. for i:=1 to (-value) div 2 do
  1281. list.concat(taicpu.op_const(A_RCALL,0));
  1282. end;
  1283. 1..7:
  1284. begin
  1285. for i:=1 to value do
  1286. list.concat(taicpu.op_reg(A_POP,NR_R0));
  1287. end;}
  1288. else
  1289. begin
  1290. list.concat(taicpu.op_reg_const(A_SUBI,NR_R28,lo(word(-value))));
  1291. list.concat(taicpu.op_reg_const(A_SBCI,NR_R29,hi(word(-value))));
  1292. // get SREG
  1293. list.concat(taicpu.op_reg_const(A_IN,NR_R0,NIO_SREG));
  1294. // block interrupts
  1295. list.concat(taicpu.op_none(A_CLI));
  1296. // write high SP
  1297. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_HI,NR_R29));
  1298. // release interrupts
  1299. list.concat(taicpu.op_const_reg(A_OUT,NIO_SREG,NR_R0));
  1300. // write low SP
  1301. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_LO,NR_R28));
  1302. end;
  1303. end;
  1304. end;
  1305. function tcgavr.GetLoad(const ref: treference) : tasmop;
  1306. begin
  1307. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1308. result:=A_LDS
  1309. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1310. result:=A_LDD
  1311. else
  1312. result:=A_LD;
  1313. end;
  1314. function tcgavr.GetStore(const ref: treference) : tasmop;
  1315. begin
  1316. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1317. result:=A_STS
  1318. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1319. result:=A_STD
  1320. else
  1321. result:=A_ST;
  1322. end;
  1323. procedure tcgavr.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
  1324. var
  1325. regs : tcpuregisterset;
  1326. reg : tsuperregister;
  1327. begin
  1328. if not(nostackframe) then
  1329. begin
  1330. { save int registers }
  1331. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1332. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1333. regs:=regs+[RS_R28,RS_R29];
  1334. for reg:=RS_R31 downto RS_R0 do
  1335. if reg in regs then
  1336. list.concat(taicpu.op_reg(A_PUSH,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1337. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1338. begin
  1339. list.concat(taicpu.op_reg_const(A_IN,NR_R28,NIO_SP_LO));
  1340. list.concat(taicpu.op_reg_const(A_IN,NR_R29,NIO_SP_HI));
  1341. end
  1342. else
  1343. { the framepointer cannot be omitted on avr because sp
  1344. is not a register but part of the i/o map
  1345. }
  1346. internalerror(2011021901);
  1347. a_adjust_sp(list,-localsize);
  1348. end;
  1349. end;
  1350. procedure tcgavr.g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean);
  1351. var
  1352. regs : tcpuregisterset;
  1353. reg : TSuperRegister;
  1354. LocalSize : longint;
  1355. begin
  1356. if not(nostackframe) then
  1357. begin
  1358. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1359. begin
  1360. LocalSize:=current_procinfo.calc_stackframe_size;
  1361. a_adjust_sp(list,LocalSize);
  1362. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1363. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1364. regs:=regs+[RS_R28,RS_R29];
  1365. for reg:=RS_R0 to RS_R31 do
  1366. if reg in regs then
  1367. list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1368. end
  1369. else
  1370. { the framepointer cannot be omitted on avr because sp
  1371. is not a register but part of the i/o map
  1372. }
  1373. internalerror(2011021902);
  1374. end;
  1375. list.concat(taicpu.op_none(A_RET));
  1376. end;
  1377. procedure tcgavr.a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);
  1378. var
  1379. tmpref : treference;
  1380. begin
  1381. if ref.addressmode<>AM_UNCHANGED then
  1382. internalerror(2011021701);
  1383. if assigned(ref.symbol) or (ref.offset<>0) then
  1384. begin
  1385. reference_reset(tmpref,0);
  1386. tmpref.symbol:=ref.symbol;
  1387. tmpref.offset:=ref.offset;
  1388. tmpref.refaddr:=addr_lo8;
  1389. list.concat(taicpu.op_reg_ref(A_LDI,r,tmpref));
  1390. tmpref.refaddr:=addr_hi8;
  1391. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(r),tmpref));
  1392. if (ref.base<>NR_NO) then
  1393. begin
  1394. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.base));
  1395. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.base)));
  1396. end;
  1397. if (ref.index<>NR_NO) then
  1398. begin
  1399. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1400. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1401. end;
  1402. end
  1403. else if (ref.base<>NR_NO)then
  1404. begin
  1405. emit_mov(list,r,ref.base);
  1406. emit_mov(list,GetNextReg(r),GetNextReg(ref.base));
  1407. if (ref.index<>NR_NO) then
  1408. begin
  1409. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1410. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1411. end;
  1412. end
  1413. else if (ref.index<>NR_NO) then
  1414. begin
  1415. emit_mov(list,r,ref.index);
  1416. emit_mov(list,GetNextReg(r),GetNextReg(ref.index));
  1417. end;
  1418. end;
  1419. procedure tcgavr.fixref(list : TAsmList;var ref : treference);
  1420. begin
  1421. internalerror(2011021320);
  1422. end;
  1423. procedure tcgavr.g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  1424. var
  1425. paraloc1,paraloc2,paraloc3 : TCGPara;
  1426. pd : tprocdef;
  1427. begin
  1428. pd:=search_system_proc('MOVE');
  1429. paraloc1.init;
  1430. paraloc2.init;
  1431. paraloc3.init;
  1432. paramanager.getintparaloc(pd,1,paraloc1);
  1433. paramanager.getintparaloc(pd,2,paraloc2);
  1434. paramanager.getintparaloc(pd,3,paraloc3);
  1435. a_load_const_cgpara(list,OS_SINT,len,paraloc3);
  1436. a_loadaddr_ref_cgpara(list,dest,paraloc2);
  1437. a_loadaddr_ref_cgpara(list,source,paraloc1);
  1438. paramanager.freecgpara(list,paraloc3);
  1439. paramanager.freecgpara(list,paraloc2);
  1440. paramanager.freecgpara(list,paraloc1);
  1441. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1442. a_call_name_static(list,'FPC_MOVE');
  1443. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1444. paraloc3.done;
  1445. paraloc2.done;
  1446. paraloc1.done;
  1447. end;
  1448. procedure tcgavr.g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);
  1449. var
  1450. countreg,tmpreg : tregister;
  1451. srcref,dstref : treference;
  1452. copysize,countregsize : tcgsize;
  1453. l : TAsmLabel;
  1454. i : longint;
  1455. SrcQuickRef, DestQuickRef : Boolean;
  1456. begin
  1457. if len>16 then
  1458. begin
  1459. current_asmdata.getjumplabel(l);
  1460. reference_reset(srcref,0);
  1461. reference_reset(dstref,0);
  1462. srcref.base:=NR_R30;
  1463. srcref.addressmode:=AM_POSTINCREMENT;
  1464. dstref.base:=NR_R26;
  1465. dstref.addressmode:=AM_POSTINCREMENT;
  1466. copysize:=OS_8;
  1467. if len<256 then
  1468. countregsize:=OS_8
  1469. else if len<65536 then
  1470. countregsize:=OS_16
  1471. else
  1472. internalerror(2011022007);
  1473. countreg:=getintregister(list,countregsize);
  1474. a_load_const_reg(list,countregsize,len,countreg);
  1475. a_loadaddr_ref_reg(list,source,NR_R30);
  1476. tmpreg:=getaddressregister(list);
  1477. a_loadaddr_ref_reg(list,dest,tmpreg);
  1478. { X is used for spilling code so we can load it
  1479. only by a push/pop sequence, this can be
  1480. optimized later on by the peephole optimizer
  1481. }
  1482. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1483. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1484. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1485. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1486. cg.a_label(list,l);
  1487. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1488. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1489. a_op_const_reg(list,OP_SUB,countregsize,1,countreg);
  1490. a_jmp_flags(list,F_NE,l);
  1491. // keep registers alive
  1492. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  1493. end
  1494. else
  1495. begin
  1496. SrcQuickRef:=false;
  1497. DestQuickRef:=false;
  1498. if not((source.addressmode=AM_UNCHANGED) and
  1499. (source.symbol=nil) and
  1500. ((source.base=NR_R28) or
  1501. (source.base=NR_R29)) and
  1502. (source.Index=NR_NO) and
  1503. (source.Offset in [0..64-len])) and
  1504. not((source.Base=NR_NO) and (source.Index=NR_NO)) then
  1505. srcref:=normalize_ref(list,source,NR_R30)
  1506. else
  1507. begin
  1508. SrcQuickRef:=true;
  1509. srcref:=source;
  1510. end;
  1511. if not((dest.addressmode=AM_UNCHANGED) and
  1512. (dest.symbol=nil) and
  1513. ((dest.base=NR_R28) or
  1514. (dest.base=NR_R29)) and
  1515. (dest.Index=NR_No) and
  1516. (dest.Offset in [0..64-len])) and
  1517. not((dest.Base=NR_NO) and (dest.Index=NR_NO)) then
  1518. begin
  1519. if not(SrcQuickRef) then
  1520. begin
  1521. tmpreg:=getaddressregister(list);
  1522. dstref:=normalize_ref(list,dest,tmpreg);
  1523. { X is used for spilling code so we can load it
  1524. only by a push/pop sequence, this can be
  1525. optimized later on by the peephole optimizer
  1526. }
  1527. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1528. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1529. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1530. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1531. dstref.base:=NR_R26;
  1532. end
  1533. else
  1534. dstref:=normalize_ref(list,dest,NR_R30);
  1535. end
  1536. else
  1537. begin
  1538. DestQuickRef:=true;
  1539. dstref:=dest;
  1540. end;
  1541. for i:=1 to len do
  1542. begin
  1543. if not(SrcQuickRef) and (i<len) then
  1544. srcref.addressmode:=AM_POSTINCREMENT
  1545. else
  1546. srcref.addressmode:=AM_UNCHANGED;
  1547. if not(DestQuickRef) and (i<len) then
  1548. dstref.addressmode:=AM_POSTINCREMENT
  1549. else
  1550. dstref.addressmode:=AM_UNCHANGED;
  1551. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1552. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1553. if SrcQuickRef then
  1554. inc(srcref.offset);
  1555. if DestQuickRef then
  1556. inc(dstref.offset);
  1557. end;
  1558. if not(SrcQuickRef) then
  1559. begin
  1560. ungetcpuregister(list,srcref.base);
  1561. ungetcpuregister(list,GetNextReg(srcref.base));
  1562. end;
  1563. end;
  1564. end;
  1565. procedure tcgavr.g_overflowCheck(list : TAsmList;const l : tlocation;def : tdef);
  1566. var
  1567. hl : tasmlabel;
  1568. ai : taicpu;
  1569. cond : TAsmCond;
  1570. begin
  1571. if not(cs_check_overflow in current_settings.localswitches) then
  1572. exit;
  1573. current_asmdata.getjumplabel(hl);
  1574. if not ((def.typ=pointerdef) or
  1575. ((def.typ=orddef) and
  1576. (torddef(def).ordtype in [u64bit,u16bit,u32bit,u8bit,uchar,
  1577. pasbool8,pasbool16,pasbool32,pasbool64]))) then
  1578. cond:=C_VC
  1579. else
  1580. cond:=C_CC;
  1581. ai:=Taicpu.Op_Sym(A_BRxx,hl);
  1582. ai.SetCondition(cond);
  1583. ai.is_jmp:=true;
  1584. list.concat(ai);
  1585. a_call_name(list,'FPC_OVERFLOW',false);
  1586. a_label(list,hl);
  1587. end;
  1588. procedure tcgavr.g_save_registers(list: TAsmList);
  1589. begin
  1590. { this is done by the entry code }
  1591. end;
  1592. procedure tcgavr.g_restore_registers(list: TAsmList);
  1593. begin
  1594. { this is done by the exit code }
  1595. end;
  1596. procedure tcgavr.a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  1597. var
  1598. ai1,ai2 : taicpu;
  1599. hl : TAsmLabel;
  1600. begin
  1601. ai1:=Taicpu.Op_sym(A_BRxx,l);
  1602. ai1.is_jmp:=true;
  1603. hl:=nil;
  1604. case cond of
  1605. OC_EQ:
  1606. ai1.SetCondition(C_EQ);
  1607. OC_GT:
  1608. begin
  1609. { emulate GT }
  1610. current_asmdata.getjumplabel(hl);
  1611. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1612. ai2.SetCondition(C_EQ);
  1613. ai2.is_jmp:=true;
  1614. list.concat(ai2);
  1615. ai1.SetCondition(C_GE);
  1616. end;
  1617. OC_LT:
  1618. ai1.SetCondition(C_LT);
  1619. OC_GTE:
  1620. ai1.SetCondition(C_GE);
  1621. OC_LTE:
  1622. begin
  1623. { emulate LTE }
  1624. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1625. ai2.SetCondition(C_EQ);
  1626. ai2.is_jmp:=true;
  1627. list.concat(ai2);
  1628. ai1.SetCondition(C_LT);
  1629. end;
  1630. OC_NE:
  1631. ai1.SetCondition(C_NE);
  1632. OC_BE:
  1633. begin
  1634. { emulate BE }
  1635. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1636. ai2.SetCondition(C_EQ);
  1637. ai2.is_jmp:=true;
  1638. list.concat(ai2);
  1639. ai1.SetCondition(C_LO);
  1640. end;
  1641. OC_B:
  1642. ai1.SetCondition(C_LO);
  1643. OC_AE:
  1644. ai1.SetCondition(C_SH);
  1645. OC_A:
  1646. begin
  1647. { emulate A (unsigned GT) }
  1648. current_asmdata.getjumplabel(hl);
  1649. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1650. ai2.SetCondition(C_EQ);
  1651. ai2.is_jmp:=true;
  1652. list.concat(ai2);
  1653. ai1.SetCondition(C_SH);
  1654. end;
  1655. else
  1656. internalerror(2011082501);
  1657. end;
  1658. list.concat(ai1);
  1659. if assigned(hl) then
  1660. a_label(list,hl);
  1661. end;
  1662. procedure tcgavr.emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  1663. var
  1664. instr: taicpu;
  1665. begin
  1666. instr:=taicpu.op_reg_reg(A_MOV,reg2,reg1);
  1667. list.Concat(instr);
  1668. { Notify the register allocator that we have written a move instruction so
  1669. it can try to eliminate it. }
  1670. add_move_instruction(instr);
  1671. end;
  1672. procedure tcg64favr.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
  1673. begin
  1674. if not(size in [OS_S64,OS_64]) then
  1675. internalerror(2012102402);
  1676. tcgavr(cg).a_op_reg_reg_internal(list,Op,size,regsrc.reglo,regsrc.reghi,regdst.reglo,regdst.reghi);
  1677. end;
  1678. procedure tcg64favr.a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);
  1679. begin
  1680. tcgavr(cg).a_op_const_reg_internal(list,Op,size,value,reg.reglo,reg.reghi);
  1681. end;
  1682. procedure create_codegen;
  1683. begin
  1684. cg:=tcgavr.create;
  1685. cg64:=tcg64favr.create;
  1686. end;
  1687. end.