cgcpu.pas 61 KB

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  1. {
  2. Copyright (c) 2008 by Florian Klaempfl
  3. Member of the Free Pascal development team
  4. This unit implements the code generator for the AVR
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. unit cgcpu;
  19. {$i fpcdefs.inc}
  20. interface
  21. uses
  22. globtype,symtype,symdef,
  23. cgbase,cgutils,cgobj,
  24. aasmbase,aasmcpu,aasmtai,aasmdata,
  25. parabase,
  26. cpubase,cpuinfo,node,cg64f32,rgcpu;
  27. type
  28. { tcgavr }
  29. tcgavr = class(tcg)
  30. { true, if the next arithmetic operation should modify the flags }
  31. cgsetflags : boolean;
  32. procedure init_register_allocators;override;
  33. procedure done_register_allocators;override;
  34. function getintregister(list:TAsmList;size:Tcgsize):Tregister;override;
  35. function getaddressregister(list:TAsmList):TRegister;override;
  36. procedure a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);override;
  37. procedure a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);override;
  38. procedure a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);override;
  39. procedure a_call_name(list : TAsmList;const s : string; weak: boolean);override;
  40. procedure a_call_reg(list : TAsmList;reg: tregister);override;
  41. procedure a_call_ref(list : TAsmList;ref: treference);override;
  42. procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister); override;
  43. procedure a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister); override;
  44. { move instructions }
  45. procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);override;
  46. procedure a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
  47. procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
  48. procedure a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
  49. { fpu move instructions }
  50. procedure a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
  51. procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
  52. procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
  53. { comparison operations }
  54. procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
  55. l : tasmlabel);override;
  56. procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
  57. procedure a_jmp_name(list : TAsmList;const s : string); override;
  58. procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
  59. procedure a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel); override;
  60. procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  61. procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
  62. procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
  63. procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
  64. procedure g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);override;
  65. procedure g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  66. procedure g_overflowcheck(list: TAsmList; const l: tlocation; def: tdef); override;
  67. procedure g_save_registers(list : TAsmList);override;
  68. procedure g_restore_registers(list : TAsmList);override;
  69. procedure a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  70. procedure fixref(list : TAsmList;var ref : treference);
  71. function normalize_ref(list : TAsmList;ref : treference;
  72. tmpreg : tregister) : treference;
  73. procedure g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);override;
  74. procedure g_stackpointer_alloc(list : TAsmList;size : longint);override;
  75. procedure emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  76. procedure a_adjust_sp(list: TAsmList; value: longint);
  77. function GetLoad(const ref : treference) : tasmop;
  78. function GetStore(const ref: treference): tasmop;
  79. procedure a_bit_scan_reg_reg(list: TAsmList; reverse: boolean; size: TCGSize; src, dst: TRegister); override;
  80. end;
  81. tcg64favr = class(tcg64f32)
  82. procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  83. procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
  84. end;
  85. procedure create_codegen;
  86. const
  87. TOpCG2AsmOp: Array[topcg] of TAsmOp = (A_NONE,A_MOV,A_ADD,A_AND,A_NONE,
  88. A_NONE,A_MUL,A_MULS,A_NEG,A_COM,A_OR,
  89. A_ASR,A_LSL,A_LSR,A_SUB,A_EOR,A_ROL,A_ROR);
  90. implementation
  91. uses
  92. globals,verbose,systems,cutils,
  93. fmodule,
  94. symconst,symsym,
  95. tgobj,rgobj,
  96. procinfo,cpupi,
  97. paramgr;
  98. procedure tcgavr.init_register_allocators;
  99. begin
  100. inherited init_register_allocators;
  101. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  102. [RS_R8,RS_R9,
  103. RS_R10,RS_R11,RS_R12,RS_R13,RS_R14,RS_R15,RS_R16,RS_R17,RS_R18,RS_R19,
  104. RS_R20,RS_R21,RS_R22,RS_R23,RS_R24,RS_R25,
  105. RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7],first_int_imreg,[]);
  106. { rg[R_ADDRESSREGISTER]:=trgintcpu.create(R_ADDRESSREGISTER,R_SUBWHOLE,
  107. [RS_R26,RS_R30],first_int_imreg,[]); }
  108. end;
  109. procedure tcgavr.done_register_allocators;
  110. begin
  111. rg[R_INTREGISTER].free;
  112. // rg[R_ADDRESSREGISTER].free;
  113. inherited done_register_allocators;
  114. end;
  115. function tcgavr.getintregister(list: TAsmList; size: Tcgsize): Tregister;
  116. var
  117. tmp1,tmp2,tmp3 : TRegister;
  118. begin
  119. case size of
  120. OS_8,OS_S8:
  121. Result:=inherited getintregister(list, size);
  122. OS_16,OS_S16:
  123. begin
  124. Result:=inherited getintregister(list, OS_8);
  125. { ensure that the high register can be retrieved by
  126. GetNextReg
  127. }
  128. if inherited getintregister(list, OS_8)<>GetNextReg(Result) then
  129. internalerror(2011021331);
  130. end;
  131. OS_32,OS_S32:
  132. begin
  133. Result:=inherited getintregister(list, OS_8);
  134. tmp1:=inherited getintregister(list, OS_8);
  135. { ensure that the high register can be retrieved by
  136. GetNextReg
  137. }
  138. if tmp1<>GetNextReg(Result) then
  139. internalerror(2011021332);
  140. tmp2:=inherited getintregister(list, OS_8);
  141. { ensure that the upper register can be retrieved by
  142. GetNextReg
  143. }
  144. if tmp2<>GetNextReg(tmp1) then
  145. internalerror(2011021333);
  146. tmp3:=inherited getintregister(list, OS_8);
  147. { ensure that the upper register can be retrieved by
  148. GetNextReg
  149. }
  150. if tmp3<>GetNextReg(tmp2) then
  151. internalerror(2011021334);
  152. end;
  153. else
  154. internalerror(2011021330);
  155. end;
  156. end;
  157. function tcgavr.getaddressregister(list: TAsmList): TRegister;
  158. begin
  159. Result:=getintregister(list,OS_ADDR);
  160. end;
  161. procedure tcgavr.a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);
  162. var
  163. ref: treference;
  164. begin
  165. paraloc.check_simple_location;
  166. paramanager.allocparaloc(list,paraloc.location);
  167. case paraloc.location^.loc of
  168. LOC_REGISTER,LOC_CREGISTER:
  169. a_load_const_reg(list,size,a,paraloc.location^.register);
  170. LOC_REFERENCE:
  171. begin
  172. reference_reset(ref,paraloc.alignment);
  173. ref.base:=paraloc.location^.reference.index;
  174. ref.offset:=paraloc.location^.reference.offset;
  175. a_load_const_ref(list,size,a,ref);
  176. end;
  177. else
  178. internalerror(2002081101);
  179. end;
  180. end;
  181. procedure tcgavr.a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);
  182. var
  183. tmpref, ref: treference;
  184. location: pcgparalocation;
  185. sizeleft: tcgint;
  186. begin
  187. location := paraloc.location;
  188. tmpref := r;
  189. sizeleft := paraloc.intsize;
  190. while assigned(location) do
  191. begin
  192. paramanager.allocparaloc(list,location);
  193. case location^.loc of
  194. LOC_REGISTER,LOC_CREGISTER:
  195. a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
  196. LOC_REFERENCE:
  197. begin
  198. reference_reset_base(ref,location^.reference.index,location^.reference.offset,paraloc.alignment);
  199. { doubles in softemu mode have a strange order of registers and references }
  200. if location^.size=OS_32 then
  201. g_concatcopy(list,tmpref,ref,4)
  202. else
  203. begin
  204. g_concatcopy(list,tmpref,ref,sizeleft);
  205. if assigned(location^.next) then
  206. internalerror(2005010710);
  207. end;
  208. end;
  209. LOC_VOID:
  210. begin
  211. // nothing to do
  212. end;
  213. else
  214. internalerror(2002081103);
  215. end;
  216. inc(tmpref.offset,tcgsize2size[location^.size]);
  217. dec(sizeleft,tcgsize2size[location^.size]);
  218. location := location^.next;
  219. end;
  220. end;
  221. procedure tcgavr.a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);
  222. var
  223. ref: treference;
  224. tmpreg: tregister;
  225. begin
  226. paraloc.check_simple_location;
  227. paramanager.allocparaloc(list,paraloc.location);
  228. case paraloc.location^.loc of
  229. LOC_REGISTER,LOC_CREGISTER:
  230. a_loadaddr_ref_reg(list,r,paraloc.location^.register);
  231. LOC_REFERENCE:
  232. begin
  233. reference_reset(ref,paraloc.alignment);
  234. ref.base := paraloc.location^.reference.index;
  235. ref.offset := paraloc.location^.reference.offset;
  236. tmpreg := getintregister(list,OS_ADDR);
  237. a_loadaddr_ref_reg(list,r,tmpreg);
  238. a_load_reg_ref(list,OS_ADDR,OS_ADDR,tmpreg,ref);
  239. end;
  240. else
  241. internalerror(2002080701);
  242. end;
  243. end;
  244. procedure tcgavr.a_call_name(list : TAsmList;const s : string; weak: boolean);
  245. begin
  246. list.concat(taicpu.op_sym(A_RCALL,current_asmdata.RefAsmSymbol(s)));
  247. {
  248. the compiler does not properly set this flag anymore in pass 1, and
  249. for now we only need it after pass 2 (I hope) (JM)
  250. if not(pi_do_call in current_procinfo.flags) then
  251. internalerror(2003060703);
  252. }
  253. include(current_procinfo.flags,pi_do_call);
  254. end;
  255. procedure tcgavr.a_call_reg(list : TAsmList;reg: tregister);
  256. begin
  257. a_reg_alloc(list,NR_ZLO);
  258. a_reg_alloc(list,NR_ZHI);
  259. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZLO,reg));
  260. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZHI,GetHigh(reg)));
  261. list.concat(taicpu.op_none(A_ICALL));
  262. a_reg_dealloc(list,NR_ZLO);
  263. a_reg_dealloc(list,NR_ZHI);
  264. include(current_procinfo.flags,pi_do_call);
  265. end;
  266. procedure tcgavr.a_call_ref(list : TAsmList;ref: treference);
  267. begin
  268. a_reg_alloc(list,NR_ZLO);
  269. a_reg_alloc(list,NR_ZHI);
  270. a_load_ref_reg(list,OS_ADDR,OS_ADDR,ref,NR_ZLO);
  271. list.concat(taicpu.op_none(A_ICALL));
  272. a_reg_dealloc(list,NR_ZLO);
  273. a_reg_dealloc(list,NR_ZHI);
  274. include(current_procinfo.flags,pi_do_call);
  275. end;
  276. procedure tcgavr.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister);
  277. var
  278. mask : qword;
  279. shift : byte;
  280. i : byte;
  281. tmpreg : tregister;
  282. begin
  283. mask:=$ff;
  284. shift:=0;
  285. case op of
  286. OP_OR:
  287. begin
  288. for i:=1 to tcgsize2size[size] do
  289. begin
  290. list.concat(taicpu.op_reg_const(A_ORI,reg,(a and mask) shr shift));
  291. reg:=GetNextReg(reg);
  292. mask:=mask shl 8;
  293. inc(shift,8);
  294. end;
  295. end;
  296. OP_AND:
  297. begin
  298. for i:=1 to tcgsize2size[size] do
  299. begin
  300. list.concat(taicpu.op_reg_const(A_ANDI,reg,(a and mask) shr shift));
  301. reg:=GetNextReg(reg);
  302. mask:=mask shl 8;
  303. inc(shift,8);
  304. end;
  305. end;
  306. OP_SUB:
  307. begin
  308. list.concat(taicpu.op_reg_const(A_SUBI,reg,a));
  309. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  310. begin
  311. for i:=2 to tcgsize2size[size] do
  312. begin
  313. reg:=GetNextReg(reg);
  314. mask:=mask shl 8;
  315. inc(shift,8);
  316. list.concat(taicpu.op_reg_const(A_SBCI,reg,(a and mask) shr shift));
  317. end;
  318. end;
  319. end;
  320. else
  321. begin
  322. tmpreg:=getintregister(list,size);
  323. a_load_const_reg(list,size,a,tmpreg);
  324. a_op_reg_reg(list,op,size,tmpreg,reg);
  325. end;
  326. end;
  327. end;
  328. procedure tcgavr.a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister);
  329. var
  330. countreg,
  331. tmpreg: tregister;
  332. i : integer;
  333. instr : taicpu;
  334. paraloc1,paraloc2,paraloc3 : TCGPara;
  335. l1,l2 : tasmlabel;
  336. begin
  337. case op of
  338. OP_ADD:
  339. begin
  340. list.concat(taicpu.op_reg_reg(A_ADD,dst,src));
  341. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  342. begin
  343. for i:=2 to tcgsize2size[size] do
  344. begin
  345. dst:=GetNextReg(dst);
  346. src:=GetNextReg(src);
  347. list.concat(taicpu.op_reg_reg(A_ADC,dst,src));
  348. end;
  349. end
  350. else
  351. end;
  352. OP_SUB:
  353. begin
  354. list.concat(taicpu.op_reg_reg(A_SUB,dst,src));
  355. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  356. begin
  357. for i:=2 to tcgsize2size[size] do
  358. begin
  359. dst:=GetNextReg(dst);
  360. src:=GetNextReg(src);
  361. list.concat(taicpu.op_reg_reg(A_SBC,dst,src));
  362. end;
  363. end;
  364. end;
  365. OP_NEG:
  366. begin
  367. if src<>dst then
  368. a_load_reg_reg(list,size,size,src,dst);
  369. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  370. begin
  371. tmpreg:=GetNextReg(dst);
  372. for i:=2 to tcgsize2size[size] do
  373. begin
  374. list.concat(taicpu.op_reg(A_COM,tmpreg));
  375. tmpreg:=GetNextReg(tmpreg);
  376. end;
  377. list.concat(taicpu.op_reg(A_NEG,dst));
  378. tmpreg:=GetNextReg(dst);
  379. for i:=2 to tcgsize2size[size] do
  380. begin
  381. list.concat(taicpu.op_reg_const(A_SBCI,dst,-1));
  382. tmpreg:=GetNextReg(tmpreg);
  383. end;
  384. end
  385. else
  386. list.concat(taicpu.op_reg(A_NEG,dst));
  387. end;
  388. OP_NOT:
  389. begin
  390. for i:=1 to tcgsize2size[size] do
  391. begin
  392. if src<>dst then
  393. a_load_reg_reg(list,OS_8,OS_8,src,dst);
  394. list.concat(taicpu.op_reg(A_COM,dst));
  395. src:=GetNextReg(src);
  396. dst:=GetNextReg(dst);
  397. end;
  398. end;
  399. OP_MUL,OP_IMUL:
  400. begin
  401. if size in [OS_8,OS_S8] then
  402. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src))
  403. else if size=OS_16 then
  404. begin
  405. paraloc1.init;
  406. paraloc2.init;
  407. paraloc3.init;
  408. paramanager.getintparaloc(pocall_default,1,paraloc1);
  409. paramanager.getintparaloc(pocall_default,2,paraloc2);
  410. paramanager.getintparaloc(pocall_default,3,paraloc3);
  411. a_load_const_cgpara(list,OS_8,0,paraloc3);
  412. a_load_reg_cgpara(list,OS_16,src,paraloc2);
  413. a_load_reg_cgpara(list,OS_16,dst,paraloc1);
  414. paramanager.freecgpara(list,paraloc3);
  415. paramanager.freecgpara(list,paraloc2);
  416. paramanager.freecgpara(list,paraloc1);
  417. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  418. a_call_name(list,'FPC_MUL_WORD',false);
  419. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  420. cg.a_reg_alloc(list,NR_FUNCTION_RESULT_REG);
  421. cg.a_load_reg_reg(list,OS_16,OS_16,NR_FUNCTION_RESULT_REG,dst);
  422. paraloc3.done;
  423. paraloc2.done;
  424. paraloc1.done;
  425. end
  426. else
  427. internalerror(2011022002);
  428. end;
  429. OP_DIV,OP_IDIV:
  430. { special stuff, needs separate handling inside code }
  431. { generator }
  432. internalerror(2011022001);
  433. OP_SHR,OP_SHL,OP_SAR,OP_ROL,OP_ROR:
  434. begin
  435. current_asmdata.getjumplabel(l1);
  436. current_asmdata.getjumplabel(l2);
  437. countreg:=getintregister(list,OS_8);
  438. a_load_reg_reg(list,size,OS_8,src,countreg);
  439. list.concat(taicpu.op_reg_const(A_CP,countreg,0));
  440. a_jmp_flags(list,F_EQ,l2);
  441. cg.a_label(list,l1);
  442. case op of
  443. OP_SHR:
  444. list.concat(taicpu.op_reg(A_LSR,GetOffsetReg(dst,tcgsize2size[size]-1)));
  445. OP_SHL:
  446. list.concat(taicpu.op_reg(A_LSL,dst));
  447. OP_SAR:
  448. list.concat(taicpu.op_reg(A_ASR,GetOffsetReg(dst,tcgsize2size[size]-1)));
  449. OP_ROR:
  450. begin
  451. { load carry? }
  452. if not(size in [OS_8,OS_S8]) then
  453. begin
  454. list.concat(taicpu.op_none(A_CLC));
  455. list.concat(taicpu.op_reg_const(A_SBRC,src,0));
  456. list.concat(taicpu.op_none(A_SEC));
  457. end;
  458. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg(dst,tcgsize2size[size]-1)));
  459. end;
  460. OP_ROL:
  461. begin
  462. { load carry? }
  463. if not(size in [OS_8,OS_S8]) then
  464. begin
  465. list.concat(taicpu.op_none(A_CLC));
  466. list.concat(taicpu.op_reg_const(A_SBRC,GetOffsetReg(dst,tcgsize2size[size]-1),7));
  467. list.concat(taicpu.op_none(A_SEC));
  468. end;
  469. list.concat(taicpu.op_reg(A_ROL,dst))
  470. end;
  471. else
  472. internalerror(2011030901);
  473. end;
  474. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  475. begin
  476. for i:=2 to tcgsize2size[size] do
  477. begin
  478. case op of
  479. OP_ROR,
  480. OP_SHR:
  481. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg(dst,tcgsize2size[size]-i)));
  482. OP_ROL,
  483. OP_SHL:
  484. list.concat(taicpu.op_reg(A_ROL,GetOffsetReg(dst,i-1)));
  485. OP_SAR:
  486. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg(dst,tcgsize2size[size]-i)));
  487. else
  488. internalerror(2011030902);
  489. end;
  490. end;
  491. end;
  492. a_op_const_reg(list,OP_SUB,OS_8,1,countreg);
  493. a_jmp_flags(list,F_NE,l1);
  494. // keep registers alive
  495. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  496. cg.a_label(list,l2);
  497. end;
  498. OP_AND,OP_OR,OP_XOR:
  499. begin
  500. for i:=1 to tcgsize2size[size] do
  501. begin
  502. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src));
  503. dst:=GetNextReg(dst);
  504. src:=GetNextReg(src);
  505. end;
  506. end;
  507. else
  508. internalerror(2011022004);
  509. end;
  510. end;
  511. procedure tcgavr.a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);
  512. var
  513. mask : qword;
  514. shift : byte;
  515. i : byte;
  516. begin
  517. mask:=$ff;
  518. shift:=0;
  519. for i:=1 to tcgsize2size[size] do
  520. begin
  521. if ((qword(a) and mask) shr shift)=0 then
  522. emit_mov(list,reg,NR_R1)
  523. else
  524. list.concat(taicpu.op_reg_const(A_LDI,reg,(qword(a) and mask) shr shift));
  525. mask:=mask shl 8;
  526. inc(shift,8);
  527. reg:=GetNextReg(reg);
  528. end;
  529. end;
  530. function tcgavr.normalize_ref(list:TAsmList;ref: treference;tmpreg : tregister) : treference;
  531. procedure maybegetcpuregister(list:tasmlist;reg : tregister);
  532. begin
  533. { allocate the register only, if a cpu register is passed }
  534. if getsupreg(reg)<first_int_imreg then
  535. getcpuregister(list,reg);
  536. end;
  537. var
  538. tmpref : treference;
  539. l : tasmlabel;
  540. begin
  541. Result:=ref;
  542. if ref.addressmode<>AM_UNCHANGED then
  543. internalerror(2011021701);
  544. { Be sure to have a base register }
  545. if (ref.base=NR_NO) then
  546. begin
  547. { only symbol+offset? }
  548. if ref.index=NR_NO then
  549. exit;
  550. ref.base:=ref.index;
  551. ref.index:=NR_NO;
  552. end;
  553. if assigned(ref.symbol) or (ref.offset<>0) then
  554. begin
  555. reference_reset(tmpref,0);
  556. tmpref.symbol:=ref.symbol;
  557. tmpref.offset:=ref.offset;
  558. tmpref.refaddr:=addr_lo8;
  559. maybegetcpuregister(list,tmpreg);
  560. list.concat(taicpu.op_reg_ref(A_LDI,tmpreg,tmpref));
  561. tmpref.refaddr:=addr_hi8;
  562. maybegetcpuregister(list,GetNextReg(tmpreg));
  563. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(tmpreg),tmpref));
  564. if (ref.base<>NR_NO) then
  565. begin
  566. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
  567. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
  568. end;
  569. if (ref.index<>NR_NO) then
  570. begin
  571. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  572. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  573. end;
  574. ref.symbol:=nil;
  575. ref.offset:=0;
  576. ref.base:=tmpreg;
  577. ref.index:=NR_NO;
  578. end
  579. else if (ref.base<>NR_NO) and (ref.index<>NR_NO) then
  580. begin
  581. maybegetcpuregister(list,tmpreg);
  582. emit_mov(list,tmpreg,ref.index);
  583. maybegetcpuregister(list,GetNextReg(tmpreg));
  584. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
  585. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
  586. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
  587. ref.base:=tmpreg;
  588. ref.index:=NR_NO;
  589. end
  590. else if (ref.base<>NR_NO) then
  591. begin
  592. maybegetcpuregister(list,tmpreg);
  593. emit_mov(list,tmpreg,ref.base);
  594. maybegetcpuregister(list,GetNextReg(tmpreg));
  595. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  596. ref.base:=tmpreg;
  597. ref.index:=NR_NO;
  598. end
  599. else if (ref.index<>NR_NO) then
  600. begin
  601. maybegetcpuregister(list,tmpreg);
  602. emit_mov(list,tmpreg,ref.index);
  603. maybegetcpuregister(list,GetNextReg(tmpreg));
  604. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
  605. ref.base:=tmpreg;
  606. ref.index:=NR_NO;
  607. end;
  608. Result:=ref;
  609. end;
  610. procedure tcgavr.a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);
  611. var
  612. href : treference;
  613. conv_done: boolean;
  614. tmpreg : tregister;
  615. i : integer;
  616. QuickRef : Boolean;
  617. begin
  618. QuickRef:=false;
  619. if not((Ref.addressmode=AM_UNCHANGED) and
  620. (Ref.symbol=nil) and
  621. ((Ref.base=NR_R28) or
  622. (Ref.base=NR_R29)) and
  623. (Ref.Index=NR_No) and
  624. (Ref.Offset in [0..64-tcgsize2size[tosize]])) and
  625. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  626. href:=normalize_ref(list,Ref,NR_R30)
  627. else
  628. begin
  629. QuickRef:=true;
  630. href:=Ref;
  631. end;
  632. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  633. internalerror(2011021307);
  634. conv_done:=false;
  635. if tosize<>fromsize then
  636. begin
  637. conv_done:=true;
  638. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  639. fromsize:=tosize;
  640. case fromsize of
  641. OS_8:
  642. begin
  643. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  644. href.addressmode:=AM_POSTINCREMENT;
  645. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  646. for i:=2 to tcgsize2size[tosize] do
  647. begin
  648. if QuickRef then
  649. inc(href.offset);
  650. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  651. href.addressmode:=AM_POSTINCREMENT
  652. else
  653. href.addressmode:=AM_UNCHANGED;
  654. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  655. end;
  656. end;
  657. OS_S8:
  658. begin
  659. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  660. href.addressmode:=AM_POSTINCREMENT;
  661. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  662. if tcgsize2size[tosize]>1 then
  663. begin
  664. tmpreg:=getintregister(list,OS_8);
  665. list.concat(taicpu.op_reg(A_CLR,tmpreg));
  666. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  667. list.concat(taicpu.op_reg(A_COM,tmpreg));
  668. for i:=2 to tcgsize2size[tosize] do
  669. begin
  670. if QuickRef then
  671. inc(href.offset);
  672. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  673. href.addressmode:=AM_POSTINCREMENT
  674. else
  675. href.addressmode:=AM_UNCHANGED;
  676. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  677. end;
  678. end;
  679. end;
  680. OS_16:
  681. begin
  682. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  683. href.addressmode:=AM_POSTINCREMENT;
  684. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  685. if QuickRef then
  686. inc(href.offset)
  687. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  688. href.addressmode:=AM_POSTINCREMENT
  689. else
  690. href.addressmode:=AM_UNCHANGED;
  691. reg:=GetNextReg(reg);
  692. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  693. for i:=3 to tcgsize2size[tosize] do
  694. begin
  695. if QuickRef then
  696. inc(href.offset);
  697. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  698. href.addressmode:=AM_POSTINCREMENT
  699. else
  700. href.addressmode:=AM_UNCHANGED;
  701. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  702. end;
  703. end;
  704. OS_S16:
  705. begin
  706. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  707. href.addressmode:=AM_POSTINCREMENT;
  708. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  709. if QuickRef then
  710. inc(href.offset)
  711. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  712. href.addressmode:=AM_POSTINCREMENT
  713. else
  714. href.addressmode:=AM_UNCHANGED;
  715. reg:=GetNextReg(reg);
  716. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  717. if tcgsize2size[tosize]>2 then
  718. begin
  719. tmpreg:=getintregister(list,OS_8);
  720. list.concat(taicpu.op_reg(A_CLR,tmpreg));
  721. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  722. list.concat(taicpu.op_reg(A_COM,tmpreg));
  723. for i:=3 to tcgsize2size[tosize] do
  724. begin
  725. if QuickRef then
  726. inc(href.offset);
  727. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  728. href.addressmode:=AM_POSTINCREMENT
  729. else
  730. href.addressmode:=AM_UNCHANGED;
  731. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  732. end;
  733. end;
  734. end;
  735. else
  736. conv_done:=false;
  737. end;
  738. end;
  739. if not conv_done then
  740. begin
  741. for i:=1 to tcgsize2size[fromsize] do
  742. begin
  743. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  744. href.addressmode:=AM_POSTINCREMENT
  745. else
  746. href.addressmode:=AM_UNCHANGED;
  747. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  748. if QuickRef then
  749. inc(href.offset);
  750. reg:=GetNextReg(reg);
  751. end;
  752. end;
  753. if not(QuickRef) then
  754. begin
  755. ungetcpuregister(list,href.base);
  756. ungetcpuregister(list,GetNextReg(href.base));
  757. end;
  758. end;
  759. procedure tcgavr.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;
  760. const Ref : treference;reg : tregister);
  761. var
  762. href : treference;
  763. conv_done: boolean;
  764. tmpreg : tregister;
  765. i : integer;
  766. QuickRef : boolean;
  767. begin
  768. QuickRef:=false;
  769. if not((Ref.addressmode=AM_UNCHANGED) and
  770. (Ref.symbol=nil) and
  771. ((Ref.base=NR_R28) or
  772. (Ref.base=NR_R29)) and
  773. (Ref.Index=NR_No) and
  774. (Ref.Offset in [0..64-tcgsize2size[fromsize]])) and
  775. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  776. href:=normalize_ref(list,Ref,NR_R30)
  777. else
  778. begin
  779. QuickRef:=true;
  780. href:=Ref;
  781. end;
  782. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  783. internalerror(2011021307);
  784. conv_done:=false;
  785. if tosize<>fromsize then
  786. begin
  787. conv_done:=true;
  788. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  789. fromsize:=tosize;
  790. case fromsize of
  791. OS_8:
  792. begin
  793. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  794. for i:=2 to tcgsize2size[tosize] do
  795. begin
  796. reg:=GetNextReg(reg);
  797. list.concat(taicpu.op_reg(A_CLR,reg));
  798. end;
  799. end;
  800. OS_S8:
  801. begin
  802. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  803. tmpreg:=reg;
  804. if tcgsize2size[tosize]>1 then
  805. begin
  806. reg:=GetNextReg(reg);
  807. list.concat(taicpu.op_reg(A_CLR,reg));
  808. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  809. list.concat(taicpu.op_reg(A_COM,reg));
  810. tmpreg:=reg;
  811. for i:=3 to tcgsize2size[tosize] do
  812. begin
  813. reg:=GetNextReg(reg);
  814. emit_mov(list,reg,tmpreg);
  815. end;
  816. end;
  817. end;
  818. OS_16:
  819. begin
  820. if not(QuickRef) then
  821. href.addressmode:=AM_POSTINCREMENT;
  822. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  823. if QuickRef then
  824. inc(href.offset);
  825. href.addressmode:=AM_UNCHANGED;
  826. reg:=GetNextReg(reg);
  827. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  828. for i:=3 to tcgsize2size[tosize] do
  829. begin
  830. reg:=GetNextReg(reg);
  831. list.concat(taicpu.op_reg(A_CLR,reg));
  832. end;
  833. end;
  834. OS_S16:
  835. begin
  836. if not(QuickRef) then
  837. href.addressmode:=AM_POSTINCREMENT;
  838. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  839. if QuickRef then
  840. inc(href.offset);
  841. href.addressmode:=AM_UNCHANGED;
  842. reg:=GetNextReg(reg);
  843. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  844. tmpreg:=reg;
  845. reg:=GetNextReg(reg);
  846. list.concat(taicpu.op_reg(A_CLR,reg));
  847. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  848. list.concat(taicpu.op_reg(A_COM,reg));
  849. tmpreg:=reg;
  850. for i:=4 to tcgsize2size[tosize] do
  851. begin
  852. reg:=GetNextReg(reg);
  853. emit_mov(list,reg,tmpreg);
  854. end;
  855. end;
  856. else
  857. conv_done:=false;
  858. end;
  859. end;
  860. if not conv_done then
  861. begin
  862. for i:=1 to tcgsize2size[fromsize] do
  863. begin
  864. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  865. href.addressmode:=AM_POSTINCREMENT
  866. else
  867. href.addressmode:=AM_UNCHANGED;
  868. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  869. if QuickRef then
  870. inc(href.offset);
  871. reg:=GetNextReg(reg);
  872. end;
  873. end;
  874. if not(QuickRef) then
  875. begin
  876. ungetcpuregister(list,href.base);
  877. ungetcpuregister(list,GetNextReg(href.base));
  878. end;
  879. end;
  880. procedure tcgavr.a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);
  881. var
  882. conv_done: boolean;
  883. tmpreg : tregister;
  884. i : integer;
  885. begin
  886. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  887. internalerror(2011021310);
  888. conv_done:=false;
  889. if tosize<>fromsize then
  890. begin
  891. conv_done:=true;
  892. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  893. fromsize:=tosize;
  894. case fromsize of
  895. OS_8:
  896. begin
  897. emit_mov(list,reg2,reg1);
  898. for i:=2 to tcgsize2size[tosize] do
  899. begin
  900. reg2:=GetNextReg(reg2);
  901. list.concat(taicpu.op_reg(A_CLR,reg2));
  902. end;
  903. end;
  904. OS_S8:
  905. begin
  906. { dest is always at least 16 bit at this point }
  907. emit_mov(list,reg2,reg1);
  908. reg2:=GetNextReg(reg2);
  909. list.concat(taicpu.op_reg(A_CLR,reg2));
  910. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  911. list.concat(taicpu.op_reg(A_COM,reg2));
  912. tmpreg:=reg2;
  913. for i:=3 to tcgsize2size[tosize] do
  914. begin
  915. reg2:=GetNextReg(reg2);
  916. emit_mov(list,reg2,tmpreg);
  917. end;
  918. end;
  919. OS_16:
  920. begin
  921. emit_mov(list,reg2,reg1);
  922. reg1:=GetNextReg(reg1);
  923. reg2:=GetNextReg(reg2);
  924. emit_mov(list,reg2,reg1);
  925. for i:=3 to tcgsize2size[tosize] do
  926. begin
  927. reg2:=GetNextReg(reg2);
  928. list.concat(taicpu.op_reg(A_CLR,reg2));
  929. end;
  930. end;
  931. OS_S16:
  932. begin
  933. { dest is always at least 32 bit at this point }
  934. emit_mov(list,reg2,reg1);
  935. reg1:=GetNextReg(reg1);
  936. reg2:=GetNextReg(reg2);
  937. emit_mov(list,reg2,reg1);
  938. reg2:=GetNextReg(reg2);
  939. list.concat(taicpu.op_reg(A_CLR,reg2));
  940. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  941. list.concat(taicpu.op_reg(A_COM,reg2));
  942. tmpreg:=reg2;
  943. for i:=4 to tcgsize2size[tosize] do
  944. begin
  945. reg2:=GetNextReg(reg2);
  946. emit_mov(list,reg2,tmpreg);
  947. end;
  948. end;
  949. else
  950. conv_done:=false;
  951. end;
  952. end;
  953. if not conv_done and (reg1<>reg2) then
  954. begin
  955. for i:=1 to tcgsize2size[fromsize] do
  956. begin
  957. emit_mov(list,reg2,reg1);
  958. reg1:=GetNextReg(reg1);
  959. reg2:=GetNextReg(reg2);
  960. end;
  961. end;
  962. end;
  963. procedure tcgavr.a_loadfpu_reg_reg(list: TAsmList; fromsize,tosize: tcgsize; reg1, reg2: tregister);
  964. begin
  965. internalerror(2012010702);
  966. end;
  967. procedure tcgavr.a_loadfpu_ref_reg(list: TAsmList; fromsize,tosize: tcgsize; const ref: treference; reg: tregister);
  968. begin
  969. internalerror(2012010703);
  970. end;
  971. procedure tcgavr.a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference);
  972. begin
  973. internalerror(2012010704);
  974. end;
  975. { comparison operations }
  976. procedure tcgavr.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;
  977. cmp_op : topcmp;a : tcgint;reg : tregister;l : tasmlabel);
  978. var
  979. swapped : boolean;
  980. tmpreg : tregister;
  981. i : byte;
  982. begin
  983. if a=0 then
  984. begin
  985. { swap parameters? }
  986. case cmp_op of
  987. OC_GT:
  988. begin
  989. swapped:=true;
  990. cmp_op:=OC_LT;
  991. end;
  992. OC_LTE:
  993. begin
  994. swapped:=true;
  995. cmp_op:=OC_GTE;
  996. end;
  997. OC_BE:
  998. begin
  999. swapped:=true;
  1000. cmp_op:=OC_AE;
  1001. end;
  1002. OC_A:
  1003. begin
  1004. swapped:=true;
  1005. cmp_op:=OC_A;
  1006. end;
  1007. end;
  1008. if swapped then
  1009. list.concat(taicpu.op_reg_reg(A_CP,reg,NR_R1))
  1010. else
  1011. list.concat(taicpu.op_reg_reg(A_CP,NR_R1,reg));
  1012. for i:=2 to tcgsize2size[size] do
  1013. begin
  1014. reg:=GetNextReg(reg);
  1015. if swapped then
  1016. list.concat(taicpu.op_reg_reg(A_CPC,reg,NR_R1))
  1017. else
  1018. list.concat(taicpu.op_reg_reg(A_CPC,NR_R1,reg));
  1019. end;
  1020. a_jmp_cond(list,cmp_op,l);
  1021. end
  1022. else
  1023. inherited a_cmp_const_reg_label(list,size,cmp_op,a,reg,l);
  1024. end;
  1025. procedure tcgavr.a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;
  1026. cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
  1027. var
  1028. swapped : boolean;
  1029. tmpreg : tregister;
  1030. i : byte;
  1031. begin
  1032. { swap parameters? }
  1033. case cmp_op of
  1034. OC_GT:
  1035. begin
  1036. swapped:=true;
  1037. cmp_op:=OC_LT;
  1038. end;
  1039. OC_LTE:
  1040. begin
  1041. swapped:=true;
  1042. cmp_op:=OC_GTE;
  1043. end;
  1044. OC_BE:
  1045. begin
  1046. swapped:=true;
  1047. cmp_op:=OC_AE;
  1048. end;
  1049. OC_A:
  1050. begin
  1051. swapped:=true;
  1052. cmp_op:=OC_A;
  1053. end;
  1054. end;
  1055. if swapped then
  1056. begin
  1057. tmpreg:=reg1;
  1058. reg1:=reg2;
  1059. reg2:=tmpreg;
  1060. end;
  1061. list.concat(taicpu.op_reg_reg(A_CP,reg1,reg2));
  1062. for i:=2 to tcgsize2size[size] do
  1063. begin
  1064. reg1:=GetNextReg(reg1);
  1065. reg2:=GetNextReg(reg2);
  1066. list.concat(taicpu.op_reg_reg(A_CPC,reg1,reg2));
  1067. end;
  1068. a_jmp_cond(list,cmp_op,l);
  1069. end;
  1070. procedure tcgavr.a_bit_scan_reg_reg(list: TAsmList; reverse: boolean; size: TCGSize; src, dst: TRegister);
  1071. begin
  1072. Comment(V_Error,'tcgarm.a_bit_scan_reg_reg method not implemented');
  1073. end;
  1074. procedure tcgavr.a_jmp_name(list : TAsmList;const s : string);
  1075. var
  1076. ai : taicpu;
  1077. begin
  1078. ai:=taicpu.op_sym(A_JMP,current_asmdata.RefAsmSymbol(s));
  1079. ai.is_jmp:=true;
  1080. list.concat(ai);
  1081. end;
  1082. procedure tcgavr.a_jmp_always(list : TAsmList;l: tasmlabel);
  1083. var
  1084. ai : taicpu;
  1085. begin
  1086. ai:=taicpu.op_sym(A_JMP,l);
  1087. ai.is_jmp:=true;
  1088. list.concat(ai);
  1089. end;
  1090. procedure tcgavr.a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel);
  1091. var
  1092. ai : taicpu;
  1093. begin
  1094. ai:=setcondition(taicpu.op_sym(A_BRxx,l),flags_to_cond(f));
  1095. ai.is_jmp:=true;
  1096. list.concat(ai);
  1097. end;
  1098. procedure tcgavr.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
  1099. var
  1100. l : TAsmLabel;
  1101. tmpflags : TResFlags;
  1102. begin
  1103. current_asmdata.getjumplabel(l);
  1104. {
  1105. if flags_to_cond(f) then
  1106. begin
  1107. tmpflags:=f;
  1108. inverse_flags(tmpflags);
  1109. list.concat(taicpu.op_reg(A_CLR,reg));
  1110. a_jmp_flags(list,tmpflags,l);
  1111. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1112. end
  1113. else
  1114. }
  1115. begin
  1116. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1117. a_jmp_flags(list,f,l);
  1118. list.concat(taicpu.op_reg(A_CLR,reg));
  1119. end;
  1120. cg.a_label(list,l);
  1121. end;
  1122. procedure tcgavr.a_adjust_sp(list : TAsmList; value : longint);
  1123. var
  1124. i : integer;
  1125. begin
  1126. case value of
  1127. 0:
  1128. ;
  1129. -14..-1:
  1130. begin
  1131. if ((-value) mod 2)<>0 then
  1132. list.concat(taicpu.op_reg(A_PUSH,NR_R0));
  1133. for i:=1 to (-value) div 2 do
  1134. list.concat(taicpu.op_const(A_RCALL,0));
  1135. end;
  1136. 1..7:
  1137. begin
  1138. for i:=1 to value do
  1139. list.concat(taicpu.op_reg(A_POP,NR_R0));
  1140. end;
  1141. else
  1142. begin
  1143. list.concat(taicpu.op_reg_const(A_SUBI,NR_R28,lo(word(-value))));
  1144. list.concat(taicpu.op_reg_const(A_SBCI,NR_R29,hi(word(-value))));
  1145. // get SREG
  1146. list.concat(taicpu.op_reg_const(A_IN,NR_R0,NIO_SREG));
  1147. // block interrupts
  1148. list.concat(taicpu.op_none(A_CLI));
  1149. // write high SP
  1150. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_HI,NR_R29));
  1151. // release interrupts
  1152. list.concat(taicpu.op_const_reg(A_OUT,NIO_SREG,NR_R0));
  1153. // write low SP
  1154. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_LO,NR_R28));
  1155. end;
  1156. end;
  1157. end;
  1158. function tcgavr.GetLoad(const ref: treference) : tasmop;
  1159. begin
  1160. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1161. result:=A_LDS
  1162. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1163. result:=A_LDD
  1164. else
  1165. result:=A_LD;
  1166. end;
  1167. function tcgavr.GetStore(const ref: treference) : tasmop;
  1168. begin
  1169. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1170. result:=A_STS
  1171. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1172. result:=A_STD
  1173. else
  1174. result:=A_ST;
  1175. end;
  1176. procedure tcgavr.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
  1177. var
  1178. regs : tcpuregisterset;
  1179. reg : tsuperregister;
  1180. begin
  1181. if not(nostackframe) then
  1182. begin
  1183. { save int registers }
  1184. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1185. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1186. regs:=regs+[RS_R28,RS_R29];
  1187. for reg:=RS_R31 downto RS_R0 do
  1188. if reg in regs then
  1189. list.concat(taicpu.op_reg(A_PUSH,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1190. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1191. begin
  1192. list.concat(taicpu.op_reg_const(A_IN,NR_R28,NIO_SP_LO));
  1193. list.concat(taicpu.op_reg_const(A_IN,NR_R29,NIO_SP_HI));
  1194. end
  1195. else
  1196. { the framepointer cannot be omitted on avr because sp
  1197. is not a register but part of the i/o map
  1198. }
  1199. internalerror(2011021901);
  1200. a_adjust_sp(list,-localsize);
  1201. end;
  1202. end;
  1203. procedure tcgavr.g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean);
  1204. var
  1205. regs : tcpuregisterset;
  1206. reg : TSuperRegister;
  1207. LocalSize : longint;
  1208. begin
  1209. if not(nostackframe) then
  1210. begin
  1211. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1212. begin
  1213. LocalSize:=current_procinfo.calc_stackframe_size;
  1214. a_adjust_sp(list,LocalSize);
  1215. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1216. for reg:=RS_R0 to RS_R31 do
  1217. if reg in regs then
  1218. list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1219. end
  1220. else
  1221. { the framepointer cannot be omitted on avr because sp
  1222. is not a register but part of the i/o map
  1223. }
  1224. internalerror(2011021902);
  1225. end;
  1226. list.concat(taicpu.op_none(A_RET));
  1227. end;
  1228. procedure tcgavr.a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);
  1229. var
  1230. tmpref : treference;
  1231. begin
  1232. if ref.addressmode<>AM_UNCHANGED then
  1233. internalerror(2011021701);
  1234. if assigned(ref.symbol) or (ref.offset<>0) then
  1235. begin
  1236. reference_reset(tmpref,0);
  1237. tmpref.symbol:=ref.symbol;
  1238. tmpref.offset:=ref.offset;
  1239. tmpref.refaddr:=addr_lo8;
  1240. list.concat(taicpu.op_reg_ref(A_LDI,r,tmpref));
  1241. tmpref.refaddr:=addr_hi8;
  1242. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(r),tmpref));
  1243. if (ref.base<>NR_NO) then
  1244. begin
  1245. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.base));
  1246. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.base)));
  1247. end;
  1248. if (ref.index<>NR_NO) then
  1249. begin
  1250. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1251. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1252. end;
  1253. end
  1254. else if (ref.base<>NR_NO)then
  1255. begin
  1256. emit_mov(list,r,ref.base);
  1257. emit_mov(list,GetNextReg(r),GetNextReg(ref.base));
  1258. if (ref.index<>NR_NO) then
  1259. begin
  1260. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1261. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1262. end;
  1263. end
  1264. else if (ref.index<>NR_NO) then
  1265. begin
  1266. emit_mov(list,r,ref.index);
  1267. emit_mov(list,GetNextReg(r),GetNextReg(ref.index));
  1268. end;
  1269. end;
  1270. procedure tcgavr.fixref(list : TAsmList;var ref : treference);
  1271. begin
  1272. internalerror(2011021320);
  1273. end;
  1274. procedure tcgavr.g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  1275. var
  1276. paraloc1,paraloc2,paraloc3 : TCGPara;
  1277. begin
  1278. paraloc1.init;
  1279. paraloc2.init;
  1280. paraloc3.init;
  1281. paramanager.getintparaloc(pocall_default,1,paraloc1);
  1282. paramanager.getintparaloc(pocall_default,2,paraloc2);
  1283. paramanager.getintparaloc(pocall_default,3,paraloc3);
  1284. a_load_const_cgpara(list,OS_INT,len,paraloc3);
  1285. a_loadaddr_ref_cgpara(list,dest,paraloc2);
  1286. a_loadaddr_ref_cgpara(list,source,paraloc1);
  1287. paramanager.freecgpara(list,paraloc3);
  1288. paramanager.freecgpara(list,paraloc2);
  1289. paramanager.freecgpara(list,paraloc1);
  1290. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1291. a_call_name_static(list,'FPC_MOVE');
  1292. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1293. paraloc3.done;
  1294. paraloc2.done;
  1295. paraloc1.done;
  1296. end;
  1297. procedure tcgavr.g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);
  1298. var
  1299. countreg,tmpreg : tregister;
  1300. srcref,dstref : treference;
  1301. copysize,countregsize : tcgsize;
  1302. l : TAsmLabel;
  1303. i : longint;
  1304. SrcQuickRef, DestQuickRef : Boolean;
  1305. begin
  1306. if len>16 then
  1307. begin
  1308. current_asmdata.getjumplabel(l);
  1309. reference_reset(srcref,0);
  1310. reference_reset(dstref,0);
  1311. srcref.base:=NR_R30;
  1312. srcref.addressmode:=AM_POSTINCREMENT;
  1313. dstref.base:=NR_R26;
  1314. dstref.addressmode:=AM_POSTINCREMENT;
  1315. copysize:=OS_8;
  1316. if len<256 then
  1317. countregsize:=OS_8
  1318. else if len<65536 then
  1319. countregsize:=OS_16
  1320. else
  1321. internalerror(2011022007);
  1322. countreg:=getintregister(list,countregsize);
  1323. a_load_const_reg(list,countregsize,len,countreg);
  1324. a_loadaddr_ref_reg(list,source,NR_R30);
  1325. tmpreg:=getaddressregister(list);
  1326. a_loadaddr_ref_reg(list,dest,tmpreg);
  1327. { X is used for spilling code so we can load it
  1328. only by a push/pop sequence, this can be
  1329. optimized later on by the peephole optimizer
  1330. }
  1331. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1332. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1333. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1334. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1335. cg.a_label(list,l);
  1336. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1337. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1338. a_op_const_reg(list,OP_SUB,countregsize,1,countreg);
  1339. a_jmp_flags(list,F_NE,l);
  1340. // keep registers alive
  1341. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  1342. end
  1343. else
  1344. begin
  1345. SrcQuickRef:=false;
  1346. DestQuickRef:=false;
  1347. if not((source.addressmode=AM_UNCHANGED) and
  1348. (source.symbol=nil) and
  1349. ((source.base=NR_R28) or
  1350. (source.base=NR_R29)) and
  1351. (source.Index=NR_NO) and
  1352. (source.Offset in [0..64-len])) and
  1353. not((source.Base=NR_NO) and (source.Index=NR_NO)) then
  1354. srcref:=normalize_ref(list,source,NR_R30)
  1355. else
  1356. begin
  1357. SrcQuickRef:=true;
  1358. srcref:=source;
  1359. end;
  1360. if not((dest.addressmode=AM_UNCHANGED) and
  1361. (dest.symbol=nil) and
  1362. ((dest.base=NR_R28) or
  1363. (dest.base=NR_R29)) and
  1364. (dest.Index=NR_No) and
  1365. (dest.Offset in [0..64-len])) and
  1366. not((dest.Base=NR_NO) and (dest.Index=NR_NO)) then
  1367. begin
  1368. if not(SrcQuickRef) then
  1369. begin
  1370. tmpreg:=getaddressregister(list);
  1371. dstref:=normalize_ref(list,dest,tmpreg);
  1372. { X is used for spilling code so we can load it
  1373. only by a push/pop sequence, this can be
  1374. optimized later on by the peephole optimizer
  1375. }
  1376. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1377. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1378. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1379. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1380. dstref.base:=NR_R26;
  1381. end
  1382. else
  1383. dstref:=normalize_ref(list,dest,NR_R30);
  1384. end
  1385. else
  1386. begin
  1387. DestQuickRef:=true;
  1388. dstref:=dest;
  1389. end;
  1390. for i:=1 to len do
  1391. begin
  1392. if not(SrcQuickRef) and (i<len) then
  1393. srcref.addressmode:=AM_POSTINCREMENT
  1394. else
  1395. srcref.addressmode:=AM_UNCHANGED;
  1396. if not(DestQuickRef) and (i<len) then
  1397. dstref.addressmode:=AM_POSTINCREMENT
  1398. else
  1399. dstref.addressmode:=AM_UNCHANGED;
  1400. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1401. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1402. if SrcQuickRef then
  1403. inc(srcref.offset);
  1404. if DestQuickRef then
  1405. inc(dstref.offset);
  1406. end;
  1407. if not(SrcQuickRef) then
  1408. begin
  1409. ungetcpuregister(list,srcref.base);
  1410. ungetcpuregister(list,GetNextReg(srcref.base));
  1411. end;
  1412. end;
  1413. end;
  1414. procedure tcgavr.g_overflowCheck(list : TAsmList;const l : tlocation;def : tdef);
  1415. var
  1416. hl : tasmlabel;
  1417. ai : taicpu;
  1418. cond : TAsmCond;
  1419. begin
  1420. if not(cs_check_overflow in current_settings.localswitches) then
  1421. exit;
  1422. current_asmdata.getjumplabel(hl);
  1423. if not ((def.typ=pointerdef) or
  1424. ((def.typ=orddef) and
  1425. (torddef(def).ordtype in [u64bit,u16bit,u32bit,u8bit,uchar,
  1426. pasbool8,pasbool16,pasbool32,pasbool64]))) then
  1427. cond:=C_VC
  1428. else
  1429. cond:=C_CC;
  1430. ai:=Taicpu.Op_Sym(A_BRxx,hl);
  1431. ai.SetCondition(cond);
  1432. ai.is_jmp:=true;
  1433. list.concat(ai);
  1434. a_call_name(list,'FPC_OVERFLOW',false);
  1435. a_label(list,hl);
  1436. end;
  1437. procedure tcgavr.g_save_registers(list: TAsmList);
  1438. begin
  1439. { this is done by the entry code }
  1440. end;
  1441. procedure tcgavr.g_restore_registers(list: TAsmList);
  1442. begin
  1443. { this is done by the exit code }
  1444. end;
  1445. procedure tcgavr.a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  1446. var
  1447. ai1,ai2 : taicpu;
  1448. hl : TAsmLabel;
  1449. begin
  1450. ai1:=Taicpu.Op_sym(A_BRxx,l);
  1451. ai1.is_jmp:=true;
  1452. hl:=nil;
  1453. case cond of
  1454. OC_EQ:
  1455. ai1.SetCondition(C_EQ);
  1456. OC_GT:
  1457. begin
  1458. { emulate GT }
  1459. current_asmdata.getjumplabel(hl);
  1460. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1461. ai2.SetCondition(C_EQ);
  1462. ai2.is_jmp:=true;
  1463. list.concat(ai2);
  1464. ai1.SetCondition(C_GE);
  1465. end;
  1466. OC_LT:
  1467. ai1.SetCondition(C_LT);
  1468. OC_GTE:
  1469. ai1.SetCondition(C_GE);
  1470. OC_LTE:
  1471. begin
  1472. { emulate LTE }
  1473. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1474. ai2.SetCondition(C_EQ);
  1475. ai2.is_jmp:=true;
  1476. list.concat(ai2);
  1477. ai1.SetCondition(C_LT);
  1478. end;
  1479. OC_NE:
  1480. ai1.SetCondition(C_NE);
  1481. OC_BE:
  1482. begin
  1483. { emulate BE }
  1484. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1485. ai2.SetCondition(C_EQ);
  1486. ai2.is_jmp:=true;
  1487. list.concat(ai2);
  1488. ai1.SetCondition(C_LO);
  1489. end;
  1490. OC_B:
  1491. ai1.SetCondition(C_LO);
  1492. OC_AE:
  1493. ai1.SetCondition(C_SH);
  1494. OC_A:
  1495. begin
  1496. { emulate A (unsigned GT) }
  1497. current_asmdata.getjumplabel(hl);
  1498. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1499. ai2.SetCondition(C_EQ);
  1500. ai2.is_jmp:=true;
  1501. list.concat(ai2);
  1502. ai1.SetCondition(C_SH);
  1503. end;
  1504. else
  1505. internalerror(2011082501);
  1506. end;
  1507. list.concat(ai1);
  1508. if assigned(hl) then
  1509. a_label(list,hl);
  1510. end;
  1511. procedure tcgavr.g_stackpointer_alloc(list: TAsmList; size: longint);
  1512. begin
  1513. internalerror(201201071);
  1514. end;
  1515. procedure tcgavr.g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);
  1516. begin
  1517. internalerror(2011021324);
  1518. end;
  1519. procedure tcgavr.emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  1520. var
  1521. instr: taicpu;
  1522. begin
  1523. instr:=taicpu.op_reg_reg(A_MOV,reg2,reg1);
  1524. list.Concat(instr);
  1525. { Notify the register allocator that we have written a move instruction so
  1526. it can try to eliminate it. }
  1527. add_move_instruction(instr);
  1528. end;
  1529. procedure tcg64favr.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
  1530. begin
  1531. { TODO : a_op64_reg_reg }
  1532. end;
  1533. procedure tcg64favr.a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);
  1534. begin
  1535. { TODO : a_op64_const_reg }
  1536. end;
  1537. procedure create_codegen;
  1538. begin
  1539. cg:=tcgavr.create;
  1540. cg64:=tcg64favr.create;
  1541. end;
  1542. end.