aoptx86.pas 198 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl and Jonas Maebe
  3. This unit contains the peephole optimizer.
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit aoptx86;
  18. {$i fpcdefs.inc}
  19. {$define DEBUG_AOPTCPU}
  20. interface
  21. uses
  22. globtype,
  23. cpubase,
  24. aasmtai,aasmcpu,
  25. cgbase,cgutils,
  26. aopt,aoptobj;
  27. type
  28. TX86AsmOptimizer = class(TAsmOptimizer)
  29. function RegLoadedWithNewValue(reg : tregister; hp : tai) : boolean; override;
  30. function InstructionLoadsFromReg(const reg : TRegister; const hp : tai) : boolean; override;
  31. function RegReadByInstruction(reg : TRegister; hp : tai) : boolean;
  32. function RegInInstruction(Reg: TRegister; p1: tai): Boolean;override;
  33. function GetNextInstructionUsingReg(Current: tai; out Next: tai; reg: TRegister): Boolean;
  34. protected
  35. { checks whether loading a new value in reg1 overwrites the entirety of reg2 }
  36. function Reg1WriteOverwritesReg2Entirely(reg1, reg2: tregister): boolean;
  37. { checks whether reading the value in reg1 depends on the value of reg2. This
  38. is very similar to SuperRegisterEquals, except it takes into account that
  39. R_SUBH and R_SUBL are independendent (e.g. reading from AL does not
  40. depend on the value in AH). }
  41. function Reg1ReadDependsOnReg2(reg1, reg2: tregister): boolean;
  42. procedure DebugMsg(const s : string; p : tai);inline;
  43. class function IsExitCode(p : tai) : boolean;
  44. class function isFoldableArithOp(hp1 : taicpu; reg : tregister) : boolean;
  45. procedure RemoveLastDeallocForFuncRes(p : tai);
  46. function DoSubAddOpt(var p : tai) : Boolean;
  47. function PrePeepholeOptSxx(var p : tai) : boolean;
  48. function PrePeepholeOptIMUL(var p : tai) : boolean;
  49. function OptPass1AND(var p : tai) : boolean;
  50. function OptPass1_V_MOVAP(var p : tai) : boolean;
  51. function OptPass1VOP(var p : tai) : boolean;
  52. function OptPass1MOV(var p : tai) : boolean;
  53. function OptPass1Movx(var p : tai) : boolean;
  54. function OptPass1MOVXX(var p : tai) : boolean;
  55. function OptPass1OP(var p : tai) : boolean;
  56. function OptPass1LEA(var p : tai) : boolean;
  57. function OptPass1Sub(var p : tai) : boolean;
  58. function OptPass1SHLSAL(var p : tai) : boolean;
  59. function OptPass1SETcc(var p : tai) : boolean;
  60. function OptPass1FSTP(var p : tai) : boolean;
  61. function OptPass1FLD(var p : tai) : boolean;
  62. function OptPass1Cmp(var p : tai) : boolean;
  63. function OptPass2MOV(var p : tai) : boolean;
  64. function OptPass2Imul(var p : tai) : boolean;
  65. function OptPass2Jmp(var p : tai) : boolean;
  66. function OptPass2Jcc(var p : tai) : boolean;
  67. function OptPass2Lea(var p: tai): Boolean;
  68. function PostPeepholeOptMov(var p : tai) : Boolean;
  69. {$ifdef x86_64} { These post-peephole optimisations only affect 64-bit registers. [Kit] }
  70. function PostPeepholeOptMovzx(var p : tai) : Boolean;
  71. function PostPeepholeOptXor(var p : tai) : Boolean;
  72. {$endif}
  73. function PostPeepholeOptCmp(var p : tai) : Boolean;
  74. function PostPeepholeOptTestOr(var p : tai) : Boolean;
  75. function PostPeepholeOptCall(var p : tai) : Boolean;
  76. function PostPeepholeOptLea(var p : tai) : Boolean;
  77. procedure OptReferences;
  78. procedure ConvertJumpToRET(const p: tai; const ret_p: tai);
  79. end;
  80. function MatchInstruction(const instr: tai; const op: TAsmOp; const opsize: topsizes): boolean;
  81. function MatchInstruction(const instr: tai; const op1,op2: TAsmOp; const opsize: topsizes): boolean;
  82. function MatchInstruction(const instr: tai; const op1,op2,op3: TAsmOp; const opsize: topsizes): boolean;
  83. function MatchInstruction(const instr: tai; const ops: array of TAsmOp; const opsize: topsizes): boolean;
  84. function MatchOperand(const oper: TOper; const reg: TRegister): boolean; inline;
  85. function MatchOperand(const oper: TOper; const a: tcgint): boolean; inline;
  86. function MatchOperand(const oper1: TOper; const oper2: TOper): boolean;
  87. function RefsEqual(const r1, r2: treference): boolean;
  88. function MatchReference(const ref : treference;base,index : TRegister) : Boolean;
  89. { returns true, if ref is a reference using only the registers passed as base and index
  90. and having an offset }
  91. function MatchReferenceWithOffset(const ref : treference;base,index : TRegister) : Boolean;
  92. implementation
  93. uses
  94. cutils,verbose,
  95. globals,
  96. cpuinfo,
  97. procinfo,
  98. aasmbase,
  99. aoptutils,
  100. symconst,symsym,
  101. cgx86,
  102. itcpugas;
  103. {$ifdef DEBUG_AOPTCPU}
  104. const
  105. SPeepholeOptimization: shortstring = 'Peephole Optimization: ';
  106. {$else DEBUG_AOPTCPU}
  107. { Empty strings help the optimizer to remove string concatenations that won't
  108. ever appear to the user on release builds. [Kit] }
  109. const
  110. SPeepholeOptimization = '';
  111. {$endif DEBUG_AOPTCPU}
  112. function MatchInstruction(const instr: tai; const op: TAsmOp; const opsize: topsizes): boolean;
  113. begin
  114. result :=
  115. (instr.typ = ait_instruction) and
  116. (taicpu(instr).opcode = op) and
  117. ((opsize = []) or (taicpu(instr).opsize in opsize));
  118. end;
  119. function MatchInstruction(const instr: tai; const op1,op2: TAsmOp; const opsize: topsizes): boolean;
  120. begin
  121. result :=
  122. (instr.typ = ait_instruction) and
  123. ((taicpu(instr).opcode = op1) or
  124. (taicpu(instr).opcode = op2)
  125. ) and
  126. ((opsize = []) or (taicpu(instr).opsize in opsize));
  127. end;
  128. function MatchInstruction(const instr: tai; const op1,op2,op3: TAsmOp; const opsize: topsizes): boolean;
  129. begin
  130. result :=
  131. (instr.typ = ait_instruction) and
  132. ((taicpu(instr).opcode = op1) or
  133. (taicpu(instr).opcode = op2) or
  134. (taicpu(instr).opcode = op3)
  135. ) and
  136. ((opsize = []) or (taicpu(instr).opsize in opsize));
  137. end;
  138. function MatchInstruction(const instr : tai;const ops : array of TAsmOp;
  139. const opsize : topsizes) : boolean;
  140. var
  141. op : TAsmOp;
  142. begin
  143. result:=false;
  144. for op in ops do
  145. begin
  146. if (instr.typ = ait_instruction) and
  147. (taicpu(instr).opcode = op) and
  148. ((opsize = []) or (taicpu(instr).opsize in opsize)) then
  149. begin
  150. result:=true;
  151. exit;
  152. end;
  153. end;
  154. end;
  155. function MatchOperand(const oper: TOper; const reg: TRegister): boolean; inline;
  156. begin
  157. result := (oper.typ = top_reg) and (oper.reg = reg);
  158. end;
  159. function MatchOperand(const oper: TOper; const a: tcgint): boolean; inline;
  160. begin
  161. result := (oper.typ = top_const) and (oper.val = a);
  162. end;
  163. function MatchOperand(const oper1: TOper; const oper2: TOper): boolean;
  164. begin
  165. result := oper1.typ = oper2.typ;
  166. if result then
  167. case oper1.typ of
  168. top_const:
  169. Result:=oper1.val = oper2.val;
  170. top_reg:
  171. Result:=oper1.reg = oper2.reg;
  172. top_ref:
  173. Result:=RefsEqual(oper1.ref^, oper2.ref^);
  174. else
  175. internalerror(2013102801);
  176. end
  177. end;
  178. function RefsEqual(const r1, r2: treference): boolean;
  179. begin
  180. RefsEqual :=
  181. (r1.offset = r2.offset) and
  182. (r1.segment = r2.segment) and (r1.base = r2.base) and
  183. (r1.index = r2.index) and (r1.scalefactor = r2.scalefactor) and
  184. (r1.symbol=r2.symbol) and (r1.refaddr = r2.refaddr) and
  185. (r1.relsymbol = r2.relsymbol) and
  186. (r1.volatility=[]) and
  187. (r2.volatility=[]);
  188. end;
  189. function MatchReference(const ref : treference;base,index : TRegister) : Boolean;
  190. begin
  191. Result:=(ref.offset=0) and
  192. (ref.scalefactor in [0,1]) and
  193. (ref.segment=NR_NO) and
  194. (ref.symbol=nil) and
  195. (ref.relsymbol=nil) and
  196. ((base=NR_INVALID) or
  197. (ref.base=base)) and
  198. ((index=NR_INVALID) or
  199. (ref.index=index)) and
  200. (ref.volatility=[]);
  201. end;
  202. function MatchReferenceWithOffset(const ref : treference;base,index : TRegister) : Boolean;
  203. begin
  204. Result:=(ref.scalefactor in [0,1]) and
  205. (ref.segment=NR_NO) and
  206. (ref.symbol=nil) and
  207. (ref.relsymbol=nil) and
  208. ((base=NR_INVALID) or
  209. (ref.base=base)) and
  210. ((index=NR_INVALID) or
  211. (ref.index=index)) and
  212. (ref.volatility=[]);
  213. end;
  214. function InstrReadsFlags(p: tai): boolean;
  215. begin
  216. InstrReadsFlags := true;
  217. case p.typ of
  218. ait_instruction:
  219. if InsProp[taicpu(p).opcode].Ch*
  220. [Ch_RCarryFlag,Ch_RParityFlag,Ch_RAuxiliaryFlag,Ch_RZeroFlag,Ch_RSignFlag,Ch_ROverflowFlag,
  221. Ch_RWCarryFlag,Ch_RWParityFlag,Ch_RWAuxiliaryFlag,Ch_RWZeroFlag,Ch_RWSignFlag,Ch_RWOverflowFlag,
  222. Ch_RFlags,Ch_RWFlags,Ch_RFLAGScc,Ch_All]<>[] then
  223. exit;
  224. ait_label:
  225. exit;
  226. else
  227. ;
  228. end;
  229. InstrReadsFlags := false;
  230. end;
  231. function TX86AsmOptimizer.GetNextInstructionUsingReg(Current: tai; out Next: tai; reg: TRegister): Boolean;
  232. begin
  233. Next:=Current;
  234. repeat
  235. Result:=GetNextInstruction(Next,Next);
  236. until not (Result) or
  237. not(cs_opt_level3 in current_settings.optimizerswitches) or
  238. (Next.typ<>ait_instruction) or
  239. RegInInstruction(reg,Next) or
  240. is_calljmp(taicpu(Next).opcode);
  241. end;
  242. function TX86AsmOptimizer.InstructionLoadsFromReg(const reg: TRegister;const hp: tai): boolean;
  243. begin
  244. Result:=RegReadByInstruction(reg,hp);
  245. end;
  246. function TX86AsmOptimizer.RegReadByInstruction(reg: TRegister; hp: tai): boolean;
  247. var
  248. p: taicpu;
  249. opcount: longint;
  250. begin
  251. RegReadByInstruction := false;
  252. if hp.typ <> ait_instruction then
  253. exit;
  254. p := taicpu(hp);
  255. case p.opcode of
  256. A_CALL:
  257. regreadbyinstruction := true;
  258. A_IMUL:
  259. case p.ops of
  260. 1:
  261. regReadByInstruction := RegInOp(reg,p.oper[0]^) or
  262. (
  263. ((getregtype(reg)=R_INTREGISTER) and (getsupreg(reg)=RS_EAX)) and
  264. ((getsubreg(reg)<>R_SUBH) or (p.opsize<>S_B))
  265. );
  266. 2,3:
  267. regReadByInstruction :=
  268. reginop(reg,p.oper[0]^) or
  269. reginop(reg,p.oper[1]^);
  270. end;
  271. A_MUL:
  272. begin
  273. regReadByInstruction := RegInOp(reg,p.oper[0]^) or
  274. (
  275. ((getregtype(reg)=R_INTREGISTER) and (getsupreg(reg)=RS_EAX)) and
  276. ((getsubreg(reg)<>R_SUBH) or (p.opsize<>S_B))
  277. );
  278. end;
  279. A_IDIV,A_DIV:
  280. begin
  281. regReadByInstruction := RegInOp(reg,p.oper[0]^) or
  282. (
  283. (getregtype(reg)=R_INTREGISTER) and
  284. (
  285. (getsupreg(reg)=RS_EAX) or ((getsupreg(reg)=RS_EDX) and (p.opsize<>S_B))
  286. )
  287. );
  288. end;
  289. else
  290. begin
  291. if (p.opcode=A_LEA) and is_segment_reg(reg) then
  292. begin
  293. RegReadByInstruction := false;
  294. exit;
  295. end;
  296. for opcount := 0 to p.ops-1 do
  297. if (p.oper[opCount]^.typ = top_ref) and
  298. RegInRef(reg,p.oper[opcount]^.ref^) then
  299. begin
  300. RegReadByInstruction := true;
  301. exit
  302. end;
  303. { special handling for SSE MOVSD }
  304. if (p.opcode=A_MOVSD) and (p.ops>0) then
  305. begin
  306. if p.ops<>2 then
  307. internalerror(2017042702);
  308. regReadByInstruction := reginop(reg,p.oper[0]^) or
  309. (
  310. (p.oper[1]^.typ=top_reg) and (p.oper[0]^.typ=top_reg) and reginop(reg, p.oper[1]^)
  311. );
  312. exit;
  313. end;
  314. with insprop[p.opcode] do
  315. begin
  316. if getregtype(reg)=R_INTREGISTER then
  317. begin
  318. case getsupreg(reg) of
  319. RS_EAX:
  320. if [Ch_REAX,Ch_RWEAX,Ch_MEAX]*Ch<>[] then
  321. begin
  322. RegReadByInstruction := true;
  323. exit
  324. end;
  325. RS_ECX:
  326. if [Ch_RECX,Ch_RWECX,Ch_MECX]*Ch<>[] then
  327. begin
  328. RegReadByInstruction := true;
  329. exit
  330. end;
  331. RS_EDX:
  332. if [Ch_REDX,Ch_RWEDX,Ch_MEDX]*Ch<>[] then
  333. begin
  334. RegReadByInstruction := true;
  335. exit
  336. end;
  337. RS_EBX:
  338. if [Ch_REBX,Ch_RWEBX,Ch_MEBX]*Ch<>[] then
  339. begin
  340. RegReadByInstruction := true;
  341. exit
  342. end;
  343. RS_ESP:
  344. if [Ch_RESP,Ch_RWESP,Ch_MESP]*Ch<>[] then
  345. begin
  346. RegReadByInstruction := true;
  347. exit
  348. end;
  349. RS_EBP:
  350. if [Ch_REBP,Ch_RWEBP,Ch_MEBP]*Ch<>[] then
  351. begin
  352. RegReadByInstruction := true;
  353. exit
  354. end;
  355. RS_ESI:
  356. if [Ch_RESI,Ch_RWESI,Ch_MESI]*Ch<>[] then
  357. begin
  358. RegReadByInstruction := true;
  359. exit
  360. end;
  361. RS_EDI:
  362. if [Ch_REDI,Ch_RWEDI,Ch_MEDI]*Ch<>[] then
  363. begin
  364. RegReadByInstruction := true;
  365. exit
  366. end;
  367. end;
  368. end;
  369. if SuperRegistersEqual(reg,NR_DEFAULTFLAGS) then
  370. begin
  371. if (Ch_RFLAGScc in Ch) and not(getsubreg(reg) in [R_SUBW,R_SUBD,R_SUBQ]) then
  372. begin
  373. case p.condition of
  374. C_A,C_NBE, { CF=0 and ZF=0 }
  375. C_BE,C_NA: { CF=1 or ZF=1 }
  376. RegReadByInstruction:=getsubreg(reg) in [R_SUBFLAGCARRY,R_SUBFLAGZERO];
  377. C_AE,C_NB,C_NC, { CF=0 }
  378. C_B,C_NAE,C_C: { CF=1 }
  379. RegReadByInstruction:=getsubreg(reg) in [R_SUBFLAGCARRY];
  380. C_NE,C_NZ, { ZF=0 }
  381. C_E,C_Z: { ZF=1 }
  382. RegReadByInstruction:=getsubreg(reg) in [R_SUBFLAGZERO];
  383. C_G,C_NLE, { ZF=0 and SF=OF }
  384. C_LE,C_NG: { ZF=1 or SF<>OF }
  385. RegReadByInstruction:=getsubreg(reg) in [R_SUBFLAGZERO,R_SUBFLAGSIGN,R_SUBFLAGOVERFLOW];
  386. C_GE,C_NL, { SF=OF }
  387. C_L,C_NGE: { SF<>OF }
  388. RegReadByInstruction:=getsubreg(reg) in [R_SUBFLAGSIGN,R_SUBFLAGOVERFLOW];
  389. C_NO, { OF=0 }
  390. C_O: { OF=1 }
  391. RegReadByInstruction:=getsubreg(reg) in [R_SUBFLAGOVERFLOW];
  392. C_NP,C_PO, { PF=0 }
  393. C_P,C_PE: { PF=1 }
  394. RegReadByInstruction:=getsubreg(reg) in [R_SUBFLAGPARITY];
  395. C_NS, { SF=0 }
  396. C_S: { SF=1 }
  397. RegReadByInstruction:=getsubreg(reg) in [R_SUBFLAGSIGN];
  398. else
  399. internalerror(2017042701);
  400. end;
  401. if RegReadByInstruction then
  402. exit;
  403. end;
  404. case getsubreg(reg) of
  405. R_SUBW,R_SUBD,R_SUBQ:
  406. RegReadByInstruction :=
  407. [Ch_RCarryFlag,Ch_RParityFlag,Ch_RAuxiliaryFlag,Ch_RZeroFlag,Ch_RSignFlag,Ch_ROverflowFlag,
  408. Ch_RWCarryFlag,Ch_RWParityFlag,Ch_RWAuxiliaryFlag,Ch_RWZeroFlag,Ch_RWSignFlag,Ch_RWOverflowFlag,
  409. Ch_RDirFlag,Ch_RFlags,Ch_RWFlags,Ch_RFLAGScc]*Ch<>[];
  410. R_SUBFLAGCARRY:
  411. RegReadByInstruction:=[Ch_RCarryFlag,Ch_RWCarryFlag,Ch_RFlags,Ch_RWFlags]*Ch<>[];
  412. R_SUBFLAGPARITY:
  413. RegReadByInstruction:=[Ch_RParityFlag,Ch_RWParityFlag,Ch_RFlags,Ch_RWFlags]*Ch<>[];
  414. R_SUBFLAGAUXILIARY:
  415. RegReadByInstruction:=[Ch_RAuxiliaryFlag,Ch_RWAuxiliaryFlag,Ch_RFlags,Ch_RWFlags]*Ch<>[];
  416. R_SUBFLAGZERO:
  417. RegReadByInstruction:=[Ch_RZeroFlag,Ch_RWZeroFlag,Ch_RFlags,Ch_RWFlags]*Ch<>[];
  418. R_SUBFLAGSIGN:
  419. RegReadByInstruction:=[Ch_RSignFlag,Ch_RWSignFlag,Ch_RFlags,Ch_RWFlags]*Ch<>[];
  420. R_SUBFLAGOVERFLOW:
  421. RegReadByInstruction:=[Ch_ROverflowFlag,Ch_RWOverflowFlag,Ch_RFlags,Ch_RWFlags]*Ch<>[];
  422. R_SUBFLAGINTERRUPT:
  423. RegReadByInstruction:=[Ch_RFlags,Ch_RWFlags]*Ch<>[];
  424. R_SUBFLAGDIRECTION:
  425. RegReadByInstruction:=[Ch_RDirFlag,Ch_RFlags,Ch_RWFlags]*Ch<>[];
  426. else
  427. internalerror(2017042601);
  428. end;
  429. exit;
  430. end;
  431. if (Ch_NoReadIfEqualRegs in Ch) and (p.ops=2) and
  432. (p.oper[0]^.typ=top_reg) and (p.oper[1]^.typ=top_reg) and
  433. (p.oper[0]^.reg=p.oper[1]^.reg) then
  434. exit;
  435. if ([CH_RWOP1,CH_ROP1,CH_MOP1]*Ch<>[]) and reginop(reg,p.oper[0]^) then
  436. begin
  437. RegReadByInstruction := true;
  438. exit
  439. end;
  440. if ([Ch_RWOP2,Ch_ROP2,Ch_MOP2]*Ch<>[]) and reginop(reg,p.oper[1]^) then
  441. begin
  442. RegReadByInstruction := true;
  443. exit
  444. end;
  445. if ([Ch_RWOP3,Ch_ROP3,Ch_MOP3]*Ch<>[]) and reginop(reg,p.oper[2]^) then
  446. begin
  447. RegReadByInstruction := true;
  448. exit
  449. end;
  450. if ([Ch_RWOP4,Ch_ROP4,Ch_MOP4]*Ch<>[]) and reginop(reg,p.oper[3]^) then
  451. begin
  452. RegReadByInstruction := true;
  453. exit
  454. end;
  455. end;
  456. end;
  457. end;
  458. end;
  459. function TX86AsmOptimizer.RegInInstruction(Reg: TRegister; p1: tai): Boolean;
  460. begin
  461. result:=false;
  462. if p1.typ<>ait_instruction then
  463. exit;
  464. if (Ch_All in insprop[taicpu(p1).opcode].Ch) then
  465. exit(true);
  466. if (getregtype(reg)=R_INTREGISTER) and
  467. { change information for xmm movsd are not correct }
  468. ((taicpu(p1).opcode<>A_MOVSD) or (taicpu(p1).ops=0)) then
  469. begin
  470. case getsupreg(reg) of
  471. { RS_EAX = RS_RAX on x86-64 }
  472. RS_EAX:
  473. result:=([Ch_REAX,Ch_RRAX,Ch_WEAX,Ch_WRAX,Ch_RWEAX,Ch_RWRAX,Ch_MEAX,Ch_MRAX]*insprop[taicpu(p1).opcode].Ch)<>[];
  474. RS_ECX:
  475. result:=([Ch_RECX,Ch_RRCX,Ch_WECX,Ch_WRCX,Ch_RWECX,Ch_RWRCX,Ch_MECX,Ch_MRCX]*insprop[taicpu(p1).opcode].Ch)<>[];
  476. RS_EDX:
  477. result:=([Ch_REDX,Ch_RRDX,Ch_WEDX,Ch_WRDX,Ch_RWEDX,Ch_RWRDX,Ch_MEDX,Ch_MRDX]*insprop[taicpu(p1).opcode].Ch)<>[];
  478. RS_EBX:
  479. result:=([Ch_REBX,Ch_RRBX,Ch_WEBX,Ch_WRBX,Ch_RWEBX,Ch_RWRBX,Ch_MEBX,Ch_MRBX]*insprop[taicpu(p1).opcode].Ch)<>[];
  480. RS_ESP:
  481. result:=([Ch_RESP,Ch_RRSP,Ch_WESP,Ch_WRSP,Ch_RWESP,Ch_RWRSP,Ch_MESP,Ch_MRSP]*insprop[taicpu(p1).opcode].Ch)<>[];
  482. RS_EBP:
  483. result:=([Ch_REBP,Ch_RRBP,Ch_WEBP,Ch_WRBP,Ch_RWEBP,Ch_RWRBP,Ch_MEBP,Ch_MRBP]*insprop[taicpu(p1).opcode].Ch)<>[];
  484. RS_ESI:
  485. result:=([Ch_RESI,Ch_RRSI,Ch_WESI,Ch_WRSI,Ch_RWESI,Ch_RWRSI,Ch_MESI,Ch_MRSI,Ch_RMemEDI]*insprop[taicpu(p1).opcode].Ch)<>[];
  486. RS_EDI:
  487. result:=([Ch_REDI,Ch_RRDI,Ch_WEDI,Ch_WRDI,Ch_RWEDI,Ch_RWRDI,Ch_MEDI,Ch_MRDI,Ch_WMemEDI]*insprop[taicpu(p1).opcode].Ch)<>[];
  488. else
  489. ;
  490. end;
  491. if result then
  492. exit;
  493. end
  494. else if SuperRegistersEqual(reg,NR_DEFAULTFLAGS) then
  495. begin
  496. if ([Ch_RFlags,Ch_WFlags,Ch_RWFlags,Ch_RFLAGScc]*insprop[taicpu(p1).opcode].Ch)<>[] then
  497. exit(true);
  498. case getsubreg(reg) of
  499. R_SUBFLAGCARRY:
  500. Result:=([Ch_RCarryFlag,Ch_RWCarryFlag,Ch_W0CarryFlag,Ch_W1CarryFlag,Ch_WCarryFlag,Ch_WUCarryFlag]*insprop[taicpu(p1).opcode].Ch)<>[];
  501. R_SUBFLAGPARITY:
  502. Result:=([Ch_RParityFlag,Ch_RWParityFlag,Ch_W0ParityFlag,Ch_W1ParityFlag,Ch_WParityFlag,Ch_WUParityFlag]*insprop[taicpu(p1).opcode].Ch)<>[];
  503. R_SUBFLAGAUXILIARY:
  504. Result:=([Ch_RAuxiliaryFlag,Ch_RWAuxiliaryFlag,Ch_W0AuxiliaryFlag,Ch_W1AuxiliaryFlag,Ch_WAuxiliaryFlag,Ch_WUAuxiliaryFlag]*insprop[taicpu(p1).opcode].Ch)<>[];
  505. R_SUBFLAGZERO:
  506. Result:=([Ch_RZeroFlag,Ch_RWZeroFlag,Ch_W0ZeroFlag,Ch_W1ZeroFlag,Ch_WZeroFlag,Ch_WUZeroFlag]*insprop[taicpu(p1).opcode].Ch)<>[];
  507. R_SUBFLAGSIGN:
  508. Result:=([Ch_RSignFlag,Ch_RWSignFlag,Ch_W0SignFlag,Ch_W1SignFlag,Ch_WSignFlag,Ch_WUSignFlag]*insprop[taicpu(p1).opcode].Ch)<>[];
  509. R_SUBFLAGOVERFLOW:
  510. Result:=([Ch_ROverflowFlag,Ch_RWOverflowFlag,Ch_W0OverflowFlag,Ch_W1OverflowFlag,Ch_WOverflowFlag,Ch_WUOverflowFlag]*insprop[taicpu(p1).opcode].Ch)<>[];
  511. R_SUBFLAGINTERRUPT:
  512. Result:=([Ch_W0IntFlag,Ch_W1IntFlag,Ch_WFlags]*insprop[taicpu(p1).opcode].Ch)<>[];
  513. R_SUBFLAGDIRECTION:
  514. Result:=([Ch_RDirFlag,Ch_W0DirFlag,Ch_W1DirFlag,Ch_WFlags]*insprop[taicpu(p1).opcode].Ch)<>[];
  515. else
  516. ;
  517. end;
  518. if result then
  519. exit;
  520. end
  521. else if (getregtype(reg)=R_FPUREGISTER) and (Ch_FPU in insprop[taicpu(p1).opcode].Ch) then
  522. exit(true);
  523. Result:=inherited RegInInstruction(Reg, p1);
  524. end;
  525. {$ifdef DEBUG_AOPTCPU}
  526. procedure TX86AsmOptimizer.DebugMsg(const s: string;p : tai);
  527. begin
  528. asml.insertbefore(tai_comment.Create(strpnew(s)), p);
  529. end;
  530. function debug_tostr(i: tcgint): string; inline;
  531. begin
  532. Result := tostr(i);
  533. end;
  534. function debug_regname(r: TRegister): string; inline;
  535. begin
  536. Result := '%' + std_regname(r);
  537. end;
  538. { Debug output function - creates a string representation of an operator }
  539. function debug_operstr(oper: TOper): string;
  540. begin
  541. case oper.typ of
  542. top_const:
  543. Result := '$' + debug_tostr(oper.val);
  544. top_reg:
  545. Result := debug_regname(oper.reg);
  546. top_ref:
  547. begin
  548. if oper.ref^.offset <> 0 then
  549. Result := debug_tostr(oper.ref^.offset) + '('
  550. else
  551. Result := '(';
  552. if (oper.ref^.base <> NR_INVALID) and (oper.ref^.base <> NR_NO) then
  553. begin
  554. Result := Result + debug_regname(oper.ref^.base);
  555. if (oper.ref^.index <> NR_INVALID) and (oper.ref^.index <> NR_NO) then
  556. Result := Result + ',' + debug_regname(oper.ref^.index);
  557. end
  558. else
  559. if (oper.ref^.index <> NR_INVALID) and (oper.ref^.index <> NR_NO) then
  560. Result := Result + debug_regname(oper.ref^.index);
  561. if (oper.ref^.scalefactor > 1) then
  562. Result := Result + ',' + debug_tostr(oper.ref^.scalefactor) + ')'
  563. else
  564. Result := Result + ')';
  565. end;
  566. else
  567. Result := '[UNKNOWN]';
  568. end;
  569. end;
  570. function debug_op2str(opcode: tasmop): string; inline;
  571. begin
  572. Result := std_op2str[opcode];
  573. end;
  574. function debug_opsize2str(opsize: topsize): string; inline;
  575. begin
  576. Result := gas_opsize2str[opsize];
  577. end;
  578. {$else DEBUG_AOPTCPU}
  579. procedure TX86AsmOptimizer.DebugMsg(const s: string;p : tai);inline;
  580. begin
  581. end;
  582. function debug_tostr(i: tcgint): string; inline;
  583. begin
  584. Result := '';
  585. end;
  586. function debug_regname(r: TRegister): string; inline;
  587. begin
  588. Result := '';
  589. end;
  590. function debug_operstr(oper: TOper): string; inline;
  591. begin
  592. Result := '';
  593. end;
  594. function debug_op2str(opcode: tasmop): string; inline;
  595. begin
  596. Result := '';
  597. end;
  598. function debug_opsize2str(opsize: topsize): string; inline;
  599. begin
  600. Result := '';
  601. end;
  602. {$endif DEBUG_AOPTCPU}
  603. function TX86AsmOptimizer.Reg1WriteOverwritesReg2Entirely(reg1, reg2: tregister): boolean;
  604. begin
  605. if not SuperRegistersEqual(reg1,reg2) then
  606. exit(false);
  607. if getregtype(reg1)<>R_INTREGISTER then
  608. exit(true); {because SuperRegisterEqual is true}
  609. case getsubreg(reg1) of
  610. { A write to R_SUBL doesn't change R_SUBH and if reg2 is R_SUBW or
  611. higher, it preserves the high bits, so the new value depends on
  612. reg2's previous value. In other words, it is equivalent to doing:
  613. reg2 := (reg2 and $ffffff00) or byte(reg1); }
  614. R_SUBL:
  615. exit(getsubreg(reg2)=R_SUBL);
  616. { A write to R_SUBH doesn't change R_SUBL and if reg2 is R_SUBW or
  617. higher, it actually does a:
  618. reg2 := (reg2 and $ffff00ff) or (reg1 and $ff00); }
  619. R_SUBH:
  620. exit(getsubreg(reg2)=R_SUBH);
  621. { If reg2 is R_SUBD or larger, a write to R_SUBW preserves the high 16
  622. bits of reg2:
  623. reg2 := (reg2 and $ffff0000) or word(reg1); }
  624. R_SUBW:
  625. exit(getsubreg(reg2) in [R_SUBL,R_SUBH,R_SUBW]);
  626. { a write to R_SUBD always overwrites every other subregister,
  627. because it clears the high 32 bits of R_SUBQ on x86_64 }
  628. R_SUBD,
  629. R_SUBQ:
  630. exit(true);
  631. else
  632. internalerror(2017042801);
  633. end;
  634. end;
  635. function TX86AsmOptimizer.Reg1ReadDependsOnReg2(reg1, reg2: tregister): boolean;
  636. begin
  637. if not SuperRegistersEqual(reg1,reg2) then
  638. exit(false);
  639. if getregtype(reg1)<>R_INTREGISTER then
  640. exit(true); {because SuperRegisterEqual is true}
  641. case getsubreg(reg1) of
  642. R_SUBL:
  643. exit(getsubreg(reg2)<>R_SUBH);
  644. R_SUBH:
  645. exit(getsubreg(reg2)<>R_SUBL);
  646. R_SUBW,
  647. R_SUBD,
  648. R_SUBQ:
  649. exit(true);
  650. else
  651. internalerror(2017042802);
  652. end;
  653. end;
  654. function TX86AsmOptimizer.PrePeepholeOptSxx(var p : tai) : boolean;
  655. var
  656. hp1 : tai;
  657. l : TCGInt;
  658. begin
  659. result:=false;
  660. { changes the code sequence
  661. shr/sar const1, x
  662. shl const2, x
  663. to
  664. either "sar/and", "shl/and" or just "and" depending on const1 and const2 }
  665. if GetNextInstruction(p, hp1) and
  666. MatchInstruction(hp1,A_SHL,[]) and
  667. (taicpu(p).oper[0]^.typ = top_const) and
  668. (taicpu(hp1).oper[0]^.typ = top_const) and
  669. (taicpu(hp1).opsize = taicpu(p).opsize) and
  670. (taicpu(hp1).oper[1]^.typ = taicpu(p).oper[1]^.typ) and
  671. OpsEqual(taicpu(hp1).oper[1]^, taicpu(p).oper[1]^) then
  672. begin
  673. if (taicpu(p).oper[0]^.val > taicpu(hp1).oper[0]^.val) and
  674. not(cs_opt_size in current_settings.optimizerswitches) then
  675. begin
  676. { shr/sar const1, %reg
  677. shl const2, %reg
  678. with const1 > const2 }
  679. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val-taicpu(hp1).oper[0]^.val);
  680. taicpu(hp1).opcode := A_AND;
  681. l := (1 shl (taicpu(hp1).oper[0]^.val)) - 1;
  682. case taicpu(p).opsize Of
  683. S_B: taicpu(hp1).loadConst(0,l Xor $ff);
  684. S_W: taicpu(hp1).loadConst(0,l Xor $ffff);
  685. S_L: taicpu(hp1).loadConst(0,l Xor tcgint($ffffffff));
  686. S_Q: taicpu(hp1).loadConst(0,l Xor tcgint($ffffffffffffffff));
  687. else
  688. Internalerror(2017050703)
  689. end;
  690. end
  691. else if (taicpu(p).oper[0]^.val<taicpu(hp1).oper[0]^.val) and
  692. not(cs_opt_size in current_settings.optimizerswitches) then
  693. begin
  694. { shr/sar const1, %reg
  695. shl const2, %reg
  696. with const1 < const2 }
  697. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val-taicpu(p).oper[0]^.val);
  698. taicpu(p).opcode := A_AND;
  699. l := (1 shl (taicpu(p).oper[0]^.val))-1;
  700. case taicpu(p).opsize Of
  701. S_B: taicpu(p).loadConst(0,l Xor $ff);
  702. S_W: taicpu(p).loadConst(0,l Xor $ffff);
  703. S_L: taicpu(p).loadConst(0,l Xor tcgint($ffffffff));
  704. S_Q: taicpu(p).loadConst(0,l Xor tcgint($ffffffffffffffff));
  705. else
  706. Internalerror(2017050702)
  707. end;
  708. end
  709. else if (taicpu(p).oper[0]^.val = taicpu(hp1).oper[0]^.val) then
  710. begin
  711. { shr/sar const1, %reg
  712. shl const2, %reg
  713. with const1 = const2 }
  714. taicpu(p).opcode := A_AND;
  715. l := (1 shl (taicpu(p).oper[0]^.val))-1;
  716. case taicpu(p).opsize Of
  717. S_B: taicpu(p).loadConst(0,l Xor $ff);
  718. S_W: taicpu(p).loadConst(0,l Xor $ffff);
  719. S_L: taicpu(p).loadConst(0,l Xor tcgint($ffffffff));
  720. S_Q: taicpu(p).loadConst(0,l Xor tcgint($ffffffffffffffff));
  721. else
  722. Internalerror(2017050701)
  723. end;
  724. asml.remove(hp1);
  725. hp1.free;
  726. end;
  727. end;
  728. end;
  729. function TX86AsmOptimizer.PrePeepholeOptIMUL(var p : tai) : boolean;
  730. var
  731. opsize : topsize;
  732. hp1 : tai;
  733. tmpref : treference;
  734. ShiftValue : Cardinal;
  735. BaseValue : TCGInt;
  736. begin
  737. result:=false;
  738. opsize:=taicpu(p).opsize;
  739. { changes certain "imul const, %reg"'s to lea sequences }
  740. if (MatchOpType(taicpu(p),top_const,top_reg) or
  741. MatchOpType(taicpu(p),top_const,top_reg,top_reg)) and
  742. (opsize in [S_L{$ifdef x86_64},S_Q{$endif x86_64}]) then
  743. if (taicpu(p).oper[0]^.val = 1) then
  744. if (taicpu(p).ops = 2) then
  745. { remove "imul $1, reg" }
  746. begin
  747. hp1 := tai(p.Next);
  748. DebugMsg(SPeepholeOptimization + 'Imul2Nop done',p);
  749. RemoveCurrentP(p);
  750. result:=true;
  751. end
  752. else
  753. { change "imul $1, reg1, reg2" to "mov reg1, reg2" }
  754. begin
  755. hp1 := taicpu.Op_Reg_Reg(A_MOV, opsize, taicpu(p).oper[1]^.reg,taicpu(p).oper[2]^.reg);
  756. InsertLLItem(p.previous, p.next, hp1);
  757. DebugMsg(SPeepholeOptimization + 'Imul2Mov done',p);
  758. p.free;
  759. p := hp1;
  760. end
  761. else if ((taicpu(p).ops <= 2) or
  762. (taicpu(p).oper[2]^.typ = Top_Reg)) and
  763. not(cs_opt_size in current_settings.optimizerswitches) and
  764. (not(GetNextInstruction(p, hp1)) or
  765. not((tai(hp1).typ = ait_instruction) and
  766. ((taicpu(hp1).opcode=A_Jcc) and
  767. (taicpu(hp1).condition in [C_O,C_NO])))) then
  768. begin
  769. {
  770. imul X, reg1, reg2 to
  771. lea (reg1,reg1,Y), reg2
  772. shl ZZ,reg2
  773. imul XX, reg1 to
  774. lea (reg1,reg1,YY), reg1
  775. shl ZZ,reg2
  776. This optimziation makes sense for pretty much every x86, except the VIA Nano3000: it has IMUL latency 2, lea/shl pair as well,
  777. it does not exist as a separate optimization target in FPC though.
  778. This optimziation can be applied as long as only two bits are set in the constant and those two bits are separated by
  779. at most two zeros
  780. }
  781. reference_reset(tmpref,1,[]);
  782. if (PopCnt(QWord(taicpu(p).oper[0]^.val))=2) and (BsrQWord(taicpu(p).oper[0]^.val)-BsfQWord(taicpu(p).oper[0]^.val)<=3) then
  783. begin
  784. ShiftValue:=BsfQWord(taicpu(p).oper[0]^.val);
  785. BaseValue:=taicpu(p).oper[0]^.val shr ShiftValue;
  786. TmpRef.base := taicpu(p).oper[1]^.reg;
  787. TmpRef.index := taicpu(p).oper[1]^.reg;
  788. if not(BaseValue in [3,5,9]) then
  789. Internalerror(2018110101);
  790. TmpRef.ScaleFactor := BaseValue-1;
  791. if (taicpu(p).ops = 2) then
  792. hp1 := taicpu.op_ref_reg(A_LEA, opsize, TmpRef, taicpu(p).oper[1]^.reg)
  793. else
  794. hp1 := taicpu.op_ref_reg(A_LEA, opsize, TmpRef, taicpu(p).oper[2]^.reg);
  795. AsmL.InsertAfter(hp1,p);
  796. DebugMsg(SPeepholeOptimization + 'Imul2LeaShl done',p);
  797. taicpu(hp1).fileinfo:=taicpu(p).fileinfo;
  798. RemoveCurrentP(p);
  799. if ShiftValue>0 then
  800. AsmL.InsertAfter(taicpu.op_const_reg(A_SHL, opsize, ShiftValue, taicpu(hp1).oper[1]^.reg),hp1);
  801. end;
  802. end;
  803. end;
  804. function TX86AsmOptimizer.RegLoadedWithNewValue(reg: tregister; hp: tai): boolean;
  805. var
  806. p: taicpu;
  807. begin
  808. if not assigned(hp) or
  809. (hp.typ <> ait_instruction) then
  810. begin
  811. Result := false;
  812. exit;
  813. end;
  814. p := taicpu(hp);
  815. if SuperRegistersEqual(reg,NR_DEFAULTFLAGS) then
  816. with insprop[p.opcode] do
  817. begin
  818. case getsubreg(reg) of
  819. R_SUBW,R_SUBD,R_SUBQ:
  820. Result:=
  821. RegLoadedWithNewValue(NR_CARRYFLAG,hp) and
  822. RegLoadedWithNewValue(NR_PARITYFLAG,hp) and
  823. RegLoadedWithNewValue(NR_AUXILIARYFLAG,hp) and
  824. RegLoadedWithNewValue(NR_ZEROFLAG,hp) and
  825. RegLoadedWithNewValue(NR_SIGNFLAG,hp) and
  826. RegLoadedWithNewValue(NR_OVERFLOWFLAG,hp);
  827. R_SUBFLAGCARRY:
  828. Result:=[Ch_W0CarryFlag,Ch_W1CarryFlag,Ch_WCarryFlag,Ch_WUCarryFlag,Ch_WFlags]*Ch<>[];
  829. R_SUBFLAGPARITY:
  830. Result:=[Ch_W0ParityFlag,Ch_W1ParityFlag,Ch_WParityFlag,Ch_WUParityFlag,Ch_WFlags]*Ch<>[];
  831. R_SUBFLAGAUXILIARY:
  832. Result:=[Ch_W0AuxiliaryFlag,Ch_W1AuxiliaryFlag,Ch_WAuxiliaryFlag,Ch_WUAuxiliaryFlag,Ch_WFlags]*Ch<>[];
  833. R_SUBFLAGZERO:
  834. Result:=[Ch_W0ZeroFlag,Ch_W1ZeroFlag,Ch_WZeroFlag,Ch_WUZeroFlag,Ch_WFlags]*Ch<>[];
  835. R_SUBFLAGSIGN:
  836. Result:=[Ch_W0SignFlag,Ch_W1SignFlag,Ch_WSignFlag,Ch_WUSignFlag,Ch_WFlags]*Ch<>[];
  837. R_SUBFLAGOVERFLOW:
  838. Result:=[Ch_W0OverflowFlag,Ch_W1OverflowFlag,Ch_WOverflowFlag,Ch_WUOverflowFlag,Ch_WFlags]*Ch<>[];
  839. R_SUBFLAGINTERRUPT:
  840. Result:=[Ch_W0IntFlag,Ch_W1IntFlag,Ch_WFlags]*Ch<>[];
  841. R_SUBFLAGDIRECTION:
  842. Result:=[Ch_W0DirFlag,Ch_W1DirFlag,Ch_WFlags]*Ch<>[];
  843. else
  844. begin
  845. writeln(getsubreg(reg));
  846. internalerror(2017050501);
  847. end;
  848. end;
  849. exit;
  850. end;
  851. Result :=
  852. (((p.opcode = A_MOV) or
  853. (p.opcode = A_MOVZX) or
  854. (p.opcode = A_MOVSX) or
  855. (p.opcode = A_LEA) or
  856. (p.opcode = A_VMOVSS) or
  857. (p.opcode = A_VMOVSD) or
  858. (p.opcode = A_VMOVAPD) or
  859. (p.opcode = A_VMOVAPS) or
  860. (p.opcode = A_VMOVQ) or
  861. (p.opcode = A_MOVSS) or
  862. (p.opcode = A_MOVSD) or
  863. (p.opcode = A_MOVQ) or
  864. (p.opcode = A_MOVAPD) or
  865. (p.opcode = A_MOVAPS) or
  866. {$ifndef x86_64}
  867. (p.opcode = A_LDS) or
  868. (p.opcode = A_LES) or
  869. {$endif not x86_64}
  870. (p.opcode = A_LFS) or
  871. (p.opcode = A_LGS) or
  872. (p.opcode = A_LSS)) and
  873. (p.ops=2) and { A_MOVSD can have zero operands, so this check is needed }
  874. (p.oper[1]^.typ = top_reg) and
  875. (Reg1WriteOverwritesReg2Entirely(p.oper[1]^.reg,reg)) and
  876. ((p.oper[0]^.typ = top_const) or
  877. ((p.oper[0]^.typ = top_reg) and
  878. not(Reg1ReadDependsOnReg2(p.oper[0]^.reg,reg))) or
  879. ((p.oper[0]^.typ = top_ref) and
  880. not RegInRef(reg,p.oper[0]^.ref^)))) or
  881. ((p.opcode = A_POP) and
  882. (Reg1WriteOverwritesReg2Entirely(p.oper[0]^.reg,reg))) or
  883. ((p.opcode = A_IMUL) and
  884. (p.ops=3) and
  885. (Reg1WriteOverwritesReg2Entirely(p.oper[2]^.reg,reg)) and
  886. (((p.oper[1]^.typ=top_reg) and not(Reg1ReadDependsOnReg2(p.oper[1]^.reg,reg))) or
  887. ((p.oper[1]^.typ=top_ref) and not(RegInRef(reg,p.oper[1]^.ref^))))) or
  888. ((((p.opcode = A_IMUL) or
  889. (p.opcode = A_MUL)) and
  890. (p.ops=1)) and
  891. (((p.oper[0]^.typ=top_reg) and not(Reg1ReadDependsOnReg2(p.oper[0]^.reg,reg))) or
  892. ((p.oper[0]^.typ=top_ref) and not(RegInRef(reg,p.oper[0]^.ref^)))) and
  893. (((p.opsize=S_B) and Reg1WriteOverwritesReg2Entirely(NR_AX,reg) and not(Reg1ReadDependsOnReg2(NR_AL,reg))) or
  894. ((p.opsize=S_W) and Reg1WriteOverwritesReg2Entirely(NR_DX,reg)) or
  895. ((p.opsize=S_L) and Reg1WriteOverwritesReg2Entirely(NR_EDX,reg))
  896. {$ifdef x86_64}
  897. or ((p.opsize=S_Q) and Reg1WriteOverwritesReg2Entirely(NR_RDX,reg))
  898. {$endif x86_64}
  899. )) or
  900. ((p.opcode = A_CWD) and Reg1WriteOverwritesReg2Entirely(NR_DX,reg)) or
  901. ((p.opcode = A_CDQ) and Reg1WriteOverwritesReg2Entirely(NR_EDX,reg)) or
  902. {$ifdef x86_64}
  903. ((p.opcode = A_CQO) and Reg1WriteOverwritesReg2Entirely(NR_RDX,reg)) or
  904. {$endif x86_64}
  905. ((p.opcode = A_CBW) and Reg1WriteOverwritesReg2Entirely(NR_AX,reg) and not(Reg1ReadDependsOnReg2(NR_AL,reg))) or
  906. {$ifndef x86_64}
  907. ((p.opcode = A_LDS) and (reg=NR_DS) and not(RegInRef(reg,p.oper[0]^.ref^))) or
  908. ((p.opcode = A_LES) and (reg=NR_ES) and not(RegInRef(reg,p.oper[0]^.ref^))) or
  909. {$endif not x86_64}
  910. ((p.opcode = A_LFS) and (reg=NR_FS) and not(RegInRef(reg,p.oper[0]^.ref^))) or
  911. ((p.opcode = A_LGS) and (reg=NR_GS) and not(RegInRef(reg,p.oper[0]^.ref^))) or
  912. ((p.opcode = A_LSS) and (reg=NR_SS) and not(RegInRef(reg,p.oper[0]^.ref^))) or
  913. {$ifndef x86_64}
  914. ((p.opcode = A_AAM) and Reg1WriteOverwritesReg2Entirely(NR_AH,reg)) or
  915. {$endif not x86_64}
  916. ((p.opcode = A_LAHF) and Reg1WriteOverwritesReg2Entirely(NR_AH,reg)) or
  917. ((p.opcode = A_LODSB) and Reg1WriteOverwritesReg2Entirely(NR_AL,reg)) or
  918. ((p.opcode = A_LODSW) and Reg1WriteOverwritesReg2Entirely(NR_AX,reg)) or
  919. ((p.opcode = A_LODSD) and Reg1WriteOverwritesReg2Entirely(NR_EAX,reg)) or
  920. {$ifdef x86_64}
  921. ((p.opcode = A_LODSQ) and Reg1WriteOverwritesReg2Entirely(NR_RAX,reg)) or
  922. {$endif x86_64}
  923. ((p.opcode = A_SETcc) and (p.oper[0]^.typ=top_reg) and Reg1WriteOverwritesReg2Entirely(p.oper[0]^.reg,reg)) or
  924. (((p.opcode = A_FSTSW) or
  925. (p.opcode = A_FNSTSW)) and
  926. (p.oper[0]^.typ=top_reg) and
  927. Reg1WriteOverwritesReg2Entirely(p.oper[0]^.reg,reg)) or
  928. (((p.opcode = A_XOR) or (p.opcode = A_SUB) or (p.opcode = A_SBB)) and
  929. (p.oper[0]^.typ=top_reg) and (p.oper[1]^.typ=top_reg) and
  930. (p.oper[0]^.reg=p.oper[1]^.reg) and
  931. Reg1WriteOverwritesReg2Entirely(p.oper[1]^.reg,reg));
  932. end;
  933. class function TX86AsmOptimizer.IsExitCode(p : tai) : boolean;
  934. var
  935. hp2,hp3 : tai;
  936. begin
  937. { some x86-64 issue a NOP before the real exit code }
  938. if MatchInstruction(p,A_NOP,[]) then
  939. GetNextInstruction(p,p);
  940. result:=assigned(p) and (p.typ=ait_instruction) and
  941. ((taicpu(p).opcode = A_RET) or
  942. ((taicpu(p).opcode=A_LEAVE) and
  943. GetNextInstruction(p,hp2) and
  944. MatchInstruction(hp2,A_RET,[S_NO])
  945. ) or
  946. (((taicpu(p).opcode=A_LEA) and
  947. MatchOpType(taicpu(p),top_ref,top_reg) and
  948. (taicpu(p).oper[0]^.ref^.base=NR_STACK_POINTER_REG) and
  949. (taicpu(p).oper[1]^.reg=NR_STACK_POINTER_REG)
  950. ) and
  951. GetNextInstruction(p,hp2) and
  952. MatchInstruction(hp2,A_RET,[S_NO])
  953. ) or
  954. ((((taicpu(p).opcode=A_MOV) and
  955. MatchOpType(taicpu(p),top_reg,top_reg) and
  956. (taicpu(p).oper[0]^.reg=current_procinfo.framepointer) and
  957. (taicpu(p).oper[1]^.reg=NR_STACK_POINTER_REG)) or
  958. ((taicpu(p).opcode=A_LEA) and
  959. MatchOpType(taicpu(p),top_ref,top_reg) and
  960. (taicpu(p).oper[0]^.ref^.base=current_procinfo.framepointer) and
  961. (taicpu(p).oper[1]^.reg=NR_STACK_POINTER_REG)
  962. )
  963. ) and
  964. GetNextInstruction(p,hp2) and
  965. MatchInstruction(hp2,A_POP,[reg2opsize(current_procinfo.framepointer)]) and
  966. MatchOpType(taicpu(hp2),top_reg) and
  967. (taicpu(hp2).oper[0]^.reg=current_procinfo.framepointer) and
  968. GetNextInstruction(hp2,hp3) and
  969. MatchInstruction(hp3,A_RET,[S_NO])
  970. )
  971. );
  972. end;
  973. class function TX86AsmOptimizer.isFoldableArithOp(hp1: taicpu; reg: tregister): boolean;
  974. begin
  975. isFoldableArithOp := False;
  976. case hp1.opcode of
  977. A_ADD,A_SUB,A_OR,A_XOR,A_AND,A_SHL,A_SHR,A_SAR:
  978. isFoldableArithOp :=
  979. ((taicpu(hp1).oper[0]^.typ = top_const) or
  980. ((taicpu(hp1).oper[0]^.typ = top_reg) and
  981. (taicpu(hp1).oper[0]^.reg <> reg))) and
  982. (taicpu(hp1).oper[1]^.typ = top_reg) and
  983. (taicpu(hp1).oper[1]^.reg = reg);
  984. A_INC,A_DEC,A_NEG,A_NOT:
  985. isFoldableArithOp :=
  986. (taicpu(hp1).oper[0]^.typ = top_reg) and
  987. (taicpu(hp1).oper[0]^.reg = reg);
  988. else
  989. ;
  990. end;
  991. end;
  992. procedure TX86AsmOptimizer.RemoveLastDeallocForFuncRes(p: tai);
  993. procedure DoRemoveLastDeallocForFuncRes( supreg: tsuperregister);
  994. var
  995. hp2: tai;
  996. begin
  997. hp2 := p;
  998. repeat
  999. hp2 := tai(hp2.previous);
  1000. if assigned(hp2) and
  1001. (hp2.typ = ait_regalloc) and
  1002. (tai_regalloc(hp2).ratype=ra_dealloc) and
  1003. (getregtype(tai_regalloc(hp2).reg) = R_INTREGISTER) and
  1004. (getsupreg(tai_regalloc(hp2).reg) = supreg) then
  1005. begin
  1006. asml.remove(hp2);
  1007. hp2.free;
  1008. break;
  1009. end;
  1010. until not(assigned(hp2)) or regInInstruction(newreg(R_INTREGISTER,supreg,R_SUBWHOLE),hp2);
  1011. end;
  1012. begin
  1013. case current_procinfo.procdef.returndef.typ of
  1014. arraydef,recorddef,pointerdef,
  1015. stringdef,enumdef,procdef,objectdef,errordef,
  1016. filedef,setdef,procvardef,
  1017. classrefdef,forwarddef:
  1018. DoRemoveLastDeallocForFuncRes(RS_EAX);
  1019. orddef:
  1020. if current_procinfo.procdef.returndef.size <> 0 then
  1021. begin
  1022. DoRemoveLastDeallocForFuncRes(RS_EAX);
  1023. { for int64/qword }
  1024. if current_procinfo.procdef.returndef.size = 8 then
  1025. DoRemoveLastDeallocForFuncRes(RS_EDX);
  1026. end;
  1027. else
  1028. ;
  1029. end;
  1030. end;
  1031. function TX86AsmOptimizer.OptPass1_V_MOVAP(var p : tai) : boolean;
  1032. var
  1033. hp1,hp2 : tai;
  1034. begin
  1035. result:=false;
  1036. if MatchOpType(taicpu(p),top_reg,top_reg) then
  1037. begin
  1038. { vmova* reg1,reg1
  1039. =>
  1040. <nop> }
  1041. if MatchOperand(taicpu(p).oper[0]^,taicpu(p).oper[1]^) then
  1042. begin
  1043. GetNextInstruction(p,hp1);
  1044. asml.Remove(p);
  1045. p.Free;
  1046. p:=hp1;
  1047. result:=true;
  1048. end
  1049. else if GetNextInstruction(p,hp1) then
  1050. begin
  1051. if MatchInstruction(hp1,[taicpu(p).opcode],[S_NO]) and
  1052. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  1053. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[0]^) then
  1054. begin
  1055. { vmova* reg1,reg2
  1056. vmova* reg2,reg3
  1057. dealloc reg2
  1058. =>
  1059. vmova* reg1,reg3 }
  1060. TransferUsedRegs(TmpUsedRegs);
  1061. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  1062. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs)) then
  1063. begin
  1064. taicpu(p).loadoper(1,taicpu(hp1).oper[1]^);
  1065. asml.Remove(hp1);
  1066. hp1.Free;
  1067. result:=true;
  1068. end
  1069. { special case:
  1070. vmova* reg1,reg2
  1071. vmova* reg2,reg1
  1072. =>
  1073. vmova* reg1,reg2 }
  1074. else if MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[1]^) then
  1075. begin
  1076. asml.Remove(hp1);
  1077. hp1.Free;
  1078. result:=true;
  1079. end
  1080. end
  1081. else if MatchInstruction(hp1,[A_VFMADDPD,
  1082. A_VFMADD132PD,
  1083. A_VFMADD132PS,
  1084. A_VFMADD132SD,
  1085. A_VFMADD132SS,
  1086. A_VFMADD213PD,
  1087. A_VFMADD213PS,
  1088. A_VFMADD213SD,
  1089. A_VFMADD213SS,
  1090. A_VFMADD231PD,
  1091. A_VFMADD231PS,
  1092. A_VFMADD231SD,
  1093. A_VFMADD231SS,
  1094. A_VFMADDSUB132PD,
  1095. A_VFMADDSUB132PS,
  1096. A_VFMADDSUB213PD,
  1097. A_VFMADDSUB213PS,
  1098. A_VFMADDSUB231PD,
  1099. A_VFMADDSUB231PS,
  1100. A_VFMSUB132PD,
  1101. A_VFMSUB132PS,
  1102. A_VFMSUB132SD,
  1103. A_VFMSUB132SS,
  1104. A_VFMSUB213PD,
  1105. A_VFMSUB213PS,
  1106. A_VFMSUB213SD,
  1107. A_VFMSUB213SS,
  1108. A_VFMSUB231PD,
  1109. A_VFMSUB231PS,
  1110. A_VFMSUB231SD,
  1111. A_VFMSUB231SS,
  1112. A_VFMSUBADD132PD,
  1113. A_VFMSUBADD132PS,
  1114. A_VFMSUBADD213PD,
  1115. A_VFMSUBADD213PS,
  1116. A_VFMSUBADD231PD,
  1117. A_VFMSUBADD231PS,
  1118. A_VFNMADD132PD,
  1119. A_VFNMADD132PS,
  1120. A_VFNMADD132SD,
  1121. A_VFNMADD132SS,
  1122. A_VFNMADD213PD,
  1123. A_VFNMADD213PS,
  1124. A_VFNMADD213SD,
  1125. A_VFNMADD213SS,
  1126. A_VFNMADD231PD,
  1127. A_VFNMADD231PS,
  1128. A_VFNMADD231SD,
  1129. A_VFNMADD231SS,
  1130. A_VFNMSUB132PD,
  1131. A_VFNMSUB132PS,
  1132. A_VFNMSUB132SD,
  1133. A_VFNMSUB132SS,
  1134. A_VFNMSUB213PD,
  1135. A_VFNMSUB213PS,
  1136. A_VFNMSUB213SD,
  1137. A_VFNMSUB213SS,
  1138. A_VFNMSUB231PD,
  1139. A_VFNMSUB231PS,
  1140. A_VFNMSUB231SD,
  1141. A_VFNMSUB231SS],[S_NO]) and
  1142. { we mix single and double opperations here because we assume that the compiler
  1143. generates vmovapd only after double operations and vmovaps only after single operations }
  1144. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[2]^) and
  1145. GetNextInstruction(hp1,hp2) and
  1146. MatchInstruction(hp2,[A_VMOVAPD,A_VMOVAPS,A_MOVAPD,A_MOVAPS],[S_NO]) and
  1147. MatchOperand(taicpu(p).oper[0]^,taicpu(hp2).oper[1]^) then
  1148. begin
  1149. TransferUsedRegs(TmpUsedRegs);
  1150. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  1151. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  1152. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp2,TmpUsedRegs))
  1153. then
  1154. begin
  1155. taicpu(hp1).loadoper(2,taicpu(p).oper[0]^);
  1156. asml.Remove(p);
  1157. p.Free;
  1158. asml.Remove(hp2);
  1159. hp2.Free;
  1160. p:=hp1;
  1161. end;
  1162. end
  1163. else if (hp1.typ = ait_instruction) and
  1164. GetNextInstruction(hp1, hp2) and
  1165. MatchInstruction(hp2,taicpu(p).opcode,[]) and
  1166. OpsEqual(taicpu(hp2).oper[1]^, taicpu(p).oper[0]^) and
  1167. MatchOpType(taicpu(hp2),top_reg,top_reg) and
  1168. MatchOperand(taicpu(hp2).oper[0]^,taicpu(p).oper[1]^) and
  1169. (((taicpu(p).opcode=A_MOVAPS) and
  1170. ((taicpu(hp1).opcode=A_ADDSS) or (taicpu(hp1).opcode=A_SUBSS) or
  1171. (taicpu(hp1).opcode=A_MULSS) or (taicpu(hp1).opcode=A_DIVSS))) or
  1172. ((taicpu(p).opcode=A_MOVAPD) and
  1173. ((taicpu(hp1).opcode=A_ADDSD) or (taicpu(hp1).opcode=A_SUBSD) or
  1174. (taicpu(hp1).opcode=A_MULSD) or (taicpu(hp1).opcode=A_DIVSD)))
  1175. ) then
  1176. { change
  1177. movapX reg,reg2
  1178. addsX/subsX/... reg3, reg2
  1179. movapX reg2,reg
  1180. to
  1181. addsX/subsX/... reg3,reg
  1182. }
  1183. begin
  1184. TransferUsedRegs(TmpUsedRegs);
  1185. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  1186. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  1187. If not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp2,TmpUsedRegs)) then
  1188. begin
  1189. DebugMsg(SPeepholeOptimization + 'MovapXOpMovapX2Op ('+
  1190. debug_op2str(taicpu(p).opcode)+' '+
  1191. debug_op2str(taicpu(hp1).opcode)+' '+
  1192. debug_op2str(taicpu(hp2).opcode)+') done',p);
  1193. { we cannot eliminate the first move if
  1194. the operations uses the same register for source and dest }
  1195. if not(OpsEqual(taicpu(hp1).oper[1]^,taicpu(hp1).oper[0]^)) then
  1196. begin
  1197. asml.remove(p);
  1198. p.Free;
  1199. end;
  1200. taicpu(hp1).loadoper(1, taicpu(hp2).oper[1]^);
  1201. asml.remove(hp2);
  1202. hp2.Free;
  1203. p:=hp1;
  1204. result:=true;
  1205. end;
  1206. end;
  1207. end;
  1208. end;
  1209. end;
  1210. function TX86AsmOptimizer.OptPass1VOP(var p : tai) : boolean;
  1211. var
  1212. hp1 : tai;
  1213. begin
  1214. result:=false;
  1215. { replace
  1216. V<Op>X %mreg1,%mreg2,%mreg3
  1217. VMovX %mreg3,%mreg4
  1218. dealloc %mreg3
  1219. by
  1220. V<Op>X %mreg1,%mreg2,%mreg4
  1221. ?
  1222. }
  1223. if GetNextInstruction(p,hp1) and
  1224. { we mix single and double operations here because we assume that the compiler
  1225. generates vmovapd only after double operations and vmovaps only after single operations }
  1226. MatchInstruction(hp1,A_VMOVAPD,A_VMOVAPS,[S_NO]) and
  1227. MatchOperand(taicpu(p).oper[2]^,taicpu(hp1).oper[0]^) and
  1228. (taicpu(hp1).oper[1]^.typ=top_reg) then
  1229. begin
  1230. TransferUsedRegs(TmpUsedRegs);
  1231. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  1232. if not(RegUsedAfterInstruction(taicpu(hp1).oper[0]^.reg,hp1,TmpUsedRegs)
  1233. ) then
  1234. begin
  1235. taicpu(p).loadoper(2,taicpu(hp1).oper[1]^);
  1236. DebugMsg(SPeepholeOptimization + 'VOpVmov2VOp done',p);
  1237. asml.Remove(hp1);
  1238. hp1.Free;
  1239. result:=true;
  1240. end;
  1241. end;
  1242. end;
  1243. function TX86AsmOptimizer.OptPass1MOV(var p : tai) : boolean;
  1244. var
  1245. hp1, hp2: tai;
  1246. GetNextInstruction_p: Boolean;
  1247. PreMessage, RegName1, RegName2, InputVal, MaskNum: string;
  1248. NewSize: topsize;
  1249. begin
  1250. Result:=false;
  1251. GetNextInstruction_p:=GetNextInstruction(p, hp1);
  1252. { remove mov reg1,reg1? }
  1253. if MatchOperand(taicpu(p).oper[0]^,taicpu(p).oper[1]^)
  1254. then
  1255. begin
  1256. DebugMsg(SPeepholeOptimization + 'Mov2Nop done',p);
  1257. { take care of the register (de)allocs following p }
  1258. UpdateUsedRegs(tai(p.next));
  1259. asml.remove(p);
  1260. p.free;
  1261. p:=hp1;
  1262. Result:=true;
  1263. exit;
  1264. end;
  1265. if GetNextInstruction_p and
  1266. MatchInstruction(hp1,A_AND,[]) and
  1267. (taicpu(p).oper[1]^.typ = top_reg) and
  1268. MatchOpType(taicpu(hp1),top_const,top_reg) then
  1269. begin
  1270. if MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[1]^) then
  1271. begin
  1272. case taicpu(p).opsize of
  1273. S_L:
  1274. if (taicpu(hp1).oper[0]^.val = $ffffffff) then
  1275. begin
  1276. { Optimize out:
  1277. mov x, %reg
  1278. and ffffffffh, %reg
  1279. }
  1280. DebugMsg(SPeepholeOptimization + 'MovAnd2Mov 1 done',p);
  1281. asml.remove(hp1);
  1282. hp1.free;
  1283. Result:=true;
  1284. exit;
  1285. end;
  1286. S_Q: { TODO: Confirm if this is even possible }
  1287. if (taicpu(hp1).oper[0]^.val = $ffffffffffffffff) then
  1288. begin
  1289. { Optimize out:
  1290. mov x, %reg
  1291. and ffffffffffffffffh, %reg
  1292. }
  1293. DebugMsg(SPeepholeOptimization + 'MovAnd2Mov 2 done',p);
  1294. asml.remove(hp1);
  1295. hp1.free;
  1296. Result:=true;
  1297. exit;
  1298. end;
  1299. else
  1300. ;
  1301. end;
  1302. end
  1303. else if (taicpu(p).oper[1]^.typ = top_reg) and (taicpu(hp1).oper[1]^.typ = top_reg) and
  1304. (taicpu(p).oper[0]^.typ <> top_const) and { MOVZX only supports registers and memory, not immediates (use MOV for that!) }
  1305. (getsupreg(taicpu(p).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg))
  1306. then
  1307. begin
  1308. InputVal := debug_operstr(taicpu(p).oper[0]^);
  1309. MaskNum := debug_tostr(taicpu(hp1).oper[0]^.val);
  1310. case taicpu(p).opsize of
  1311. S_B:
  1312. if (taicpu(hp1).oper[0]^.val = $ff) then
  1313. begin
  1314. { Convert:
  1315. movb x, %regl movb x, %regl
  1316. andw ffh, %regw andl ffh, %regd
  1317. To:
  1318. movzbw x, %regd movzbl x, %regd
  1319. (Identical registers, just different sizes)
  1320. }
  1321. RegName1 := debug_regname(taicpu(p).oper[1]^.reg); { 8-bit register name }
  1322. RegName2 := debug_regname(taicpu(hp1).oper[1]^.reg); { 16/32-bit register name }
  1323. case taicpu(hp1).opsize of
  1324. S_W: NewSize := S_BW;
  1325. S_L: NewSize := S_BL;
  1326. {$ifdef x86_64}
  1327. S_Q: NewSize := S_BQ;
  1328. {$endif x86_64}
  1329. else
  1330. InternalError(2018011510);
  1331. end;
  1332. end
  1333. else
  1334. NewSize := S_NO;
  1335. S_W:
  1336. if (taicpu(hp1).oper[0]^.val = $ffff) then
  1337. begin
  1338. { Convert:
  1339. movw x, %regw
  1340. andl ffffh, %regd
  1341. To:
  1342. movzwl x, %regd
  1343. (Identical registers, just different sizes)
  1344. }
  1345. RegName1 := debug_regname(taicpu(p).oper[1]^.reg); { 16-bit register name }
  1346. RegName2 := debug_regname(taicpu(hp1).oper[1]^.reg); { 32-bit register name }
  1347. case taicpu(hp1).opsize of
  1348. S_L: NewSize := S_WL;
  1349. {$ifdef x86_64}
  1350. S_Q: NewSize := S_WQ;
  1351. {$endif x86_64}
  1352. else
  1353. InternalError(2018011511);
  1354. end;
  1355. end
  1356. else
  1357. NewSize := S_NO;
  1358. else
  1359. NewSize := S_NO;
  1360. end;
  1361. if NewSize <> S_NO then
  1362. begin
  1363. PreMessage := 'mov' + debug_opsize2str(taicpu(p).opsize) + ' ' + InputVal + ',' + RegName1;
  1364. { The actual optimization }
  1365. taicpu(p).opcode := A_MOVZX;
  1366. taicpu(p).changeopsize(NewSize);
  1367. taicpu(p).oper[1]^ := taicpu(hp1).oper[1]^;
  1368. { Safeguard if "and" is followed by a conditional command }
  1369. TransferUsedRegs(TmpUsedRegs);
  1370. UpdateUsedRegs(TmpUsedRegs,tai(p.next));
  1371. if (RegUsedAfterInstruction(NR_DEFAULTFLAGS, hp1, TmpUsedRegs)) then
  1372. begin
  1373. { At this point, the "and" command is effectively equivalent to
  1374. "test %reg,%reg". This will be handled separately by the
  1375. Peephole Optimizer. [Kit] }
  1376. DebugMsg(SPeepholeOptimization + PreMessage +
  1377. ' -> movz' + debug_opsize2str(NewSize) + ' ' + InputVal + ',' + RegName2, p);
  1378. end
  1379. else
  1380. begin
  1381. DebugMsg(SPeepholeOptimization + PreMessage + '; and' + debug_opsize2str(taicpu(hp1).opsize) + ' $' + MaskNum + ',' + RegName2 +
  1382. ' -> movz' + debug_opsize2str(NewSize) + ' ' + InputVal + ',' + RegName2, p);
  1383. asml.Remove(hp1);
  1384. hp1.Free;
  1385. end;
  1386. Result := True;
  1387. Exit;
  1388. end;
  1389. end;
  1390. end;
  1391. { Next instruction is also a MOV ? }
  1392. if GetNextInstruction_p and
  1393. MatchInstruction(hp1,A_MOV,[taicpu(p).opsize]) then
  1394. begin
  1395. if (taicpu(p).oper[1]^.typ = top_reg) and
  1396. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[0]^) then
  1397. begin
  1398. TransferUsedRegs(TmpUsedRegs);
  1399. UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
  1400. { we have
  1401. mov x, %treg
  1402. mov %treg, y
  1403. }
  1404. if not(RegInOp(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[1]^)) and
  1405. not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp1, TmpUsedRegs)) then
  1406. { we've got
  1407. mov x, %treg
  1408. mov %treg, y
  1409. with %treg is not used after }
  1410. case taicpu(p).oper[0]^.typ Of
  1411. top_reg:
  1412. begin
  1413. { change
  1414. mov %reg, %treg
  1415. mov %treg, y
  1416. to
  1417. mov %reg, y
  1418. }
  1419. if taicpu(hp1).oper[1]^.typ=top_reg then
  1420. AllocRegBetween(taicpu(hp1).oper[1]^.reg,p,hp1,usedregs);
  1421. taicpu(p).loadOper(1,taicpu(hp1).oper[1]^);
  1422. DebugMsg(SPeepholeOptimization + 'MovMov2Mov 2 done',p);
  1423. asml.remove(hp1);
  1424. hp1.free;
  1425. Result:=true;
  1426. Exit;
  1427. end;
  1428. top_const:
  1429. begin
  1430. { change
  1431. mov const, %treg
  1432. mov %treg, y
  1433. to
  1434. mov const, y
  1435. }
  1436. if (taicpu(hp1).oper[1]^.typ=top_reg) or
  1437. ((taicpu(p).oper[0]^.val>=low(longint)) and (taicpu(p).oper[0]^.val<=high(longint))) then
  1438. begin
  1439. if taicpu(hp1).oper[1]^.typ=top_reg then
  1440. AllocRegBetween(taicpu(hp1).oper[1]^.reg,p,hp1,usedregs);
  1441. taicpu(p).loadOper(1,taicpu(hp1).oper[1]^);
  1442. DebugMsg(SPeepholeOptimization + 'MovMov2Mov 5 done',p);
  1443. asml.remove(hp1);
  1444. hp1.free;
  1445. Result:=true;
  1446. Exit;
  1447. end;
  1448. end;
  1449. top_ref:
  1450. if (taicpu(hp1).oper[1]^.typ = top_reg) then
  1451. begin
  1452. { change
  1453. mov mem, %treg
  1454. mov %treg, %reg
  1455. to
  1456. mov mem, %reg"
  1457. }
  1458. taicpu(p).loadoper(1,taicpu(hp1).oper[1]^);
  1459. DebugMsg(SPeepholeOptimization + 'MovMov2Mov 3 done',p);
  1460. asml.remove(hp1);
  1461. hp1.free;
  1462. Result:=true;
  1463. Exit;
  1464. end;
  1465. else
  1466. ;
  1467. end;
  1468. end;
  1469. if (taicpu(hp1).oper[0]^.typ = taicpu(p).oper[1]^.typ) and
  1470. (taicpu(hp1).oper[1]^.typ = taicpu(p).oper[0]^.typ) then
  1471. { mov reg1, mem1 or mov mem1, reg1
  1472. mov mem2, reg2 mov reg2, mem2}
  1473. begin
  1474. if OpsEqual(taicpu(hp1).oper[1]^,taicpu(p).oper[0]^) then
  1475. { mov reg1, mem1 or mov mem1, reg1
  1476. mov mem2, reg1 mov reg2, mem1}
  1477. begin
  1478. if OpsEqual(taicpu(hp1).oper[0]^,taicpu(p).oper[1]^) then
  1479. { Removes the second statement from
  1480. mov reg1, mem1/reg2
  1481. mov mem1/reg2, reg1 }
  1482. begin
  1483. if taicpu(p).oper[0]^.typ=top_reg then
  1484. AllocRegBetween(taicpu(p).oper[0]^.reg,p,hp1,usedregs);
  1485. DebugMsg(SPeepholeOptimization + 'MovMov2Mov 1',p);
  1486. asml.remove(hp1);
  1487. hp1.free;
  1488. Result:=true;
  1489. exit;
  1490. end
  1491. else
  1492. begin
  1493. TransferUsedRegs(TmpUsedRegs);
  1494. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  1495. if (taicpu(p).oper[1]^.typ = top_ref) and
  1496. { mov reg1, mem1
  1497. mov mem2, reg1 }
  1498. (taicpu(hp1).oper[0]^.ref^.refaddr = addr_no) and
  1499. GetNextInstruction(hp1, hp2) and
  1500. MatchInstruction(hp2,A_CMP,[taicpu(p).opsize]) and
  1501. OpsEqual(taicpu(p).oper[1]^,taicpu(hp2).oper[0]^) and
  1502. OpsEqual(taicpu(p).oper[0]^,taicpu(hp2).oper[1]^) and
  1503. not(RegUsedAfterInstruction(taicpu(p).oper[0]^.reg, hp2, TmpUsedRegs)) then
  1504. { change to
  1505. mov reg1, mem1 mov reg1, mem1
  1506. mov mem2, reg1 cmp reg1, mem2
  1507. cmp mem1, reg1
  1508. }
  1509. begin
  1510. asml.remove(hp2);
  1511. hp2.free;
  1512. taicpu(hp1).opcode := A_CMP;
  1513. taicpu(hp1).loadref(1,taicpu(hp1).oper[0]^.ref^);
  1514. taicpu(hp1).loadreg(0,taicpu(p).oper[0]^.reg);
  1515. AllocRegBetween(taicpu(p).oper[0]^.reg,p,hp1,UsedRegs);
  1516. DebugMsg(SPeepholeOptimization + 'MovMovCmp2MovCmp done',hp1);
  1517. end;
  1518. end;
  1519. end
  1520. else if (taicpu(p).oper[1]^.typ=top_ref) and
  1521. OpsEqual(taicpu(hp1).oper[0]^,taicpu(p).oper[1]^) then
  1522. begin
  1523. AllocRegBetween(taicpu(p).oper[0]^.reg,p,hp1,UsedRegs);
  1524. taicpu(hp1).loadreg(0,taicpu(p).oper[0]^.reg);
  1525. DebugMsg(SPeepholeOptimization + 'MovMov2MovMov1 done',p);
  1526. end
  1527. else
  1528. begin
  1529. TransferUsedRegs(TmpUsedRegs);
  1530. if GetNextInstruction(hp1, hp2) and
  1531. MatchOpType(taicpu(p),top_ref,top_reg) and
  1532. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[0]^) and
  1533. (taicpu(hp1).oper[1]^.typ = top_ref) and
  1534. MatchInstruction(hp2,A_MOV,[taicpu(p).opsize]) and
  1535. MatchOpType(taicpu(hp2),top_ref,top_reg) and
  1536. RefsEqual(taicpu(hp2).oper[0]^.ref^, taicpu(hp1).oper[1]^.ref^) then
  1537. if not RegInRef(taicpu(hp2).oper[1]^.reg,taicpu(hp2).oper[0]^.ref^) and
  1538. not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,tmpUsedRegs)) then
  1539. { mov mem1, %reg1
  1540. mov %reg1, mem2
  1541. mov mem2, reg2
  1542. to:
  1543. mov mem1, reg2
  1544. mov reg2, mem2}
  1545. begin
  1546. AllocRegBetween(taicpu(hp2).oper[1]^.reg,p,hp2,usedregs);
  1547. DebugMsg(SPeepholeOptimization + 'MovMovMov2MovMov 1 done',p);
  1548. taicpu(p).loadoper(1,taicpu(hp2).oper[1]^);
  1549. taicpu(hp1).loadoper(0,taicpu(hp2).oper[1]^);
  1550. asml.remove(hp2);
  1551. hp2.free;
  1552. end
  1553. {$ifdef i386}
  1554. { this is enabled for i386 only, as the rules to create the reg sets below
  1555. are too complicated for x86-64, so this makes this code too error prone
  1556. on x86-64
  1557. }
  1558. else if (taicpu(p).oper[1]^.reg <> taicpu(hp2).oper[1]^.reg) and
  1559. not(RegInRef(taicpu(p).oper[1]^.reg,taicpu(p).oper[0]^.ref^)) and
  1560. not(RegInRef(taicpu(hp2).oper[1]^.reg,taicpu(hp2).oper[0]^.ref^)) then
  1561. { mov mem1, reg1 mov mem1, reg1
  1562. mov reg1, mem2 mov reg1, mem2
  1563. mov mem2, reg2 mov mem2, reg1
  1564. to: to:
  1565. mov mem1, reg1 mov mem1, reg1
  1566. mov mem1, reg2 mov reg1, mem2
  1567. mov reg1, mem2
  1568. or (if mem1 depends on reg1
  1569. and/or if mem2 depends on reg2)
  1570. to:
  1571. mov mem1, reg1
  1572. mov reg1, mem2
  1573. mov reg1, reg2
  1574. }
  1575. begin
  1576. taicpu(hp1).loadRef(0,taicpu(p).oper[0]^.ref^);
  1577. taicpu(hp1).loadReg(1,taicpu(hp2).oper[1]^.reg);
  1578. taicpu(hp2).loadRef(1,taicpu(hp2).oper[0]^.ref^);
  1579. taicpu(hp2).loadReg(0,taicpu(p).oper[1]^.reg);
  1580. AllocRegBetween(taicpu(p).oper[1]^.reg,p,hp2,usedregs);
  1581. if (taicpu(p).oper[0]^.ref^.base <> NR_NO) and
  1582. (getsupreg(taicpu(p).oper[0]^.ref^.base) in [RS_EAX,RS_EBX,RS_ECX,RS_EDX,RS_ESI,RS_EDI]) then
  1583. AllocRegBetween(taicpu(p).oper[0]^.ref^.base,p,hp2,usedregs);
  1584. if (taicpu(p).oper[0]^.ref^.index <> NR_NO) and
  1585. (getsupreg(taicpu(p).oper[0]^.ref^.index) in [RS_EAX,RS_EBX,RS_ECX,RS_EDX,RS_ESI,RS_EDI]) then
  1586. AllocRegBetween(taicpu(p).oper[0]^.ref^.index,p,hp2,usedregs);
  1587. end
  1588. else if (taicpu(hp1).Oper[0]^.reg <> taicpu(hp2).Oper[1]^.reg) then
  1589. begin
  1590. taicpu(hp2).loadReg(0,taicpu(hp1).Oper[0]^.reg);
  1591. AllocRegBetween(taicpu(p).oper[1]^.reg,p,hp2,usedregs);
  1592. end
  1593. else
  1594. begin
  1595. asml.remove(hp2);
  1596. hp2.free;
  1597. end
  1598. {$endif i386}
  1599. ;
  1600. end;
  1601. end;
  1602. (* { movl [mem1],reg1
  1603. movl [mem1],reg2
  1604. to
  1605. movl [mem1],reg1
  1606. movl reg1,reg2
  1607. }
  1608. else if (taicpu(p).oper[0]^.typ = top_ref) and
  1609. (taicpu(p).oper[1]^.typ = top_reg) and
  1610. (taicpu(hp1).oper[0]^.typ = top_ref) and
  1611. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1612. (taicpu(p).opsize = taicpu(hp1).opsize) and
  1613. RefsEqual(TReference(taicpu(p).oper[0]^^),taicpu(hp1).oper[0]^^.ref^) and
  1614. (taicpu(p).oper[1]^.reg<>taicpu(hp1).oper[0]^^.ref^.base) and
  1615. (taicpu(p).oper[1]^.reg<>taicpu(hp1).oper[0]^^.ref^.index) then
  1616. taicpu(hp1).loadReg(0,taicpu(p).oper[1]^.reg)
  1617. else*)
  1618. { movl const1,[mem1]
  1619. movl [mem1],reg1
  1620. to
  1621. movl const1,reg1
  1622. movl reg1,[mem1]
  1623. }
  1624. if MatchOpType(Taicpu(p),top_const,top_ref) and
  1625. MatchOpType(Taicpu(hp1),top_ref,top_reg) and
  1626. (taicpu(p).opsize = taicpu(hp1).opsize) and
  1627. RefsEqual(taicpu(hp1).oper[0]^.ref^,taicpu(p).oper[1]^.ref^) and
  1628. not(RegInRef(taicpu(hp1).oper[1]^.reg,taicpu(hp1).oper[0]^.ref^)) then
  1629. begin
  1630. AllocRegBetween(taicpu(hp1).oper[1]^.reg,p,hp1,usedregs);
  1631. taicpu(hp1).loadReg(0,taicpu(hp1).oper[1]^.reg);
  1632. taicpu(hp1).loadRef(1,taicpu(p).oper[1]^.ref^);
  1633. taicpu(p).loadReg(1,taicpu(hp1).oper[0]^.reg);
  1634. taicpu(hp1).fileinfo := taicpu(p).fileinfo;
  1635. DebugMsg(SPeepholeOptimization + 'MovMov2MovMov 1',p);
  1636. Result:=true;
  1637. exit;
  1638. end;
  1639. {
  1640. mov* x,reg1
  1641. mov* y,reg1
  1642. to
  1643. mov* y,reg1
  1644. }
  1645. if (taicpu(p).oper[1]^.typ=top_reg) and
  1646. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[1]^) and
  1647. not(RegInOp(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[0]^)) then
  1648. begin
  1649. DebugMsg(SPeepholeOptimization + 'MovMov2Mov 4 done',p);
  1650. { take care of the register (de)allocs following p }
  1651. UpdateUsedRegs(tai(p.next));
  1652. asml.remove(p);
  1653. p.free;
  1654. p:=hp1;
  1655. Result:=true;
  1656. exit;
  1657. end;
  1658. end;
  1659. { search further than the next instruction for a mov }
  1660. if (cs_opt_level3 in current_settings.optimizerswitches) and
  1661. { check as much as possible before the expensive GetNextInstructionUsingReg call }
  1662. (taicpu(p).oper[1]^.typ = top_reg) and
  1663. (taicpu(p).oper[0]^.typ in [top_reg,top_const]) and
  1664. { we work with hp2 here, so hp1 can be still used later on when
  1665. checking for GetNextInstruction_p }
  1666. GetNextInstructionUsingReg(p,hp2,taicpu(p).oper[1]^.reg) and
  1667. MatchInstruction(hp2,A_MOV,[]) and
  1668. MatchOperand(taicpu(p).oper[1]^,taicpu(hp2).oper[0]^) and
  1669. ((taicpu(p).oper[0]^.typ=top_const) or
  1670. ((taicpu(p).oper[0]^.typ=top_reg) and
  1671. not(RegUsedBetween(taicpu(p).oper[0]^.reg, p, hp2))
  1672. )
  1673. ) then
  1674. begin
  1675. TransferUsedRegs(TmpUsedRegs);
  1676. { we have
  1677. mov x, %treg
  1678. mov %treg, y
  1679. }
  1680. if not(RegInOp(taicpu(p).oper[1]^.reg,taicpu(hp2).oper[1]^)) and
  1681. not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp2, TmpUsedRegs)) then
  1682. { we've got
  1683. mov x, %treg
  1684. mov %treg, y
  1685. with %treg is not used after }
  1686. case taicpu(p).oper[0]^.typ Of
  1687. top_reg:
  1688. begin
  1689. { change
  1690. mov %reg, %treg
  1691. mov %treg, y
  1692. to
  1693. mov %reg, y
  1694. }
  1695. AllocRegBetween(taicpu(p).oper[0]^.reg,p,hp2,usedregs);
  1696. taicpu(hp2).loadOper(0,taicpu(p).oper[0]^);
  1697. DebugMsg(SPeepholeOptimization + 'MovMov2Mov 6 done',p);
  1698. { take care of the register (de)allocs following p }
  1699. UpdateUsedRegs(tai(p.next));
  1700. asml.remove(p);
  1701. p.free;
  1702. p:=hp1;
  1703. Result:=true;
  1704. Exit;
  1705. end;
  1706. top_const:
  1707. begin
  1708. { change
  1709. mov const, %treg
  1710. mov %treg, y
  1711. to
  1712. mov const, y
  1713. }
  1714. if (taicpu(hp2).oper[1]^.typ=top_reg) or
  1715. ((taicpu(p).oper[0]^.val>=low(longint)) and (taicpu(p).oper[0]^.val<=high(longint))) then
  1716. begin
  1717. taicpu(hp2).loadOper(0,taicpu(p).oper[0]^);
  1718. DebugMsg(SPeepholeOptimization + 'MovMov2Mov 7 done',p);
  1719. { take care of the register (de)allocs following p }
  1720. UpdateUsedRegs(tai(p.next));
  1721. asml.remove(p);
  1722. p.free;
  1723. p:=hp1;
  1724. Result:=true;
  1725. Exit;
  1726. end;
  1727. end;
  1728. else
  1729. Internalerror(2019103001);
  1730. end;
  1731. end;
  1732. { Change
  1733. mov %reg1, %reg2
  1734. xxx %reg2, ???
  1735. to
  1736. mov %reg1, %reg2
  1737. xxx %reg1, ???
  1738. to avoid a write/read penalty
  1739. }
  1740. if GetNextInstruction_p and
  1741. MatchOpType(taicpu(p),top_reg,top_reg) and
  1742. MatchInstruction(hp1,A_OR,A_AND,A_TEST,[]) and
  1743. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[0]^) and
  1744. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1745. (taicpu(hp1).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) then
  1746. { we have
  1747. mov %reg1, %reg2
  1748. test/or/and %reg2, %reg2
  1749. }
  1750. begin
  1751. TransferUsedRegs(TmpUsedRegs);
  1752. { reg1 will be used after the first instruction,
  1753. so update the allocation info }
  1754. AllocRegBetween(taicpu(p).oper[0]^.reg,p,hp1,usedregs);
  1755. if GetNextInstruction(hp1, hp2) and
  1756. (hp2.typ = ait_instruction) and
  1757. taicpu(hp2).is_jmp and
  1758. not(RegUsedAfterInstruction(taicpu(hp1).oper[0]^.reg, hp1, TmpUsedRegs)) then
  1759. { change
  1760. mov %reg1, %reg2
  1761. test/or/and %reg2, %reg2
  1762. jxx
  1763. to
  1764. test %reg1, %reg1
  1765. jxx
  1766. }
  1767. begin
  1768. taicpu(hp1).loadoper(0,taicpu(p).oper[0]^);
  1769. taicpu(hp1).loadoper(1,taicpu(p).oper[0]^);
  1770. DebugMsg(SPeepholeOptimization + 'MovTestJxx2TestMov done',p);
  1771. asml.remove(p);
  1772. p.free;
  1773. p := hp1;
  1774. Exit;
  1775. end
  1776. else
  1777. { change
  1778. mov %reg1, %reg2
  1779. test/or/and %reg2, %reg2
  1780. to
  1781. mov %reg1, %reg2
  1782. test/or/and %reg1, %reg1
  1783. }
  1784. begin
  1785. taicpu(hp1).loadoper(0,taicpu(p).oper[0]^);
  1786. taicpu(hp1).loadoper(1,taicpu(p).oper[0]^);
  1787. DebugMsg(SPeepholeOptimization + 'MovTestJxx2MovTestJxx done',p);
  1788. end;
  1789. end;
  1790. { leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
  1791. x >= RetOffset) as it doesn't do anything (it writes either to a
  1792. parameter or to the temporary storage room for the function
  1793. result)
  1794. }
  1795. if GetNextInstruction_p and
  1796. IsExitCode(hp1) and
  1797. MatchOpType(taicpu(p),top_reg,top_ref) and
  1798. (taicpu(p).oper[1]^.ref^.base = current_procinfo.FramePointer) and
  1799. not(assigned(current_procinfo.procdef.funcretsym) and
  1800. (taicpu(p).oper[1]^.ref^.offset < tabstractnormalvarsym(current_procinfo.procdef.funcretsym).localloc.reference.offset)) and
  1801. (taicpu(p).oper[1]^.ref^.index = NR_NO) then
  1802. begin
  1803. asml.remove(p);
  1804. p.free;
  1805. p:=hp1;
  1806. DebugMsg(SPeepholeOptimization + 'removed deadstore before leave/ret',p);
  1807. RemoveLastDeallocForFuncRes(p);
  1808. Result:=true;
  1809. exit;
  1810. end;
  1811. if GetNextInstruction_p and
  1812. MatchOpType(taicpu(p),top_reg,top_ref) and
  1813. MatchInstruction(hp1,A_CMP,A_TEST,[taicpu(p).opsize]) and
  1814. (taicpu(hp1).oper[1]^.typ = top_ref) and
  1815. RefsEqual(taicpu(p).oper[1]^.ref^, taicpu(hp1).oper[1]^.ref^) then
  1816. begin
  1817. { change
  1818. mov reg1, mem1
  1819. test/cmp x, mem1
  1820. to
  1821. mov reg1, mem1
  1822. test/cmp x, reg1
  1823. }
  1824. taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
  1825. DebugMsg(SPeepholeOptimization + 'MovTestCmp2MovTestCmp 1',hp1);
  1826. AllocRegBetween(taicpu(p).oper[0]^.reg,p,hp1,usedregs);
  1827. exit;
  1828. end;
  1829. if GetNextInstruction_p and
  1830. (taicpu(p).oper[1]^.typ = top_reg) and
  1831. (hp1.typ = ait_instruction) and
  1832. GetNextInstruction(hp1, hp2) and
  1833. MatchInstruction(hp2,A_MOV,[]) and
  1834. (SuperRegistersEqual(taicpu(hp2).oper[0]^.reg,taicpu(p).oper[1]^.reg)) and
  1835. (IsFoldableArithOp(taicpu(hp1), taicpu(p).oper[1]^.reg) or
  1836. ((taicpu(p).opsize=S_L) and (taicpu(hp1).opsize=S_Q) and (taicpu(hp2).opsize=S_L) and
  1837. IsFoldableArithOp(taicpu(hp1), newreg(R_INTREGISTER,getsupreg(taicpu(p).oper[1]^.reg),R_SUBQ)))
  1838. ) then
  1839. begin
  1840. if OpsEqual(taicpu(hp2).oper[1]^, taicpu(p).oper[0]^) and
  1841. (taicpu(hp2).oper[0]^.typ=top_reg) then
  1842. { change movsX/movzX reg/ref, reg2
  1843. add/sub/or/... reg3/$const, reg2
  1844. mov reg2 reg/ref
  1845. dealloc reg2
  1846. to
  1847. add/sub/or/... reg3/$const, reg/ref }
  1848. begin
  1849. TransferUsedRegs(TmpUsedRegs);
  1850. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  1851. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  1852. If not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp2,TmpUsedRegs)) then
  1853. begin
  1854. { by example:
  1855. movswl %si,%eax movswl %si,%eax p
  1856. decl %eax addl %edx,%eax hp1
  1857. movw %ax,%si movw %ax,%si hp2
  1858. ->
  1859. movswl %si,%eax movswl %si,%eax p
  1860. decw %eax addw %edx,%eax hp1
  1861. movw %ax,%si movw %ax,%si hp2
  1862. }
  1863. DebugMsg(SPeepholeOptimization + 'MovOpMov2Op ('+
  1864. debug_op2str(taicpu(p).opcode)+debug_opsize2str(taicpu(p).opsize)+' '+
  1865. debug_op2str(taicpu(hp1).opcode)+debug_opsize2str(taicpu(hp1).opsize)+' '+
  1866. debug_op2str(taicpu(hp2).opcode)+debug_opsize2str(taicpu(hp2).opsize),p);
  1867. taicpu(hp1).changeopsize(taicpu(hp2).opsize);
  1868. {
  1869. ->
  1870. movswl %si,%eax movswl %si,%eax p
  1871. decw %si addw %dx,%si hp1
  1872. movw %ax,%si movw %ax,%si hp2
  1873. }
  1874. case taicpu(hp1).ops of
  1875. 1:
  1876. begin
  1877. taicpu(hp1).loadoper(0, taicpu(hp2).oper[1]^);
  1878. if taicpu(hp1).oper[0]^.typ=top_reg then
  1879. setsubreg(taicpu(hp1).oper[0]^.reg,getsubreg(taicpu(hp2).oper[0]^.reg));
  1880. end;
  1881. 2:
  1882. begin
  1883. taicpu(hp1).loadoper(1, taicpu(hp2).oper[1]^);
  1884. if (taicpu(hp1).oper[0]^.typ=top_reg) and
  1885. (taicpu(hp1).opcode<>A_SHL) and
  1886. (taicpu(hp1).opcode<>A_SHR) and
  1887. (taicpu(hp1).opcode<>A_SAR) then
  1888. setsubreg(taicpu(hp1).oper[0]^.reg,getsubreg(taicpu(hp2).oper[0]^.reg));
  1889. end;
  1890. else
  1891. internalerror(2008042701);
  1892. end;
  1893. {
  1894. ->
  1895. decw %si addw %dx,%si p
  1896. }
  1897. asml.remove(hp2);
  1898. hp2.Free;
  1899. RemoveCurrentP(p);
  1900. Result:=True;
  1901. Exit;
  1902. end;
  1903. end;
  1904. if MatchOpType(taicpu(hp2),top_reg,top_reg) and
  1905. not(SuperRegistersEqual(taicpu(hp1).oper[0]^.reg,taicpu(hp2).oper[1]^.reg)) and
  1906. ((topsize2memsize[taicpu(hp1).opsize]<= topsize2memsize[taicpu(hp2).opsize]) or
  1907. { opsize matters for these opcodes, we could probably work around this, but it is not worth the effort }
  1908. ((taicpu(hp1).opcode<>A_SHL) and (taicpu(hp1).opcode<>A_SHR) and (taicpu(hp1).opcode<>A_SAR))
  1909. )
  1910. {$ifdef i386}
  1911. { byte registers of esi, edi, ebp, esp are not available on i386 }
  1912. and ((taicpu(hp2).opsize<>S_B) or not(getsupreg(taicpu(hp1).oper[0]^.reg) in [RS_ESI,RS_EDI,RS_EBP,RS_ESP]))
  1913. and ((taicpu(hp2).opsize<>S_B) or not(getsupreg(taicpu(p).oper[0]^.reg) in [RS_ESI,RS_EDI,RS_EBP,RS_ESP]))
  1914. {$endif i386}
  1915. then
  1916. { change movsX/movzX reg/ref, reg2
  1917. add/sub/or/... regX/$const, reg2
  1918. mov reg2, reg3
  1919. dealloc reg2
  1920. to
  1921. movsX/movzX reg/ref, reg3
  1922. add/sub/or/... reg3/$const, reg3
  1923. }
  1924. begin
  1925. TransferUsedRegs(TmpUsedRegs);
  1926. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  1927. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  1928. If not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp2,TmpUsedRegs)) then
  1929. begin
  1930. { by example:
  1931. movswl %si,%eax movswl %si,%eax p
  1932. decl %eax addl %edx,%eax hp1
  1933. movw %ax,%si movw %ax,%si hp2
  1934. ->
  1935. movswl %si,%eax movswl %si,%eax p
  1936. decw %eax addw %edx,%eax hp1
  1937. movw %ax,%si movw %ax,%si hp2
  1938. }
  1939. DebugMsg(SPeepholeOptimization + 'MovOpMov2MovOp ('+
  1940. debug_op2str(taicpu(p).opcode)+debug_opsize2str(taicpu(p).opsize)+' '+
  1941. debug_op2str(taicpu(hp1).opcode)+debug_opsize2str(taicpu(hp1).opsize)+' '+
  1942. debug_op2str(taicpu(hp2).opcode)+debug_opsize2str(taicpu(hp2).opsize)+')',p);
  1943. { limit size of constants as well to avoid assembler errors, but
  1944. check opsize to avoid overflow when left shifting the 1 }
  1945. if (taicpu(p).oper[0]^.typ=top_const) and (topsize2memsize[taicpu(hp2).opsize]<=4) then
  1946. taicpu(p).oper[0]^.val:=taicpu(p).oper[0]^.val and ((qword(1) shl (topsize2memsize[taicpu(hp2).opsize]*8))-1);
  1947. taicpu(hp1).changeopsize(taicpu(hp2).opsize);
  1948. taicpu(p).changeopsize(taicpu(hp2).opsize);
  1949. if taicpu(p).oper[0]^.typ=top_reg then
  1950. setsubreg(taicpu(p).oper[0]^.reg,getsubreg(taicpu(hp2).oper[0]^.reg));
  1951. taicpu(p).loadoper(1, taicpu(hp2).oper[1]^);
  1952. AllocRegBetween(taicpu(p).oper[1]^.reg,p,hp1,usedregs);
  1953. {
  1954. ->
  1955. movswl %si,%eax movswl %si,%eax p
  1956. decw %si addw %dx,%si hp1
  1957. movw %ax,%si movw %ax,%si hp2
  1958. }
  1959. case taicpu(hp1).ops of
  1960. 1:
  1961. begin
  1962. taicpu(hp1).loadoper(0, taicpu(hp2).oper[1]^);
  1963. if taicpu(hp1).oper[0]^.typ=top_reg then
  1964. setsubreg(taicpu(hp1).oper[0]^.reg,getsubreg(taicpu(hp2).oper[0]^.reg));
  1965. end;
  1966. 2:
  1967. begin
  1968. taicpu(hp1).loadoper(1, taicpu(hp2).oper[1]^);
  1969. if (taicpu(hp1).oper[0]^.typ=top_reg) and
  1970. (taicpu(hp1).opcode<>A_SHL) and
  1971. (taicpu(hp1).opcode<>A_SHR) and
  1972. (taicpu(hp1).opcode<>A_SAR) then
  1973. setsubreg(taicpu(hp1).oper[0]^.reg,getsubreg(taicpu(hp2).oper[0]^.reg));
  1974. end;
  1975. else
  1976. internalerror(2018111801);
  1977. end;
  1978. {
  1979. ->
  1980. decw %si addw %dx,%si p
  1981. }
  1982. asml.remove(hp2);
  1983. hp2.Free;
  1984. end;
  1985. end;
  1986. end;
  1987. if GetNextInstruction_p and
  1988. MatchInstruction(hp1,A_BTS,A_BTR,[Taicpu(p).opsize]) and
  1989. GetNextInstruction(hp1, hp2) and
  1990. MatchInstruction(hp2,A_OR,[Taicpu(p).opsize]) and
  1991. MatchOperand(Taicpu(p).oper[0]^,0) and
  1992. (Taicpu(p).oper[1]^.typ = top_reg) and
  1993. MatchOperand(Taicpu(p).oper[1]^,Taicpu(hp1).oper[1]^) and
  1994. MatchOperand(Taicpu(p).oper[1]^,Taicpu(hp2).oper[1]^) then
  1995. { mov reg1,0
  1996. bts reg1,operand1 --> mov reg1,operand2
  1997. or reg1,operand2 bts reg1,operand1}
  1998. begin
  1999. Taicpu(hp2).opcode:=A_MOV;
  2000. asml.remove(hp1);
  2001. insertllitem(hp2,hp2.next,hp1);
  2002. asml.remove(p);
  2003. p.free;
  2004. p:=hp1;
  2005. Result:=true;
  2006. exit;
  2007. end;
  2008. if GetNextInstruction_p and
  2009. MatchInstruction(hp1,A_LEA,[S_L]) and
  2010. MatchOpType(Taicpu(p),top_ref,top_reg) and
  2011. ((MatchReference(Taicpu(hp1).oper[0]^.ref^,Taicpu(hp1).oper[1]^.reg,Taicpu(p).oper[1]^.reg) and
  2012. (Taicpu(hp1).oper[0]^.ref^.base<>Taicpu(p).oper[1]^.reg)
  2013. ) or
  2014. (MatchReference(Taicpu(hp1).oper[0]^.ref^,Taicpu(p).oper[1]^.reg,Taicpu(hp1).oper[1]^.reg) and
  2015. (Taicpu(hp1).oper[0]^.ref^.index<>Taicpu(p).oper[1]^.reg)
  2016. )
  2017. ) then
  2018. { mov reg1,ref
  2019. lea reg2,[reg1,reg2]
  2020. to
  2021. add reg2,ref}
  2022. begin
  2023. TransferUsedRegs(TmpUsedRegs);
  2024. { reg1 may not be used afterwards }
  2025. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp1, TmpUsedRegs)) then
  2026. begin
  2027. Taicpu(hp1).opcode:=A_ADD;
  2028. Taicpu(hp1).oper[0]^.ref^:=Taicpu(p).oper[0]^.ref^;
  2029. DebugMsg(SPeepholeOptimization + 'MovLea2Add done',hp1);
  2030. asml.remove(p);
  2031. p.free;
  2032. p:=hp1;
  2033. result:=true;
  2034. exit;
  2035. end;
  2036. end;
  2037. end;
  2038. function TX86AsmOptimizer.OptPass1MOVXX(var p : tai) : boolean;
  2039. var
  2040. hp1 : tai;
  2041. begin
  2042. Result:=false;
  2043. if taicpu(p).ops <> 2 then
  2044. exit;
  2045. if GetNextInstruction(p,hp1) and
  2046. MatchInstruction(hp1,taicpu(p).opcode,[taicpu(p).opsize]) and
  2047. (taicpu(hp1).ops = 2) then
  2048. begin
  2049. if (taicpu(hp1).oper[0]^.typ = taicpu(p).oper[1]^.typ) and
  2050. (taicpu(hp1).oper[1]^.typ = taicpu(p).oper[0]^.typ) then
  2051. { movXX reg1, mem1 or movXX mem1, reg1
  2052. movXX mem2, reg2 movXX reg2, mem2}
  2053. begin
  2054. if OpsEqual(taicpu(hp1).oper[1]^,taicpu(p).oper[0]^) then
  2055. { movXX reg1, mem1 or movXX mem1, reg1
  2056. movXX mem2, reg1 movXX reg2, mem1}
  2057. begin
  2058. if OpsEqual(taicpu(hp1).oper[0]^,taicpu(p).oper[1]^) then
  2059. begin
  2060. { Removes the second statement from
  2061. movXX reg1, mem1/reg2
  2062. movXX mem1/reg2, reg1
  2063. }
  2064. if taicpu(p).oper[0]^.typ=top_reg then
  2065. AllocRegBetween(taicpu(p).oper[0]^.reg,p,hp1,usedregs);
  2066. { Removes the second statement from
  2067. movXX mem1/reg1, reg2
  2068. movXX reg2, mem1/reg1
  2069. }
  2070. if (taicpu(p).oper[1]^.typ=top_reg) and
  2071. not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,UsedRegs)) then
  2072. begin
  2073. asml.remove(p);
  2074. p.free;
  2075. GetNextInstruction(hp1,p);
  2076. DebugMsg(SPeepholeOptimization + 'MovXXMovXX2Nop 1 done',p);
  2077. end
  2078. else
  2079. DebugMsg(SPeepholeOptimization + 'MovXXMovXX2MoVXX 1 done',p);
  2080. asml.remove(hp1);
  2081. hp1.free;
  2082. Result:=true;
  2083. exit;
  2084. end
  2085. end;
  2086. end;
  2087. end;
  2088. end;
  2089. function TX86AsmOptimizer.OptPass1OP(var p : tai) : boolean;
  2090. var
  2091. hp1 : tai;
  2092. begin
  2093. result:=false;
  2094. { replace
  2095. <Op>X %mreg1,%mreg2 // Op in [ADD,MUL]
  2096. MovX %mreg2,%mreg1
  2097. dealloc %mreg2
  2098. by
  2099. <Op>X %mreg2,%mreg1
  2100. ?
  2101. }
  2102. if GetNextInstruction(p,hp1) and
  2103. { we mix single and double opperations here because we assume that the compiler
  2104. generates vmovapd only after double operations and vmovaps only after single operations }
  2105. MatchInstruction(hp1,A_MOVAPD,A_MOVAPS,[S_NO]) and
  2106. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[0]^) and
  2107. MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[1]^) and
  2108. (taicpu(p).oper[0]^.typ=top_reg) then
  2109. begin
  2110. TransferUsedRegs(TmpUsedRegs);
  2111. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  2112. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs)) then
  2113. begin
  2114. taicpu(p).loadoper(0,taicpu(hp1).oper[0]^);
  2115. taicpu(p).loadoper(1,taicpu(hp1).oper[1]^);
  2116. DebugMsg(SPeepholeOptimization + 'OpMov2Op done',p);
  2117. asml.Remove(hp1);
  2118. hp1.Free;
  2119. result:=true;
  2120. end;
  2121. end;
  2122. end;
  2123. function TX86AsmOptimizer.OptPass1LEA(var p : tai) : boolean;
  2124. var
  2125. hp1, hp2, hp3: tai;
  2126. l : ASizeInt;
  2127. ref: Integer;
  2128. saveref: treference;
  2129. begin
  2130. Result:=false;
  2131. { removes seg register prefixes from LEA operations, as they
  2132. don't do anything}
  2133. taicpu(p).oper[0]^.ref^.Segment:=NR_NO;
  2134. { changes "lea (%reg1), %reg2" into "mov %reg1, %reg2" }
  2135. if (taicpu(p).oper[0]^.ref^.base <> NR_NO) and
  2136. (taicpu(p).oper[0]^.ref^.index = NR_NO) and
  2137. { do not mess with leas acessing the stack pointer }
  2138. (taicpu(p).oper[1]^.reg <> NR_STACK_POINTER_REG) and
  2139. (not(Assigned(taicpu(p).oper[0]^.ref^.Symbol))) then
  2140. begin
  2141. if (taicpu(p).oper[0]^.ref^.base <> taicpu(p).oper[1]^.reg) and
  2142. (taicpu(p).oper[0]^.ref^.offset = 0) then
  2143. begin
  2144. hp1:=taicpu.op_reg_reg(A_MOV,taicpu(p).opsize,taicpu(p).oper[0]^.ref^.base,
  2145. taicpu(p).oper[1]^.reg);
  2146. InsertLLItem(p.previous,p.next, hp1);
  2147. DebugMsg(SPeepholeOptimization + 'Lea2Mov done',hp1);
  2148. p.free;
  2149. p:=hp1;
  2150. Result:=true;
  2151. exit;
  2152. end
  2153. else if (taicpu(p).oper[0]^.ref^.offset = 0) then
  2154. begin
  2155. DebugMsg(SPeepholeOptimization + 'Lea2Nop done',p);
  2156. RemoveCurrentP(p);
  2157. Result:=true;
  2158. exit;
  2159. end
  2160. { continue to use lea to adjust the stack pointer,
  2161. it is the recommended way, but only if not optimizing for size }
  2162. else if (taicpu(p).oper[1]^.reg<>NR_STACK_POINTER_REG) or
  2163. (cs_opt_size in current_settings.optimizerswitches) then
  2164. with taicpu(p).oper[0]^.ref^ do
  2165. if (base = taicpu(p).oper[1]^.reg) then
  2166. begin
  2167. l:=offset;
  2168. if (l=1) and UseIncDec then
  2169. begin
  2170. taicpu(p).opcode:=A_INC;
  2171. taicpu(p).loadreg(0,taicpu(p).oper[1]^.reg);
  2172. taicpu(p).ops:=1;
  2173. DebugMsg(SPeepholeOptimization + 'Lea2Inc done',p);
  2174. end
  2175. else if (l=-1) and UseIncDec then
  2176. begin
  2177. taicpu(p).opcode:=A_DEC;
  2178. taicpu(p).loadreg(0,taicpu(p).oper[1]^.reg);
  2179. taicpu(p).ops:=1;
  2180. DebugMsg(SPeepholeOptimization + 'Lea2Dec done',p);
  2181. end
  2182. else
  2183. begin
  2184. if (l<0) and (l<>-2147483648) then
  2185. begin
  2186. taicpu(p).opcode:=A_SUB;
  2187. taicpu(p).loadConst(0,-l);
  2188. DebugMsg(SPeepholeOptimization + 'Lea2Sub done',p);
  2189. end
  2190. else
  2191. begin
  2192. taicpu(p).opcode:=A_ADD;
  2193. taicpu(p).loadConst(0,l);
  2194. DebugMsg(SPeepholeOptimization + 'Lea2Add done',p);
  2195. end;
  2196. end;
  2197. Result:=true;
  2198. exit;
  2199. end;
  2200. end;
  2201. if GetNextInstruction(p,hp1) and
  2202. MatchInstruction(hp1,A_MOV,[taicpu(p).opsize]) and
  2203. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[0]^) and
  2204. MatchOpType(Taicpu(hp1),top_reg,top_reg) and
  2205. (taicpu(p).oper[1]^.reg<>NR_STACK_POINTER_REG) then
  2206. begin
  2207. TransferUsedRegs(TmpUsedRegs);
  2208. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  2209. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs)) then
  2210. begin
  2211. taicpu(p).loadoper(1,taicpu(hp1).oper[1]^);
  2212. DebugMsg(SPeepholeOptimization + 'LeaMov2Lea done',p);
  2213. asml.Remove(hp1);
  2214. hp1.Free;
  2215. result:=true;
  2216. end;
  2217. end;
  2218. { changes
  2219. lea offset1(regX), reg1
  2220. lea offset2(reg1), reg1
  2221. to
  2222. lea offset1+offset2(regX), reg1 }
  2223. if GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[1]^.reg) and
  2224. MatchInstruction(hp1,A_LEA,[S_L]) and
  2225. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[1]^) and
  2226. (taicpu(hp1).oper[0]^.ref^.base=taicpu(p).oper[1]^.reg) and
  2227. (taicpu(p).oper[0]^.ref^.index=NR_NO) and
  2228. (taicpu(p).oper[0]^.ref^.relsymbol=nil) and
  2229. (taicpu(p).oper[0]^.ref^.scalefactor in [0,1]) and
  2230. (taicpu(p).oper[0]^.ref^.segment=NR_NO) and
  2231. (taicpu(p).oper[0]^.ref^.symbol=nil) and
  2232. (taicpu(p).oper[0]^.ref^.index=taicpu(hp1).oper[0]^.ref^.index) and
  2233. (taicpu(p).oper[0]^.ref^.relsymbol=taicpu(hp1).oper[0]^.ref^.relsymbol) and
  2234. (taicpu(p).oper[0]^.ref^.scalefactor=taicpu(hp1).oper[0]^.ref^.scalefactor) and
  2235. (taicpu(p).oper[0]^.ref^.segment=taicpu(hp1).oper[0]^.ref^.segment) and
  2236. (taicpu(p).oper[0]^.ref^.symbol=taicpu(hp1).oper[0]^.ref^.symbol) then
  2237. begin
  2238. DebugMsg(SPeepholeOptimization + 'LeaLea2Lea done',p);
  2239. inc(taicpu(hp1).oper[0]^.ref^.offset,taicpu(p).oper[0]^.ref^.offset);
  2240. taicpu(hp1).oper[0]^.ref^.base:=taicpu(p).oper[0]^.ref^.base;
  2241. RemoveCurrentP(p);
  2242. result:=true;
  2243. exit;
  2244. end;
  2245. { changes
  2246. lea <ref1>, reg1
  2247. <op> ...,<ref. with reg1>,...
  2248. to
  2249. <op> ...,<ref1>,... }
  2250. if (taicpu(p).oper[1]^.reg<>current_procinfo.framepointer) and
  2251. (taicpu(p).oper[1]^.reg<>NR_STACK_POINTER_REG) and
  2252. GetNextInstruction(p,hp1) and
  2253. (hp1.typ=ait_instruction) and
  2254. not(MatchInstruction(hp1,A_LEA,[])) then
  2255. begin
  2256. { find a reference which uses reg1 }
  2257. if (taicpu(hp1).ops>=1) and (taicpu(hp1).oper[0]^.typ=top_ref) and RegInOp(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[0]^) then
  2258. ref:=0
  2259. else if (taicpu(hp1).ops>=2) and (taicpu(hp1).oper[1]^.typ=top_ref) and RegInOp(taicpu(p).oper[1]^.reg,taicpu(hp1).oper[1]^) then
  2260. ref:=1
  2261. else
  2262. ref:=-1;
  2263. if (ref<>-1) and
  2264. { reg1 must be either the base or the index }
  2265. ((taicpu(hp1).oper[ref]^.ref^.base=taicpu(p).oper[1]^.reg) xor (taicpu(hp1).oper[ref]^.ref^.index=taicpu(p).oper[1]^.reg)) then
  2266. begin
  2267. { reg1 can be removed from the reference }
  2268. saveref:=taicpu(hp1).oper[ref]^.ref^;
  2269. if taicpu(hp1).oper[ref]^.ref^.base=taicpu(p).oper[1]^.reg then
  2270. taicpu(hp1).oper[ref]^.ref^.base:=NR_NO
  2271. else if taicpu(hp1).oper[ref]^.ref^.index=taicpu(p).oper[1]^.reg then
  2272. taicpu(hp1).oper[ref]^.ref^.index:=NR_NO
  2273. else
  2274. Internalerror(2019111201);
  2275. { check if the can insert all data of the lea into the second instruction }
  2276. if ((taicpu(hp1).oper[ref]^.ref^.base=taicpu(p).oper[1]^.reg) or (taicpu(hp1).oper[ref]^.ref^.scalefactor in [0,1])) and
  2277. ((taicpu(p).oper[0]^.ref^.base=NR_NO) or (taicpu(hp1).oper[ref]^.ref^.base=NR_NO)) and
  2278. ((taicpu(p).oper[0]^.ref^.index=NR_NO) or (taicpu(hp1).oper[ref]^.ref^.index=NR_NO)) and
  2279. ((taicpu(p).oper[0]^.ref^.symbol=nil) or (taicpu(hp1).oper[ref]^.ref^.symbol=nil)) and
  2280. ((taicpu(p).oper[0]^.ref^.relsymbol=nil) or (taicpu(hp1).oper[ref]^.ref^.relsymbol=nil)) and
  2281. ((taicpu(p).oper[0]^.ref^.scalefactor in [0,1]) or (taicpu(hp1).oper[ref]^.ref^.scalefactor in [0,1])) and
  2282. (taicpu(p).oper[0]^.ref^.segment=NR_NO) and (taicpu(hp1).oper[ref]^.ref^.segment=NR_NO)
  2283. {$ifdef x86_64}
  2284. and (abs(taicpu(hp1).oper[ref]^.ref^.offset+taicpu(p).oper[0]^.ref^.offset)<=$7fffffff)
  2285. and (((taicpu(p).oper[0]^.ref^.base<>NR_RIP) and (taicpu(p).oper[0]^.ref^.index<>NR_RIP)) or
  2286. ((taicpu(hp1).oper[ref]^.ref^.base=NR_NO) and (taicpu(hp1).oper[ref]^.ref^.index=NR_NO))
  2287. )
  2288. {$endif x86_64}
  2289. then
  2290. begin
  2291. { reg1 might not used by the second instruction after it is remove from the reference }
  2292. if not(RegInInstruction(taicpu(p).oper[1]^.reg,taicpu(hp1))) then
  2293. begin
  2294. TransferUsedRegs(TmpUsedRegs);
  2295. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  2296. { reg1 is not updated so it might not be used afterwards }
  2297. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,TmpUsedRegs)) then
  2298. begin
  2299. DebugMsg(SPeepholeOptimization + 'LeaOp2Op done',p);
  2300. if taicpu(p).oper[0]^.ref^.base<>NR_NO then
  2301. taicpu(hp1).oper[ref]^.ref^.base:=taicpu(p).oper[0]^.ref^.base;
  2302. if taicpu(p).oper[0]^.ref^.index<>NR_NO then
  2303. taicpu(hp1).oper[ref]^.ref^.index:=taicpu(p).oper[0]^.ref^.index;
  2304. if taicpu(p).oper[0]^.ref^.symbol<>nil then
  2305. taicpu(hp1).oper[ref]^.ref^.symbol:=taicpu(p).oper[0]^.ref^.symbol;
  2306. if taicpu(p).oper[0]^.ref^.relsymbol<>nil then
  2307. taicpu(hp1).oper[ref]^.ref^.relsymbol:=taicpu(p).oper[0]^.ref^.relsymbol;
  2308. if not(taicpu(p).oper[0]^.ref^.scalefactor in [0,1]) then
  2309. taicpu(hp1).oper[ref]^.ref^.scalefactor:=taicpu(p).oper[0]^.ref^.scalefactor;
  2310. inc(taicpu(hp1).oper[ref]^.ref^.offset,taicpu(p).oper[0]^.ref^.offset);
  2311. RemoveCurrentP(p);
  2312. result:=true;
  2313. exit;
  2314. end
  2315. end;
  2316. end;
  2317. { recover }
  2318. taicpu(hp1).oper[ref]^.ref^:=saveref;
  2319. end;
  2320. end;
  2321. { replace
  2322. lea x(stackpointer),stackpointer
  2323. call procname
  2324. lea -x(stackpointer),stackpointer
  2325. ret
  2326. by
  2327. jmp procname
  2328. this should never hurt except when pic is used, not sure
  2329. how to handle it then
  2330. but do it only on level 4 because it destroys stack back traces
  2331. }
  2332. if (cs_opt_level4 in current_settings.optimizerswitches) and
  2333. not(cs_create_pic in current_settings.moduleswitches) and
  2334. (taicpu(p).oper[1]^.reg=NR_STACK_POINTER_REG) and
  2335. (taicpu(p).oper[0]^.ref^.base=NR_STACK_POINTER_REG) and
  2336. (taicpu(p).oper[0]^.ref^.index=NR_NO) and
  2337. (taicpu(p).oper[0]^.ref^.relsymbol=nil) and
  2338. (taicpu(p).oper[0]^.ref^.scalefactor in [0,1]) and
  2339. (taicpu(p).oper[0]^.ref^.segment=NR_NO) and
  2340. (taicpu(p).oper[0]^.ref^.symbol=nil) and
  2341. GetNextInstruction(p, hp1) and
  2342. MatchInstruction(hp1,A_CALL,[S_NO]) and
  2343. GetNextInstruction(hp1, hp2) and
  2344. MatchInstruction(hp2,A_LEA,[taicpu(p).opsize]) and
  2345. (taicpu(hp2).oper[1]^.reg=NR_STACK_POINTER_REG) and
  2346. (taicpu(p).oper[0]^.ref^.base=taicpu(hp2).oper[0]^.ref^.base) and
  2347. (taicpu(p).oper[0]^.ref^.index=taicpu(hp2).oper[0]^.ref^.index) and
  2348. (taicpu(p).oper[0]^.ref^.offset=-taicpu(hp2).oper[0]^.ref^.offset) and
  2349. (taicpu(p).oper[0]^.ref^.relsymbol=taicpu(hp2).oper[0]^.ref^.relsymbol) and
  2350. (taicpu(p).oper[0]^.ref^.scalefactor=taicpu(hp2).oper[0]^.ref^.scalefactor) and
  2351. (taicpu(p).oper[0]^.ref^.segment=taicpu(hp2).oper[0]^.ref^.segment) and
  2352. (taicpu(p).oper[0]^.ref^.symbol=taicpu(hp2).oper[0]^.ref^.symbol) and
  2353. GetNextInstruction(hp2, hp3) and
  2354. MatchInstruction(hp3,A_RET,[S_NO]) and
  2355. (taicpu(hp3).ops=0) then
  2356. begin
  2357. DebugMsg(SPeepholeOptimization + 'LeaCallLeaRet2Jmp done',p);
  2358. taicpu(hp1).opcode:=A_JMP;
  2359. taicpu(hp1).is_jmp:=true;
  2360. asml.remove(p);
  2361. asml.remove(hp2);
  2362. asml.remove(hp3);
  2363. p.free;
  2364. hp2.free;
  2365. hp3.free;
  2366. p:=hp1;
  2367. Result:=true;
  2368. end;
  2369. end;
  2370. function TX86AsmOptimizer.DoSubAddOpt(var p: tai): Boolean;
  2371. var
  2372. hp1 : tai;
  2373. begin
  2374. DoSubAddOpt := False;
  2375. if GetLastInstruction(p, hp1) and
  2376. (hp1.typ = ait_instruction) and
  2377. (taicpu(hp1).opsize = taicpu(p).opsize) then
  2378. case taicpu(hp1).opcode Of
  2379. A_DEC:
  2380. if (taicpu(hp1).oper[0]^.typ = top_reg) and
  2381. MatchOperand(taicpu(hp1).oper[0]^,taicpu(p).oper[1]^) then
  2382. begin
  2383. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val+1);
  2384. asml.remove(hp1);
  2385. hp1.free;
  2386. end;
  2387. A_SUB:
  2388. if MatchOpType(taicpu(hp1),top_const,top_reg) and
  2389. MatchOperand(taicpu(hp1).oper[1]^,taicpu(p).oper[1]^) then
  2390. begin
  2391. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val+taicpu(hp1).oper[0]^.val);
  2392. asml.remove(hp1);
  2393. hp1.free;
  2394. end;
  2395. A_ADD:
  2396. begin
  2397. if MatchOpType(taicpu(hp1),top_const,top_reg) and
  2398. MatchOperand(taicpu(hp1).oper[1]^,taicpu(p).oper[1]^) then
  2399. begin
  2400. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val-taicpu(hp1).oper[0]^.val);
  2401. asml.remove(hp1);
  2402. hp1.free;
  2403. if (taicpu(p).oper[0]^.val = 0) then
  2404. begin
  2405. hp1 := tai(p.next);
  2406. asml.remove(p);
  2407. p.free;
  2408. if not GetLastInstruction(hp1, p) then
  2409. p := hp1;
  2410. DoSubAddOpt := True;
  2411. end
  2412. end;
  2413. end;
  2414. else
  2415. ;
  2416. end;
  2417. end;
  2418. function TX86AsmOptimizer.OptPass1Sub(var p : tai) : boolean;
  2419. {$ifdef i386}
  2420. var
  2421. hp1 : tai;
  2422. {$endif i386}
  2423. begin
  2424. Result:=false;
  2425. { * change "subl $2, %esp; pushw x" to "pushl x"}
  2426. { * change "sub/add const1, reg" or "dec reg" followed by
  2427. "sub const2, reg" to one "sub ..., reg" }
  2428. if MatchOpType(taicpu(p),top_const,top_reg) then
  2429. begin
  2430. {$ifdef i386}
  2431. if (taicpu(p).oper[0]^.val = 2) and
  2432. (taicpu(p).oper[1]^.reg = NR_ESP) and
  2433. { Don't do the sub/push optimization if the sub }
  2434. { comes from setting up the stack frame (JM) }
  2435. (not(GetLastInstruction(p,hp1)) or
  2436. not(MatchInstruction(hp1,A_MOV,[S_L]) and
  2437. MatchOperand(taicpu(hp1).oper[0]^,NR_ESP) and
  2438. MatchOperand(taicpu(hp1).oper[0]^,NR_EBP))) then
  2439. begin
  2440. hp1 := tai(p.next);
  2441. while Assigned(hp1) and
  2442. (tai(hp1).typ in [ait_instruction]+SkipInstr) and
  2443. not RegReadByInstruction(NR_ESP,hp1) and
  2444. not RegModifiedByInstruction(NR_ESP,hp1) do
  2445. hp1 := tai(hp1.next);
  2446. if Assigned(hp1) and
  2447. MatchInstruction(hp1,A_PUSH,[S_W]) then
  2448. begin
  2449. taicpu(hp1).changeopsize(S_L);
  2450. if taicpu(hp1).oper[0]^.typ=top_reg then
  2451. setsubreg(taicpu(hp1).oper[0]^.reg,R_SUBWHOLE);
  2452. hp1 := tai(p.next);
  2453. asml.remove(p);
  2454. p.free;
  2455. p := hp1;
  2456. Result:=true;
  2457. exit;
  2458. end;
  2459. end;
  2460. {$endif i386}
  2461. if DoSubAddOpt(p) then
  2462. Result:=true;
  2463. end;
  2464. end;
  2465. function TX86AsmOptimizer.OptPass1SHLSAL(var p : tai) : boolean;
  2466. var
  2467. TmpBool1,TmpBool2 : Boolean;
  2468. tmpref : treference;
  2469. hp1,hp2: tai;
  2470. begin
  2471. Result:=false;
  2472. if MatchOpType(taicpu(p),top_const,top_reg) and
  2473. (taicpu(p).opsize in [S_L{$ifdef x86_64},S_Q{$endif x86_64}]) and
  2474. (taicpu(p).oper[0]^.val <= 3) then
  2475. { Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement }
  2476. begin
  2477. { should we check the next instruction? }
  2478. TmpBool1 := True;
  2479. { have we found an add/sub which could be
  2480. integrated in the lea? }
  2481. TmpBool2 := False;
  2482. reference_reset(tmpref,2,[]);
  2483. TmpRef.index := taicpu(p).oper[1]^.reg;
  2484. TmpRef.scalefactor := 1 shl taicpu(p).oper[0]^.val;
  2485. while TmpBool1 and
  2486. GetNextInstruction(p, hp1) and
  2487. (tai(hp1).typ = ait_instruction) and
  2488. ((((taicpu(hp1).opcode = A_ADD) or
  2489. (taicpu(hp1).opcode = A_SUB)) and
  2490. (taicpu(hp1).oper[1]^.typ = Top_Reg) and
  2491. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg)) or
  2492. (((taicpu(hp1).opcode = A_INC) or
  2493. (taicpu(hp1).opcode = A_DEC)) and
  2494. (taicpu(hp1).oper[0]^.typ = Top_Reg) and
  2495. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg)) or
  2496. ((taicpu(hp1).opcode = A_LEA) and
  2497. (taicpu(hp1).oper[0]^.ref^.index = taicpu(p).oper[1]^.reg) and
  2498. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg))) and
  2499. (not GetNextInstruction(hp1,hp2) or
  2500. not instrReadsFlags(hp2)) Do
  2501. begin
  2502. TmpBool1 := False;
  2503. if taicpu(hp1).opcode=A_LEA then
  2504. begin
  2505. if (TmpRef.base = NR_NO) and
  2506. (taicpu(hp1).oper[0]^.ref^.symbol=nil) and
  2507. (taicpu(hp1).oper[0]^.ref^.relsymbol=nil) and
  2508. (taicpu(hp1).oper[0]^.ref^.segment=NR_NO) and
  2509. ((taicpu(hp1).oper[0]^.ref^.scalefactor=0) or
  2510. (taicpu(hp1).oper[0]^.ref^.scalefactor*tmpref.scalefactor<=8)) then
  2511. begin
  2512. TmpBool1 := True;
  2513. TmpBool2 := True;
  2514. inc(TmpRef.offset, taicpu(hp1).oper[0]^.ref^.offset);
  2515. if taicpu(hp1).oper[0]^.ref^.scalefactor<>0 then
  2516. tmpref.scalefactor:=tmpref.scalefactor*taicpu(hp1).oper[0]^.ref^.scalefactor;
  2517. TmpRef.base := taicpu(hp1).oper[0]^.ref^.base;
  2518. asml.remove(hp1);
  2519. hp1.free;
  2520. end
  2521. end
  2522. else if (taicpu(hp1).oper[0]^.typ = Top_Const) then
  2523. begin
  2524. TmpBool1 := True;
  2525. TmpBool2 := True;
  2526. case taicpu(hp1).opcode of
  2527. A_ADD:
  2528. inc(TmpRef.offset, longint(taicpu(hp1).oper[0]^.val));
  2529. A_SUB:
  2530. dec(TmpRef.offset, longint(taicpu(hp1).oper[0]^.val));
  2531. else
  2532. internalerror(2019050536);
  2533. end;
  2534. asml.remove(hp1);
  2535. hp1.free;
  2536. end
  2537. else
  2538. if (taicpu(hp1).oper[0]^.typ = Top_Reg) and
  2539. (((taicpu(hp1).opcode = A_ADD) and
  2540. (TmpRef.base = NR_NO)) or
  2541. (taicpu(hp1).opcode = A_INC) or
  2542. (taicpu(hp1).opcode = A_DEC)) then
  2543. begin
  2544. TmpBool1 := True;
  2545. TmpBool2 := True;
  2546. case taicpu(hp1).opcode of
  2547. A_ADD:
  2548. TmpRef.base := taicpu(hp1).oper[0]^.reg;
  2549. A_INC:
  2550. inc(TmpRef.offset);
  2551. A_DEC:
  2552. dec(TmpRef.offset);
  2553. else
  2554. internalerror(2019050535);
  2555. end;
  2556. asml.remove(hp1);
  2557. hp1.free;
  2558. end;
  2559. end;
  2560. if TmpBool2
  2561. {$ifndef x86_64}
  2562. or
  2563. ((current_settings.optimizecputype < cpu_Pentium2) and
  2564. (taicpu(p).oper[0]^.val <= 3) and
  2565. not(cs_opt_size in current_settings.optimizerswitches))
  2566. {$endif x86_64}
  2567. then
  2568. begin
  2569. if not(TmpBool2) and
  2570. (taicpu(p).oper[0]^.val=1) then
  2571. begin
  2572. hp1:=taicpu.Op_reg_reg(A_ADD,taicpu(p).opsize,
  2573. taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg)
  2574. end
  2575. else
  2576. hp1:=taicpu.op_ref_reg(A_LEA, taicpu(p).opsize, TmpRef,
  2577. taicpu(p).oper[1]^.reg);
  2578. DebugMsg(SPeepholeOptimization + 'ShlAddLeaSubIncDec2Lea',p);
  2579. InsertLLItem(p.previous, p.next, hp1);
  2580. p.free;
  2581. p := hp1;
  2582. end;
  2583. end
  2584. {$ifndef x86_64}
  2585. else if (current_settings.optimizecputype < cpu_Pentium2) and
  2586. MatchOpType(taicpu(p),top_const,top_reg) then
  2587. begin
  2588. { changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
  2589. but faster on a 486, and Tairable in both U and V pipes on the Pentium
  2590. (unlike shl, which is only Tairable in the U pipe) }
  2591. if taicpu(p).oper[0]^.val=1 then
  2592. begin
  2593. hp1 := taicpu.Op_reg_reg(A_ADD,taicpu(p).opsize,
  2594. taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg);
  2595. InsertLLItem(p.previous, p.next, hp1);
  2596. p.free;
  2597. p := hp1;
  2598. end
  2599. { changes "shl $2, %reg" to "lea (,%reg,4), %reg"
  2600. "shl $3, %reg" to "lea (,%reg,8), %reg }
  2601. else if (taicpu(p).opsize = S_L) and
  2602. (taicpu(p).oper[0]^.val<= 3) then
  2603. begin
  2604. reference_reset(tmpref,2,[]);
  2605. TmpRef.index := taicpu(p).oper[1]^.reg;
  2606. TmpRef.scalefactor := 1 shl taicpu(p).oper[0]^.val;
  2607. hp1 := taicpu.Op_ref_reg(A_LEA,S_L,TmpRef, taicpu(p).oper[1]^.reg);
  2608. InsertLLItem(p.previous, p.next, hp1);
  2609. p.free;
  2610. p := hp1;
  2611. end;
  2612. end
  2613. {$endif x86_64}
  2614. ;
  2615. end;
  2616. function TX86AsmOptimizer.OptPass1SETcc(var p: tai): boolean;
  2617. var
  2618. hp1,hp2,next: tai; SetC, JumpC: TAsmCond;
  2619. begin
  2620. Result:=false;
  2621. if MatchOpType(taicpu(p),top_reg) and
  2622. GetNextInstruction(p, hp1) and
  2623. MatchInstruction(hp1, A_TEST, [S_B]) and
  2624. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  2625. (taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg) and
  2626. (taicpu(hp1).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) and
  2627. GetNextInstruction(hp1, hp2) and
  2628. MatchInstruction(hp2, A_Jcc, []) then
  2629. { Change from: To:
  2630. set(C) %reg j(~C) label
  2631. test %reg,%reg
  2632. je label
  2633. set(C) %reg j(C) label
  2634. test %reg,%reg
  2635. jne label
  2636. }
  2637. begin
  2638. next := tai(p.Next);
  2639. TransferUsedRegs(TmpUsedRegs);
  2640. UpdateUsedRegs(TmpUsedRegs, next);
  2641. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  2642. asml.Remove(hp1);
  2643. hp1.Free;
  2644. JumpC := taicpu(hp2).condition;
  2645. if conditions_equal(JumpC, C_E) then
  2646. SetC := inverse_cond(taicpu(p).condition)
  2647. else if conditions_equal(JumpC, C_NE) then
  2648. SetC := taicpu(p).condition
  2649. else
  2650. InternalError(2018061400);
  2651. if SetC = C_NONE then
  2652. InternalError(2018061401);
  2653. taicpu(hp2).SetCondition(SetC);
  2654. if not RegUsedAfterInstruction(taicpu(p).oper[0]^.reg, hp2, TmpUsedRegs) then
  2655. begin
  2656. asml.Remove(p);
  2657. UpdateUsedRegs(next);
  2658. p.Free;
  2659. Result := True;
  2660. p := hp2;
  2661. end;
  2662. DebugMsg(SPeepholeOptimization + 'SETcc/TEST/Jcc -> Jcc',p);
  2663. end;
  2664. end;
  2665. function TX86AsmOptimizer.OptPass1FSTP(var p: tai): boolean;
  2666. { returns true if a "continue" should be done after this optimization }
  2667. var
  2668. hp1, hp2: tai;
  2669. begin
  2670. Result := false;
  2671. if MatchOpType(taicpu(p),top_ref) and
  2672. GetNextInstruction(p, hp1) and
  2673. (hp1.typ = ait_instruction) and
  2674. (((taicpu(hp1).opcode = A_FLD) and
  2675. (taicpu(p).opcode = A_FSTP)) or
  2676. ((taicpu(p).opcode = A_FISTP) and
  2677. (taicpu(hp1).opcode = A_FILD))) and
  2678. MatchOpType(taicpu(hp1),top_ref) and
  2679. (taicpu(hp1).opsize = taicpu(p).opsize) and
  2680. RefsEqual(taicpu(p).oper[0]^.ref^, taicpu(hp1).oper[0]^.ref^) then
  2681. begin
  2682. { replacing fstp f;fld f by fst f is only valid for extended because of rounding }
  2683. if (taicpu(p).opsize=S_FX) and
  2684. GetNextInstruction(hp1, hp2) and
  2685. (hp2.typ = ait_instruction) and
  2686. IsExitCode(hp2) and
  2687. (taicpu(p).oper[0]^.ref^.base = current_procinfo.FramePointer) and
  2688. not(assigned(current_procinfo.procdef.funcretsym) and
  2689. (taicpu(p).oper[0]^.ref^.offset < tabstractnormalvarsym(current_procinfo.procdef.funcretsym).localloc.reference.offset)) and
  2690. (taicpu(p).oper[0]^.ref^.index = NR_NO) then
  2691. begin
  2692. asml.remove(p);
  2693. asml.remove(hp1);
  2694. p.free;
  2695. hp1.free;
  2696. p := hp2;
  2697. RemoveLastDeallocForFuncRes(p);
  2698. Result := true;
  2699. end
  2700. (* can't be done because the store operation rounds
  2701. else
  2702. { fst can't store an extended value! }
  2703. if (taicpu(p).opsize <> S_FX) and
  2704. (taicpu(p).opsize <> S_IQ) then
  2705. begin
  2706. if (taicpu(p).opcode = A_FSTP) then
  2707. taicpu(p).opcode := A_FST
  2708. else taicpu(p).opcode := A_FIST;
  2709. asml.remove(hp1);
  2710. hp1.free;
  2711. end
  2712. *)
  2713. end;
  2714. end;
  2715. function TX86AsmOptimizer.OptPass1FLD(var p : tai) : boolean;
  2716. var
  2717. hp1, hp2: tai;
  2718. begin
  2719. result:=false;
  2720. if MatchOpType(taicpu(p),top_reg) and
  2721. GetNextInstruction(p, hp1) and
  2722. (hp1.typ = Ait_Instruction) and
  2723. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  2724. (taicpu(hp1).oper[0]^.reg = NR_ST) and
  2725. (taicpu(hp1).oper[1]^.reg = NR_ST1) then
  2726. { change to
  2727. fld reg fxxx reg,st
  2728. fxxxp st, st1 (hp1)
  2729. Remark: non commutative operations must be reversed!
  2730. }
  2731. begin
  2732. case taicpu(hp1).opcode Of
  2733. A_FMULP,A_FADDP,
  2734. A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  2735. begin
  2736. case taicpu(hp1).opcode Of
  2737. A_FADDP: taicpu(hp1).opcode := A_FADD;
  2738. A_FMULP: taicpu(hp1).opcode := A_FMUL;
  2739. A_FSUBP: taicpu(hp1).opcode := A_FSUBR;
  2740. A_FSUBRP: taicpu(hp1).opcode := A_FSUB;
  2741. A_FDIVP: taicpu(hp1).opcode := A_FDIVR;
  2742. A_FDIVRP: taicpu(hp1).opcode := A_FDIV;
  2743. else
  2744. internalerror(2019050534);
  2745. end;
  2746. taicpu(hp1).oper[0]^.reg := taicpu(p).oper[0]^.reg;
  2747. taicpu(hp1).oper[1]^.reg := NR_ST;
  2748. asml.remove(p);
  2749. p.free;
  2750. p := hp1;
  2751. Result:=true;
  2752. exit;
  2753. end;
  2754. else
  2755. ;
  2756. end;
  2757. end
  2758. else
  2759. if MatchOpType(taicpu(p),top_ref) and
  2760. GetNextInstruction(p, hp2) and
  2761. (hp2.typ = Ait_Instruction) and
  2762. MatchOpType(taicpu(hp2),top_reg,top_reg) and
  2763. (taicpu(p).opsize in [S_FS, S_FL]) and
  2764. (taicpu(hp2).oper[0]^.reg = NR_ST) and
  2765. (taicpu(hp2).oper[1]^.reg = NR_ST1) then
  2766. if GetLastInstruction(p, hp1) and
  2767. MatchInstruction(hp1,A_FLD,A_FST,[taicpu(p).opsize]) and
  2768. MatchOpType(taicpu(hp1),top_ref) and
  2769. RefsEqual(taicpu(p).oper[0]^.ref^, taicpu(hp1).oper[0]^.ref^) then
  2770. if ((taicpu(hp2).opcode = A_FMULP) or
  2771. (taicpu(hp2).opcode = A_FADDP)) then
  2772. { change to
  2773. fld/fst mem1 (hp1) fld/fst mem1
  2774. fld mem1 (p) fadd/
  2775. faddp/ fmul st, st
  2776. fmulp st, st1 (hp2) }
  2777. begin
  2778. asml.remove(p);
  2779. p.free;
  2780. p := hp1;
  2781. if (taicpu(hp2).opcode = A_FADDP) then
  2782. taicpu(hp2).opcode := A_FADD
  2783. else
  2784. taicpu(hp2).opcode := A_FMUL;
  2785. taicpu(hp2).oper[1]^.reg := NR_ST;
  2786. end
  2787. else
  2788. { change to
  2789. fld/fst mem1 (hp1) fld/fst mem1
  2790. fld mem1 (p) fld st}
  2791. begin
  2792. taicpu(p).changeopsize(S_FL);
  2793. taicpu(p).loadreg(0,NR_ST);
  2794. end
  2795. else
  2796. begin
  2797. case taicpu(hp2).opcode Of
  2798. A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  2799. { change to
  2800. fld/fst mem1 (hp1) fld/fst mem1
  2801. fld mem2 (p) fxxx mem2
  2802. fxxxp st, st1 (hp2) }
  2803. begin
  2804. case taicpu(hp2).opcode Of
  2805. A_FADDP: taicpu(p).opcode := A_FADD;
  2806. A_FMULP: taicpu(p).opcode := A_FMUL;
  2807. A_FSUBP: taicpu(p).opcode := A_FSUBR;
  2808. A_FSUBRP: taicpu(p).opcode := A_FSUB;
  2809. A_FDIVP: taicpu(p).opcode := A_FDIVR;
  2810. A_FDIVRP: taicpu(p).opcode := A_FDIV;
  2811. else
  2812. internalerror(2019050533);
  2813. end;
  2814. asml.remove(hp2);
  2815. hp2.free;
  2816. end
  2817. else
  2818. ;
  2819. end
  2820. end
  2821. end;
  2822. function TX86AsmOptimizer.OptPass1Cmp(var p: tai): boolean;
  2823. var
  2824. v: QWord;
  2825. hp1, hp2, hp3, hp4: tai;
  2826. begin
  2827. Result:=false;
  2828. { cmp register,$8000 neg register
  2829. je target --> jo target
  2830. .... only if register is deallocated before jump.}
  2831. case Taicpu(p).opsize of
  2832. S_B: v:=$80;
  2833. S_W: v:=$8000;
  2834. S_L: v:=qword($80000000);
  2835. S_Q : v:=qword($8000000000000000);
  2836. else
  2837. internalerror(2013112905);
  2838. end;
  2839. if MatchOpType(taicpu(p),Top_const,top_reg) and
  2840. (taicpu(p).oper[0]^.val=v) and
  2841. GetNextInstruction(p, hp1) and
  2842. MatchInstruction(hp1,A_Jcc,[]) and
  2843. (Taicpu(hp1).condition in [C_E,C_NE]) then
  2844. begin
  2845. TransferUsedRegs(TmpUsedRegs);
  2846. UpdateUsedRegs(TmpUsedRegs,tai(p.next));
  2847. if not(RegInUsedRegs(Taicpu(p).oper[1]^.reg, TmpUsedRegs)) then
  2848. begin
  2849. DebugMsg(SPeepholeOptimization + 'CmpJe2NegJo done',p);
  2850. Taicpu(p).opcode:=A_NEG;
  2851. Taicpu(p).loadoper(0,Taicpu(p).oper[1]^);
  2852. Taicpu(p).clearop(1);
  2853. Taicpu(p).ops:=1;
  2854. if Taicpu(hp1).condition=C_E then
  2855. Taicpu(hp1).condition:=C_O
  2856. else
  2857. Taicpu(hp1).condition:=C_NO;
  2858. Result:=true;
  2859. exit;
  2860. end;
  2861. end;
  2862. {
  2863. @@2: @@2:
  2864. .... ....
  2865. cmp operand1,0
  2866. jle/jbe @@1
  2867. dec operand1 --> sub operand1,1
  2868. jmp @@2 jge/jae @@2
  2869. @@1: @@1:
  2870. ... ....}
  2871. if (taicpu(p).oper[0]^.typ = top_const) and
  2872. (taicpu(p).oper[1]^.typ in [top_reg,top_ref]) and
  2873. (taicpu(p).oper[0]^.val = 0) and
  2874. GetNextInstruction(p, hp1) and
  2875. MatchInstruction(hp1,A_Jcc,[]) and
  2876. (taicpu(hp1).condition in [C_LE,C_BE]) and
  2877. GetNextInstruction(hp1,hp2) and
  2878. MatchInstruction(hp1,A_DEC,[]) and
  2879. OpsEqual(taicpu(hp2).oper[0]^,taicpu(p).oper[1]^) and
  2880. GetNextInstruction(hp2, hp3) and
  2881. MatchInstruction(hp1,A_JMP,[]) and
  2882. GetNextInstruction(hp3, hp4) and
  2883. FindLabel(tasmlabel(taicpu(hp1).oper[0]^.ref^.symbol),hp4) then
  2884. begin
  2885. DebugMsg(SPeepholeOptimization + 'CmpJxxDecJmp2SubJcc done',p);
  2886. taicpu(hp2).Opcode := A_SUB;
  2887. taicpu(hp2).loadoper(1,taicpu(hp2).oper[0]^);
  2888. taicpu(hp2).loadConst(0,1);
  2889. taicpu(hp2).ops:=2;
  2890. taicpu(hp3).Opcode := A_Jcc;
  2891. case taicpu(hp1).condition of
  2892. C_LE: taicpu(hp3).condition := C_GE;
  2893. C_BE: taicpu(hp3).condition := C_AE;
  2894. else
  2895. internalerror(2019050903);
  2896. end;
  2897. asml.remove(p);
  2898. asml.remove(hp1);
  2899. p.free;
  2900. hp1.free;
  2901. p := hp2;
  2902. Result:=true;
  2903. exit;
  2904. end;
  2905. end;
  2906. function TX86AsmOptimizer.OptPass2MOV(var p : tai) : boolean;
  2907. var
  2908. hp1,hp2: tai;
  2909. {$ifdef x86_64}
  2910. hp3: tai;
  2911. {$endif x86_64}
  2912. begin
  2913. Result:=false;
  2914. if not GetNextInstruction(p, hp1) then
  2915. Exit;
  2916. if MatchInstruction(hp1, A_JMP, [S_NO]) then
  2917. begin
  2918. { Sometimes the MOVs that OptPass2JMP produces can be improved
  2919. further, but we can't just put this jump optimisation in pass 1
  2920. because it tends to perform worse when conditional jumps are
  2921. nearby (e.g. when converting CMOV instructions). [Kit] }
  2922. if OptPass2JMP(hp1) then
  2923. { call OptPass1MOV once to potentially merge any MOVs that were created }
  2924. Result := OptPass1MOV(p)
  2925. { OptPass2MOV will now exit but will be called again if OptPass1MOV
  2926. returned True and the instruction is still a MOV, thus checking
  2927. the optimisations below }
  2928. else
  2929. { Since OptPass2JMP returned false, no optimisations were done to
  2930. the jump. Additionally, a label will definitely follow the jump
  2931. (although it may have become dead), so skip ahead as far as
  2932. possible }
  2933. begin
  2934. while (p <> hp1) do
  2935. begin
  2936. { Nothing changed between the MOV and the JMP, so
  2937. don't bother with "UpdateUsedRegsAndOptimize" }
  2938. UpdateUsedRegs(p);
  2939. p := tai(p.Next);
  2940. end;
  2941. { Use "UpdateUsedRegsAndOptimize" here though, because the
  2942. label might now be dead and can be stripped out }
  2943. p := tai(UpdateUsedRegsAndOptimize(hp1).Next);
  2944. { If p is a label, then Result will be False and program flow
  2945. will move onto the next list entry in "PeepHoleOptPass2" }
  2946. if (p = BlockEnd) or not (p.typ in [ait_align, ait_label]) then
  2947. Result := True;
  2948. end;
  2949. end
  2950. else if MatchOpType(taicpu(p),top_reg,top_reg) and
  2951. {$ifdef x86_64}
  2952. MatchInstruction(hp1,A_MOVZX,A_MOVSX,A_MOVSXD,[]) and
  2953. {$else x86_64}
  2954. MatchInstruction(hp1,A_MOVZX,A_MOVSX,[]) and
  2955. {$endif x86_64}
  2956. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  2957. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  2958. { mov reg1, reg2 mov reg1, reg2
  2959. movzx/sx reg2, reg3 to movzx/sx reg1, reg3}
  2960. begin
  2961. taicpu(hp1).oper[0]^.reg := taicpu(p).oper[0]^.reg;
  2962. DebugMsg(SPeepholeOptimization + 'mov %reg1,%reg2; movzx/sx %reg2,%reg3 -> mov %reg1,%reg2;movzx/sx %reg1,%reg3',p);
  2963. { Don't remove the MOV command without first checking that reg2 isn't used afterwards,
  2964. or unless supreg(reg3) = supreg(reg2)). [Kit] }
  2965. TransferUsedRegs(TmpUsedRegs);
  2966. UpdateUsedRegs(TmpUsedRegs, tai(p.next));
  2967. if (getsupreg(taicpu(p).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) or
  2968. not RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp1, TmpUsedRegs)
  2969. then
  2970. begin
  2971. asml.remove(p);
  2972. p.free;
  2973. p := hp1;
  2974. Result:=true;
  2975. end;
  2976. exit;
  2977. end
  2978. else if MatchOpType(taicpu(p),top_reg,top_reg) and
  2979. {$ifdef x86_64}
  2980. MatchInstruction(hp1,[A_MOV,A_MOVZX,A_MOVSX,A_MOVSXD],[]) and
  2981. {$else x86_64}
  2982. MatchInstruction(hp1,A_MOV,A_MOVZX,A_MOVSX,[]) and
  2983. {$endif x86_64}
  2984. MatchOpType(taicpu(hp1),top_ref,top_reg) and
  2985. ((taicpu(hp1).oper[0]^.ref^.base = taicpu(p).oper[1]^.reg)
  2986. or
  2987. (taicpu(hp1).oper[0]^.ref^.index = taicpu(p).oper[1]^.reg)
  2988. ) and
  2989. (getsupreg(taicpu(hp1).oper[1]^.reg) = getsupreg(taicpu(p).oper[1]^.reg)) then
  2990. { mov reg1, reg2
  2991. mov/zx/sx (reg2, ..), reg2 to mov/zx/sx (reg1, ..), reg2}
  2992. begin
  2993. if (taicpu(hp1).oper[0]^.ref^.base = taicpu(p).oper[1]^.reg) then
  2994. taicpu(hp1).oper[0]^.ref^.base := taicpu(p).oper[0]^.reg;
  2995. if (taicpu(hp1).oper[0]^.ref^.index = taicpu(p).oper[1]^.reg) then
  2996. taicpu(hp1).oper[0]^.ref^.index := taicpu(p).oper[0]^.reg;
  2997. DebugMsg(SPeepholeOptimization + 'MovMovXX2MoVXX 1 done',p);
  2998. asml.remove(p);
  2999. p.free;
  3000. p := hp1;
  3001. Result:=true;
  3002. exit;
  3003. end
  3004. else if (taicpu(p).oper[0]^.typ = top_ref) and
  3005. (hp1.typ = ait_instruction) and
  3006. { while the GetNextInstruction(hp1,hp2) call could be factored out,
  3007. doing it separately in both branches allows to do the cheap checks
  3008. with low probability earlier }
  3009. ((IsFoldableArithOp(taicpu(hp1),taicpu(p).oper[1]^.reg) and
  3010. GetNextInstruction(hp1,hp2) and
  3011. MatchInstruction(hp2,A_MOV,[])
  3012. ) or
  3013. ((taicpu(hp1).opcode=A_LEA) and
  3014. GetNextInstruction(hp1,hp2) and
  3015. MatchInstruction(hp2,A_MOV,[]) and
  3016. ((MatchReference(taicpu(hp1).oper[0]^.ref^,taicpu(p).oper[1]^.reg,NR_INVALID) and
  3017. (taicpu(hp1).oper[0]^.ref^.index<>taicpu(p).oper[1]^.reg)
  3018. ) or
  3019. (MatchReference(taicpu(hp1).oper[0]^.ref^,NR_INVALID,
  3020. taicpu(p).oper[1]^.reg) and
  3021. (taicpu(hp1).oper[0]^.ref^.base<>taicpu(p).oper[1]^.reg)) or
  3022. (MatchReferenceWithOffset(taicpu(hp1).oper[0]^.ref^,taicpu(p).oper[1]^.reg,NR_NO)) or
  3023. (MatchReferenceWithOffset(taicpu(hp1).oper[0]^.ref^,NR_NO,taicpu(p).oper[1]^.reg))
  3024. ) and
  3025. ((MatchOperand(taicpu(p).oper[1]^,taicpu(hp2).oper[0]^)) or not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,UsedRegs)))
  3026. )
  3027. ) and
  3028. MatchOperand(taicpu(hp1).oper[taicpu(hp1).ops-1]^,taicpu(hp2).oper[0]^) and
  3029. (taicpu(hp2).oper[1]^.typ = top_ref) then
  3030. begin
  3031. TransferUsedRegs(TmpUsedRegs);
  3032. UpdateUsedRegs(TmpUsedRegs,tai(p.next));
  3033. UpdateUsedRegs(TmpUsedRegs,tai(hp1.next));
  3034. if (RefsEqual(taicpu(hp2).oper[1]^.ref^,taicpu(p).oper[0]^.ref^) and
  3035. not(RegUsedAfterInstruction(taicpu(hp2).oper[0]^.reg,hp2,TmpUsedRegs))) then
  3036. { change mov (ref), reg
  3037. add/sub/or/... reg2/$const, reg
  3038. mov reg, (ref)
  3039. # release reg
  3040. to add/sub/or/... reg2/$const, (ref) }
  3041. begin
  3042. case taicpu(hp1).opcode of
  3043. A_INC,A_DEC,A_NOT,A_NEG :
  3044. taicpu(hp1).loadRef(0,taicpu(p).oper[0]^.ref^);
  3045. A_LEA :
  3046. begin
  3047. taicpu(hp1).opcode:=A_ADD;
  3048. if (taicpu(hp1).oper[0]^.ref^.index<>taicpu(p).oper[1]^.reg) and (taicpu(hp1).oper[0]^.ref^.index<>NR_NO) then
  3049. taicpu(hp1).loadreg(0,taicpu(hp1).oper[0]^.ref^.index)
  3050. else if (taicpu(hp1).oper[0]^.ref^.base<>taicpu(p).oper[1]^.reg) and (taicpu(hp1).oper[0]^.ref^.base<>NR_NO) then
  3051. taicpu(hp1).loadreg(0,taicpu(hp1).oper[0]^.ref^.base)
  3052. else
  3053. taicpu(hp1).loadconst(0,taicpu(hp1).oper[0]^.ref^.offset);
  3054. taicpu(hp1).loadRef(1,taicpu(p).oper[0]^.ref^);
  3055. DebugMsg(SPeepholeOptimization + 'FoldLea done',hp1);
  3056. end
  3057. else
  3058. taicpu(hp1).loadRef(1,taicpu(p).oper[0]^.ref^);
  3059. end;
  3060. asml.remove(p);
  3061. asml.remove(hp2);
  3062. p.free;
  3063. hp2.free;
  3064. p := hp1
  3065. end;
  3066. Exit;
  3067. {$ifdef x86_64}
  3068. end
  3069. else if (taicpu(p).opsize = S_L) and
  3070. (taicpu(p).oper[1]^.typ = top_reg) and
  3071. (
  3072. MatchInstruction(hp1, A_MOV,[]) and
  3073. (taicpu(hp1).opsize = S_L) and
  3074. (taicpu(hp1).oper[1]^.typ = top_reg)
  3075. ) and (
  3076. GetNextInstruction(hp1, hp2) and
  3077. (tai(hp2).typ=ait_instruction) and
  3078. (taicpu(hp2).opsize = S_Q) and
  3079. (
  3080. (
  3081. MatchInstruction(hp2, A_ADD,[]) and
  3082. (taicpu(hp2).opsize = S_Q) and
  3083. (taicpu(hp2).oper[0]^.typ = top_reg) and (taicpu(hp2).oper[1]^.typ = top_reg) and
  3084. (
  3085. (
  3086. (getsupreg(taicpu(hp2).oper[0]^.reg) = getsupreg(taicpu(p).oper[1]^.reg)) and
  3087. (getsupreg(taicpu(hp2).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg))
  3088. ) or (
  3089. (getsupreg(taicpu(hp2).oper[0]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) and
  3090. (getsupreg(taicpu(hp2).oper[1]^.reg) = getsupreg(taicpu(p).oper[1]^.reg))
  3091. )
  3092. )
  3093. ) or (
  3094. MatchInstruction(hp2, A_LEA,[]) and
  3095. (taicpu(hp2).oper[0]^.ref^.offset = 0) and
  3096. (taicpu(hp2).oper[0]^.ref^.scalefactor <= 1) and
  3097. (
  3098. (
  3099. (getsupreg(taicpu(hp2).oper[0]^.ref^.base) = getsupreg(taicpu(p).oper[1]^.reg)) and
  3100. (getsupreg(taicpu(hp2).oper[0]^.ref^.index) = getsupreg(taicpu(hp1).oper[1]^.reg))
  3101. ) or (
  3102. (getsupreg(taicpu(hp2).oper[0]^.ref^.base) = getsupreg(taicpu(hp1).oper[1]^.reg)) and
  3103. (getsupreg(taicpu(hp2).oper[0]^.ref^.index) = getsupreg(taicpu(p).oper[1]^.reg))
  3104. )
  3105. ) and (
  3106. (
  3107. (getsupreg(taicpu(hp2).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg))
  3108. ) or (
  3109. (getsupreg(taicpu(hp2).oper[1]^.reg) = getsupreg(taicpu(p).oper[1]^.reg))
  3110. )
  3111. )
  3112. )
  3113. )
  3114. ) and (
  3115. GetNextInstruction(hp2, hp3) and
  3116. MatchInstruction(hp3, A_SHR,[]) and
  3117. (taicpu(hp3).opsize = S_Q) and
  3118. (taicpu(hp3).oper[0]^.typ = top_const) and (taicpu(hp2).oper[1]^.typ = top_reg) and
  3119. (taicpu(hp3).oper[0]^.val = 1) and
  3120. (taicpu(hp3).oper[1]^.reg = taicpu(hp2).oper[1]^.reg)
  3121. ) then
  3122. begin
  3123. { Change movl x, reg1d movl x, reg1d
  3124. movl y, reg2d movl y, reg2d
  3125. addq reg2q,reg1q or leaq (reg1q,reg2q),reg1q
  3126. shrq $1, reg1q shrq $1, reg1q
  3127. ( reg1d and reg2d can be switched around in the first two instructions )
  3128. To movl x, reg1d
  3129. addl y, reg1d
  3130. rcrl $1, reg1d
  3131. This corresponds to the common expression (x + y) shr 1, where
  3132. x and y are Cardinals (replacing "shr 1" with "div 2" produces
  3133. smaller code, but won't account for x + y causing an overflow). [Kit]
  3134. }
  3135. if (getsupreg(taicpu(hp2).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) then
  3136. { Change first MOV command to have the same register as the final output }
  3137. taicpu(p).oper[1]^.reg := taicpu(hp1).oper[1]^.reg
  3138. else
  3139. taicpu(hp1).oper[1]^.reg := taicpu(p).oper[1]^.reg;
  3140. { Change second MOV command to an ADD command. This is easier than
  3141. converting the existing command because it means we don't have to
  3142. touch 'y', which might be a complicated reference, and also the
  3143. fact that the third command might either be ADD or LEA. [Kit] }
  3144. taicpu(hp1).opcode := A_ADD;
  3145. { Delete old ADD/LEA instruction }
  3146. asml.remove(hp2);
  3147. hp2.free;
  3148. { Convert "shrq $1, reg1q" to "rcr $1, reg1d" }
  3149. taicpu(hp3).opcode := A_RCR;
  3150. taicpu(hp3).changeopsize(S_L);
  3151. setsubreg(taicpu(hp3).oper[1]^.reg, R_SUBD);
  3152. {$endif x86_64}
  3153. end;
  3154. end;
  3155. function TX86AsmOptimizer.OptPass2Imul(var p : tai) : boolean;
  3156. var
  3157. hp1 : tai;
  3158. begin
  3159. Result:=false;
  3160. if (taicpu(p).ops >= 2) and
  3161. ((taicpu(p).oper[0]^.typ = top_const) or
  3162. ((taicpu(p).oper[0]^.typ = top_ref) and (taicpu(p).oper[0]^.ref^.refaddr=addr_full))) and
  3163. (taicpu(p).oper[1]^.typ = top_reg) and
  3164. ((taicpu(p).ops = 2) or
  3165. ((taicpu(p).oper[2]^.typ = top_reg) and
  3166. (taicpu(p).oper[2]^.reg = taicpu(p).oper[1]^.reg))) and
  3167. GetLastInstruction(p,hp1) and
  3168. MatchInstruction(hp1,A_MOV,[]) and
  3169. MatchOpType(taicpu(hp1),top_reg,top_reg) and
  3170. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  3171. begin
  3172. TransferUsedRegs(TmpUsedRegs);
  3173. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,p,TmpUsedRegs)) or
  3174. ((taicpu(p).ops = 3) and (taicpu(p).oper[1]^.reg=taicpu(p).oper[2]^.reg)) then
  3175. { change
  3176. mov reg1,reg2
  3177. imul y,reg2 to imul y,reg1,reg2 }
  3178. begin
  3179. taicpu(p).ops := 3;
  3180. taicpu(p).loadreg(2,taicpu(p).oper[1]^.reg);
  3181. taicpu(p).loadreg(1,taicpu(hp1).oper[0]^.reg);
  3182. DebugMsg(SPeepholeOptimization + 'MovImul2Imul done',p);
  3183. asml.remove(hp1);
  3184. hp1.free;
  3185. result:=true;
  3186. end;
  3187. end;
  3188. end;
  3189. procedure TX86AsmOptimizer.ConvertJumpToRET(const p: tai; const ret_p: tai);
  3190. var
  3191. ThisLabel: TAsmLabel;
  3192. begin
  3193. ThisLabel := tasmlabel(taicpu(p).oper[0]^.ref^.symbol);
  3194. ThisLabel.decrefs;
  3195. taicpu(p).opcode := A_RET;
  3196. taicpu(p).is_jmp := false;
  3197. taicpu(p).ops := taicpu(ret_p).ops;
  3198. case taicpu(ret_p).ops of
  3199. 0:
  3200. taicpu(p).clearop(0);
  3201. 1:
  3202. taicpu(p).loadconst(0,taicpu(ret_p).oper[0]^.val);
  3203. else
  3204. internalerror(2016041301);
  3205. end;
  3206. { If the original label is now dead, it might turn out that the label
  3207. immediately follows p. As a result, everything beyond it, which will
  3208. be just some final register configuration and a RET instruction, is
  3209. now dead code. [Kit] }
  3210. { NOTE: This is much faster than introducing a OptPass2RET routine and
  3211. running RemoveDeadCodeAfterJump for each RET instruction, because
  3212. this optimisation rarely happens and most RETs appear at the end of
  3213. routines where there is nothing that can be stripped. [Kit] }
  3214. if not ThisLabel.is_used then
  3215. RemoveDeadCodeAfterJump(p);
  3216. end;
  3217. function TX86AsmOptimizer.OptPass2Jmp(var p : tai) : boolean;
  3218. var
  3219. hp1, hp2 : tai;
  3220. begin
  3221. result:=false;
  3222. if (taicpu(p).oper[0]^.typ=top_ref) and (taicpu(p).oper[0]^.ref^.refaddr=addr_full) and (taicpu(p).oper[0]^.ref^.base=NR_NO) and
  3223. (taicpu(p).oper[0]^.ref^.index=NR_NO) then
  3224. begin
  3225. hp1:=getlabelwithsym(tasmlabel(taicpu(p).oper[0]^.ref^.symbol));
  3226. if (taicpu(p).condition=C_None) and assigned(hp1) and SkipLabels(hp1,hp1) and (hp1.typ = ait_instruction) then
  3227. begin
  3228. case taicpu(hp1).opcode of
  3229. A_RET:
  3230. {
  3231. change
  3232. jmp .L1
  3233. ...
  3234. .L1:
  3235. ret
  3236. into
  3237. ret
  3238. }
  3239. begin
  3240. ConvertJumpToRET(p, hp1);
  3241. result:=true;
  3242. end;
  3243. A_MOV:
  3244. {
  3245. change
  3246. jmp .L1
  3247. ...
  3248. .L1:
  3249. mov ##, ##
  3250. ret
  3251. into
  3252. mov ##, ##
  3253. ret
  3254. }
  3255. { This optimisation tends to increase code size if the pass 1 MOV optimisations aren't
  3256. re-run, so only do this particular optimisation if optimising for speed or when
  3257. optimisations are very in-depth. [Kit] }
  3258. if (current_settings.optimizerswitches * [cs_opt_level3, cs_opt_size]) <> [cs_opt_size] then
  3259. begin
  3260. GetNextInstruction(hp1, hp2);
  3261. if not Assigned(hp2) then
  3262. Exit;
  3263. if (hp2.typ in [ait_label, ait_align]) then
  3264. SkipLabels(hp2,hp2);
  3265. if Assigned(hp2) and MatchInstruction(hp2, A_RET, [S_NO]) then
  3266. begin
  3267. { Duplicate the MOV instruction }
  3268. asml.InsertBefore(hp1.getcopy, p);
  3269. { Now change the jump into a RET instruction }
  3270. ConvertJumpToRET(p, hp2);
  3271. result:=true;
  3272. end;
  3273. end;
  3274. else
  3275. { Do nothing };
  3276. end;
  3277. end;
  3278. end;
  3279. end;
  3280. function CanBeCMOV(p : tai) : boolean;
  3281. begin
  3282. CanBeCMOV:=assigned(p) and
  3283. MatchInstruction(p,A_MOV,[S_W,S_L,S_Q]) and
  3284. { we can't use cmov ref,reg because
  3285. ref could be nil and cmov still throws an exception
  3286. if ref=nil but the mov isn't done (FK)
  3287. or ((taicpu(p).oper[0]^.typ = top_ref) and
  3288. (taicpu(p).oper[0]^.ref^.refaddr = addr_no))
  3289. }
  3290. (MatchOpType(taicpu(p),top_reg,top_reg) or
  3291. { allow references, but only pure symbols or got rel. addressing with RIP as based,
  3292. it is not expected that this can cause a seg. violation }
  3293. (MatchOpType(taicpu(p),top_ref,top_reg) and
  3294. (((taicpu(p).oper[0]^.ref^.base=NR_NO) and (taicpu(p).oper[0]^.ref^.refaddr=addr_no)){$ifdef x86_64} or
  3295. ((taicpu(p).oper[0]^.ref^.base=NR_RIP) and (taicpu(p).oper[0]^.ref^.refaddr=addr_pic)){$endif x86_64}
  3296. ) and
  3297. (taicpu(p).oper[0]^.ref^.index=NR_NO) and
  3298. (taicpu(p).oper[0]^.ref^.offset=0)
  3299. )
  3300. );
  3301. end;
  3302. function TX86AsmOptimizer.OptPass2Jcc(var p : tai) : boolean;
  3303. var
  3304. hp1,hp2,hp3,hp4,hpmov2: tai;
  3305. carryadd_opcode : TAsmOp;
  3306. l : Longint;
  3307. condition : TAsmCond;
  3308. symbol: TAsmSymbol;
  3309. begin
  3310. result:=false;
  3311. symbol:=nil;
  3312. if GetNextInstruction(p,hp1) then
  3313. begin
  3314. symbol := TAsmLabel(taicpu(p).oper[0]^.ref^.symbol);
  3315. if (hp1.typ=ait_instruction) and
  3316. GetNextInstruction(hp1,hp2) and (hp2.typ=ait_label) and
  3317. (Tasmlabel(symbol) = Tai_label(hp2).labsym) then
  3318. { jb @@1 cmc
  3319. inc/dec operand --> adc/sbb operand,0
  3320. @@1:
  3321. ... and ...
  3322. jnb @@1
  3323. inc/dec operand --> adc/sbb operand,0
  3324. @@1: }
  3325. begin
  3326. carryadd_opcode:=A_NONE;
  3327. if Taicpu(p).condition in [C_NAE,C_B] then
  3328. begin
  3329. if Taicpu(hp1).opcode=A_INC then
  3330. carryadd_opcode:=A_ADC;
  3331. if Taicpu(hp1).opcode=A_DEC then
  3332. carryadd_opcode:=A_SBB;
  3333. if carryadd_opcode<>A_NONE then
  3334. begin
  3335. Taicpu(p).clearop(0);
  3336. Taicpu(p).ops:=0;
  3337. Taicpu(p).is_jmp:=false;
  3338. Taicpu(p).opcode:=A_CMC;
  3339. Taicpu(p).condition:=C_NONE;
  3340. Taicpu(hp1).ops:=2;
  3341. Taicpu(hp1).loadoper(1,Taicpu(hp1).oper[0]^);
  3342. Taicpu(hp1).loadconst(0,0);
  3343. Taicpu(hp1).opcode:=carryadd_opcode;
  3344. result:=true;
  3345. exit;
  3346. end;
  3347. end;
  3348. if Taicpu(p).condition in [C_AE,C_NB] then
  3349. begin
  3350. if Taicpu(hp1).opcode=A_INC then
  3351. carryadd_opcode:=A_ADC;
  3352. if Taicpu(hp1).opcode=A_DEC then
  3353. carryadd_opcode:=A_SBB;
  3354. if carryadd_opcode<>A_NONE then
  3355. begin
  3356. asml.remove(p);
  3357. p.free;
  3358. Taicpu(hp1).ops:=2;
  3359. Taicpu(hp1).loadoper(1,Taicpu(hp1).oper[0]^);
  3360. Taicpu(hp1).loadconst(0,0);
  3361. Taicpu(hp1).opcode:=carryadd_opcode;
  3362. p:=hp1;
  3363. result:=true;
  3364. exit;
  3365. end;
  3366. end;
  3367. end;
  3368. { Detect the following:
  3369. jmp<cond> @Lbl1
  3370. jmp @Lbl2
  3371. ...
  3372. @Lbl1:
  3373. ret
  3374. Change to:
  3375. jmp<inv_cond> @Lbl2
  3376. ret
  3377. }
  3378. if MatchInstruction(hp1,A_JMP,[]) and (taicpu(hp1).oper[0]^.ref^.refaddr=addr_full) then
  3379. begin
  3380. hp2:=getlabelwithsym(TAsmLabel(symbol));
  3381. if Assigned(hp2) and SkipLabels(hp2,hp2) and
  3382. MatchInstruction(hp2,A_RET,[S_NO]) then
  3383. begin
  3384. taicpu(p).condition := inverse_cond(taicpu(p).condition);
  3385. { Change label address to that of the unconditional jump }
  3386. taicpu(p).loadoper(0, taicpu(hp1).oper[0]^);
  3387. TAsmLabel(symbol).DecRefs;
  3388. taicpu(hp1).opcode := A_RET;
  3389. taicpu(hp1).is_jmp := false;
  3390. taicpu(hp1).ops := taicpu(hp2).ops;
  3391. DebugMsg(SPeepholeOptimization+'JccJmpRet2J!ccRet',p);
  3392. case taicpu(hp2).ops of
  3393. 0:
  3394. taicpu(hp1).clearop(0);
  3395. 1:
  3396. taicpu(hp1).loadconst(0,taicpu(hp2).oper[0]^.val);
  3397. else
  3398. internalerror(2016041302);
  3399. end;
  3400. end;
  3401. end;
  3402. end;
  3403. {$ifndef i8086}
  3404. if CPUX86_HAS_CMOV in cpu_capabilities[current_settings.cputype] then
  3405. begin
  3406. { check for
  3407. jCC xxx
  3408. <several movs>
  3409. xxx:
  3410. }
  3411. l:=0;
  3412. GetNextInstruction(p, hp1);
  3413. while assigned(hp1) and
  3414. CanBeCMOV(hp1) and
  3415. { stop on labels }
  3416. not(hp1.typ=ait_label) do
  3417. begin
  3418. inc(l);
  3419. GetNextInstruction(hp1,hp1);
  3420. end;
  3421. if assigned(hp1) then
  3422. begin
  3423. if FindLabel(tasmlabel(symbol),hp1) then
  3424. begin
  3425. if (l<=4) and (l>0) then
  3426. begin
  3427. condition:=inverse_cond(taicpu(p).condition);
  3428. GetNextInstruction(p,hp1);
  3429. repeat
  3430. if not Assigned(hp1) then
  3431. InternalError(2018062900);
  3432. taicpu(hp1).opcode:=A_CMOVcc;
  3433. taicpu(hp1).condition:=condition;
  3434. UpdateUsedRegs(hp1);
  3435. GetNextInstruction(hp1,hp1);
  3436. until not(CanBeCMOV(hp1));
  3437. { Remember what hp1 is in case there's multiple aligns to get rid of }
  3438. hp2 := hp1;
  3439. repeat
  3440. if not Assigned(hp2) then
  3441. InternalError(2018062910);
  3442. case hp2.typ of
  3443. ait_label:
  3444. { What we expected - break out of the loop (it won't be a dead label at the top of
  3445. a cluster because that was optimised at an earlier stage) }
  3446. Break;
  3447. ait_align:
  3448. { Go to the next entry until a label is found (may be multiple aligns before it) }
  3449. begin
  3450. hp2 := tai(hp2.Next);
  3451. Continue;
  3452. end;
  3453. else
  3454. begin
  3455. { Might be a comment or temporary allocation entry }
  3456. if not (hp2.typ in SkipInstr) then
  3457. InternalError(2018062911);
  3458. hp2 := tai(hp2.Next);
  3459. Continue;
  3460. end;
  3461. end;
  3462. until False;
  3463. { Now we can safely decrement the reference count }
  3464. tasmlabel(symbol).decrefs;
  3465. DebugMsg(SPeepholeOptimization+'JccMov2CMov',p);
  3466. { Remove the original jump }
  3467. asml.Remove(p);
  3468. p.Free;
  3469. GetNextInstruction(hp2, p); { Instruction after the label }
  3470. { Remove the label if this is its final reference }
  3471. if (tasmlabel(symbol).getrefs=0) then
  3472. StripLabelFast(hp1);
  3473. if Assigned(p) then
  3474. begin
  3475. UpdateUsedRegs(p);
  3476. result:=true;
  3477. end;
  3478. exit;
  3479. end;
  3480. end
  3481. else
  3482. begin
  3483. { check further for
  3484. jCC xxx
  3485. <several movs 1>
  3486. jmp yyy
  3487. xxx:
  3488. <several movs 2>
  3489. yyy:
  3490. }
  3491. { hp2 points to jmp yyy }
  3492. hp2:=hp1;
  3493. { skip hp1 to xxx (or an align right before it) }
  3494. GetNextInstruction(hp1, hp1);
  3495. if assigned(hp2) and
  3496. assigned(hp1) and
  3497. (l<=3) and
  3498. (hp2.typ=ait_instruction) and
  3499. (taicpu(hp2).is_jmp) and
  3500. (taicpu(hp2).condition=C_None) and
  3501. { real label and jump, no further references to the
  3502. label are allowed }
  3503. (tasmlabel(symbol).getrefs=1) and
  3504. FindLabel(tasmlabel(symbol),hp1) then
  3505. begin
  3506. l:=0;
  3507. { skip hp1 to <several moves 2> }
  3508. if (hp1.typ = ait_align) then
  3509. GetNextInstruction(hp1, hp1);
  3510. GetNextInstruction(hp1, hpmov2);
  3511. hp1 := hpmov2;
  3512. while assigned(hp1) and
  3513. CanBeCMOV(hp1) do
  3514. begin
  3515. inc(l);
  3516. GetNextInstruction(hp1, hp1);
  3517. end;
  3518. { hp1 points to yyy (or an align right before it) }
  3519. hp3 := hp1;
  3520. if assigned(hp1) and
  3521. FindLabel(tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol),hp1) then
  3522. begin
  3523. condition:=inverse_cond(taicpu(p).condition);
  3524. GetNextInstruction(p,hp1);
  3525. repeat
  3526. taicpu(hp1).opcode:=A_CMOVcc;
  3527. taicpu(hp1).condition:=condition;
  3528. UpdateUsedRegs(hp1);
  3529. GetNextInstruction(hp1,hp1);
  3530. until not(assigned(hp1)) or
  3531. not(CanBeCMOV(hp1));
  3532. condition:=inverse_cond(condition);
  3533. hp1 := hpmov2;
  3534. { hp1 is now at <several movs 2> }
  3535. while Assigned(hp1) and CanBeCMOV(hp1) do
  3536. begin
  3537. taicpu(hp1).opcode:=A_CMOVcc;
  3538. taicpu(hp1).condition:=condition;
  3539. UpdateUsedRegs(hp1);
  3540. GetNextInstruction(hp1,hp1);
  3541. end;
  3542. hp1 := p;
  3543. { Get first instruction after label }
  3544. GetNextInstruction(hp3, p);
  3545. if assigned(p) and (hp3.typ = ait_align) then
  3546. GetNextInstruction(p, p);
  3547. { Don't dereference yet, as doing so will cause
  3548. GetNextInstruction to skip the label and
  3549. optional align marker. [Kit] }
  3550. GetNextInstruction(hp2, hp4);
  3551. DebugMsg(SPeepholeOptimization+'JccMovJmpMov2CMovCMov',hp1);
  3552. { remove jCC }
  3553. asml.remove(hp1);
  3554. hp1.free;
  3555. { Now we can safely decrement it }
  3556. tasmlabel(symbol).decrefs;
  3557. { Remove label xxx (it will have a ref of zero due to the initial check }
  3558. StripLabelFast(hp4);
  3559. { remove jmp }
  3560. symbol := taicpu(hp2).oper[0]^.ref^.symbol;
  3561. asml.remove(hp2);
  3562. hp2.free;
  3563. { As before, now we can safely decrement it }
  3564. tasmlabel(symbol).decrefs;
  3565. { Remove label yyy (and the optional alignment) if its reference falls to zero }
  3566. if tasmlabel(symbol).getrefs = 0 then
  3567. StripLabelFast(hp3);
  3568. if Assigned(p) then
  3569. begin
  3570. UpdateUsedRegs(p);
  3571. result:=true;
  3572. end;
  3573. exit;
  3574. end;
  3575. end;
  3576. end;
  3577. end;
  3578. end;
  3579. {$endif i8086}
  3580. end;
  3581. function TX86AsmOptimizer.OptPass1Movx(var p : tai) : boolean;
  3582. var
  3583. hp1,hp2: tai;
  3584. begin
  3585. result:=false;
  3586. if (taicpu(p).oper[1]^.typ = top_reg) and
  3587. GetNextInstruction(p,hp1) and
  3588. (hp1.typ = ait_instruction) and
  3589. IsFoldableArithOp(taicpu(hp1),taicpu(p).oper[1]^.reg) and
  3590. GetNextInstruction(hp1,hp2) and
  3591. MatchInstruction(hp2,A_MOV,[]) and
  3592. (taicpu(hp2).oper[0]^.typ = top_reg) and
  3593. OpsEqual(taicpu(hp2).oper[1]^,taicpu(p).oper[0]^) and
  3594. {$ifdef i386}
  3595. { not all registers have byte size sub registers on i386 }
  3596. ((taicpu(hp2).opsize<>S_B) or (getsupreg(taicpu(hp1).oper[0]^.reg) in [RS_EAX, RS_EBX, RS_ECX, RS_EDX])) and
  3597. {$endif i386}
  3598. (((taicpu(hp1).ops=2) and
  3599. (getsupreg(taicpu(hp2).oper[0]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg))) or
  3600. ((taicpu(hp1).ops=1) and
  3601. (getsupreg(taicpu(hp2).oper[0]^.reg)=getsupreg(taicpu(hp1).oper[0]^.reg)))) and
  3602. not(RegUsedAfterInstruction(taicpu(hp2).oper[0]^.reg,hp2,UsedRegs)) then
  3603. begin
  3604. { change movsX/movzX reg/ref, reg2
  3605. add/sub/or/... reg3/$const, reg2
  3606. mov reg2 reg/ref
  3607. to add/sub/or/... reg3/$const, reg/ref }
  3608. { by example:
  3609. movswl %si,%eax movswl %si,%eax p
  3610. decl %eax addl %edx,%eax hp1
  3611. movw %ax,%si movw %ax,%si hp2
  3612. ->
  3613. movswl %si,%eax movswl %si,%eax p
  3614. decw %eax addw %edx,%eax hp1
  3615. movw %ax,%si movw %ax,%si hp2
  3616. }
  3617. taicpu(hp1).changeopsize(taicpu(hp2).opsize);
  3618. {
  3619. ->
  3620. movswl %si,%eax movswl %si,%eax p
  3621. decw %si addw %dx,%si hp1
  3622. movw %ax,%si movw %ax,%si hp2
  3623. }
  3624. case taicpu(hp1).ops of
  3625. 1:
  3626. taicpu(hp1).loadoper(0,taicpu(hp2).oper[1]^);
  3627. 2:
  3628. begin
  3629. taicpu(hp1).loadoper(1,taicpu(hp2).oper[1]^);
  3630. if (taicpu(hp1).oper[0]^.typ = top_reg) then
  3631. setsubreg(taicpu(hp1).oper[0]^.reg,getsubreg(taicpu(hp2).oper[0]^.reg));
  3632. end;
  3633. else
  3634. internalerror(2008042701);
  3635. end;
  3636. {
  3637. ->
  3638. decw %si addw %dx,%si p
  3639. }
  3640. DebugMsg(SPeepholeOptimization + 'var3',p);
  3641. asml.remove(p);
  3642. asml.remove(hp2);
  3643. p.free;
  3644. hp2.free;
  3645. p:=hp1;
  3646. end
  3647. else if taicpu(p).opcode=A_MOVZX then
  3648. begin
  3649. { removes superfluous And's after movzx's }
  3650. if (taicpu(p).oper[1]^.typ = top_reg) and
  3651. GetNextInstruction(p, hp1) and
  3652. (tai(hp1).typ = ait_instruction) and
  3653. (taicpu(hp1).opcode = A_AND) and
  3654. (taicpu(hp1).oper[0]^.typ = top_const) and
  3655. (taicpu(hp1).oper[1]^.typ = top_reg) and
  3656. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  3657. begin
  3658. case taicpu(p).opsize Of
  3659. S_BL, S_BW{$ifdef x86_64}, S_BQ{$endif x86_64}:
  3660. if (taicpu(hp1).oper[0]^.val = $ff) then
  3661. begin
  3662. DebugMsg(SPeepholeOptimization + 'var4',p);
  3663. asml.remove(hp1);
  3664. hp1.free;
  3665. end;
  3666. S_WL{$ifdef x86_64}, S_WQ{$endif x86_64}:
  3667. if (taicpu(hp1).oper[0]^.val = $ffff) then
  3668. begin
  3669. DebugMsg(SPeepholeOptimization + 'var5',p);
  3670. asml.remove(hp1);
  3671. hp1.free;
  3672. end;
  3673. {$ifdef x86_64}
  3674. S_LQ:
  3675. if (taicpu(hp1).oper[0]^.val = $ffffffff) then
  3676. begin
  3677. if (cs_asm_source in current_settings.globalswitches) then
  3678. asml.insertbefore(tai_comment.create(strpnew(SPeepholeOptimization + 'var6')),p);
  3679. asml.remove(hp1);
  3680. hp1.Free;
  3681. end;
  3682. {$endif x86_64}
  3683. else
  3684. ;
  3685. end;
  3686. end;
  3687. { changes some movzx constructs to faster synonims (all examples
  3688. are given with eax/ax, but are also valid for other registers)}
  3689. if (taicpu(p).oper[1]^.typ = top_reg) then
  3690. if (taicpu(p).oper[0]^.typ = top_reg) then
  3691. case taicpu(p).opsize of
  3692. S_BW:
  3693. begin
  3694. if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) and
  3695. not(cs_opt_size in current_settings.optimizerswitches) then
  3696. {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
  3697. begin
  3698. taicpu(p).opcode := A_AND;
  3699. taicpu(p).changeopsize(S_W);
  3700. taicpu(p).loadConst(0,$ff);
  3701. DebugMsg(SPeepholeOptimization + 'var7',p);
  3702. end
  3703. else if GetNextInstruction(p, hp1) and
  3704. (tai(hp1).typ = ait_instruction) and
  3705. (taicpu(hp1).opcode = A_AND) and
  3706. (taicpu(hp1).oper[0]^.typ = top_const) and
  3707. (taicpu(hp1).oper[1]^.typ = top_reg) and
  3708. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  3709. { Change "movzbw %reg1, %reg2; andw $const, %reg2"
  3710. to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
  3711. begin
  3712. DebugMsg(SPeepholeOptimization + 'var8',p);
  3713. taicpu(p).opcode := A_MOV;
  3714. taicpu(p).changeopsize(S_W);
  3715. setsubreg(taicpu(p).oper[0]^.reg,R_SUBW);
  3716. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  3717. end;
  3718. end;
  3719. S_BL:
  3720. begin
  3721. if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) and
  3722. not(cs_opt_size in current_settings.optimizerswitches) then
  3723. { Change "movzbl %al, %eax" to "andl $0x0ffh, %eax" }
  3724. begin
  3725. taicpu(p).opcode := A_AND;
  3726. taicpu(p).changeopsize(S_L);
  3727. taicpu(p).loadConst(0,$ff)
  3728. end
  3729. else if GetNextInstruction(p, hp1) and
  3730. (tai(hp1).typ = ait_instruction) and
  3731. (taicpu(hp1).opcode = A_AND) and
  3732. (taicpu(hp1).oper[0]^.typ = top_const) and
  3733. (taicpu(hp1).oper[1]^.typ = top_reg) and
  3734. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  3735. { Change "movzbl %reg1, %reg2; andl $const, %reg2"
  3736. to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
  3737. begin
  3738. DebugMsg(SPeepholeOptimization + 'var10',p);
  3739. taicpu(p).opcode := A_MOV;
  3740. taicpu(p).changeopsize(S_L);
  3741. { do not use R_SUBWHOLE
  3742. as movl %rdx,%eax
  3743. is invalid in assembler PM }
  3744. setsubreg(taicpu(p).oper[0]^.reg, R_SUBD);
  3745. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  3746. end
  3747. end;
  3748. {$ifndef i8086}
  3749. S_WL:
  3750. begin
  3751. if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) and
  3752. not(cs_opt_size in current_settings.optimizerswitches) then
  3753. { Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax" }
  3754. begin
  3755. DebugMsg(SPeepholeOptimization + 'var11',p);
  3756. taicpu(p).opcode := A_AND;
  3757. taicpu(p).changeopsize(S_L);
  3758. taicpu(p).loadConst(0,$ffff);
  3759. end
  3760. else if GetNextInstruction(p, hp1) and
  3761. (tai(hp1).typ = ait_instruction) and
  3762. (taicpu(hp1).opcode = A_AND) and
  3763. (taicpu(hp1).oper[0]^.typ = top_const) and
  3764. (taicpu(hp1).oper[1]^.typ = top_reg) and
  3765. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  3766. { Change "movzwl %reg1, %reg2; andl $const, %reg2"
  3767. to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
  3768. begin
  3769. DebugMsg(SPeepholeOptimization + 'var12',p);
  3770. taicpu(p).opcode := A_MOV;
  3771. taicpu(p).changeopsize(S_L);
  3772. { do not use R_SUBWHOLE
  3773. as movl %rdx,%eax
  3774. is invalid in assembler PM }
  3775. setsubreg(taicpu(p).oper[0]^.reg, R_SUBD);
  3776. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ffff);
  3777. end;
  3778. end;
  3779. {$endif i8086}
  3780. else
  3781. ;
  3782. end
  3783. else if (taicpu(p).oper[0]^.typ = top_ref) then
  3784. begin
  3785. if GetNextInstruction(p, hp1) and
  3786. (tai(hp1).typ = ait_instruction) and
  3787. (taicpu(hp1).opcode = A_AND) and
  3788. MatchOpType(taicpu(hp1),top_const,top_reg) and
  3789. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  3790. begin
  3791. //taicpu(p).opcode := A_MOV;
  3792. case taicpu(p).opsize Of
  3793. S_BL:
  3794. begin
  3795. DebugMsg(SPeepholeOptimization + 'var13',p);
  3796. taicpu(hp1).changeopsize(S_L);
  3797. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  3798. end;
  3799. S_WL:
  3800. begin
  3801. DebugMsg(SPeepholeOptimization + 'var14',p);
  3802. taicpu(hp1).changeopsize(S_L);
  3803. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ffff);
  3804. end;
  3805. S_BW:
  3806. begin
  3807. DebugMsg(SPeepholeOptimization + 'var15',p);
  3808. taicpu(hp1).changeopsize(S_W);
  3809. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  3810. end;
  3811. {$ifdef x86_64}
  3812. S_BQ:
  3813. begin
  3814. DebugMsg(SPeepholeOptimization + 'var16',p);
  3815. taicpu(hp1).changeopsize(S_Q);
  3816. taicpu(hp1).loadConst(
  3817. 0, taicpu(hp1).oper[0]^.val and $ff);
  3818. end;
  3819. S_WQ:
  3820. begin
  3821. DebugMsg(SPeepholeOptimization + 'var17',p);
  3822. taicpu(hp1).changeopsize(S_Q);
  3823. taicpu(hp1).loadConst(0, taicpu(hp1).oper[0]^.val and $ffff);
  3824. end;
  3825. S_LQ:
  3826. begin
  3827. DebugMsg(SPeepholeOptimization + 'var18',p);
  3828. taicpu(hp1).changeopsize(S_Q);
  3829. taicpu(hp1).loadConst(
  3830. 0, taicpu(hp1).oper[0]^.val and $ffffffff);
  3831. end;
  3832. {$endif x86_64}
  3833. else
  3834. Internalerror(2017050704)
  3835. end;
  3836. end;
  3837. end;
  3838. end;
  3839. end;
  3840. function TX86AsmOptimizer.OptPass1AND(var p : tai) : boolean;
  3841. var
  3842. hp1 : tai;
  3843. MaskLength : Cardinal;
  3844. begin
  3845. Result:=false;
  3846. if GetNextInstruction(p, hp1) then
  3847. begin
  3848. if MatchOpType(taicpu(p),top_const,top_reg) and
  3849. MatchInstruction(hp1,A_AND,[]) and
  3850. MatchOpType(taicpu(hp1),top_const,top_reg) and
  3851. (getsupreg(taicpu(p).oper[1]^.reg) = getsupreg(taicpu(hp1).oper[1]^.reg)) and
  3852. { the second register must contain the first one, so compare their subreg types }
  3853. (getsubreg(taicpu(p).oper[1]^.reg)<=getsubreg(taicpu(hp1).oper[1]^.reg)) and
  3854. (abs(taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val)<$80000000) then
  3855. { change
  3856. and const1, reg
  3857. and const2, reg
  3858. to
  3859. and (const1 and const2), reg
  3860. }
  3861. begin
  3862. taicpu(hp1).loadConst(0, taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val);
  3863. DebugMsg(SPeepholeOptimization + 'AndAnd2And done',hp1);
  3864. asml.remove(p);
  3865. p.Free;
  3866. p:=hp1;
  3867. Result:=true;
  3868. exit;
  3869. end
  3870. else if MatchOpType(taicpu(p),top_const,top_reg) and
  3871. MatchInstruction(hp1,A_MOVZX,[]) and
  3872. (taicpu(hp1).oper[0]^.typ = top_reg) and
  3873. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[1]^) and
  3874. (getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) and
  3875. (((taicpu(p).opsize=S_W) and
  3876. (taicpu(hp1).opsize=S_BW)) or
  3877. ((taicpu(p).opsize=S_L) and
  3878. (taicpu(hp1).opsize in [S_WL,S_BL]))
  3879. {$ifdef x86_64}
  3880. or
  3881. ((taicpu(p).opsize=S_Q) and
  3882. (taicpu(hp1).opsize in [S_BQ,S_WQ]))
  3883. {$endif x86_64}
  3884. ) then
  3885. begin
  3886. if (((taicpu(hp1).opsize) in [S_BW,S_BL{$ifdef x86_64},S_BQ{$endif x86_64}]) and
  3887. ((taicpu(p).oper[0]^.val and $ff)=taicpu(p).oper[0]^.val)
  3888. ) or
  3889. (((taicpu(hp1).opsize) in [S_WL{$ifdef x86_64},S_WQ{$endif x86_64}]) and
  3890. ((taicpu(p).oper[0]^.val and $ffff)=taicpu(p).oper[0]^.val))
  3891. then
  3892. begin
  3893. { Unlike MOVSX, MOVZX doesn't actually have a version that zero-extends a
  3894. 32-bit register to a 64-bit register, or even a version called MOVZXD, so
  3895. code that tests for the presence of AND 0xffffffff followed by MOVZX is
  3896. wasted, and is indictive of a compiler bug if it were triggered. [Kit]
  3897. NOTE: To zero-extend from 32 bits to 64 bits, simply use the standard MOV.
  3898. }
  3899. DebugMsg(SPeepholeOptimization + 'AndMovzToAnd done',p);
  3900. asml.remove(hp1);
  3901. hp1.free;
  3902. Exit;
  3903. end;
  3904. end
  3905. else if MatchOpType(taicpu(p),top_const,top_reg) and
  3906. MatchInstruction(hp1,A_SHL,[]) and
  3907. MatchOpType(taicpu(hp1),top_const,top_reg) and
  3908. (getsupreg(taicpu(p).oper[1]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) then
  3909. begin
  3910. {$ifopt R+}
  3911. {$define RANGE_WAS_ON}
  3912. {$R-}
  3913. {$endif}
  3914. { get length of potential and mask }
  3915. MaskLength:=SizeOf(taicpu(p).oper[0]^.val)*8-BsrQWord(taicpu(p).oper[0]^.val)-1;
  3916. { really a mask? }
  3917. {$ifdef RANGE_WAS_ON}
  3918. {$R+}
  3919. {$endif}
  3920. if (((QWord(1) shl MaskLength)-1)=taicpu(p).oper[0]^.val) and
  3921. { unmasked part shifted out? }
  3922. ((MaskLength+taicpu(hp1).oper[0]^.val)>=topsize2memsize[taicpu(hp1).opsize]) then
  3923. begin
  3924. DebugMsg(SPeepholeOptimization + 'AndShlToShl done',p);
  3925. { take care of the register (de)allocs following p }
  3926. UpdateUsedRegs(tai(p.next));
  3927. asml.remove(p);
  3928. p.free;
  3929. p:=hp1;
  3930. Result:=true;
  3931. exit;
  3932. end;
  3933. end
  3934. else if MatchOpType(taicpu(p),top_const,top_reg) and
  3935. MatchInstruction(hp1,A_MOVSX{$ifdef x86_64},A_MOVSXD{$endif x86_64},[]) and
  3936. (taicpu(hp1).oper[0]^.typ = top_reg) and
  3937. MatchOperand(taicpu(p).oper[1]^,taicpu(hp1).oper[1]^) and
  3938. (getsupreg(taicpu(hp1).oper[0]^.reg)=getsupreg(taicpu(hp1).oper[1]^.reg)) and
  3939. (((taicpu(p).opsize=S_W) and
  3940. (taicpu(hp1).opsize=S_BW)) or
  3941. ((taicpu(p).opsize=S_L) and
  3942. (taicpu(hp1).opsize in [S_WL,S_BL]))
  3943. {$ifdef x86_64}
  3944. or
  3945. ((taicpu(p).opsize=S_Q) and
  3946. (taicpu(hp1).opsize in [S_BQ,S_WQ,S_LQ]))
  3947. {$endif x86_64}
  3948. ) then
  3949. begin
  3950. if (((taicpu(hp1).opsize) in [S_BW,S_BL{$ifdef x86_64},S_BQ{$endif x86_64}]) and
  3951. ((taicpu(p).oper[0]^.val and $7f)=taicpu(p).oper[0]^.val)
  3952. ) or
  3953. (((taicpu(hp1).opsize) in [S_WL{$ifdef x86_64},S_WQ{$endif x86_64}]) and
  3954. ((taicpu(p).oper[0]^.val and $7fff)=taicpu(p).oper[0]^.val))
  3955. {$ifdef x86_64}
  3956. or
  3957. (((taicpu(hp1).opsize)=S_LQ) and
  3958. ((taicpu(p).oper[0]^.val and $7fffffff)=taicpu(p).oper[0]^.val)
  3959. )
  3960. {$endif x86_64}
  3961. then
  3962. begin
  3963. DebugMsg(SPeepholeOptimization + 'AndMovsxToAnd',p);
  3964. asml.remove(hp1);
  3965. hp1.free;
  3966. Exit;
  3967. end;
  3968. end
  3969. else if (taicpu(p).oper[1]^.typ = top_reg) and
  3970. (hp1.typ = ait_instruction) and
  3971. (taicpu(hp1).is_jmp) and
  3972. (taicpu(hp1).opcode<>A_JMP) and
  3973. not(RegInUsedRegs(taicpu(p).oper[1]^.reg,UsedRegs)) then
  3974. begin
  3975. { change
  3976. and x, reg
  3977. jxx
  3978. to
  3979. test x, reg
  3980. jxx
  3981. if reg is deallocated before the
  3982. jump, but only if it's a conditional jump (PFV)
  3983. }
  3984. taicpu(p).opcode := A_TEST;
  3985. Exit;
  3986. end;
  3987. end;
  3988. { Lone AND tests }
  3989. if MatchOpType(taicpu(p),top_const,top_reg) then
  3990. begin
  3991. {
  3992. - Convert and $0xFF,reg to and reg,reg if reg is 8-bit
  3993. - Convert and $0xFFFF,reg to and reg,reg if reg is 16-bit
  3994. - Convert and $0xFFFFFFFF,reg to and reg,reg if reg is 32-bit
  3995. }
  3996. if ((taicpu(p).oper[0]^.val = $FF) and (taicpu(p).opsize = S_B)) or
  3997. ((taicpu(p).oper[0]^.val = $FFFF) and (taicpu(p).opsize = S_W)) or
  3998. ((taicpu(p).oper[0]^.val = $FFFFFFFF) and (taicpu(p).opsize = S_L)) then
  3999. begin
  4000. taicpu(p).loadreg(0, taicpu(p).oper[1]^.reg)
  4001. end;
  4002. end;
  4003. end;
  4004. function TX86AsmOptimizer.OptPass2Lea(var p : tai) : Boolean;
  4005. begin
  4006. Result:=false;
  4007. if not (RegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs)) and
  4008. MatchReference(taicpu(p).oper[0]^.ref^,taicpu(p).oper[1]^.reg,NR_INVALID) and
  4009. (taicpu(p).oper[0]^.ref^.index<>NR_NO) then
  4010. begin
  4011. taicpu(p).loadreg(1,taicpu(p).oper[0]^.ref^.base);
  4012. taicpu(p).loadreg(0,taicpu(p).oper[0]^.ref^.index);
  4013. taicpu(p).opcode:=A_ADD;
  4014. DebugMsg(SPeepholeOptimization + 'Lea2AddBase done',p);
  4015. result:=true;
  4016. end
  4017. else if not (RegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs)) and
  4018. MatchReference(taicpu(p).oper[0]^.ref^,NR_INVALID,taicpu(p).oper[1]^.reg) and
  4019. (taicpu(p).oper[0]^.ref^.base<>NR_NO) then
  4020. begin
  4021. taicpu(p).loadreg(1,taicpu(p).oper[0]^.ref^.index);
  4022. taicpu(p).loadreg(0,taicpu(p).oper[0]^.ref^.base);
  4023. taicpu(p).opcode:=A_ADD;
  4024. DebugMsg(SPeepholeOptimization + 'Lea2AddIndex done',p);
  4025. result:=true;
  4026. end;
  4027. end;
  4028. function TX86AsmOptimizer.PostPeepholeOptLea(var p : tai) : Boolean;
  4029. function SkipSimpleInstructions(var hp1 : tai) : Boolean;
  4030. begin
  4031. { we can skip all instructions not messing with the stack pointer }
  4032. while assigned(hp1) and {MatchInstruction(taicpu(hp1),[A_LEA,A_MOV,A_MOVQ,A_MOVSQ,A_MOVSX,A_MOVSXD,A_MOVZX,
  4033. A_AND,A_OR,A_XOR,A_ADD,A_SHR,A_SHL,A_IMUL,A_SETcc,A_SAR,A_SUB,A_TEST,A_CMOVcc,
  4034. A_MOVSS,A_MOVSD,A_MOVAPS,A_MOVUPD,A_MOVAPD,A_MOVUPS,
  4035. A_VMOVSS,A_VMOVSD,A_VMOVAPS,A_VMOVUPD,A_VMOVAPD,A_VMOVUPS],[]) and}
  4036. ({(taicpu(hp1).ops=0) or }
  4037. ({(MatchOpType(taicpu(hp1),top_reg,top_reg) or MatchOpType(taicpu(hp1),top_const,top_reg) or
  4038. (MatchOpType(taicpu(hp1),top_ref,top_reg))
  4039. ) and }
  4040. not(RegInInstruction(NR_STACK_POINTER_REG,hp1)) { and not(RegInInstruction(NR_FRAME_POINTER_REG,hp1))}
  4041. )
  4042. ) do
  4043. GetNextInstruction(hp1,hp1);
  4044. Result:=assigned(hp1);
  4045. end;
  4046. var
  4047. hp1, hp2, hp3: tai;
  4048. begin
  4049. Result:=false;
  4050. { replace
  4051. leal(q) x(<stackpointer>),<stackpointer>
  4052. call procname
  4053. leal(q) -x(<stackpointer>),<stackpointer>
  4054. ret
  4055. by
  4056. jmp procname
  4057. but do it only on level 4 because it destroys stack back traces
  4058. }
  4059. if (cs_opt_level4 in current_settings.optimizerswitches) and
  4060. MatchOpType(taicpu(p),top_ref,top_reg) and
  4061. (taicpu(p).oper[0]^.ref^.base=NR_STACK_POINTER_REG) and
  4062. (taicpu(p).oper[0]^.ref^.index=NR_NO) and
  4063. { the -8 or -24 are not required, but bail out early if possible,
  4064. higher values are unlikely }
  4065. ((taicpu(p).oper[0]^.ref^.offset=-8) or
  4066. (taicpu(p).oper[0]^.ref^.offset=-24)) and
  4067. (taicpu(p).oper[0]^.ref^.symbol=nil) and
  4068. (taicpu(p).oper[0]^.ref^.relsymbol=nil) and
  4069. (taicpu(p).oper[0]^.ref^.segment=NR_NO) and
  4070. (taicpu(p).oper[1]^.reg=NR_STACK_POINTER_REG) and
  4071. GetNextInstruction(p, hp1) and
  4072. { trick to skip label }
  4073. ((hp1.typ=ait_instruction) or GetNextInstruction(hp1, hp1)) and
  4074. SkipSimpleInstructions(hp1) and
  4075. MatchInstruction(hp1,A_CALL,[S_NO]) and
  4076. GetNextInstruction(hp1, hp2) and
  4077. MatchInstruction(hp2,A_LEA,[taicpu(p).opsize]) and
  4078. MatchOpType(taicpu(hp2),top_ref,top_reg) and
  4079. (taicpu(hp2).oper[0]^.ref^.offset=-taicpu(p).oper[0]^.ref^.offset) and
  4080. (taicpu(hp2).oper[0]^.ref^.base=NR_STACK_POINTER_REG) and
  4081. (taicpu(hp2).oper[0]^.ref^.index=NR_NO) and
  4082. (taicpu(hp2).oper[0]^.ref^.symbol=nil) and
  4083. (taicpu(hp2).oper[0]^.ref^.relsymbol=nil) and
  4084. (taicpu(hp2).oper[0]^.ref^.segment=NR_NO) and
  4085. (taicpu(hp2).oper[1]^.reg=NR_STACK_POINTER_REG) and
  4086. GetNextInstruction(hp2, hp3) and
  4087. { trick to skip label }
  4088. ((hp3.typ=ait_instruction) or GetNextInstruction(hp3, hp3)) and
  4089. MatchInstruction(hp3,A_RET,[S_NO]) and
  4090. (taicpu(hp3).ops=0) then
  4091. begin
  4092. taicpu(hp1).opcode := A_JMP;
  4093. taicpu(hp1).is_jmp := true;
  4094. DebugMsg(SPeepholeOptimization + 'LeaCallLeaRet2Jmp done',p);
  4095. RemoveCurrentP(p);
  4096. AsmL.Remove(hp2);
  4097. hp2.free;
  4098. AsmL.Remove(hp3);
  4099. hp3.free;
  4100. Result:=true;
  4101. end;
  4102. end;
  4103. function TX86AsmOptimizer.PostPeepholeOptMov(var p : tai) : Boolean;
  4104. var
  4105. Value, RegName: string;
  4106. begin
  4107. Result:=false;
  4108. if (taicpu(p).oper[1]^.typ = top_reg) and (taicpu(p).oper[0]^.typ = top_const) then
  4109. begin
  4110. case taicpu(p).oper[0]^.val of
  4111. 0:
  4112. { Don't make this optimisation if the CPU flags are required, since XOR scrambles them }
  4113. if not (RegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs)) then
  4114. begin
  4115. { change "mov $0,%reg" into "xor %reg,%reg" }
  4116. taicpu(p).opcode := A_XOR;
  4117. taicpu(p).loadReg(0,taicpu(p).oper[1]^.reg);
  4118. Result := True;
  4119. end;
  4120. $1..$FFFFFFFF:
  4121. begin
  4122. { Code size reduction by J. Gareth "Kit" Moreton }
  4123. { change 64-bit register to 32-bit register to reduce code size (upper 32 bits will be set to zero) }
  4124. case taicpu(p).opsize of
  4125. S_Q:
  4126. begin
  4127. RegName := debug_regname(taicpu(p).oper[1]^.reg); { 64-bit register name }
  4128. Value := debug_tostr(taicpu(p).oper[0]^.val);
  4129. { The actual optimization }
  4130. setsubreg(taicpu(p).oper[1]^.reg, R_SUBD);
  4131. taicpu(p).changeopsize(S_L);
  4132. DebugMsg(SPeepholeOptimization + 'movq $' + Value + ',' + RegName + ' -> movl $' + Value + ',' + debug_regname(taicpu(p).oper[1]^.reg) + ' (immediate can be represented with just 32 bits)', p);
  4133. Result := True;
  4134. end;
  4135. else
  4136. { Do nothing };
  4137. end;
  4138. end;
  4139. -1:
  4140. { Don't make this optimisation if the CPU flags are required, since OR scrambles them }
  4141. if (cs_opt_size in current_settings.optimizerswitches) and
  4142. (taicpu(p).opsize <> S_B) and
  4143. not (RegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs)) then
  4144. begin
  4145. { change "mov $-1,%reg" into "or $-1,%reg" }
  4146. { NOTES:
  4147. - No size saving is made when changing a Word-sized assignment unless the register is AX (smaller encoding)
  4148. - This operation creates a false dependency on the register, so only do it when optimising for size
  4149. - It is possible to set memory operands using this method, but this creates an even greater false dependency, so don't do this at all
  4150. }
  4151. taicpu(p).opcode := A_OR;
  4152. Result := True;
  4153. end;
  4154. end;
  4155. end;
  4156. end;
  4157. function TX86AsmOptimizer.PostPeepholeOptCmp(var p : tai) : Boolean;
  4158. begin
  4159. Result:=false;
  4160. { change "cmp $0, %reg" to "test %reg, %reg" }
  4161. if MatchOpType(taicpu(p),top_const,top_reg) and
  4162. (taicpu(p).oper[0]^.val = 0) then
  4163. begin
  4164. taicpu(p).opcode := A_TEST;
  4165. taicpu(p).loadreg(0,taicpu(p).oper[1]^.reg);
  4166. Result:=true;
  4167. end;
  4168. end;
  4169. function TX86AsmOptimizer.PostPeepholeOptTestOr(var p : tai) : Boolean;
  4170. var
  4171. IsTestConstX : Boolean;
  4172. hp1,hp2 : tai;
  4173. begin
  4174. Result:=false;
  4175. { removes the line marked with (x) from the sequence
  4176. and/or/xor/add/sub/... $x, %y
  4177. test/or %y, %y | test $-1, %y (x)
  4178. j(n)z _Label
  4179. as the first instruction already adjusts the ZF
  4180. %y operand may also be a reference }
  4181. IsTestConstX:=(taicpu(p).opcode=A_TEST) and
  4182. MatchOperand(taicpu(p).oper[0]^,-1);
  4183. if (OpsEqual(taicpu(p).oper[0]^,taicpu(p).oper[1]^) or IsTestConstX) and
  4184. GetLastInstruction(p, hp1) and
  4185. (tai(hp1).typ = ait_instruction) and
  4186. GetNextInstruction(p,hp2) and
  4187. MatchInstruction(hp2,A_SETcc,A_Jcc,A_CMOVcc,[]) then
  4188. case taicpu(hp1).opcode Of
  4189. A_ADD, A_SUB, A_OR, A_XOR, A_AND:
  4190. begin
  4191. if OpsEqual(taicpu(hp1).oper[1]^,taicpu(p).oper[1]^) and
  4192. { does not work in case of overflow for G(E)/L(E)/C_O/C_NO }
  4193. { and in case of carry for A(E)/B(E)/C/NC }
  4194. ((taicpu(hp2).condition in [C_Z,C_NZ,C_E,C_NE]) or
  4195. ((taicpu(hp1).opcode <> A_ADD) and
  4196. (taicpu(hp1).opcode <> A_SUB))) then
  4197. begin
  4198. hp1 := tai(p.next);
  4199. asml.remove(p);
  4200. p.free;
  4201. p := tai(hp1);
  4202. Result:=true;
  4203. end;
  4204. end;
  4205. A_SHL, A_SAL, A_SHR, A_SAR:
  4206. begin
  4207. if OpsEqual(taicpu(hp1).oper[1]^,taicpu(p).oper[1]^) and
  4208. { SHL/SAL/SHR/SAR with a value of 0 do not change the flags }
  4209. { therefore, it's only safe to do this optimization for }
  4210. { shifts by a (nonzero) constant }
  4211. (taicpu(hp1).oper[0]^.typ = top_const) and
  4212. (taicpu(hp1).oper[0]^.val <> 0) and
  4213. { does not work in case of overflow for G(E)/L(E)/C_O/C_NO }
  4214. { and in case of carry for A(E)/B(E)/C/NC }
  4215. (taicpu(hp2).condition in [C_Z,C_NZ,C_E,C_NE]) then
  4216. begin
  4217. hp1 := tai(p.next);
  4218. asml.remove(p);
  4219. p.free;
  4220. p := tai(hp1);
  4221. Result:=true;
  4222. end;
  4223. end;
  4224. A_DEC, A_INC, A_NEG:
  4225. begin
  4226. if OpsEqual(taicpu(hp1).oper[0]^,taicpu(p).oper[1]^) and
  4227. { does not work in case of overflow for G(E)/L(E)/C_O/C_NO }
  4228. { and in case of carry for A(E)/B(E)/C/NC }
  4229. (taicpu(hp2).condition in [C_Z,C_NZ,C_E,C_NE]) then
  4230. begin
  4231. case taicpu(hp1).opcode of
  4232. A_DEC, A_INC:
  4233. { replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag }
  4234. begin
  4235. case taicpu(hp1).opcode Of
  4236. A_DEC: taicpu(hp1).opcode := A_SUB;
  4237. A_INC: taicpu(hp1).opcode := A_ADD;
  4238. else
  4239. ;
  4240. end;
  4241. taicpu(hp1).loadoper(1,taicpu(hp1).oper[0]^);
  4242. taicpu(hp1).loadConst(0,1);
  4243. taicpu(hp1).ops:=2;
  4244. end;
  4245. else
  4246. ;
  4247. end;
  4248. hp1 := tai(p.next);
  4249. asml.remove(p);
  4250. p.free;
  4251. p := tai(hp1);
  4252. Result:=true;
  4253. end;
  4254. end
  4255. else
  4256. { change "test $-1,%reg" into "test %reg,%reg" }
  4257. if IsTestConstX and (taicpu(p).oper[1]^.typ=top_reg) then
  4258. taicpu(p).loadoper(0,taicpu(p).oper[1]^);
  4259. end { case }
  4260. { change "test $-1,%reg" into "test %reg,%reg" }
  4261. else if IsTestConstX and (taicpu(p).oper[1]^.typ=top_reg) then
  4262. taicpu(p).loadoper(0,taicpu(p).oper[1]^);
  4263. end;
  4264. function TX86AsmOptimizer.PostPeepholeOptCall(var p : tai) : Boolean;
  4265. var
  4266. hp1 : tai;
  4267. {$ifndef x86_64}
  4268. hp2 : taicpu;
  4269. {$endif x86_64}
  4270. begin
  4271. Result:=false;
  4272. {$ifndef x86_64}
  4273. { don't do this on modern CPUs, this really hurts them due to
  4274. broken call/ret pairing }
  4275. if (current_settings.optimizecputype < cpu_Pentium2) and
  4276. not(cs_create_pic in current_settings.moduleswitches) and
  4277. GetNextInstruction(p, hp1) and
  4278. MatchInstruction(hp1,A_JMP,[S_NO]) and
  4279. MatchOpType(taicpu(hp1),top_ref) and
  4280. (taicpu(hp1).oper[0]^.ref^.refaddr=addr_full) then
  4281. begin
  4282. hp2 := taicpu.Op_sym(A_PUSH,S_L,taicpu(hp1).oper[0]^.ref^.symbol);
  4283. InsertLLItem(p.previous, p, hp2);
  4284. taicpu(p).opcode := A_JMP;
  4285. taicpu(p).is_jmp := true;
  4286. asml.remove(hp1);
  4287. hp1.free;
  4288. Result:=true;
  4289. end
  4290. else
  4291. {$endif x86_64}
  4292. { replace
  4293. call procname
  4294. ret
  4295. by
  4296. jmp procname
  4297. but do it only on level 4 because it destroys stack back traces
  4298. }
  4299. if (cs_opt_level4 in current_settings.optimizerswitches) and
  4300. GetNextInstruction(p, hp1) and
  4301. MatchInstruction(hp1,A_RET,[S_NO]) and
  4302. (taicpu(hp1).ops=0) then
  4303. begin
  4304. taicpu(p).opcode := A_JMP;
  4305. taicpu(p).is_jmp := true;
  4306. DebugMsg(SPeepholeOptimization + 'CallRet2Jmp done',p);
  4307. asml.remove(hp1);
  4308. hp1.free;
  4309. Result:=true;
  4310. end;
  4311. end;
  4312. {$ifdef x86_64}
  4313. function TX86AsmOptimizer.PostPeepholeOptMovzx(var p : tai) : Boolean;
  4314. var
  4315. PreMessage: string;
  4316. begin
  4317. Result := False;
  4318. { Code size reduction by J. Gareth "Kit" Moreton }
  4319. { Convert MOVZBQ and MOVZWQ to MOVZBL and MOVZWL respectively if it removes the REX prefix }
  4320. if (taicpu(p).opsize in [S_BQ, S_WQ]) and
  4321. (getsupreg(taicpu(p).oper[1]^.reg) in [RS_RAX, RS_RCX, RS_RDX, RS_RBX, RS_RSI, RS_RDI, RS_RBP, RS_RSP])
  4322. then
  4323. begin
  4324. { Has 64-bit register name and opcode suffix }
  4325. PreMessage := 'movz' + debug_opsize2str(taicpu(p).opsize) + ' ' + debug_operstr(taicpu(p).oper[0]^) + ',' + debug_regname(taicpu(p).oper[1]^.reg) + ' -> movz';
  4326. { The actual optimization }
  4327. setsubreg(taicpu(p).oper[1]^.reg, R_SUBD);
  4328. if taicpu(p).opsize = S_BQ then
  4329. taicpu(p).changeopsize(S_BL)
  4330. else
  4331. taicpu(p).changeopsize(S_WL);
  4332. DebugMsg(SPeepholeOptimization + PreMessage +
  4333. debug_opsize2str(taicpu(p).opsize) + ' ' + debug_operstr(taicpu(p).oper[0]^) + ',' + debug_regname(taicpu(p).oper[1]^.reg) + ' (removes REX prefix)', p);
  4334. end;
  4335. end;
  4336. function TX86AsmOptimizer.PostPeepholeOptXor(var p : tai) : Boolean;
  4337. var
  4338. PreMessage, RegName: string;
  4339. begin
  4340. { Code size reduction by J. Gareth "Kit" Moreton }
  4341. { change "xorq %reg,%reg" to "xorl %reg,%reg" for %rax, %rcx, %rdx, %rbx, %rsi, %rdi, %rbp and %rsp,
  4342. as this removes the REX prefix }
  4343. Result := False;
  4344. if not OpsEqual(taicpu(p).oper[0]^,taicpu(p).oper[1]^) then
  4345. Exit;
  4346. if taicpu(p).oper[0]^.typ <> top_reg then
  4347. { Should be impossible if both operands were equal, since one of XOR's operands must be a register }
  4348. InternalError(2018011500);
  4349. case taicpu(p).opsize of
  4350. S_Q:
  4351. begin
  4352. if (getsupreg(taicpu(p).oper[0]^.reg) in [RS_RAX, RS_RCX, RS_RDX, RS_RBX, RS_RSI, RS_RDI, RS_RBP, RS_RSP]) then
  4353. begin
  4354. RegName := debug_regname(taicpu(p).oper[0]^.reg); { 64-bit register name }
  4355. PreMessage := 'xorq ' + RegName + ',' + RegName + ' -> xorl ';
  4356. { The actual optimization }
  4357. setsubreg(taicpu(p).oper[0]^.reg, R_SUBD);
  4358. setsubreg(taicpu(p).oper[1]^.reg, R_SUBD);
  4359. taicpu(p).changeopsize(S_L);
  4360. RegName := debug_regname(taicpu(p).oper[0]^.reg); { 32-bit register name }
  4361. DebugMsg(SPeepholeOptimization + PreMessage + RegName + ',' + RegName + ' (removes REX prefix)', p);
  4362. end;
  4363. end;
  4364. else
  4365. ;
  4366. end;
  4367. end;
  4368. {$endif}
  4369. procedure TX86AsmOptimizer.OptReferences;
  4370. var
  4371. p: tai;
  4372. i: Integer;
  4373. begin
  4374. p := BlockStart;
  4375. while (p <> BlockEnd) Do
  4376. begin
  4377. if p.typ=ait_instruction then
  4378. begin
  4379. for i:=0 to taicpu(p).ops-1 do
  4380. if taicpu(p).oper[i]^.typ=top_ref then
  4381. optimize_ref(taicpu(p).oper[i]^.ref^,false);
  4382. end;
  4383. p:=tai(p.next);
  4384. end;
  4385. end;
  4386. end.