aasmcpu.pas 86 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl and Peter Vreman
  3. Contains the abstract assembler implementation for the i386
  4. * Portions of this code was inspired by the NASM sources
  5. The Netwide Assembler is Copyright (c) 1996 Simon Tatham and
  6. Julian Hall. All rights reserved.
  7. This program is free software; you can redistribute it and/or modify
  8. it under the terms of the GNU General Public License as published by
  9. the Free Software Foundation; either version 2 of the License, or
  10. (at your option) any later version.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. ****************************************************************************
  19. }
  20. unit aasmcpu;
  21. {$i fpcdefs.inc}
  22. interface
  23. uses
  24. globtype,verbose,
  25. cpubase,
  26. cgbase,cgutils,
  27. symtype,
  28. aasmbase,aasmtai,aasmdata,aasmsym,
  29. ogbase;
  30. const
  31. { "mov reg,reg" source operand number }
  32. O_MOV_SOURCE = 0;
  33. { "mov reg,reg" destination operand number }
  34. O_MOV_DEST = 1;
  35. { Operand types }
  36. OT_NONE = $00000000;
  37. { Bits 0..7: sizes }
  38. OT_BITS8 = $00000001;
  39. OT_BITS16 = $00000002;
  40. OT_BITS32 = $00000004;
  41. OT_BITS64 = $00000008; { x86_64 and FPU }
  42. OT_BITS80 = $00000010; { FPU only }
  43. OT_FAR = $00000020; { this means 16:16 or 16:32, like in CALL/JMP }
  44. OT_NEAR = $00000040;
  45. OT_SHORT = $00000080;
  46. { TODO: FAR/NEAR/SHORT are sizes too, they should be included into size mask,
  47. but this requires adjusting the opcode table }
  48. OT_SIZE_MASK = $0000001F; { all the size attributes }
  49. OT_NON_SIZE = longint(not OT_SIZE_MASK);
  50. { Bits 8..11: modifiers }
  51. OT_SIGNED = $00000100; { the operand need to be signed -128-127 }
  52. OT_TO = $00000200; { reverse effect in FADD, FSUB &c }
  53. OT_COLON = $00000400; { operand is followed by a colon }
  54. OT_MODIFIER_MASK = $00000F00;
  55. { Bits 12..15: type of operand }
  56. OT_REGISTER = $00001000;
  57. OT_IMMEDIATE = $00002000;
  58. OT_MEMORY = $0000C000; { always includes 'OT_REGMEM' bit as well }
  59. OT_REGMEM = $00008000; { for r/m, ie EA, operands }
  60. OT_TYPE_MASK = OT_REGISTER or OT_IMMEDIATE or OT_MEMORY or OT_REGMEM;
  61. OT_REGNORM = OT_REGISTER or OT_REGMEM; { 'normal' reg, qualifies as EA }
  62. { Bits 20..22, 24..26: register classes
  63. otf_* consts are not used alone, only to build other constants. }
  64. otf_reg_cdt = $00100000;
  65. otf_reg_gpr = $00200000;
  66. otf_reg_sreg = $00400000;
  67. otf_reg_fpu = $01000000;
  68. otf_reg_mmx = $02000000;
  69. otf_reg_xmm = $04000000;
  70. { Bits 16..19: subclasses, meaning depends on classes field }
  71. otf_sub0 = $00010000;
  72. otf_sub1 = $00020000;
  73. otf_sub2 = $00040000;
  74. otf_sub3 = $00080000;
  75. OT_REG_SMASK = otf_sub0 or otf_sub1 or otf_sub2 or otf_sub3;
  76. { register class 0: CRx, DRx and TRx }
  77. OT_REG_CDT = OT_REGISTER or otf_reg_cdt or OT_BITS32;
  78. OT_REG_CREG = OT_REG_CDT or otf_sub0; { CRn }
  79. OT_REG_DREG = OT_REG_CDT or otf_sub1; { DRn }
  80. OT_REG_TREG = OT_REG_CDT or otf_sub2; { TRn }
  81. OT_REG_CR4 = OT_REG_CDT or otf_sub3; { CR4 (Pentium only) }
  82. { register class 1: general-purpose registers }
  83. OT_REG_GPR = OT_REGNORM or otf_reg_gpr;
  84. OT_RM_GPR = OT_REGMEM or otf_reg_gpr;
  85. OT_REG8 = OT_REG_GPR or OT_BITS8; { 8-bit GPR }
  86. OT_REG16 = OT_REG_GPR or OT_BITS16;
  87. OT_REG32 = OT_REG_GPR or OT_BITS32;
  88. OT_REG64 = OT_REG_GPR or OT_BITS64;
  89. { GPR subclass 0: accumulator: AL, AX, EAX or RAX }
  90. OT_REG_ACCUM = OT_REG_GPR or otf_sub0;
  91. OT_REG_AL = OT_REG_ACCUM or OT_BITS8;
  92. OT_REG_AX = OT_REG_ACCUM or OT_BITS16;
  93. OT_REG_EAX = OT_REG_ACCUM or OT_BITS32;
  94. {$ifdef x86_64}
  95. OT_REG_RAX = OT_REG_ACCUM or OT_BITS64;
  96. {$endif x86_64}
  97. { GPR subclass 1: counter: CL, CX, ECX or RCX }
  98. OT_REG_COUNT = OT_REG_GPR or otf_sub1;
  99. OT_REG_CL = OT_REG_COUNT or OT_BITS8;
  100. OT_REG_CX = OT_REG_COUNT or OT_BITS16;
  101. OT_REG_ECX = OT_REG_COUNT or OT_BITS32;
  102. {$ifdef x86_64}
  103. OT_REG_RCX = OT_REG_COUNT or OT_BITS64;
  104. {$endif x86_64}
  105. { GPR subclass 2: data register: DL, DX, EDX or RDX }
  106. OT_REG_DX = OT_REG_GPR or otf_sub2 or OT_BITS16;
  107. OT_REG_EDX = OT_REG_GPR or otf_sub2 or OT_BITS32;
  108. { register class 2: Segment registers }
  109. OT_REG_SREG = OT_REGISTER or otf_reg_sreg or OT_BITS16;
  110. OT_REG_CS = OT_REG_SREG or otf_sub0; { CS }
  111. OT_REG_DESS = OT_REG_SREG or otf_sub1; { DS, ES, SS (non-CS 86 registers) }
  112. OT_REG_FSGS = OT_REG_SREG or otf_sub2; { FS, GS (386 extended registers) }
  113. { register class 3: FPU registers }
  114. OT_FPUREG = OT_REGISTER or otf_reg_fpu;
  115. OT_FPU0 = OT_FPUREG or otf_sub0; { FPU stack register zero }
  116. { register class 4: MMX (both reg and r/m) }
  117. OT_MMXREG = OT_REGNORM or otf_reg_mmx;
  118. OT_MMXRM = OT_REGMEM or otf_reg_mmx;
  119. { register class 5: XMM (both reg and r/m) }
  120. OT_XMMREG = OT_REGNORM or otf_reg_xmm;
  121. OT_XMMRM = OT_REGMEM or otf_reg_xmm;
  122. { Memory operands }
  123. OT_MEM8 = OT_MEMORY or OT_BITS8;
  124. OT_MEM16 = OT_MEMORY or OT_BITS16;
  125. OT_MEM32 = OT_MEMORY or OT_BITS32;
  126. OT_MEM64 = OT_MEMORY or OT_BITS64;
  127. OT_MEM80 = OT_MEMORY or OT_BITS80;
  128. OT_MEM_OFFS = OT_MEMORY or otf_sub0; { special type of EA }
  129. { simple [address] offset }
  130. { Matches any type of r/m operand }
  131. OT_MEMORY_ANY = OT_MEMORY or OT_RM_GPR or OT_XMMRM or OT_MMXRM;
  132. { Immediate operands }
  133. OT_IMM8 = OT_IMMEDIATE or OT_BITS8;
  134. OT_IMM16 = OT_IMMEDIATE or OT_BITS16;
  135. OT_IMM32 = OT_IMMEDIATE or OT_BITS32;
  136. OT_IMM64 = OT_IMMEDIATE or OT_BITS64;
  137. OT_ONENESS = otf_sub0; { special type of immediate operand }
  138. OT_UNITY = OT_IMMEDIATE or OT_ONENESS; { for shift/rotate instructions }
  139. { Size of the instruction table converted by nasmconv.pas }
  140. {$ifdef x86_64}
  141. instabentries = {$i x8664nop.inc}
  142. {$else x86_64}
  143. instabentries = {$i i386nop.inc}
  144. {$endif x86_64}
  145. maxinfolen = 8;
  146. MaxInsChanges = 3; { Max things a instruction can change }
  147. type
  148. { What an instruction can change. Needed for optimizer and spilling code.
  149. Note: The order of this enumeration is should not be changed! }
  150. TInsChange = (Ch_None,
  151. {Read from a register}
  152. Ch_REAX, Ch_RECX, Ch_REDX, Ch_REBX, Ch_RESP, Ch_REBP, Ch_RESI, Ch_REDI,
  153. {write from a register}
  154. Ch_WEAX, Ch_WECX, Ch_WEDX, Ch_WEBX, Ch_WESP, Ch_WEBP, Ch_WESI, Ch_WEDI,
  155. {read and write from/to a register}
  156. Ch_RWEAX, Ch_RWECX, Ch_RWEDX, Ch_RWEBX, Ch_RWESP, Ch_RWEBP, Ch_RWESI, Ch_RWEDI,
  157. {modify the contents of a register with the purpose of using
  158. this changed content afterwards (add/sub/..., but e.g. not rep
  159. or movsd)}
  160. Ch_MEAX, Ch_MECX, Ch_MEDX, Ch_MEBX, Ch_MESP, Ch_MEBP, Ch_MESI, Ch_MEDI,
  161. Ch_CDirFlag {clear direction flag}, Ch_SDirFlag {set dir flag},
  162. Ch_RFlags, Ch_WFlags, Ch_RWFlags, Ch_FPU,
  163. Ch_Rop1, Ch_Wop1, Ch_RWop1,Ch_Mop1,
  164. Ch_Rop2, Ch_Wop2, Ch_RWop2,Ch_Mop2,
  165. Ch_Rop3, Ch_WOp3, Ch_RWOp3,Ch_Mop3,
  166. Ch_WMemEDI,
  167. Ch_All,
  168. { x86_64 registers }
  169. Ch_RRAX, Ch_RRCX, Ch_RRDX, Ch_RRBX, Ch_RRSP, Ch_RRBP, Ch_RRSI, Ch_RRDI,
  170. Ch_WRAX, Ch_WRCX, Ch_WRDX, Ch_WRBX, Ch_WRSP, Ch_WRBP, Ch_WRSI, Ch_WRDI,
  171. Ch_RWRAX, Ch_RWRCX, Ch_RWRDX, Ch_RWRBX, Ch_RWRSP, Ch_RWRBP, Ch_RWRSI, Ch_RWRDI,
  172. Ch_MRAX, Ch_MRCX, Ch_MRDX, Ch_MRBX, Ch_MRSP, Ch_MRBP, Ch_MRSI, Ch_MRDI
  173. );
  174. TInsProp = packed record
  175. Ch : Array[1..MaxInsChanges] of TInsChange;
  176. end;
  177. const
  178. InsProp : array[tasmop] of TInsProp =
  179. {$ifdef x86_64}
  180. {$i x8664pro.inc}
  181. {$else x86_64}
  182. {$i i386prop.inc}
  183. {$endif x86_64}
  184. type
  185. TOperandOrder = (op_intel,op_att);
  186. tinsentry=packed record
  187. opcode : tasmop;
  188. ops : byte;
  189. optypes : array[0..max_operands-1] of longint;
  190. code : array[0..maxinfolen] of char;
  191. flags : cardinal;
  192. end;
  193. pinsentry=^tinsentry;
  194. { alignment for operator }
  195. tai_align = class(tai_align_abstract)
  196. reg : tregister;
  197. constructor create(b:byte);override;
  198. constructor create_op(b: byte; _op: byte);override;
  199. function calculatefillbuf(var buf : tfillbuffer;executable : boolean):pchar;override;
  200. end;
  201. taicpu = class(tai_cpu_abstract_sym)
  202. opsize : topsize;
  203. constructor op_none(op : tasmop);
  204. constructor op_none(op : tasmop;_size : topsize);
  205. constructor op_reg(op : tasmop;_size : topsize;_op1 : tregister);
  206. constructor op_const(op : tasmop;_size : topsize;_op1 : aint);
  207. constructor op_ref(op : tasmop;_size : topsize;const _op1 : treference);
  208. constructor op_reg_reg(op : tasmop;_size : topsize;_op1,_op2 : tregister);
  209. constructor op_reg_ref(op : tasmop;_size : topsize;_op1 : tregister;const _op2 : treference);
  210. constructor op_reg_const(op:tasmop; _size: topsize; _op1: tregister; _op2: aint);
  211. constructor op_const_reg(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister);
  212. constructor op_const_const(op : tasmop;_size : topsize;_op1,_op2 : aint);
  213. constructor op_const_ref(op : tasmop;_size : topsize;_op1 : aint;const _op2 : treference);
  214. constructor op_ref_reg(op : tasmop;_size : topsize;const _op1 : treference;_op2 : tregister);
  215. constructor op_reg_reg_reg(op : tasmop;_size : topsize;_op1,_op2,_op3 : tregister);
  216. constructor op_const_reg_reg(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister;_op3 : tregister);
  217. constructor op_const_ref_reg(op : tasmop;_size : topsize;_op1 : aint;const _op2 : treference;_op3 : tregister);
  218. constructor op_reg_reg_ref(op : tasmop;_size : topsize;_op1,_op2 : tregister; const _op3 : treference);
  219. constructor op_const_reg_ref(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister;const _op3 : treference);
  220. { this is for Jmp instructions }
  221. constructor op_cond_sym(op : tasmop;cond:TAsmCond;_size : topsize;_op1 : tasmsymbol);
  222. constructor op_sym(op : tasmop;_size : topsize;_op1 : tasmsymbol);
  223. constructor op_sym_ofs(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint);
  224. constructor op_sym_ofs_reg(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;_op2 : tregister);
  225. constructor op_sym_ofs_ref(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  226. procedure changeopsize(siz:topsize);
  227. function GetString:string;
  228. procedure CheckNonCommutativeOpcodes;
  229. private
  230. FOperandOrder : TOperandOrder;
  231. procedure init(_size : topsize); { this need to be called by all constructor }
  232. public
  233. { the next will reset all instructions that can change in pass 2 }
  234. procedure ResetPass1;override;
  235. procedure ResetPass2;override;
  236. function CheckIfValid:boolean;
  237. function Pass1(objdata:TObjData):longint;override;
  238. procedure Pass2(objdata:TObjData);override;
  239. procedure SetOperandOrder(order:TOperandOrder);
  240. function is_same_reg_move(regtype: Tregistertype):boolean;override;
  241. { register spilling code }
  242. function spilling_get_operation_type(opnr: longint): topertype;override;
  243. private
  244. { next fields are filled in pass1, so pass2 is faster }
  245. insentry : PInsEntry;
  246. insoffset : longint;
  247. LastInsOffset : longint; { need to be public to be reset }
  248. inssize : shortint;
  249. {$ifdef x86_64}
  250. rex : byte;
  251. {$endif x86_64}
  252. function InsEnd:longint;
  253. procedure create_ot(objdata:TObjData);
  254. function Matches(p:PInsEntry):boolean;
  255. function calcsize(p:PInsEntry):shortint;
  256. procedure gencode(objdata:TObjData);
  257. function NeedAddrPrefix(opidx:byte):boolean;
  258. procedure Swapoperands;
  259. function FindInsentry(objdata:TObjData):boolean;
  260. end;
  261. function spilling_create_load(const ref:treference;r:tregister):Taicpu;
  262. function spilling_create_store(r:tregister; const ref:treference):Taicpu;
  263. procedure InitAsm;
  264. procedure DoneAsm;
  265. implementation
  266. uses
  267. cutils,
  268. globals,
  269. systems,
  270. procinfo,
  271. itcpugas,
  272. symsym;
  273. {*****************************************************************************
  274. Instruction table
  275. *****************************************************************************}
  276. const
  277. {Instruction flags }
  278. IF_NONE = $00000000;
  279. IF_SM = $00000001; { size match first two operands }
  280. IF_SM2 = $00000002;
  281. IF_SB = $00000004; { unsized operands can't be non-byte }
  282. IF_SW = $00000008; { unsized operands can't be non-word }
  283. IF_SD = $00000010; { unsized operands can't be nondword }
  284. IF_SMASK = $0000001f;
  285. IF_AR0 = $00000020; { SB, SW, SD applies to argument 0 }
  286. IF_AR1 = $00000040; { SB, SW, SD applies to argument 1 }
  287. IF_AR2 = $00000060; { SB, SW, SD applies to argument 2 }
  288. IF_ARMASK = $00000060; { mask for unsized argument spec }
  289. IF_ARSHIFT = 5; { LSB of IF_ARMASK }
  290. IF_PRIV = $00000100; { it's a privileged instruction }
  291. IF_SMM = $00000200; { it's only valid in SMM }
  292. IF_PROT = $00000400; { it's protected mode only }
  293. IF_NOX86_64 = $00000800; { removed instruction in x86_64 }
  294. IF_UNDOC = $00001000; { it's an undocumented instruction }
  295. IF_FPU = $00002000; { it's an FPU instruction }
  296. IF_MMX = $00004000; { it's an MMX instruction }
  297. { it's a 3DNow! instruction }
  298. IF_3DNOW = $00008000;
  299. { it's a SSE (KNI, MMX2) instruction }
  300. IF_SSE = $00010000;
  301. { SSE2 instructions }
  302. IF_SSE2 = $00020000;
  303. { SSE3 instructions }
  304. IF_SSE3 = $00040000;
  305. { SSE64 instructions }
  306. IF_SSE64 = $00080000;
  307. { the mask for processor types }
  308. {IF_PMASK = longint($FF000000);}
  309. { the mask for disassembly "prefer" }
  310. {IF_PFMASK = longint($F001FF00);}
  311. { SVM instructions }
  312. IF_SVM = $00100000;
  313. { SSE4 instructions }
  314. IF_SSE4 = $00200000;
  315. { TODO: These flags were added to make x86ins.dat more readable.
  316. Values must be reassigned to make any other use of them. }
  317. IF_SSSE3 = $00200000;
  318. IF_SSE41 = $00200000;
  319. IF_SSE42 = $00200000;
  320. IF_8086 = $00000000; { 8086 instruction }
  321. IF_186 = $01000000; { 186+ instruction }
  322. IF_286 = $02000000; { 286+ instruction }
  323. IF_386 = $03000000; { 386+ instruction }
  324. IF_486 = $04000000; { 486+ instruction }
  325. IF_PENT = $05000000; { Pentium instruction }
  326. IF_P6 = $06000000; { P6 instruction }
  327. IF_KATMAI = $07000000; { Katmai instructions }
  328. { Willamette instructions }
  329. IF_WILLAMETTE = $08000000;
  330. { Prescott instructions }
  331. IF_PRESCOTT = $09000000;
  332. IF_X86_64 = $0a000000;
  333. IF_CYRIX = $0b000000; { Cyrix-specific instruction }
  334. IF_AMD = $0c000000; { AMD-specific instruction }
  335. IF_CENTAUR = $0d000000; { centaur-specific instruction }
  336. { added flags }
  337. IF_PRE = $40000000; { it's a prefix instruction }
  338. IF_PASS2 = $80000000; { if the instruction can change in a second pass }
  339. type
  340. TInsTabCache=array[TasmOp] of longint;
  341. PInsTabCache=^TInsTabCache;
  342. const
  343. {$ifdef x86_64}
  344. InsTab:array[0..instabentries-1] of TInsEntry={$i x8664tab.inc}
  345. {$else x86_64}
  346. InsTab:array[0..instabentries-1] of TInsEntry={$i i386tab.inc}
  347. {$endif x86_64}
  348. var
  349. InsTabCache : PInsTabCache;
  350. const
  351. {$ifdef x86_64}
  352. { Intel style operands ! }
  353. opsize_2_type:array[0..2,topsize] of longint=(
  354. (OT_NONE,
  355. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS16,OT_BITS32,OT_BITS32,OT_BITS64,OT_BITS64,OT_BITS64,
  356. OT_BITS16,OT_BITS32,OT_BITS64,
  357. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  358. OT_BITS64,
  359. OT_NEAR,OT_FAR,OT_SHORT,
  360. OT_NONE,
  361. OT_NONE
  362. ),
  363. (OT_NONE,
  364. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS8,OT_BITS8,OT_BITS16,OT_BITS8,OT_BITS16,OT_BITS32,
  365. OT_BITS16,OT_BITS32,OT_BITS64,
  366. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  367. OT_BITS64,
  368. OT_NEAR,OT_FAR,OT_SHORT,
  369. OT_NONE,
  370. OT_NONE
  371. ),
  372. (OT_NONE,
  373. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_NONE,OT_NONE,OT_NONE,OT_NONE,OT_NONE,OT_NONE,
  374. OT_BITS16,OT_BITS32,OT_BITS64,
  375. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  376. OT_BITS64,
  377. OT_NEAR,OT_FAR,OT_SHORT,
  378. OT_NONE,
  379. OT_NONE
  380. )
  381. );
  382. reg_ot_table : array[tregisterindex] of longint = (
  383. {$i r8664ot.inc}
  384. );
  385. {$else x86_64}
  386. { Intel style operands ! }
  387. opsize_2_type:array[0..2,topsize] of longint=(
  388. (OT_NONE,
  389. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS16,OT_BITS32,OT_BITS32,
  390. OT_BITS16,OT_BITS32,OT_BITS64,
  391. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  392. OT_BITS64,
  393. OT_NEAR,OT_FAR,OT_SHORT,
  394. OT_NONE,
  395. OT_NONE
  396. ),
  397. (OT_NONE,
  398. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS8,OT_BITS8,OT_BITS16,
  399. OT_BITS16,OT_BITS32,OT_BITS64,
  400. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  401. OT_BITS64,
  402. OT_NEAR,OT_FAR,OT_SHORT,
  403. OT_NONE,
  404. OT_NONE
  405. ),
  406. (OT_NONE,
  407. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_NONE,OT_NONE,OT_NONE,
  408. OT_BITS16,OT_BITS32,OT_BITS64,
  409. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  410. OT_BITS64,
  411. OT_NEAR,OT_FAR,OT_SHORT,
  412. OT_NONE,
  413. OT_NONE
  414. )
  415. );
  416. reg_ot_table : array[tregisterindex] of longint = (
  417. {$i r386ot.inc}
  418. );
  419. {$endif x86_64}
  420. { Operation type for spilling code }
  421. type
  422. toperation_type_table=array[tasmop,0..Max_Operands] of topertype;
  423. var
  424. operation_type_table : ^toperation_type_table;
  425. {****************************************************************************
  426. TAI_ALIGN
  427. ****************************************************************************}
  428. constructor tai_align.create(b: byte);
  429. begin
  430. inherited create(b);
  431. reg:=NR_ECX;
  432. end;
  433. constructor tai_align.create_op(b: byte; _op: byte);
  434. begin
  435. inherited create_op(b,_op);
  436. reg:=NR_NO;
  437. end;
  438. function tai_align.calculatefillbuf(var buf : tfillbuffer;executable : boolean):pchar;
  439. const
  440. {$ifdef x86_64}
  441. alignarray:array[0..3] of string[4]=(
  442. #$66#$66#$66#$90,
  443. #$66#$66#$90,
  444. #$66#$90,
  445. #$90
  446. );
  447. {$else x86_64}
  448. alignarray:array[0..5] of string[8]=(
  449. #$8D#$B4#$26#$00#$00#$00#$00,
  450. #$8D#$B6#$00#$00#$00#$00,
  451. #$8D#$74#$26#$00,
  452. #$8D#$76#$00,
  453. #$89#$F6,
  454. #$90);
  455. {$endif x86_64}
  456. var
  457. bufptr : pchar;
  458. j : longint;
  459. localsize: byte;
  460. begin
  461. inherited calculatefillbuf(buf,executable);
  462. if not(use_op) and executable then
  463. begin
  464. bufptr:=pchar(@buf);
  465. { fillsize may still be used afterwards, so don't modify }
  466. { e.g. writebytes(hp.calculatefillbuf(buf)^,hp.fillsize) }
  467. localsize:=fillsize;
  468. while (localsize>0) do
  469. begin
  470. for j:=low(alignarray) to high(alignarray) do
  471. if (localsize>=length(alignarray[j])) then
  472. break;
  473. move(alignarray[j][1],bufptr^,length(alignarray[j]));
  474. inc(bufptr,length(alignarray[j]));
  475. dec(localsize,length(alignarray[j]));
  476. end;
  477. end;
  478. calculatefillbuf:=pchar(@buf);
  479. end;
  480. {*****************************************************************************
  481. Taicpu Constructors
  482. *****************************************************************************}
  483. procedure taicpu.changeopsize(siz:topsize);
  484. begin
  485. opsize:=siz;
  486. end;
  487. procedure taicpu.init(_size : topsize);
  488. begin
  489. { default order is att }
  490. FOperandOrder:=op_att;
  491. segprefix:=NR_NO;
  492. opsize:=_size;
  493. insentry:=nil;
  494. LastInsOffset:=-1;
  495. InsOffset:=0;
  496. InsSize:=0;
  497. end;
  498. constructor taicpu.op_none(op : tasmop);
  499. begin
  500. inherited create(op);
  501. init(S_NO);
  502. end;
  503. constructor taicpu.op_none(op : tasmop;_size : topsize);
  504. begin
  505. inherited create(op);
  506. init(_size);
  507. end;
  508. constructor taicpu.op_reg(op : tasmop;_size : topsize;_op1 : tregister);
  509. begin
  510. inherited create(op);
  511. init(_size);
  512. ops:=1;
  513. loadreg(0,_op1);
  514. end;
  515. constructor taicpu.op_const(op : tasmop;_size : topsize;_op1 : aint);
  516. begin
  517. inherited create(op);
  518. init(_size);
  519. ops:=1;
  520. loadconst(0,_op1);
  521. end;
  522. constructor taicpu.op_ref(op : tasmop;_size : topsize;const _op1 : treference);
  523. begin
  524. inherited create(op);
  525. init(_size);
  526. ops:=1;
  527. loadref(0,_op1);
  528. end;
  529. constructor taicpu.op_reg_reg(op : tasmop;_size : topsize;_op1,_op2 : tregister);
  530. begin
  531. inherited create(op);
  532. init(_size);
  533. ops:=2;
  534. loadreg(0,_op1);
  535. loadreg(1,_op2);
  536. end;
  537. constructor taicpu.op_reg_const(op:tasmop; _size: topsize; _op1: tregister; _op2: aint);
  538. begin
  539. inherited create(op);
  540. init(_size);
  541. ops:=2;
  542. loadreg(0,_op1);
  543. loadconst(1,_op2);
  544. end;
  545. constructor taicpu.op_reg_ref(op : tasmop;_size : topsize;_op1 : tregister;const _op2 : treference);
  546. begin
  547. inherited create(op);
  548. init(_size);
  549. ops:=2;
  550. loadreg(0,_op1);
  551. loadref(1,_op2);
  552. end;
  553. constructor taicpu.op_const_reg(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister);
  554. begin
  555. inherited create(op);
  556. init(_size);
  557. ops:=2;
  558. loadconst(0,_op1);
  559. loadreg(1,_op2);
  560. end;
  561. constructor taicpu.op_const_const(op : tasmop;_size : topsize;_op1,_op2 : aint);
  562. begin
  563. inherited create(op);
  564. init(_size);
  565. ops:=2;
  566. loadconst(0,_op1);
  567. loadconst(1,_op2);
  568. end;
  569. constructor taicpu.op_const_ref(op : tasmop;_size : topsize;_op1 : aint;const _op2 : treference);
  570. begin
  571. inherited create(op);
  572. init(_size);
  573. ops:=2;
  574. loadconst(0,_op1);
  575. loadref(1,_op2);
  576. end;
  577. constructor taicpu.op_ref_reg(op : tasmop;_size : topsize;const _op1 : treference;_op2 : tregister);
  578. begin
  579. inherited create(op);
  580. init(_size);
  581. ops:=2;
  582. loadref(0,_op1);
  583. loadreg(1,_op2);
  584. end;
  585. constructor taicpu.op_reg_reg_reg(op : tasmop;_size : topsize;_op1,_op2,_op3 : tregister);
  586. begin
  587. inherited create(op);
  588. init(_size);
  589. ops:=3;
  590. loadreg(0,_op1);
  591. loadreg(1,_op2);
  592. loadreg(2,_op3);
  593. end;
  594. constructor taicpu.op_const_reg_reg(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister;_op3 : tregister);
  595. begin
  596. inherited create(op);
  597. init(_size);
  598. ops:=3;
  599. loadconst(0,_op1);
  600. loadreg(1,_op2);
  601. loadreg(2,_op3);
  602. end;
  603. constructor taicpu.op_reg_reg_ref(op : tasmop;_size : topsize;_op1,_op2 : tregister;const _op3 : treference);
  604. begin
  605. inherited create(op);
  606. init(_size);
  607. ops:=3;
  608. loadreg(0,_op1);
  609. loadreg(1,_op2);
  610. loadref(2,_op3);
  611. end;
  612. constructor taicpu.op_const_ref_reg(op : tasmop;_size : topsize;_op1 : aint;const _op2 : treference;_op3 : tregister);
  613. begin
  614. inherited create(op);
  615. init(_size);
  616. ops:=3;
  617. loadconst(0,_op1);
  618. loadref(1,_op2);
  619. loadreg(2,_op3);
  620. end;
  621. constructor taicpu.op_const_reg_ref(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister;const _op3 : treference);
  622. begin
  623. inherited create(op);
  624. init(_size);
  625. ops:=3;
  626. loadconst(0,_op1);
  627. loadreg(1,_op2);
  628. loadref(2,_op3);
  629. end;
  630. constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_size : topsize;_op1 : tasmsymbol);
  631. begin
  632. inherited create(op);
  633. init(_size);
  634. condition:=cond;
  635. ops:=1;
  636. loadsymbol(0,_op1,0);
  637. end;
  638. constructor taicpu.op_sym(op : tasmop;_size : topsize;_op1 : tasmsymbol);
  639. begin
  640. inherited create(op);
  641. init(_size);
  642. ops:=1;
  643. loadsymbol(0,_op1,0);
  644. end;
  645. constructor taicpu.op_sym_ofs(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint);
  646. begin
  647. inherited create(op);
  648. init(_size);
  649. ops:=1;
  650. loadsymbol(0,_op1,_op1ofs);
  651. end;
  652. constructor taicpu.op_sym_ofs_reg(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;_op2 : tregister);
  653. begin
  654. inherited create(op);
  655. init(_size);
  656. ops:=2;
  657. loadsymbol(0,_op1,_op1ofs);
  658. loadreg(1,_op2);
  659. end;
  660. constructor taicpu.op_sym_ofs_ref(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  661. begin
  662. inherited create(op);
  663. init(_size);
  664. ops:=2;
  665. loadsymbol(0,_op1,_op1ofs);
  666. loadref(1,_op2);
  667. end;
  668. function taicpu.GetString:string;
  669. var
  670. i : longint;
  671. s : string;
  672. addsize : boolean;
  673. begin
  674. s:='['+std_op2str[opcode];
  675. for i:=0 to ops-1 do
  676. begin
  677. with oper[i]^ do
  678. begin
  679. if i=0 then
  680. s:=s+' '
  681. else
  682. s:=s+',';
  683. { type }
  684. addsize:=false;
  685. if (ot and OT_XMMREG)=OT_XMMREG then
  686. s:=s+'xmmreg'
  687. else
  688. if (ot and OT_MMXREG)=OT_MMXREG then
  689. s:=s+'mmxreg'
  690. else
  691. if (ot and OT_FPUREG)=OT_FPUREG then
  692. s:=s+'fpureg'
  693. else
  694. if (ot and OT_REGISTER)=OT_REGISTER then
  695. begin
  696. s:=s+'reg';
  697. addsize:=true;
  698. end
  699. else
  700. if (ot and OT_IMMEDIATE)=OT_IMMEDIATE then
  701. begin
  702. s:=s+'imm';
  703. addsize:=true;
  704. end
  705. else
  706. if (ot and OT_MEMORY)=OT_MEMORY then
  707. begin
  708. s:=s+'mem';
  709. addsize:=true;
  710. end
  711. else
  712. s:=s+'???';
  713. { size }
  714. if addsize then
  715. begin
  716. if (ot and OT_BITS8)<>0 then
  717. s:=s+'8'
  718. else
  719. if (ot and OT_BITS16)<>0 then
  720. s:=s+'16'
  721. else
  722. if (ot and OT_BITS32)<>0 then
  723. s:=s+'32'
  724. else
  725. if (ot and OT_BITS64)<>0 then
  726. s:=s+'64'
  727. else
  728. s:=s+'??';
  729. { signed }
  730. if (ot and OT_SIGNED)<>0 then
  731. s:=s+'s';
  732. end;
  733. end;
  734. end;
  735. GetString:=s+']';
  736. end;
  737. procedure taicpu.Swapoperands;
  738. var
  739. p : POper;
  740. begin
  741. { Fix the operands which are in AT&T style and we need them in Intel style }
  742. case ops of
  743. 0,1:
  744. ;
  745. 2 : begin
  746. { 0,1 -> 1,0 }
  747. p:=oper[0];
  748. oper[0]:=oper[1];
  749. oper[1]:=p;
  750. end;
  751. 3 : begin
  752. { 0,1,2 -> 2,1,0 }
  753. p:=oper[0];
  754. oper[0]:=oper[2];
  755. oper[2]:=p;
  756. end;
  757. 4 : begin
  758. { 0,1,2,3 -> 3,2,1,0 }
  759. p:=oper[0];
  760. oper[0]:=oper[3];
  761. oper[3]:=p;
  762. p:=oper[1];
  763. oper[1]:=oper[2];
  764. oper[2]:=p;
  765. end;
  766. else
  767. internalerror(201108141);
  768. end;
  769. end;
  770. procedure taicpu.SetOperandOrder(order:TOperandOrder);
  771. begin
  772. if FOperandOrder<>order then
  773. begin
  774. Swapoperands;
  775. FOperandOrder:=order;
  776. end;
  777. end;
  778. procedure taicpu.CheckNonCommutativeOpcodes;
  779. begin
  780. { we need ATT order }
  781. SetOperandOrder(op_att);
  782. if (
  783. (ops=2) and
  784. (oper[0]^.typ=top_reg) and
  785. (oper[1]^.typ=top_reg) and
  786. { if the first is ST and the second is also a register
  787. it is necessarily ST1 .. ST7 }
  788. ((oper[0]^.reg=NR_ST) or
  789. (oper[0]^.reg=NR_ST0))
  790. ) or
  791. { ((ops=1) and
  792. (oper[0]^.typ=top_reg) and
  793. (oper[0]^.reg in [R_ST1..R_ST7])) or}
  794. (ops=0) then
  795. begin
  796. if opcode=A_FSUBR then
  797. opcode:=A_FSUB
  798. else if opcode=A_FSUB then
  799. opcode:=A_FSUBR
  800. else if opcode=A_FDIVR then
  801. opcode:=A_FDIV
  802. else if opcode=A_FDIV then
  803. opcode:=A_FDIVR
  804. else if opcode=A_FSUBRP then
  805. opcode:=A_FSUBP
  806. else if opcode=A_FSUBP then
  807. opcode:=A_FSUBRP
  808. else if opcode=A_FDIVRP then
  809. opcode:=A_FDIVP
  810. else if opcode=A_FDIVP then
  811. opcode:=A_FDIVRP;
  812. end;
  813. if (
  814. (ops=1) and
  815. (oper[0]^.typ=top_reg) and
  816. (getregtype(oper[0]^.reg)=R_FPUREGISTER) and
  817. (oper[0]^.reg<>NR_ST)
  818. ) then
  819. begin
  820. if opcode=A_FSUBRP then
  821. opcode:=A_FSUBP
  822. else if opcode=A_FSUBP then
  823. opcode:=A_FSUBRP
  824. else if opcode=A_FDIVRP then
  825. opcode:=A_FDIVP
  826. else if opcode=A_FDIVP then
  827. opcode:=A_FDIVRP;
  828. end;
  829. end;
  830. {*****************************************************************************
  831. Assembler
  832. *****************************************************************************}
  833. type
  834. ea = packed record
  835. sib_present : boolean;
  836. bytes : byte;
  837. size : byte;
  838. modrm : byte;
  839. sib : byte;
  840. {$ifdef x86_64}
  841. rex : byte;
  842. {$endif x86_64}
  843. end;
  844. procedure taicpu.create_ot(objdata:TObjData);
  845. {
  846. this function will also fix some other fields which only needs to be once
  847. }
  848. var
  849. i,l,relsize : longint;
  850. currsym : TObjSymbol;
  851. begin
  852. if ops=0 then
  853. exit;
  854. { update oper[].ot field }
  855. for i:=0 to ops-1 do
  856. with oper[i]^ do
  857. begin
  858. case typ of
  859. top_reg :
  860. begin
  861. ot:=reg_ot_table[findreg_by_number(reg)];
  862. end;
  863. top_ref :
  864. begin
  865. if (ref^.refaddr=addr_no)
  866. {$ifdef i386}
  867. or (
  868. (ref^.refaddr in [addr_pic]) and
  869. { allow any base for assembler blocks }
  870. ((assigned(current_procinfo) and
  871. (pi_has_assembler_block in current_procinfo.flags) and
  872. (ref^.base<>NR_NO)) or (ref^.base=NR_EBX))
  873. )
  874. {$endif i386}
  875. {$ifdef x86_64}
  876. or (
  877. (ref^.refaddr in [addr_pic,addr_pic_no_got]) and
  878. (ref^.base<>NR_NO)
  879. )
  880. {$endif x86_64}
  881. then
  882. begin
  883. { create ot field }
  884. if (ot and OT_SIZE_MASK)=0 then
  885. ot:=OT_MEMORY_ANY or opsize_2_type[i,opsize]
  886. else
  887. ot:=OT_MEMORY_ANY or (ot and OT_SIZE_MASK);
  888. if (ref^.base=NR_NO) and (ref^.index=NR_NO) then
  889. ot:=ot or OT_MEM_OFFS;
  890. { fix scalefactor }
  891. if (ref^.index=NR_NO) then
  892. ref^.scalefactor:=0
  893. else
  894. if (ref^.scalefactor=0) then
  895. ref^.scalefactor:=1;
  896. end
  897. else
  898. begin
  899. { Jumps use a relative offset which can be 8bit,
  900. for other opcodes we always need to generate the full
  901. 32bit address }
  902. if assigned(objdata) and
  903. is_jmp then
  904. begin
  905. currsym:=objdata.symbolref(ref^.symbol);
  906. l:=ref^.offset;
  907. if assigned(currsym) then
  908. inc(l,currsym.address);
  909. { when it is a forward jump we need to compensate the
  910. offset of the instruction since the previous time,
  911. because the symbol address is then still using the
  912. 'old-style' addressing.
  913. For backwards jumps this is not required because the
  914. address of the symbol is already adjusted to the
  915. new offset }
  916. if (l>InsOffset) and (LastInsOffset<>-1) then
  917. inc(l,InsOffset-LastInsOffset);
  918. { instruction size will then always become 2 (PFV) }
  919. relsize:=(InsOffset+2)-l;
  920. if (relsize>=-128) and (relsize<=127) and
  921. (
  922. not assigned(currsym) or
  923. (currsym.objsection=objdata.currobjsec)
  924. ) then
  925. ot:=OT_IMM8 or OT_SHORT
  926. else
  927. ot:=OT_IMM32 or OT_NEAR;
  928. end
  929. else
  930. ot:=OT_IMM32 or OT_NEAR;
  931. end;
  932. end;
  933. top_local :
  934. begin
  935. if (ot and OT_SIZE_MASK)=0 then
  936. ot:=OT_MEMORY or opsize_2_type[i,opsize]
  937. else
  938. ot:=OT_MEMORY or (ot and OT_SIZE_MASK);
  939. end;
  940. top_const :
  941. begin
  942. { allow 2nd, 3rd or 4th operand being a constant and expect no size for shuf* etc. }
  943. { further, allow AAD and AAM with imm. operand }
  944. if (opsize=S_NO) and not((i in [1,2,3]) or ((i=0) and (opcode in [A_AAD,A_AAM]))) then
  945. message(asmr_e_invalid_opcode_and_operand);
  946. if (opsize<>S_W) and (aint(val)>=-128) and (val<=127) then
  947. ot:=OT_IMM8 or OT_SIGNED
  948. else
  949. ot:=OT_IMMEDIATE or opsize_2_type[i,opsize];
  950. if (val=1) and (i=1) then
  951. ot := ot or OT_ONENESS;
  952. end;
  953. top_none :
  954. begin
  955. { generated when there was an error in the
  956. assembler reader. It never happends when generating
  957. assembler }
  958. end;
  959. else
  960. internalerror(200402261);
  961. end;
  962. end;
  963. end;
  964. function taicpu.InsEnd:longint;
  965. begin
  966. InsEnd:=InsOffset+InsSize;
  967. end;
  968. function taicpu.Matches(p:PInsEntry):boolean;
  969. { * IF_SM stands for Size Match: any operand whose size is not
  970. * explicitly specified by the template is `really' intended to be
  971. * the same size as the first size-specified operand.
  972. * Non-specification is tolerated in the input instruction, but
  973. * _wrong_ specification is not.
  974. *
  975. * IF_SM2 invokes Size Match on only the first _two_ operands, for
  976. * three-operand instructions such as SHLD: it implies that the
  977. * first two operands must match in size, but that the third is
  978. * required to be _unspecified_.
  979. *
  980. * IF_SB invokes Size Byte: operands with unspecified size in the
  981. * template are really bytes, and so no non-byte specification in
  982. * the input instruction will be tolerated. IF_SW similarly invokes
  983. * Size Word, and IF_SD invokes Size Doubleword.
  984. *
  985. * (The default state if neither IF_SM nor IF_SM2 is specified is
  986. * that any operand with unspecified size in the template is
  987. * required to have unspecified size in the instruction too...)
  988. }
  989. var
  990. insot,
  991. currot,
  992. i,j,asize,oprs : longint;
  993. insflags:cardinal;
  994. siz : array[0..max_operands-1] of longint;
  995. begin
  996. result:=false;
  997. { Check the opcode and operands }
  998. if (p^.opcode<>opcode) or (p^.ops<>ops) then
  999. exit;
  1000. for i:=0 to p^.ops-1 do
  1001. begin
  1002. insot:=p^.optypes[i];
  1003. currot:=oper[i]^.ot;
  1004. { Check the operand flags }
  1005. if (insot and (not currot) and OT_NON_SIZE)<>0 then
  1006. exit;
  1007. { Check if the passed operand size matches with one of
  1008. the supported operand sizes }
  1009. if ((insot and OT_SIZE_MASK)<>0) and
  1010. ((insot and currot and OT_SIZE_MASK)<>(currot and OT_SIZE_MASK)) then
  1011. exit;
  1012. end;
  1013. { Check operand sizes }
  1014. insflags:=p^.flags;
  1015. if insflags and IF_SMASK<>0 then
  1016. begin
  1017. { as default an untyped size can get all the sizes, this is different
  1018. from nasm, but else we need to do a lot checking which opcodes want
  1019. size or not with the automatic size generation }
  1020. asize:=-1;
  1021. if (insflags and IF_SB)<>0 then
  1022. asize:=OT_BITS8
  1023. else if (insflags and IF_SW)<>0 then
  1024. asize:=OT_BITS16
  1025. else if (insflags and IF_SD)<>0 then
  1026. asize:=OT_BITS32;
  1027. if (insflags and IF_ARMASK)<>0 then
  1028. begin
  1029. siz[0]:=-1;
  1030. siz[1]:=-1;
  1031. siz[2]:=-1;
  1032. siz[((insflags and IF_ARMASK) shr IF_ARSHIFT)-1]:=asize;
  1033. end
  1034. else
  1035. begin
  1036. siz[0]:=asize;
  1037. siz[1]:=asize;
  1038. siz[2]:=asize;
  1039. end;
  1040. if (insflags and (IF_SM or IF_SM2))<>0 then
  1041. begin
  1042. if (insflags and IF_SM2)<>0 then
  1043. oprs:=2
  1044. else
  1045. oprs:=p^.ops;
  1046. for i:=0 to oprs-1 do
  1047. if ((p^.optypes[i] and OT_SIZE_MASK) <> 0) then
  1048. begin
  1049. for j:=0 to oprs-1 do
  1050. siz[j]:=p^.optypes[i] and OT_SIZE_MASK;
  1051. break;
  1052. end;
  1053. end
  1054. else
  1055. oprs:=2;
  1056. { Check operand sizes }
  1057. for i:=0 to p^.ops-1 do
  1058. begin
  1059. insot:=p^.optypes[i];
  1060. currot:=oper[i]^.ot;
  1061. if ((insot and OT_SIZE_MASK)=0) and
  1062. ((currot and OT_SIZE_MASK and (not siz[i]))<>0) and
  1063. { Immediates can always include smaller size }
  1064. ((currot and OT_IMMEDIATE)=0) and
  1065. (((insot and OT_SIZE_MASK) or siz[i])<(currot and OT_SIZE_MASK)) then
  1066. exit;
  1067. end;
  1068. end;
  1069. result:=true;
  1070. end;
  1071. procedure taicpu.ResetPass1;
  1072. begin
  1073. { we need to reset everything here, because the choosen insentry
  1074. can be invalid for a new situation where the previously optimized
  1075. insentry is not correct }
  1076. InsEntry:=nil;
  1077. InsSize:=0;
  1078. LastInsOffset:=-1;
  1079. end;
  1080. procedure taicpu.ResetPass2;
  1081. begin
  1082. { we are here in a second pass, check if the instruction can be optimized }
  1083. if assigned(InsEntry) and
  1084. ((InsEntry^.flags and IF_PASS2)<>0) then
  1085. begin
  1086. InsEntry:=nil;
  1087. InsSize:=0;
  1088. end;
  1089. LastInsOffset:=-1;
  1090. end;
  1091. function taicpu.CheckIfValid:boolean;
  1092. begin
  1093. result:=FindInsEntry(nil);
  1094. end;
  1095. function taicpu.FindInsentry(objdata:TObjData):boolean;
  1096. var
  1097. i : longint;
  1098. begin
  1099. result:=false;
  1100. { Things which may only be done once, not when a second pass is done to
  1101. optimize }
  1102. if (Insentry=nil) or ((InsEntry^.flags and IF_PASS2)<>0) then
  1103. begin
  1104. current_filepos:=fileinfo;
  1105. { We need intel style operands }
  1106. SetOperandOrder(op_intel);
  1107. { create the .ot fields }
  1108. create_ot(objdata);
  1109. { set the file postion }
  1110. end
  1111. else
  1112. begin
  1113. { we've already an insentry so it's valid }
  1114. result:=true;
  1115. exit;
  1116. end;
  1117. { Lookup opcode in the table }
  1118. InsSize:=-1;
  1119. i:=instabcache^[opcode];
  1120. if i=-1 then
  1121. begin
  1122. Message1(asmw_e_opcode_not_in_table,gas_op2str[opcode]);
  1123. exit;
  1124. end;
  1125. insentry:=@instab[i];
  1126. while (insentry^.opcode=opcode) do
  1127. begin
  1128. if matches(insentry) then
  1129. begin
  1130. result:=true;
  1131. exit;
  1132. end;
  1133. inc(insentry);
  1134. end;
  1135. Message1(asmw_e_invalid_opcode_and_operands,GetString);
  1136. { No instruction found, set insentry to nil and inssize to -1 }
  1137. insentry:=nil;
  1138. inssize:=-1;
  1139. end;
  1140. function taicpu.Pass1(objdata:TObjData):longint;
  1141. begin
  1142. Pass1:=0;
  1143. { Save the old offset and set the new offset }
  1144. InsOffset:=ObjData.CurrObjSec.Size;
  1145. { Error? }
  1146. if (Insentry=nil) and (InsSize=-1) then
  1147. exit;
  1148. { set the file postion }
  1149. current_filepos:=fileinfo;
  1150. { Get InsEntry }
  1151. if FindInsEntry(ObjData) then
  1152. begin
  1153. { Calculate instruction size }
  1154. InsSize:=calcsize(insentry);
  1155. if segprefix<>NR_NO then
  1156. inc(InsSize);
  1157. { Fix opsize if size if forced }
  1158. if (insentry^.flags and (IF_SB or IF_SW or IF_SD))<>0 then
  1159. begin
  1160. if (insentry^.flags and IF_ARMASK)=0 then
  1161. begin
  1162. if (insentry^.flags and IF_SB)<>0 then
  1163. begin
  1164. if opsize=S_NO then
  1165. opsize:=S_B;
  1166. end
  1167. else if (insentry^.flags and IF_SW)<>0 then
  1168. begin
  1169. if opsize=S_NO then
  1170. opsize:=S_W;
  1171. end
  1172. else if (insentry^.flags and IF_SD)<>0 then
  1173. begin
  1174. if opsize=S_NO then
  1175. opsize:=S_L;
  1176. end;
  1177. end;
  1178. end;
  1179. LastInsOffset:=InsOffset;
  1180. Pass1:=InsSize;
  1181. exit;
  1182. end;
  1183. LastInsOffset:=-1;
  1184. end;
  1185. const
  1186. segprefixes: array[NR_CS..NR_GS] of Byte=(
  1187. //cs ds es ss fs gs
  1188. $2E, $3E, $26, $36, $64, $65
  1189. );
  1190. procedure taicpu.Pass2(objdata:TObjData);
  1191. begin
  1192. { error in pass1 ? }
  1193. if insentry=nil then
  1194. exit;
  1195. current_filepos:=fileinfo;
  1196. { Segment override }
  1197. if (segprefix>=NR_CS) and (segprefix<=NR_GS) then
  1198. begin
  1199. objdata.writebytes(segprefixes[segprefix],1);
  1200. { fix the offset for GenNode }
  1201. inc(InsOffset);
  1202. end
  1203. else if segprefix<>NR_NO then
  1204. InternalError(201001071);
  1205. { Generate the instruction }
  1206. GenCode(objdata);
  1207. end;
  1208. function taicpu.needaddrprefix(opidx:byte):boolean;
  1209. begin
  1210. result:=(oper[opidx]^.typ=top_ref) and
  1211. (oper[opidx]^.ref^.refaddr=addr_no) and
  1212. {$ifdef x86_64}
  1213. (oper[opidx]^.ref^.base<>NR_RIP) and
  1214. {$endif x86_64}
  1215. (
  1216. (
  1217. (oper[opidx]^.ref^.index<>NR_NO) and
  1218. (getsubreg(oper[opidx]^.ref^.index)<>R_SUBADDR)
  1219. ) or
  1220. (
  1221. (oper[opidx]^.ref^.base<>NR_NO) and
  1222. (getsubreg(oper[opidx]^.ref^.base)<>R_SUBADDR)
  1223. )
  1224. );
  1225. end;
  1226. function regval(r:Tregister):byte;
  1227. const
  1228. {$ifdef x86_64}
  1229. opcode_table:array[tregisterindex] of tregisterindex = (
  1230. {$i r8664op.inc}
  1231. );
  1232. {$else x86_64}
  1233. opcode_table:array[tregisterindex] of tregisterindex = (
  1234. {$i r386op.inc}
  1235. );
  1236. {$endif x86_64}
  1237. var
  1238. regidx : tregisterindex;
  1239. begin
  1240. regidx:=findreg_by_number(r);
  1241. if regidx<>0 then
  1242. result:=opcode_table[regidx]
  1243. else
  1244. begin
  1245. Message1(asmw_e_invalid_register,generic_regname(r));
  1246. result:=0;
  1247. end;
  1248. end;
  1249. {$ifdef x86_64}
  1250. function rexbits(r: tregister): byte;
  1251. begin
  1252. result:=0;
  1253. case getregtype(r) of
  1254. R_INTREGISTER:
  1255. if (getsupreg(r)>=RS_R8) then
  1256. { Either B,X or R bits can be set, depending on register role in instruction.
  1257. Set all three bits here, caller will discard unnecessary ones. }
  1258. result:=result or $47
  1259. else if (getsubreg(r)=R_SUBL) and
  1260. (getsupreg(r) in [RS_RDI,RS_RSI,RS_RBP,RS_RSP]) then
  1261. result:=result or $40
  1262. else if (getsubreg(r)=R_SUBH) then
  1263. { Not an actual REX bit, used to detect incompatible usage of
  1264. AH/BH/CH/DH }
  1265. result:=result or $80;
  1266. R_MMREGISTER:
  1267. if getsupreg(r)>=RS_XMM8 then
  1268. result:=result or $47;
  1269. end;
  1270. end;
  1271. function process_ea(const input:toper;out output:ea;rfield:longint):boolean;
  1272. var
  1273. sym : tasmsymbol;
  1274. md,s,rv : byte;
  1275. base,index,scalefactor,
  1276. o : longint;
  1277. ir,br : Tregister;
  1278. isub,bsub : tsubregister;
  1279. begin
  1280. process_ea:=false;
  1281. fillchar(output,sizeof(output),0);
  1282. {Register ?}
  1283. if (input.typ=top_reg) then
  1284. begin
  1285. rv:=regval(input.reg);
  1286. output.modrm:=$c0 or (rfield shl 3) or rv;
  1287. output.size:=1;
  1288. output.rex:=output.rex or (rexbits(input.reg) and $F1);
  1289. process_ea:=true;
  1290. exit;
  1291. end;
  1292. {No register, so memory reference.}
  1293. if input.typ<>top_ref then
  1294. internalerror(200409263);
  1295. ir:=input.ref^.index;
  1296. br:=input.ref^.base;
  1297. isub:=getsubreg(ir);
  1298. bsub:=getsubreg(br);
  1299. s:=input.ref^.scalefactor;
  1300. o:=input.ref^.offset;
  1301. sym:=input.ref^.symbol;
  1302. if ((ir<>NR_NO) and (getregtype(ir)<>R_INTREGISTER)) or
  1303. ((br<>NR_NO) and (br<>NR_RIP) and (getregtype(br)<>R_INTREGISTER)) then
  1304. internalerror(200301081);
  1305. { it's direct address }
  1306. if (br=NR_NO) and (ir=NR_NO) then
  1307. begin
  1308. output.sib_present:=true;
  1309. output.bytes:=4;
  1310. output.modrm:=4 or (rfield shl 3);
  1311. output.sib:=$25;
  1312. end
  1313. else if (br=NR_RIP) and (ir=NR_NO) then
  1314. begin
  1315. { rip based }
  1316. output.sib_present:=false;
  1317. output.bytes:=4;
  1318. output.modrm:=5 or (rfield shl 3);
  1319. end
  1320. else
  1321. { it's an indirection }
  1322. begin
  1323. { 16 bit or 32 bit address? }
  1324. if ((ir<>NR_NO) and (isub<>R_SUBADDR)) or
  1325. ((br<>NR_NO) and (bsub<>R_SUBADDR)) then
  1326. message(asmw_e_16bit_32bit_not_supported);
  1327. { wrong, for various reasons }
  1328. if (ir=NR_ESP) or ((s<>1) and (s<>2) and (s<>4) and (s<>8) and (ir<>NR_NO)) then
  1329. exit;
  1330. output.rex:=output.rex or (rexbits(br) and $F1) or (rexbits(ir) and $F2);
  1331. process_ea:=true;
  1332. { base }
  1333. case br of
  1334. NR_R8,
  1335. NR_RAX : base:=0;
  1336. NR_R9,
  1337. NR_RCX : base:=1;
  1338. NR_R10,
  1339. NR_RDX : base:=2;
  1340. NR_R11,
  1341. NR_RBX : base:=3;
  1342. NR_R12,
  1343. NR_RSP : base:=4;
  1344. NR_R13,
  1345. NR_NO,
  1346. NR_RBP : base:=5;
  1347. NR_R14,
  1348. NR_RSI : base:=6;
  1349. NR_R15,
  1350. NR_RDI : base:=7;
  1351. else
  1352. exit;
  1353. end;
  1354. { index }
  1355. case ir of
  1356. NR_R8,
  1357. NR_RAX : index:=0;
  1358. NR_R9,
  1359. NR_RCX : index:=1;
  1360. NR_R10,
  1361. NR_RDX : index:=2;
  1362. NR_R11,
  1363. NR_RBX : index:=3;
  1364. NR_R12,
  1365. NR_NO : index:=4;
  1366. NR_R13,
  1367. NR_RBP : index:=5;
  1368. NR_R14,
  1369. NR_RSI : index:=6;
  1370. NR_R15,
  1371. NR_RDI : index:=7;
  1372. else
  1373. exit;
  1374. end;
  1375. case s of
  1376. 0,
  1377. 1 : scalefactor:=0;
  1378. 2 : scalefactor:=1;
  1379. 4 : scalefactor:=2;
  1380. 8 : scalefactor:=3;
  1381. else
  1382. exit;
  1383. end;
  1384. { If rbp or r13 is used we must always include an offset }
  1385. if (br=NR_NO) or
  1386. ((br<>NR_RBP) and (br<>NR_R13) and (o=0) and (sym=nil)) then
  1387. md:=0
  1388. else
  1389. if ((o>=-128) and (o<=127) and (sym=nil)) then
  1390. md:=1
  1391. else
  1392. md:=2;
  1393. if (br=NR_NO) or (md=2) then
  1394. output.bytes:=4
  1395. else
  1396. output.bytes:=md;
  1397. { SIB needed ? }
  1398. if (ir=NR_NO) and (br<>NR_RSP) and (br<>NR_R12) then
  1399. begin
  1400. output.sib_present:=false;
  1401. output.modrm:=(md shl 6) or (rfield shl 3) or base;
  1402. end
  1403. else
  1404. begin
  1405. output.sib_present:=true;
  1406. output.modrm:=(md shl 6) or (rfield shl 3) or 4;
  1407. output.sib:=(scalefactor shl 6) or (index shl 3) or base;
  1408. end;
  1409. end;
  1410. output.size:=1+ord(output.sib_present)+output.bytes;
  1411. process_ea:=true;
  1412. end;
  1413. {$else x86_64}
  1414. function process_ea(const input:toper;out output:ea;rfield:longint):boolean;
  1415. var
  1416. sym : tasmsymbol;
  1417. md,s,rv : byte;
  1418. base,index,scalefactor,
  1419. o : longint;
  1420. ir,br : Tregister;
  1421. isub,bsub : tsubregister;
  1422. begin
  1423. process_ea:=false;
  1424. fillchar(output,sizeof(output),0);
  1425. {Register ?}
  1426. if (input.typ=top_reg) then
  1427. begin
  1428. rv:=regval(input.reg);
  1429. output.modrm:=$c0 or (rfield shl 3) or rv;
  1430. output.size:=1;
  1431. process_ea:=true;
  1432. exit;
  1433. end;
  1434. {No register, so memory reference.}
  1435. if (input.typ<>top_ref) then
  1436. internalerror(200409262);
  1437. if ((input.ref^.index<>NR_NO) and (getregtype(input.ref^.index)<>R_INTREGISTER)) or
  1438. ((input.ref^.base<>NR_NO) and (getregtype(input.ref^.base)<>R_INTREGISTER)) then
  1439. internalerror(200301081);
  1440. ir:=input.ref^.index;
  1441. br:=input.ref^.base;
  1442. isub:=getsubreg(ir);
  1443. bsub:=getsubreg(br);
  1444. s:=input.ref^.scalefactor;
  1445. o:=input.ref^.offset;
  1446. sym:=input.ref^.symbol;
  1447. { it's direct address }
  1448. if (br=NR_NO) and (ir=NR_NO) then
  1449. begin
  1450. { it's a pure offset }
  1451. output.sib_present:=false;
  1452. output.bytes:=4;
  1453. output.modrm:=5 or (rfield shl 3);
  1454. end
  1455. else
  1456. { it's an indirection }
  1457. begin
  1458. { 16 bit address? }
  1459. if ((ir<>NR_NO) and (isub<>R_SUBADDR)) or
  1460. ((br<>NR_NO) and (bsub<>R_SUBADDR)) then
  1461. message(asmw_e_16bit_not_supported);
  1462. {$ifdef OPTEA}
  1463. { make single reg base }
  1464. if (br=NR_NO) and (s=1) then
  1465. begin
  1466. br:=ir;
  1467. ir:=NR_NO;
  1468. end;
  1469. { convert [3,5,9]*EAX to EAX+[2,4,8]*EAX }
  1470. if (br=NR_NO) and
  1471. (((s=2) and (ir<>NR_ESP)) or
  1472. (s=3) or (s=5) or (s=9)) then
  1473. begin
  1474. br:=ir;
  1475. dec(s);
  1476. end;
  1477. { swap ESP into base if scalefactor is 1 }
  1478. if (s=1) and (ir=NR_ESP) then
  1479. begin
  1480. ir:=br;
  1481. br:=NR_ESP;
  1482. end;
  1483. {$endif OPTEA}
  1484. { wrong, for various reasons }
  1485. if (ir=NR_ESP) or ((s<>1) and (s<>2) and (s<>4) and (s<>8) and (ir<>NR_NO)) then
  1486. exit;
  1487. { base }
  1488. case br of
  1489. NR_EAX : base:=0;
  1490. NR_ECX : base:=1;
  1491. NR_EDX : base:=2;
  1492. NR_EBX : base:=3;
  1493. NR_ESP : base:=4;
  1494. NR_NO,
  1495. NR_EBP : base:=5;
  1496. NR_ESI : base:=6;
  1497. NR_EDI : base:=7;
  1498. else
  1499. exit;
  1500. end;
  1501. { index }
  1502. case ir of
  1503. NR_EAX : index:=0;
  1504. NR_ECX : index:=1;
  1505. NR_EDX : index:=2;
  1506. NR_EBX : index:=3;
  1507. NR_NO : index:=4;
  1508. NR_EBP : index:=5;
  1509. NR_ESI : index:=6;
  1510. NR_EDI : index:=7;
  1511. else
  1512. exit;
  1513. end;
  1514. case s of
  1515. 0,
  1516. 1 : scalefactor:=0;
  1517. 2 : scalefactor:=1;
  1518. 4 : scalefactor:=2;
  1519. 8 : scalefactor:=3;
  1520. else
  1521. exit;
  1522. end;
  1523. if (br=NR_NO) or
  1524. ((br<>NR_EBP) and (o=0) and (sym=nil)) then
  1525. md:=0
  1526. else
  1527. if ((o>=-128) and (o<=127) and (sym=nil)) then
  1528. md:=1
  1529. else
  1530. md:=2;
  1531. if (br=NR_NO) or (md=2) then
  1532. output.bytes:=4
  1533. else
  1534. output.bytes:=md;
  1535. { SIB needed ? }
  1536. if (ir=NR_NO) and (br<>NR_ESP) then
  1537. begin
  1538. output.sib_present:=false;
  1539. output.modrm:=(longint(md) shl 6) or (rfield shl 3) or base;
  1540. end
  1541. else
  1542. begin
  1543. output.sib_present:=true;
  1544. output.modrm:=(longint(md) shl 6) or (rfield shl 3) or 4;
  1545. output.sib:=(scalefactor shl 6) or (index shl 3) or base;
  1546. end;
  1547. end;
  1548. if output.sib_present then
  1549. output.size:=2+output.bytes
  1550. else
  1551. output.size:=1+output.bytes;
  1552. process_ea:=true;
  1553. end;
  1554. {$endif x86_64}
  1555. function taicpu.calcsize(p:PInsEntry):shortint;
  1556. var
  1557. codes : pchar;
  1558. c : byte;
  1559. len : shortint;
  1560. ea_data : ea;
  1561. omit_rexw : boolean;
  1562. begin
  1563. len:=0;
  1564. codes:=@p^.code[0];
  1565. {$ifdef x86_64}
  1566. rex:=0;
  1567. omit_rexw:=false;
  1568. {$endif x86_64}
  1569. repeat
  1570. c:=ord(codes^);
  1571. inc(codes);
  1572. case c of
  1573. 0 :
  1574. break;
  1575. 1,2,3 :
  1576. begin
  1577. inc(codes,c);
  1578. inc(len,c);
  1579. end;
  1580. 8,9,10 :
  1581. begin
  1582. {$ifdef x86_64}
  1583. rex:=rex or (rexbits(oper[c-8]^.reg) and $F1);
  1584. {$endif x86_64}
  1585. inc(codes);
  1586. inc(len);
  1587. end;
  1588. 11 :
  1589. begin
  1590. inc(codes);
  1591. inc(len);
  1592. end;
  1593. 4,5,6,7 :
  1594. begin
  1595. if opsize=S_W then
  1596. inc(len,2)
  1597. else
  1598. inc(len);
  1599. end;
  1600. 12,13,14,
  1601. 16,17,18,
  1602. 20,21,22,23,
  1603. 40,41,42 :
  1604. inc(len);
  1605. 24,25,26,
  1606. 31,
  1607. 48,49,50 :
  1608. inc(len,2);
  1609. 28,29,30:
  1610. begin
  1611. if opsize=S_Q then
  1612. inc(len,8)
  1613. else
  1614. inc(len,4);
  1615. end;
  1616. 36,37,38:
  1617. inc(len,sizeof(pint));
  1618. 44,45,46:
  1619. inc(len,8);
  1620. 32,33,34,
  1621. 52,53,54,
  1622. 56,57,58,
  1623. 172,173,174 :
  1624. inc(len,4);
  1625. 208,209,210 :
  1626. begin
  1627. case (oper[c-208]^.ot and OT_SIZE_MASK) of
  1628. OT_BITS16:
  1629. inc(len);
  1630. {$ifdef x86_64}
  1631. OT_BITS64:
  1632. begin
  1633. rex:=rex or $48;
  1634. end;
  1635. {$endif x86_64}
  1636. end;
  1637. end;
  1638. 200 :
  1639. {$ifndef x86_64}
  1640. inc(len);
  1641. {$else x86_64}
  1642. { every insentry with code 0310 must be marked with NOX86_64 }
  1643. InternalError(2011051301);
  1644. {$endif x86_64}
  1645. 201 :
  1646. {$ifdef x86_64}
  1647. inc(len)
  1648. {$endif x86_64}
  1649. ;
  1650. 212 :
  1651. inc(len);
  1652. 214 :
  1653. begin
  1654. {$ifdef x86_64}
  1655. rex:=rex or $48;
  1656. {$endif x86_64}
  1657. end;
  1658. 202,
  1659. 211,
  1660. 213,
  1661. 215,
  1662. 217,218: ;
  1663. 219,220,241 :
  1664. inc(len);
  1665. 221:
  1666. {$ifdef x86_64}
  1667. omit_rexw:=true
  1668. {$endif x86_64}
  1669. ;
  1670. 64..151 :
  1671. begin
  1672. {$ifdef x86_64}
  1673. if (c<127) then
  1674. begin
  1675. if (oper[c and 7]^.typ=top_reg) then
  1676. begin
  1677. rex:=rex or (rexbits(oper[c and 7]^.reg) and $F4);
  1678. end;
  1679. end;
  1680. {$endif x86_64}
  1681. if not process_ea(oper[(c shr 3) and 7]^, ea_data, 0) then
  1682. Message(asmw_e_invalid_effective_address)
  1683. else
  1684. inc(len,ea_data.size);
  1685. {$ifdef x86_64}
  1686. rex:=rex or ea_data.rex;
  1687. {$endif x86_64}
  1688. end;
  1689. else
  1690. InternalError(200603141);
  1691. end;
  1692. until false;
  1693. {$ifdef x86_64}
  1694. if ((rex and $80)<>0) and ((rex and $4F)<>0) then
  1695. Message(asmw_e_bad_reg_with_rex);
  1696. rex:=rex and $4F; { reset extra bits in upper nibble }
  1697. if omit_rexw then
  1698. begin
  1699. if rex=$48 then { remove rex entirely? }
  1700. rex:=0
  1701. else
  1702. rex:=rex and $F7;
  1703. end;
  1704. if rex<>0 then
  1705. Inc(len);
  1706. {$endif}
  1707. calcsize:=len;
  1708. end;
  1709. procedure taicpu.GenCode(objdata:TObjData);
  1710. {
  1711. * the actual codes (C syntax, i.e. octal):
  1712. * \0 - terminates the code. (Unless it's a literal of course.)
  1713. * \1, \2, \3 - that many literal bytes follow in the code stream
  1714. * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
  1715. * (POP is never used for CS) depending on operand 0
  1716. * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
  1717. * on operand 0
  1718. * \10, \11, \12 - a literal byte follows in the code stream, to be added
  1719. * to the register value of operand 0, 1 or 2
  1720. * \13 - a literal byte follows in the code stream, to be added
  1721. * to the condition code value of the instruction.
  1722. * \14, \15, \16 - a signed byte immediate operand, from operand 0, 1 or 2
  1723. * \20, \21, \22 - a byte immediate operand, from operand 0, 1 or 2
  1724. * \24, \25, \26, \27 - an unsigned byte immediate operand, from operand 0, 1, 2 or 3
  1725. * \30, \31, \32 - a word immediate operand, from operand 0, 1 or 2
  1726. * \34, \35, \36 - select between \3[012] and \4[012] depending on 16/32 bit
  1727. * assembly mode or the address-size override on the operand
  1728. * \37 - a word constant, from the _segment_ part of operand 0
  1729. * \40, \41, \42 - a long immediate operand, from operand 0, 1 or 2
  1730. * \44, \45, \46 - select between \3[012], \4[012] or \5[456] depending
  1731. on the address size of instruction
  1732. * \50, \51, \52 - a byte relative operand, from operand 0, 1 or 2
  1733. * \54, \55, \56 - a qword immediate, from operand 0, 1 or 2
  1734. * \60, \61, \62 - a word relative operand, from operand 0, 1 or 2
  1735. * \64, \65, \66 - select between \6[012] and \7[012] depending on 16/32 bit
  1736. * assembly mode or the address-size override on the operand
  1737. * \70, \71, \72 - a long relative operand, from operand 0, 1 or 2
  1738. * \1ab - a ModRM, calculated on EA in operand a, with the spare
  1739. * field the register value of operand b.
  1740. * \2ab - a ModRM, calculated on EA in operand a, with the spare
  1741. * field equal to digit b.
  1742. * \254,\255,\256 - a signed 32-bit immediate to be extended to 64 bits
  1743. * \300,\301,\302 - might be an 0x67, depending on the address size of
  1744. * the memory reference in operand x.
  1745. * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
  1746. * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
  1747. * \312 - (disassembler only) invalid with non-default address size.
  1748. * \320,\321,\322 - might be an 0x66 or 0x48 byte, depending on the operand
  1749. * size of operand x.
  1750. * \324 - indicates fixed 16-bit operand size, i.e. optional 0x66.
  1751. * \325 - indicates fixed 32-bit operand size, i.e. optional 0x66.
  1752. * \326 - indicates fixed 64-bit operand size, i.e. optional 0x48.
  1753. * \327 - indicates that this instruction is only valid when the
  1754. * operand size is the default (instruction to disassembler,
  1755. * generates no code in the assembler)
  1756. * \331 - instruction not valid with REP prefix. Hint for
  1757. * disassembler only; for SSE instructions.
  1758. * \332 - disassemble a rep (0xF3 byte) prefix as repe not rep.
  1759. * \333 - 0xF3 prefix for SSE instructions
  1760. * \334 - 0xF2 prefix for SSE instructions
  1761. * \335 - Indicates 64-bit operand size with REX.W not necessary
  1762. * \361 - 0x66 prefix for SSE instructions
  1763. }
  1764. var
  1765. currval : aint;
  1766. currsym : tobjsymbol;
  1767. currrelreloc,
  1768. currabsreloc,
  1769. currabsreloc32 : TObjRelocationType;
  1770. {$ifdef x86_64}
  1771. rexwritten : boolean;
  1772. {$endif x86_64}
  1773. procedure getvalsym(opidx:longint);
  1774. begin
  1775. case oper[opidx]^.typ of
  1776. top_ref :
  1777. begin
  1778. currval:=oper[opidx]^.ref^.offset;
  1779. currsym:=ObjData.symbolref(oper[opidx]^.ref^.symbol);
  1780. {$ifdef i386}
  1781. if (oper[opidx]^.ref^.refaddr=addr_pic) and
  1782. (tf_pic_uses_got in target_info.flags) then
  1783. begin
  1784. currrelreloc:=RELOC_PLT32;
  1785. currabsreloc:=RELOC_GOT32;
  1786. currabsreloc32:=RELOC_GOT32;
  1787. end
  1788. else
  1789. {$endif i386}
  1790. {$ifdef x86_64}
  1791. if oper[opidx]^.ref^.refaddr=addr_pic then
  1792. begin
  1793. currrelreloc:=RELOC_PLT32;
  1794. currabsreloc:=RELOC_GOTPCREL;
  1795. currabsreloc32:=RELOC_GOTPCREL;
  1796. end
  1797. else if oper[opidx]^.ref^.refaddr=addr_pic_no_got then
  1798. begin
  1799. currrelreloc:=RELOC_RELATIVE;
  1800. currabsreloc:=RELOC_RELATIVE;
  1801. currabsreloc32:=RELOC_RELATIVE;
  1802. end
  1803. else
  1804. {$endif x86_64}
  1805. begin
  1806. currrelreloc:=RELOC_RELATIVE;
  1807. currabsreloc:=RELOC_ABSOLUTE;
  1808. currabsreloc32:=RELOC_ABSOLUTE32;
  1809. end;
  1810. end;
  1811. top_const :
  1812. begin
  1813. currval:=aint(oper[opidx]^.val);
  1814. currsym:=nil;
  1815. currabsreloc:=RELOC_ABSOLUTE;
  1816. currabsreloc32:=RELOC_ABSOLUTE32;
  1817. end;
  1818. else
  1819. Message(asmw_e_immediate_or_reference_expected);
  1820. end;
  1821. end;
  1822. {$ifdef x86_64}
  1823. procedure maybewriterex;
  1824. begin
  1825. if (rex<>0) and not(rexwritten) then
  1826. begin
  1827. rexwritten:=true;
  1828. objdata.writebytes(rex,1);
  1829. end;
  1830. end;
  1831. {$endif x86_64}
  1832. procedure objdata_writereloc(Data:aint;len:aword;p:TObjSymbol;Reloctype:TObjRelocationType);
  1833. begin
  1834. {$ifdef i386}
  1835. { Special case of '_GLOBAL_OFFSET_TABLE_'
  1836. which needs a special relocation type R_386_GOTPC }
  1837. if assigned (p) and
  1838. (p.name='_GLOBAL_OFFSET_TABLE_') and
  1839. (tf_pic_uses_got in target_info.flags) then
  1840. begin
  1841. { nothing else than a 4 byte relocation should occur
  1842. for GOT }
  1843. if len<>4 then
  1844. Message1(asmw_e_invalid_opcode_and_operands,GetString);
  1845. Reloctype:=RELOC_GOTPC;
  1846. { We need to add the offset of the relocation
  1847. of _GLOBAL_OFFSET_TABLE symbol within
  1848. the current instruction }
  1849. inc(data,objdata.currobjsec.size-insoffset);
  1850. end;
  1851. {$endif i386}
  1852. objdata.writereloc(data,len,p,Reloctype);
  1853. end;
  1854. const
  1855. CondVal:array[TAsmCond] of byte=($0,
  1856. $7, $3, $2, $6, $2, $4, $F, $D, $C, $E, $6, $2,
  1857. $3, $7, $3, $5, $E, $C, $D, $F, $1, $B, $9, $5,
  1858. $0, $A, $A, $B, $8, $4);
  1859. var
  1860. c : byte;
  1861. pb : pbyte;
  1862. codes : pchar;
  1863. bytes : array[0..3] of byte;
  1864. rfield,
  1865. data,s,opidx : longint;
  1866. ea_data : ea;
  1867. relsym : TObjSymbol;
  1868. begin
  1869. { safety check }
  1870. if objdata.currobjsec.size<>longword(insoffset) then
  1871. internalerror(200130121);
  1872. { load data to write }
  1873. codes:=insentry^.code;
  1874. {$ifdef x86_64}
  1875. rexwritten:=false;
  1876. {$endif x86_64}
  1877. { Force word push/pop for registers }
  1878. if (opsize=S_W) and ((codes[0]=#4) or (codes[0]=#6) or
  1879. ((codes[0]=#1) and ((codes[2]=#5) or (codes[2]=#7)))) then
  1880. begin
  1881. bytes[0]:=$66;
  1882. objdata.writebytes(bytes,1);
  1883. end;
  1884. repeat
  1885. c:=ord(codes^);
  1886. inc(codes);
  1887. case c of
  1888. 0 :
  1889. break;
  1890. 1,2,3 :
  1891. begin
  1892. {$ifdef x86_64}
  1893. maybewriterex;
  1894. {$endif x86_64}
  1895. objdata.writebytes(codes^,c);
  1896. inc(codes,c);
  1897. end;
  1898. 4,6 :
  1899. begin
  1900. case oper[0]^.reg of
  1901. NR_CS:
  1902. bytes[0]:=$e;
  1903. NR_NO,
  1904. NR_DS:
  1905. bytes[0]:=$1e;
  1906. NR_ES:
  1907. bytes[0]:=$6;
  1908. NR_SS:
  1909. bytes[0]:=$16;
  1910. else
  1911. internalerror(777004);
  1912. end;
  1913. if c=4 then
  1914. inc(bytes[0]);
  1915. objdata.writebytes(bytes,1);
  1916. end;
  1917. 5,7 :
  1918. begin
  1919. case oper[0]^.reg of
  1920. NR_FS:
  1921. bytes[0]:=$a0;
  1922. NR_GS:
  1923. bytes[0]:=$a8;
  1924. else
  1925. internalerror(777005);
  1926. end;
  1927. if c=5 then
  1928. inc(bytes[0]);
  1929. objdata.writebytes(bytes,1);
  1930. end;
  1931. 8,9,10 :
  1932. begin
  1933. {$ifdef x86_64}
  1934. maybewriterex;
  1935. {$endif x86_64}
  1936. bytes[0]:=ord(codes^)+regval(oper[c-8]^.reg);
  1937. inc(codes);
  1938. objdata.writebytes(bytes,1);
  1939. end;
  1940. 11 :
  1941. begin
  1942. bytes[0]:=ord(codes^)+condval[condition];
  1943. inc(codes);
  1944. objdata.writebytes(bytes,1);
  1945. end;
  1946. 12,13,14 :
  1947. begin
  1948. getvalsym(c-12);
  1949. if (currval<-128) or (currval>127) then
  1950. Message2(asmw_e_value_exceeds_bounds,'signed byte',tostr(currval));
  1951. if assigned(currsym) then
  1952. objdata_writereloc(currval,1,currsym,currabsreloc)
  1953. else
  1954. objdata.writebytes(currval,1);
  1955. end;
  1956. 16,17,18 :
  1957. begin
  1958. getvalsym(c-16);
  1959. if (currval<-256) or (currval>255) then
  1960. Message2(asmw_e_value_exceeds_bounds,'byte',tostr(currval));
  1961. if assigned(currsym) then
  1962. objdata_writereloc(currval,1,currsym,currabsreloc)
  1963. else
  1964. objdata.writebytes(currval,1);
  1965. end;
  1966. 20,21,22,23 :
  1967. begin
  1968. getvalsym(c-20);
  1969. if (currval<0) or (currval>255) then
  1970. Message2(asmw_e_value_exceeds_bounds,'unsigned byte',tostr(currval));
  1971. if assigned(currsym) then
  1972. objdata_writereloc(currval,1,currsym,currabsreloc)
  1973. else
  1974. objdata.writebytes(currval,1);
  1975. end;
  1976. 24,25,26 : // 030..032
  1977. begin
  1978. getvalsym(c-24);
  1979. if (currval<-65536) or (currval>65535) then
  1980. Message2(asmw_e_value_exceeds_bounds,'word',tostr(currval));
  1981. if assigned(currsym) then
  1982. objdata_writereloc(currval,2,currsym,currabsreloc)
  1983. else
  1984. objdata.writebytes(currval,2);
  1985. end;
  1986. 28,29,30 : // 034..036
  1987. { !!! These are intended (and used in opcode table) to select depending
  1988. on address size, *not* operand size. Works by coincidence only. }
  1989. begin
  1990. getvalsym(c-28);
  1991. if opsize=S_Q then
  1992. begin
  1993. if assigned(currsym) then
  1994. objdata_writereloc(currval,8,currsym,currabsreloc)
  1995. else
  1996. objdata.writebytes(currval,8);
  1997. end
  1998. else
  1999. begin
  2000. if assigned(currsym) then
  2001. objdata_writereloc(currval,4,currsym,currabsreloc32)
  2002. else
  2003. objdata.writebytes(currval,4);
  2004. end
  2005. end;
  2006. 32,33,34 : // 040..042
  2007. begin
  2008. getvalsym(c-32);
  2009. if assigned(currsym) then
  2010. objdata_writereloc(currval,4,currsym,currabsreloc32)
  2011. else
  2012. objdata.writebytes(currval,4);
  2013. end;
  2014. 36,37,38 : // 044..046 - select between word/dword/qword depending on
  2015. begin // address size (we support only default address sizes).
  2016. getvalsym(c-36);
  2017. {$ifdef x86_64}
  2018. if assigned(currsym) then
  2019. objdata_writereloc(currval,8,currsym,currabsreloc)
  2020. else
  2021. objdata.writebytes(currval,8);
  2022. {$else x86_64}
  2023. if assigned(currsym) then
  2024. objdata_writereloc(currval,4,currsym,currabsreloc32)
  2025. else
  2026. objdata.writebytes(currval,4);
  2027. {$endif x86_64}
  2028. end;
  2029. 40,41,42 : // 050..052 - byte relative operand
  2030. begin
  2031. getvalsym(c-40);
  2032. data:=currval-insend;
  2033. if assigned(currsym) then
  2034. inc(data,currsym.address);
  2035. if (data>127) or (data<-128) then
  2036. Message1(asmw_e_short_jmp_out_of_range,tostr(data));
  2037. objdata.writebytes(data,1);
  2038. end;
  2039. 44,45,46: // 054..056 - qword immediate operand
  2040. begin
  2041. getvalsym(c-44);
  2042. if assigned(currsym) then
  2043. objdata_writereloc(currval,8,currsym,currabsreloc)
  2044. else
  2045. objdata.writebytes(currval,8);
  2046. end;
  2047. 52,53,54 : // 064..066 - select between 16/32 address mode, but we support only 32
  2048. begin
  2049. getvalsym(c-52);
  2050. if assigned(currsym) then
  2051. objdata_writereloc(currval,4,currsym,currrelreloc)
  2052. else
  2053. objdata_writereloc(currval-insend,4,nil,currabsreloc32)
  2054. end;
  2055. 56,57,58 : // 070..072 - long relative operand
  2056. begin
  2057. getvalsym(c-56);
  2058. if assigned(currsym) then
  2059. objdata_writereloc(currval,4,currsym,currrelreloc)
  2060. else
  2061. objdata_writereloc(currval-insend,4,nil,currabsreloc32)
  2062. end;
  2063. 172,173,174 : // 0254..0256 - dword implicitly sign-extended to 64-bit (x86_64 only)
  2064. begin
  2065. getvalsym(c-172);
  2066. {$ifdef x86_64}
  2067. { for i386 as aint type is longint the
  2068. following test is useless }
  2069. if (currval<low(longint)) or (currval>high(longint)) then
  2070. Message2(asmw_e_value_exceeds_bounds,'signed dword',tostr(currval));
  2071. {$endif x86_64}
  2072. if assigned(currsym) then
  2073. objdata_writereloc(currval,4,currsym,currabsreloc32)
  2074. else
  2075. objdata.writebytes(currval,4);
  2076. end;
  2077. 200 : { fixed 16-bit addr }
  2078. {$ifndef x86_64}
  2079. begin
  2080. bytes[0]:=$67;
  2081. objdata.writebytes(bytes,1);
  2082. end;
  2083. {$else x86_64}
  2084. { every insentry having code 0310 must be marked with NOX86_64 }
  2085. InternalError(2011051302);
  2086. {$endif}
  2087. 201 : { fixed 32-bit addr }
  2088. {$ifdef x86_64}
  2089. begin
  2090. bytes[0]:=$67;
  2091. objdata.writebytes(bytes,1);
  2092. end
  2093. {$endif x86_64}
  2094. ;
  2095. 208,209,210 :
  2096. begin
  2097. case oper[c-208]^.ot and OT_SIZE_MASK of
  2098. OT_BITS16 :
  2099. begin
  2100. bytes[0]:=$66;
  2101. objdata.writebytes(bytes,1);
  2102. end;
  2103. {$ifndef x86_64}
  2104. OT_BITS64 :
  2105. Message(asmw_e_64bit_not_supported);
  2106. {$endif x86_64}
  2107. end;
  2108. end;
  2109. 211,
  2110. 213 : {no action needed};
  2111. 212, 241 :
  2112. begin
  2113. bytes[0]:=$66;
  2114. objdata.writebytes(bytes,1);
  2115. end;
  2116. 214 :
  2117. begin
  2118. {$ifndef x86_64}
  2119. Message(asmw_e_64bit_not_supported);
  2120. {$endif x86_64}
  2121. end;
  2122. 219 :
  2123. begin
  2124. bytes[0]:=$f3;
  2125. objdata.writebytes(bytes,1);
  2126. end;
  2127. 220 :
  2128. begin
  2129. bytes[0]:=$f2;
  2130. objdata.writebytes(bytes,1);
  2131. end;
  2132. 221:
  2133. ;
  2134. 202,
  2135. 215,
  2136. 217,218 :
  2137. begin
  2138. { these are dissambler hints or 32 bit prefixes which
  2139. are not needed }
  2140. end;
  2141. 31,
  2142. 48,49,50 :
  2143. begin
  2144. InternalError(777006);
  2145. end
  2146. else
  2147. begin
  2148. { rex should be written at this point }
  2149. {$ifdef x86_64}
  2150. if (rex<>0) and not(rexwritten) then
  2151. internalerror(200603191);
  2152. {$endif x86_64}
  2153. if (c>=64) and (c<=151) then // 0100..0227
  2154. begin
  2155. if (c<127) then // 0177
  2156. begin
  2157. if (oper[c and 7]^.typ=top_reg) then
  2158. rfield:=regval(oper[c and 7]^.reg)
  2159. else
  2160. rfield:=regval(oper[c and 7]^.ref^.base);
  2161. end
  2162. else
  2163. rfield:=c and 7;
  2164. opidx:=(c shr 3) and 7;
  2165. if not process_ea(oper[opidx]^,ea_data,rfield) then
  2166. Message(asmw_e_invalid_effective_address);
  2167. pb:=@bytes[0];
  2168. pb^:=ea_data.modrm;
  2169. inc(pb);
  2170. if ea_data.sib_present then
  2171. begin
  2172. pb^:=ea_data.sib;
  2173. inc(pb);
  2174. end;
  2175. s:=pb-@bytes[0];
  2176. objdata.writebytes(bytes,s);
  2177. case ea_data.bytes of
  2178. 0 : ;
  2179. 1 :
  2180. begin
  2181. if (oper[opidx]^.ot and OT_MEMORY)=OT_MEMORY then
  2182. begin
  2183. currsym:=objdata.symbolref(oper[opidx]^.ref^.symbol);
  2184. {$ifdef i386}
  2185. if (oper[opidx]^.ref^.refaddr=addr_pic) and
  2186. (tf_pic_uses_got in target_info.flags) then
  2187. currabsreloc:=RELOC_GOT32
  2188. else
  2189. {$endif i386}
  2190. {$ifdef x86_64}
  2191. if oper[opidx]^.ref^.refaddr=addr_pic then
  2192. currabsreloc:=RELOC_GOTPCREL
  2193. else
  2194. {$endif x86_64}
  2195. currabsreloc:=RELOC_ABSOLUTE;
  2196. objdata_writereloc(oper[opidx]^.ref^.offset,1,currsym,currabsreloc);
  2197. end
  2198. else
  2199. begin
  2200. bytes[0]:=oper[opidx]^.ref^.offset;
  2201. objdata.writebytes(bytes,1);
  2202. end;
  2203. inc(s);
  2204. end;
  2205. 2,4 :
  2206. begin
  2207. currsym:=objdata.symbolref(oper[opidx]^.ref^.symbol);
  2208. currval:=oper[opidx]^.ref^.offset;
  2209. {$ifdef x86_64}
  2210. if oper[opidx]^.ref^.refaddr=addr_pic then
  2211. currabsreloc:=RELOC_GOTPCREL
  2212. else
  2213. if oper[opidx]^.ref^.base=NR_RIP then
  2214. begin
  2215. currabsreloc:=RELOC_RELATIVE;
  2216. { Adjust reloc value by number of bytes following the displacement,
  2217. but not if displacement is specified by literal constant }
  2218. if Assigned(currsym) then
  2219. Dec(currval,InsEnd-objdata.CurrObjSec.Size-ea_data.bytes);
  2220. end
  2221. else
  2222. {$endif x86_64}
  2223. {$ifdef i386}
  2224. if (oper[opidx]^.ref^.refaddr=addr_pic) and
  2225. (tf_pic_uses_got in target_info.flags) then
  2226. currabsreloc:=RELOC_GOT32
  2227. else
  2228. {$endif i386}
  2229. currabsreloc:=RELOC_ABSOLUTE32;
  2230. if (currabsreloc=RELOC_ABSOLUTE32) and
  2231. (Assigned(oper[opidx]^.ref^.relsymbol)) then
  2232. begin
  2233. relsym:=objdata.symbolref(oper[opidx]^.ref^.relsymbol);
  2234. currabsreloc:=RELOC_PIC_PAIR;
  2235. currval:=relsym.offset;
  2236. end;
  2237. objdata_writereloc(currval,ea_data.bytes,currsym,currabsreloc);
  2238. inc(s,ea_data.bytes);
  2239. end;
  2240. end;
  2241. end
  2242. else
  2243. InternalError(777007);
  2244. end;
  2245. end;
  2246. until false;
  2247. end;
  2248. function taicpu.is_same_reg_move(regtype: Tregistertype):boolean;
  2249. begin
  2250. result:=(((opcode=A_MOV) or (opcode=A_XCHG)) and
  2251. (regtype = R_INTREGISTER) and
  2252. (ops=2) and
  2253. (oper[0]^.typ=top_reg) and
  2254. (oper[1]^.typ=top_reg) and
  2255. (oper[0]^.reg=oper[1]^.reg)
  2256. ) or
  2257. (((opcode=A_MOVSS) or (opcode=A_MOVSD) or (opcode=A_MOVQ) or
  2258. (opcode=A_MOVAPS) or (OPCODE=A_MOVAPD)) and
  2259. (regtype = R_MMREGISTER) and
  2260. (ops=2) and
  2261. (oper[0]^.typ=top_reg) and
  2262. (oper[1]^.typ=top_reg) and
  2263. (oper[0]^.reg=oper[1]^.reg)
  2264. );
  2265. end;
  2266. procedure build_spilling_operation_type_table;
  2267. var
  2268. opcode : tasmop;
  2269. i : integer;
  2270. begin
  2271. new(operation_type_table);
  2272. fillchar(operation_type_table^,sizeof(toperation_type_table),byte(operand_read));
  2273. for opcode:=low(tasmop) to high(tasmop) do
  2274. begin
  2275. for i:=1 to MaxInsChanges do
  2276. begin
  2277. case InsProp[opcode].Ch[i] of
  2278. Ch_Rop1 :
  2279. operation_type_table^[opcode,0]:=operand_read;
  2280. Ch_Wop1 :
  2281. operation_type_table^[opcode,0]:=operand_write;
  2282. Ch_RWop1,
  2283. Ch_Mop1 :
  2284. operation_type_table^[opcode,0]:=operand_readwrite;
  2285. Ch_Rop2 :
  2286. operation_type_table^[opcode,1]:=operand_read;
  2287. Ch_Wop2 :
  2288. operation_type_table^[opcode,1]:=operand_write;
  2289. Ch_RWop2,
  2290. Ch_Mop2 :
  2291. operation_type_table^[opcode,1]:=operand_readwrite;
  2292. Ch_Rop3 :
  2293. operation_type_table^[opcode,2]:=operand_read;
  2294. Ch_Wop3 :
  2295. operation_type_table^[opcode,2]:=operand_write;
  2296. Ch_RWop3,
  2297. Ch_Mop3 :
  2298. operation_type_table^[opcode,2]:=operand_readwrite;
  2299. end;
  2300. end;
  2301. end;
  2302. { Special cases that can't be decoded from the InsChanges flags }
  2303. operation_type_table^[A_IMUL,1]:=operand_readwrite;
  2304. end;
  2305. function taicpu.spilling_get_operation_type(opnr: longint): topertype;
  2306. begin
  2307. { the information in the instruction table is made for the string copy
  2308. operation MOVSD so hack here (FK)
  2309. }
  2310. if (opcode=A_MOVSD) and (ops=2) then
  2311. begin
  2312. case opnr of
  2313. 0:
  2314. result:=operand_read;
  2315. 1:
  2316. result:=operand_write;
  2317. else
  2318. internalerror(200506055);
  2319. end
  2320. end
  2321. else
  2322. result:=operation_type_table^[opcode,opnr];
  2323. end;
  2324. function spilling_create_load(const ref:treference;r:tregister):Taicpu;
  2325. begin
  2326. case getregtype(r) of
  2327. R_INTREGISTER :
  2328. { we don't need special code here for 32 bit loads on x86_64, since
  2329. those will automatically zero-extend the upper 32 bits. }
  2330. result:=taicpu.op_ref_reg(A_MOV,reg2opsize(r),ref,r);
  2331. R_MMREGISTER :
  2332. case getsubreg(r) of
  2333. R_SUBMMD:
  2334. result:=taicpu.op_ref_reg(A_MOVSD,reg2opsize(r),ref,r);
  2335. R_SUBMMS:
  2336. result:=taicpu.op_ref_reg(A_MOVSS,reg2opsize(r),ref,r);
  2337. R_SUBMMWHOLE:
  2338. result:=taicpu.op_ref_reg(A_MOVQ,S_NO,ref,r);
  2339. else
  2340. internalerror(200506043);
  2341. end;
  2342. else
  2343. internalerror(200401041);
  2344. end;
  2345. end;
  2346. function spilling_create_store(r:tregister; const ref:treference):Taicpu;
  2347. var
  2348. size: topsize;
  2349. begin
  2350. case getregtype(r) of
  2351. R_INTREGISTER :
  2352. begin
  2353. size:=reg2opsize(r);
  2354. {$ifdef x86_64}
  2355. { even if it's a 32 bit reg, we still have to spill 64 bits
  2356. because we often perform 64 bit operations on them }
  2357. if (size=S_L) then
  2358. begin
  2359. size:=S_Q;
  2360. r:=newreg(getregtype(r),getsupreg(r),R_SUBWHOLE);
  2361. end;
  2362. {$endif x86_64}
  2363. result:=taicpu.op_reg_ref(A_MOV,size,r,ref);
  2364. end;
  2365. R_MMREGISTER :
  2366. case getsubreg(r) of
  2367. R_SUBMMD:
  2368. result:=taicpu.op_reg_ref(A_MOVSD,reg2opsize(r),r,ref);
  2369. R_SUBMMS:
  2370. result:=taicpu.op_reg_ref(A_MOVSS,reg2opsize(r),r,ref);
  2371. R_SUBMMWHOLE:
  2372. result:=taicpu.op_reg_ref(A_MOVQ,S_NO,r,ref);
  2373. else
  2374. internalerror(200506042);
  2375. end;
  2376. else
  2377. internalerror(200401041);
  2378. end;
  2379. end;
  2380. {*****************************************************************************
  2381. Instruction table
  2382. *****************************************************************************}
  2383. procedure BuildInsTabCache;
  2384. var
  2385. i : longint;
  2386. begin
  2387. new(instabcache);
  2388. FillChar(instabcache^,sizeof(tinstabcache),$ff);
  2389. i:=0;
  2390. while (i<InsTabEntries) do
  2391. begin
  2392. if InsTabCache^[InsTab[i].OPcode]=-1 then
  2393. InsTabCache^[InsTab[i].OPcode]:=i;
  2394. inc(i);
  2395. end;
  2396. end;
  2397. procedure InitAsm;
  2398. begin
  2399. build_spilling_operation_type_table;
  2400. if not assigned(instabcache) then
  2401. BuildInsTabCache;
  2402. end;
  2403. procedure DoneAsm;
  2404. begin
  2405. if assigned(operation_type_table) then
  2406. begin
  2407. dispose(operation_type_table);
  2408. operation_type_table:=nil;
  2409. end;
  2410. if assigned(instabcache) then
  2411. begin
  2412. dispose(instabcache);
  2413. instabcache:=nil;
  2414. end;
  2415. end;
  2416. begin
  2417. cai_align:=tai_align;
  2418. cai_cpu:=taicpu;
  2419. end.