.. |
aasmcpu.pas
|
d4968e054b
+ arm: tsettings.instructionset
|
12 years ago |
agarmgas.pas
|
d4968e054b
+ arm: tsettings.instructionset
|
12 years ago |
aoptcpu.pas
|
10ae87f11c
* fixed LdrLdr2LdrMov optimisation in case the first and second ldr have
|
12 years ago |
aoptcpub.pas
|
7e5b8584cf
* set MaxOps to 4 for the optimizer because fpc generates now mla instructions
|
13 years ago |
aoptcpuc.pas
|
790a4fe2d3
* log and id tags removed
|
20 years ago |
aoptcpud.pas
|
790a4fe2d3
* log and id tags removed
|
20 years ago |
armatt.inc
|
b67e4fb8b3
added the ADR ARM pseudo instruction to instruction list
|
11 years ago |
armatts.inc
|
b67e4fb8b3
added the ADR ARM pseudo instruction to instruction list
|
11 years ago |
armins.dat
|
b67e4fb8b3
added the ADR ARM pseudo instruction to instruction list
|
11 years ago |
armnop.inc
|
666332385d
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
|
13 years ago |
armop.inc
|
b67e4fb8b3
added the ADR ARM pseudo instruction to instruction list
|
11 years ago |
armreg.dat
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
13 years ago |
armtab.inc
|
666332385d
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
|
13 years ago |
cgcpu.pas
|
555634b755
* (re)set upper bits of register when appropriate for all operations in
|
12 years ago |
cpubase.pas
|
c48d572996
Implement support for saving and restoring address registers.
|
12 years ago |
cpuelf.pas
|
97a706c672
+ Add definitions for ELF header flags.
|
11 years ago |
cpuinfo.pas
|
73e6af4864
+ cpu flag CPUARM_HAS_THUMB_IDIV
|
12 years ago |
cpunode.pas
|
638d0d49c0
+ take advantage of the mla instruction when calculating array offsets
|
13 years ago |
cpupara.pas
|
d4968e054b
+ arm: tsettings.instructionset
|
12 years ago |
cpupi.pas
|
5276159e77
* correct ofset for saving floating point registers + explanation behind
|
12 years ago |
cputarg.pas
|
d26f0552a0
* Sync with trunk r23404.
|
12 years ago |
hlcgcpu.pas
|
72e9cfee24
* create/destroy also the high level code generator for all architectures,
|
14 years ago |
itcpugas.pas
|
47d43750e4
* remove unused units from uses statements
|
12 years ago |
narmadd.pas
|
25619d4991
removed the const-in-the-left internalerror
|
12 years ago |
narmcal.pas
|
8b8a786823
* moved ARM/x86 ifdef'ed code from ncgcal to virtual methods
|
12 years ago |
narmcnv.pas
|
5051453806
+ support for LOC_(C)MMREGISTER in hlcg
|
12 years ago |
narmcon.pas
|
47d43750e4
* remove unused units from uses statements
|
12 years ago |
narminl.pas
|
2c49af3191
added missing closing parentheses
|
12 years ago |
narmmat.pas
|
b6d279d4aa
* don't transform div-by-power-of-2 into a shift when overflow checking is
|
11 years ago |
narmmem.pas
|
d4968e054b
+ arm: tsettings.instructionset
|
12 years ago |
narmset.pas
|
24d88edf37
* fixes arm building after 26004
|
11 years ago |
pp.lpi.template
|
1f032375c3
* improved template with help from Mattias Gaertner
|
19 years ago |
raarm.pas
|
780e75bfac
o patch by Jeppe Johansen to fix mantis #17472:
|
14 years ago |
raarmgas.pas
|
628149d923
support label offsets for ARM like GAS, allows things like ADR r4, .label + 256
|
11 years ago |
rarmcon.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
13 years ago |
rarmdwa.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
13 years ago |
rarmnor.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
13 years ago |
rarmnum.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
13 years ago |
rarmrni.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
13 years ago |
rarmsri.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
13 years ago |
rarmsta.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
13 years ago |
rarmstd.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
13 years ago |
rarmsup.inc
|
7150832ec9
+ Cortex-M3 special registers, resolves #23185
|
13 years ago |
rgcpu.pas
|
d4968e054b
+ arm: tsettings.instructionset
|
12 years ago |