cgbase.pas 31 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl
  3. Some basic types and constants for the code generation
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. {# This unit exports some types which are used across the code generator }
  18. unit cgbase;
  19. {$i fpcdefs.inc}
  20. interface
  21. uses
  22. globtype,
  23. symconst;
  24. type
  25. { Location types where value can be stored }
  26. TCGLoc=(
  27. LOC_INVALID, { added for tracking problems}
  28. LOC_VOID, { no value is available }
  29. LOC_CONSTANT, { constant value }
  30. LOC_JUMP, { boolean results only, jump to false or true label }
  31. LOC_FLAGS, { boolean results only, flags are set }
  32. LOC_REGISTER, { in a processor register }
  33. LOC_CREGISTER, { Constant register which shouldn't be modified }
  34. LOC_FPUREGISTER, { FPU stack }
  35. LOC_CFPUREGISTER, { if it is a FPU register variable on the fpu stack }
  36. LOC_MMXREGISTER, { MMX register }
  37. { MMX register variable }
  38. LOC_CMMXREGISTER,
  39. { multimedia register }
  40. LOC_MMREGISTER,
  41. { Constant multimedia reg which shouldn't be modified }
  42. LOC_CMMREGISTER,
  43. { contiguous subset of bits of an integer register }
  44. LOC_SUBSETREG,
  45. LOC_CSUBSETREG,
  46. { contiguous subset of bits in memory }
  47. LOC_SUBSETREF,
  48. LOC_CSUBSETREF,
  49. { keep these last for range checking purposes }
  50. LOC_CREFERENCE, { in memory constant value reference (cannot change) }
  51. LOC_REFERENCE { in memory value }
  52. );
  53. TCGNonRefLoc=low(TCGLoc)..pred(LOC_CREFERENCE);
  54. TCGRefLoc=LOC_CREFERENCE..LOC_REFERENCE;
  55. trefaddr = (
  56. addr_no,
  57. addr_full,
  58. addr_pic,
  59. addr_pic_no_got
  60. {$IF defined(POWERPC) or defined(POWERPC64) or defined(SPARC) or defined(MIPS) or defined(SPARC64)}
  61. ,
  62. { since we have only 16bit offsets, we need to be able to specify the high
  63. and lower 16 bits of the address of a symbol of up to 64 bit }
  64. addr_low, // bits 48-63
  65. addr_high, // bits 32-47
  66. {$IF defined(POWERPC64)}
  67. addr_higher, // bits 16-31
  68. addr_highest, // bits 00-15
  69. {$ENDIF}
  70. addr_higha // bits 16-31, adjusted
  71. {$IF defined(POWERPC64)}
  72. ,
  73. addr_highera, // bits 32-47, adjusted
  74. addr_highesta // bits 48-63, adjusted
  75. {$ENDIF}
  76. {$ENDIF POWERPC or POWERPC64 or SPARC or MIPS or SPARC64}
  77. {$IFDEF MIPS}
  78. ,
  79. addr_pic_call16, // like addr_pic, but generates call16 reloc instead of got16
  80. addr_low_pic, // for large GOT model, generate got_hi16 and got_lo16 relocs
  81. addr_high_pic,
  82. addr_low_call, // counterpart of two above, generate call_hi16 and call_lo16 relocs
  83. addr_high_call
  84. {$ENDIF}
  85. {$if defined(RISCV32) or defined(RISCV64)}
  86. ,
  87. addr_hi20,
  88. addr_lo12,
  89. addr_pcrel_hi20,
  90. addr_pcrel_lo12,
  91. addr_pcrel,
  92. addr_got_pcrel_hi,
  93. addr_plt
  94. {$endif RISCV}
  95. {$if defined(LOONGARCH64)}
  96. ,
  97. addr_b16, { %b16(sym) }
  98. addr_b21, { %b21(sym) }
  99. addr_b26, { %b26(sym) }
  100. addr_pcrel, { Some times we only use sym like 'bxx rd,rj,sym'. And la.pcrel..sym }
  101. addr_plt, { %plt(sym) }
  102. addr_abs_hi20, { %abs_hi20(sym) }
  103. addr_abs_lo12, { %abs_lo12(sym) }
  104. addr_abs64_lo20, { %abs_lo20(sym) }
  105. addr_abs64_hi12, { %abs_hi12(sym) }
  106. addr_pc_hi20, { %pc_hi20(sym) }
  107. addr_got_pc_hi20, { %got_pc_hi20(sym) }
  108. addr_got_pc_lo12, { %got_pc_lo12(sym) }
  109. addr_pc_lo12, { %pc_lo12(sym) }
  110. addr_got, { la.got..sym }
  111. addr_abs, { la.abs..sym }
  112. addr_reg_reg, { use by [ld/st]x }
  113. addr_reg_12i, { use by [ld/st] }
  114. addr_reg_14i, { use by [ldptr/stptr] }
  115. addr_reg { use by jr.. }
  116. {$endif LOONGARCH64}
  117. {$IFDEF AVR}
  118. ,addr_lo8
  119. ,addr_lo8_gs
  120. ,addr_hi8
  121. ,addr_hi8_gs
  122. {$ENDIF}
  123. {$IFDEF Z80}
  124. ,addr_lo8
  125. ,addr_hi8
  126. {$ENDIF}
  127. {$IFDEF i8086}
  128. ,addr_dgroup // the data segment group
  129. ,addr_fardataseg // the far data segment of the current pascal module (unit or program)
  130. ,addr_seg // used for getting the segment of an object, e.g. 'mov ax, SEG symbol'
  131. {$ENDIF}
  132. {$IFDEF AARCH64}
  133. ,addr_page
  134. ,addr_pageoffset
  135. ,addr_gotpage
  136. ,addr_gotpageoffset
  137. {$ENDIF AARCH64}
  138. {$ifdef SPARC64}
  139. ,addr_gdop_hix22
  140. ,addr_gdop_lox22
  141. {$endif SPARC64}
  142. {$IFDEF ARM}
  143. ,addr_gottpoff
  144. ,addr_tpoff
  145. ,addr_tlsgd
  146. ,addr_tlsdesc
  147. ,addr_tlscall
  148. {$ENDIF}
  149. {$IFDEF i386}
  150. ,addr_ntpoff
  151. ,addr_tlsgd
  152. {$ENDIF}
  153. {$ifdef x86_64}
  154. ,addr_tpoff
  155. ,addr_tlsgd
  156. {$endif x86_64}
  157. {$ifdef wasm32}
  158. ,addr_got_tls
  159. {$endif wasm32}
  160. );
  161. {# Generic opcodes, which must be supported by all processors
  162. }
  163. topcg =
  164. (
  165. OP_NONE,
  166. OP_MOVE, { replaced operation with direct load }
  167. OP_ADD, { simple addition }
  168. OP_AND, { simple logical and }
  169. OP_DIV, { simple unsigned division }
  170. OP_IDIV, { simple signed division }
  171. OP_IMUL, { simple signed multiply }
  172. OP_MUL, { simple unsigned multiply }
  173. OP_NEG, { simple negate }
  174. OP_NOT, { simple logical not }
  175. OP_OR, { simple logical or }
  176. OP_SAR, { arithmetic shift-right }
  177. OP_SHL, { logical shift left }
  178. OP_SHR, { logical shift right }
  179. OP_SUB, { simple subtraction }
  180. OP_XOR, { simple exclusive or }
  181. OP_ROL, { rotate left }
  182. OP_ROR { rotate right }
  183. );
  184. {# Generic flag values - used for jump locations }
  185. TOpCmp =
  186. (
  187. OC_NONE,
  188. OC_EQ, { equality comparison }
  189. OC_GT, { greater than (signed) }
  190. OC_LT, { less than (signed) }
  191. OC_GTE, { greater or equal than (signed) }
  192. OC_LTE, { less or equal than (signed) }
  193. OC_NE, { not equal }
  194. OC_BE, { less or equal than (unsigned) }
  195. OC_B, { less than (unsigned) }
  196. OC_AE, { greater or equal than (unsigned) }
  197. OC_A { greater than (unsigned) }
  198. );
  199. { indirect symbol flags }
  200. tindsymflag = (is_data,is_weak);
  201. tindsymflags = set of tindsymflag;
  202. { OS_NO is also used memory references with large data that can
  203. not be loaded in a register directly }
  204. TCgSize = (OS_NO,
  205. OS_8, OS_16, OS_32, OS_64, OS_128,
  206. OS_S8, OS_S16, OS_S32, OS_S64, OS_S128,
  207. { single, double, extended, comp, float128 }
  208. OS_F32, OS_F64, OS_F80, OS_C64, OS_F128,
  209. { multi-media sizes, describes only the register size but not how it is split,
  210. this information must be passed separately }
  211. OS_M8, OS_M16, OS_M32, OS_M64, OS_M128, OS_M256, OS_M512);
  212. { Register types }
  213. TRegisterType = (
  214. R_INVALIDREGISTER, { = 0 }
  215. R_INTREGISTER, { = 1 }
  216. R_FPUREGISTER, { = 2 }
  217. { used by Intel only }
  218. R_MMXREGISTER, { = 3 }
  219. R_MMREGISTER, { = 4 }
  220. R_SPECIALREGISTER, { = 5 }
  221. R_ADDRESSREGISTER, { = 6 }
  222. { used on llvm, every temp gets its own "base register" }
  223. R_TEMPREGISTER, { = 7 }
  224. { used on llvm for tracking metadata (every unique metadata has its own base register) }
  225. R_METADATAREGISTER,{ = 8 }
  226. { optional MAC16 (16 bit multiply-accumulate) registers on Xtensa }
  227. R_MAC16REGISTER, { = 9 }
  228. { WebAssembly externref }
  229. R_EXTERNREFREGISTER, { = 10 }
  230. { WebAssembly funcref }
  231. R_FUNCREFREGISTER { = 11 }
  232. { do not add more than 16 elements (ifdef by cpu type if needed)
  233. so we can store this in one nibble and pack TRegister
  234. if the supreg width should be extended }
  235. );
  236. { Sub registers }
  237. TSubRegister = (
  238. R_SUBNONE, { = 0; no sub register possible }
  239. R_SUBL, { = 1; 8 bits, Like AL }
  240. R_SUBH, { = 2; 8 bits, Like AH }
  241. R_SUBW, { = 3; 16 bits, Like AX }
  242. R_SUBD, { = 4; 32 bits, Like EAX }
  243. R_SUBQ, { = 5; 64 bits, Like RAX }
  244. { For Sparc floats that use F0:F1 to store doubles }
  245. R_SUBFS, { = 6; Float that allocates 1 FPU register }
  246. R_SUBFD, { = 7; Float that allocates 2 FPU registers }
  247. R_SUBFQ, { = 8; Float that allocates 4 FPU registers }
  248. R_SUBMMS, { = 9; single scalar in multi media register }
  249. R_SUBMMD, { = 10; double scalar in multi media register }
  250. R_SUBMMWHOLE, { = 11; complete MM register, size depends on CPU }
  251. { For Intel X86 AVX-Register }
  252. R_SUBMMX, { = 12; 128 BITS }
  253. R_SUBMMY, { = 13; 256 BITS }
  254. R_SUBMMZ, { = 14; 512 BITS }
  255. {$ifdef Z80}
  256. { Subregisters for the flags register (Z80) }
  257. R_SUBFLAGCARRY, { = 15; Carry flag }
  258. R_SUBFLAGADDSUBTRACT, { = 16; Add/Subtract flag }
  259. R_SUBFLAGPARITYOVERFLOW, { = 17; Parity/Overflow flag }
  260. R_SUBFLAGUNUSEDBIT3, { = 18; Unused flag (bit 3) }
  261. R_SUBFLAGHALFCARRY, { = 19; Half Carry flag }
  262. R_SUBFLAGUNUSEDBIT5, { = 20; Unused flag (bit 5) }
  263. R_SUBFLAGZERO, { = 21; Zero flag }
  264. R_SUBFLAGSIGN, { = 22; Sign flag }
  265. {$else Z80}
  266. { Subregisters for the flags register (x86) }
  267. R_SUBFLAGCARRY, { = 15; Carry flag }
  268. R_SUBFLAGPARITY, { = 16; Parity flag }
  269. R_SUBFLAGAUXILIARY, { = 17; Auxiliary flag }
  270. R_SUBFLAGZERO, { = 18; Zero flag }
  271. R_SUBFLAGSIGN, { = 19; Sign flag }
  272. R_SUBFLAGOVERFLOW, { = 20; Overflow flag }
  273. R_SUBFLAGINTERRUPT, { = 21; Interrupt enable flag }
  274. R_SUBFLAGDIRECTION, { = 22; Direction flag }
  275. {$endif Z80}
  276. { subregisters for the metadata register (llvm) }
  277. R_SUBMETASTRING { = 23 }
  278. {$ifdef aarch64}
  279. , R_SUBMM8B { = 24; for arrangement of v regs on aarch64 }
  280. , R_SUBMM16B { = 25; for arrangement of v regs on aarch64 }
  281. , R_SUBMM4H { = 26; for arrangement of v regs on aarch64 }
  282. , R_SUBMM8H { = 27; for arrangement of v regs on aarch64 }
  283. , R_SUBMM2S { = 28; for arrangement of v regs on aarch64 }
  284. , R_SUBMM4S { = 29; for arrangement of v regs on aarch64 }
  285. , R_SUBMM1D { = 30; for arrangement of v regs on aarch64 }
  286. , R_SUBMM2D { = 31; for arrangement of v regs on aarch64 }
  287. , R_SUBMMB1 { = 32; for arrangement of v regs on aarch64; for use with ldN/stN }
  288. , R_SUBMMH1 { = 33; for arrangement of v regs on aarch64; for use with ldN/stN }
  289. , R_SUBMMS1 { = 34; for arrangement of v regs on aarch64; for use with ldN/stN }
  290. , R_SUBMMD1 { = 35; for arrangement of v regs on aarch64; for use with ldN/stN }
  291. {$endif aarch64}
  292. );
  293. TSubRegisterSet = set of TSubRegister;
  294. TSuperRegister = type word;
  295. {
  296. The new register coding:
  297. SuperRegister (bits 0..15)
  298. Subregister (bits 16..23)
  299. Register type (bits 24..31)
  300. TRegister is defined as an enum to make it incompatible
  301. with TSuperRegister to avoid mixing them
  302. }
  303. TRegister = (
  304. TRegisterLowEnum := Low(longint),
  305. TRegisterHighEnum := High(longint)
  306. );
  307. TRegisterRec=packed record
  308. {$ifdef FPC_BIG_ENDIAN}
  309. regtype : Tregistertype;
  310. subreg : Tsubregister;
  311. supreg : Tsuperregister;
  312. {$else FPC_BIG_ENDIAN}
  313. supreg : Tsuperregister;
  314. subreg : Tsubregister;
  315. regtype : Tregistertype;
  316. {$endif FPC_BIG_ENDIAN}
  317. end;
  318. { A type to store register locations for 64 Bit values. }
  319. {$ifdef cpu64bitalu}
  320. tregister64 = tregister;
  321. tregister128 = record
  322. reglo,reghi : tregister;
  323. end;
  324. {$else cpu64bitalu}
  325. tregister64 = record
  326. reglo,reghi : tregister;
  327. end;
  328. {$endif cpu64bitalu}
  329. { Set type definition for registers }
  330. tsuperregisterset = array[byte] of set of byte;
  331. pmmshuffle = ^tmmshuffle;
  332. { this record describes shuffle operations for mm operations; if a pointer a shuffle record
  333. passed to an mm operation is nil, it means that the whole location is moved }
  334. tmmshuffle = record
  335. { describes how many shuffles are actually described, if len=0 then
  336. moving the scalar with index 0 to the scalar with index 0 is meant,
  337. if len=-1, then a variable/unknown length is assumed }
  338. len : Shortint;
  339. { lower byte of each entry of this array describes index of the source data index while
  340. the upper byte describes the destination index }
  341. shuffles : array[1..1] of word;
  342. end;
  343. Tsuperregisterarray=array[0..$ffff] of Tsuperregister;
  344. Psuperregisterarray=^Tsuperregisterarray;
  345. Tsuperregisterworklist=object
  346. buflength,
  347. buflengthinc,
  348. length:word;
  349. buf:Psuperregisterarray;
  350. constructor init;
  351. constructor copyfrom(const x:Tsuperregisterworklist);
  352. destructor done;
  353. procedure clear;
  354. procedure add(s:tsuperregister);
  355. function addnodup(s:tsuperregister): boolean;
  356. { returns the last element and removes it from the list }
  357. function get:tsuperregister;
  358. function readidx(i:word):tsuperregister;
  359. procedure deleteidx(i:word);
  360. function delete(s:tsuperregister):boolean;
  361. end;
  362. psuperregisterworklist=^tsuperregisterworklist;
  363. const
  364. { alias for easier understanding }
  365. R_SSEREGISTER = R_MMREGISTER;
  366. { Invalid register number }
  367. RS_INVALID = high(tsuperregister);
  368. NR_INVALID = tregister($ffffffff);
  369. tcgsize2size : Array[tcgsize] of integer =
  370. (0,
  371. { integer values }
  372. 1, 2, 4, 8, 16,
  373. 1, 2, 4, 8, 16,
  374. { floating point values }
  375. 4, 8, 10, 8, 16,
  376. { multimedia values }
  377. 1, 2, 4, 8, 16, 32, 64);
  378. tfloat2tcgsize: array[tfloattype] of tcgsize =
  379. (OS_F32,OS_F64,OS_F80,OS_F80,OS_C64,OS_C64,OS_F128);
  380. tcgsize2tfloat: array[OS_F32..OS_C64] of tfloattype =
  381. (s32real,s64real,s80real,s64comp);
  382. tvarregable2tcgloc : array[tvarregable] of tcgloc = (LOC_VOID,
  383. LOC_CREGISTER,LOC_CFPUREGISTER,LOC_CMMREGISTER,LOC_CREGISTER);
  384. {$if defined(cpu64bitalu)}
  385. { operand size describing an unsigned value in a pair of int registers }
  386. OS_PAIR = OS_128;
  387. { operand size describing an signed value in a pair of int registers }
  388. OS_SPAIR = OS_S128;
  389. {$elseif defined(cpu32bitalu)}
  390. { operand size describing an unsigned value in a pair of int registers }
  391. OS_PAIR = OS_64;
  392. { operand size describing an signed value in a pair of int registers }
  393. OS_SPAIR = OS_S64;
  394. {$elseif defined(cpu16bitalu)}
  395. { operand size describing an unsigned value in a pair of int registers }
  396. OS_PAIR = OS_32;
  397. { operand size describing an signed value in a pair of int registers }
  398. OS_SPAIR = OS_S32;
  399. {$elseif defined(cpu8bitalu)}
  400. { operand size describing an unsigned value in a pair of int registers }
  401. OS_PAIR = OS_16;
  402. { operand size describing an signed value in a pair of int registers }
  403. OS_SPAIR = OS_S16;
  404. {$endif}
  405. { Table to convert tcgsize variables to the correspondending
  406. unsigned types }
  407. tcgsize2unsigned : array[tcgsize] of tcgsize = (OS_NO,
  408. OS_8, OS_16, OS_32, OS_64, OS_128,
  409. OS_8, OS_16, OS_32, OS_64, OS_128,
  410. OS_F32, OS_F64, OS_F80, OS_C64, OS_F128,
  411. OS_M8, OS_M16, OS_M32, OS_M64, OS_M128, OS_M256, OS_M512);
  412. tcgsize2signed : array[tcgsize] of tcgsize = (OS_NO,
  413. OS_S8, OS_S16, OS_S32, OS_S64, OS_S128,
  414. OS_S8, OS_S16, OS_S32, OS_S64, OS_S128,
  415. OS_F32, OS_F64, OS_F80, OS_C64, OS_F128,
  416. OS_M8, OS_M16, OS_M32, OS_M64, OS_M128, OS_M256,OS_M512);
  417. tcgloc2str : array[TCGLoc] of string[12] = (
  418. 'LOC_INVALID',
  419. 'LOC_VOID',
  420. 'LOC_CONST',
  421. 'LOC_JUMP',
  422. 'LOC_FLAGS',
  423. 'LOC_REG',
  424. 'LOC_CREG',
  425. 'LOC_FPUREG',
  426. 'LOC_CFPUREG',
  427. 'LOC_MMXREG',
  428. 'LOC_CMMXREG',
  429. 'LOC_MMREG',
  430. 'LOC_CMMREG',
  431. 'LOC_SSETREG',
  432. 'LOC_CSSETREG',
  433. 'LOC_SSETREF',
  434. 'LOC_CSSETREF',
  435. 'LOC_CREF',
  436. 'LOC_REF'
  437. );
  438. var
  439. mms_movescalar,
  440. mms_variable,
  441. mms_2,
  442. mms_4,
  443. mms_8,
  444. mms_16,
  445. mms_32 : pmmshuffle;
  446. procedure supregset_reset(out regs:tsuperregisterset;setall:boolean;
  447. maxreg:Tsuperregister);{$ifdef USEINLINE}inline;{$endif}
  448. procedure supregset_include(var regs:tsuperregisterset;s:tsuperregister);{$ifdef USEINLINE}inline;{$endif}
  449. procedure supregset_exclude(var regs:tsuperregisterset;s:tsuperregister);{$ifdef USEINLINE}inline;{$endif}
  450. function supregset_in(const regs:tsuperregisterset;s:tsuperregister):boolean;{$ifdef USEINLINE}inline;{$endif}
  451. function newreg(rt:tregistertype;sr:tsuperregister;sb:tsubregister):tregister;{$ifdef USEINLINE}inline;{$endif}
  452. function getsubreg(r:tregister):tsubregister;{$ifdef USEINLINE}inline;{$endif}
  453. function getsupreg(r:tregister):tsuperregister;{$ifdef USEINLINE}inline;{$endif}
  454. function getregtype(r:tregister):tregistertype;{$ifdef USEINLINE}inline;{$endif}
  455. procedure setsubreg(var r:tregister;sr:tsubregister);{$ifdef USEINLINE}inline;{$endif}
  456. procedure setsupreg(var r:tregister;sr:tsuperregister);{$ifdef USEINLINE}inline;{$endif}
  457. function generic_regname(r:tregister):string;
  458. {# From a constant numeric value, return the abstract code generator
  459. size.
  460. }
  461. function int_cgsize(const a: tcgint): tcgsize;{$ifdef USEINLINE}inline;{$endif}
  462. function int_float_cgsize(const a: tcgint): tcgsize;
  463. function float_array_cgsize(const a: tcgint): tcgsize;{$ifdef USEINLINE}inline;{$endif}
  464. function double_array_cgsize(const a: tcgint): tcgsize;{$ifdef USEINLINE}inline;{$endif}
  465. function tcgsize2str(cgsize: tcgsize):string;
  466. { return the inverse condition of opcmp }
  467. function inverse_opcmp(opcmp: topcmp): topcmp;{$ifdef USEINLINE}inline;{$endif}
  468. { return the opcmp needed when swapping the operands }
  469. function swap_opcmp(opcmp: topcmp): topcmp;{$ifdef USEINLINE}inline;{$endif}
  470. { return whether op is commutative }
  471. function commutativeop(op: topcg): boolean;{$ifdef USEINLINE}inline;{$endif}
  472. { returns true, if shuffle describes a real shuffle operation and not only a move }
  473. function realshuffle(shuffle : pmmshuffle) : boolean;
  474. { returns true, if the shuffle describes only a move of the scalar at index 0 }
  475. function shufflescalar(shuffle : pmmshuffle) : boolean;
  476. { removes shuffling from shuffle, this means that the destenation index of each shuffle is copied to
  477. the source }
  478. procedure removeshuffles(var shuffle : tmmshuffle);
  479. function is_float_cgsize(size: tcgsize): boolean;{$ifdef USEINLINE}inline;{$endif}
  480. implementation
  481. uses
  482. verbose,
  483. cutils;
  484. {******************************************************************************
  485. tsuperregisterworklist
  486. ******************************************************************************}
  487. constructor tsuperregisterworklist.init;
  488. begin
  489. length:=0;
  490. buflength:=0;
  491. buflengthinc:=16;
  492. buf:=nil;
  493. end;
  494. constructor Tsuperregisterworklist.copyfrom(const x:Tsuperregisterworklist);
  495. begin
  496. self:=x;
  497. if x.buf<>nil then
  498. begin
  499. getmem(buf,buflength*sizeof(Tsuperregister));
  500. move(x.buf^,buf^,length*sizeof(Tsuperregister));
  501. end;
  502. end;
  503. destructor tsuperregisterworklist.done;
  504. begin
  505. if assigned(buf) then
  506. freemem(buf);
  507. end;
  508. procedure tsuperregisterworklist.add(s:tsuperregister);
  509. begin
  510. inc(length);
  511. { Need to increase buffer length? }
  512. if length>=buflength then
  513. begin
  514. inc(buflength,buflengthinc);
  515. buflengthinc:=buflengthinc*2;
  516. if buflengthinc>256 then
  517. buflengthinc:=256;
  518. reallocmem(buf,buflength*sizeof(Tsuperregister));
  519. end;
  520. buf^[length-1]:=s;
  521. end;
  522. function tsuperregisterworklist.addnodup(s:tsuperregister): boolean;
  523. begin
  524. addnodup := false;
  525. if indexword(buf^,length,s) = -1 then
  526. begin
  527. add(s);
  528. addnodup := true;
  529. end;
  530. end;
  531. procedure tsuperregisterworklist.clear;
  532. begin
  533. length:=0;
  534. end;
  535. procedure tsuperregisterworklist.deleteidx(i:word);
  536. begin
  537. if i>=length then
  538. internalerror(200310144);
  539. buf^[i]:=buf^[length-1];
  540. dec(length);
  541. end;
  542. function tsuperregisterworklist.readidx(i:word):tsuperregister;
  543. begin
  544. if (i >= length) then
  545. internalerror(2005010601);
  546. result := buf^[i];
  547. end;
  548. function tsuperregisterworklist.get:tsuperregister;
  549. begin
  550. if length=0 then
  551. internalerror(200310142);
  552. dec(length);
  553. get:=buf^[length];
  554. end;
  555. function tsuperregisterworklist.delete(s:tsuperregister):boolean;
  556. var
  557. i:longint;
  558. begin
  559. delete:=false;
  560. { indexword in 1.0.x and 1.9.4 is broken }
  561. i:=indexword(buf^,length,s);
  562. if i<>-1 then
  563. begin
  564. deleteidx(i);
  565. delete := true;
  566. end;
  567. end;
  568. procedure supregset_reset(out regs:tsuperregisterset;setall:boolean;
  569. maxreg:Tsuperregister);{$ifdef USEINLINE}inline;{$endif}
  570. begin
  571. fillchar(regs,(maxreg+7) shr 3,-byte(setall));
  572. end;
  573. procedure supregset_include(var regs:tsuperregisterset;s:tsuperregister);{$ifdef USEINLINE}inline;{$endif}
  574. begin
  575. include(regs[s shr 8],(s and $ff));
  576. end;
  577. procedure supregset_exclude(var regs:tsuperregisterset;s:tsuperregister);{$ifdef USEINLINE}inline;{$endif}
  578. begin
  579. exclude(regs[s shr 8],(s and $ff));
  580. end;
  581. function supregset_in(const regs:tsuperregisterset;s:tsuperregister):boolean;{$ifdef USEINLINE}inline;{$endif}
  582. begin
  583. result:=(s and $ff) in regs[s shr 8];
  584. end;
  585. function newreg(rt:tregistertype;sr:tsuperregister;sb:tsubregister):tregister;{$ifdef USEINLINE}inline;{$endif}
  586. begin
  587. tregisterrec(result).regtype:=rt;
  588. tregisterrec(result).supreg:=sr;
  589. tregisterrec(result).subreg:=sb;
  590. end;
  591. function getsubreg(r:tregister):tsubregister;{$ifdef USEINLINE}inline;{$endif}
  592. begin
  593. result:=tregisterrec(r).subreg;
  594. end;
  595. function getsupreg(r:tregister):tsuperregister;{$ifdef USEINLINE}inline;{$endif}
  596. begin
  597. result:=tregisterrec(r).supreg;
  598. end;
  599. function getregtype(r:tregister):tregistertype;{$ifdef USEINLINE}inline;{$endif}
  600. begin
  601. result:=tregisterrec(r).regtype;
  602. end;
  603. procedure setsubreg(var r:tregister;sr:tsubregister);{$ifdef USEINLINE}inline;{$endif}
  604. begin
  605. tregisterrec(r).subreg:=sr;
  606. end;
  607. procedure setsupreg(var r:tregister;sr:tsuperregister);{$ifdef USEINLINE}inline;{$endif}
  608. begin
  609. tregisterrec(r).supreg:=sr;
  610. end;
  611. function generic_regname(r:tregister):string;
  612. var
  613. nr : string[12];
  614. begin
  615. str(getsupreg(r),nr);
  616. case getregtype(r) of
  617. R_INTREGISTER:
  618. result:='ireg'+nr;
  619. R_FPUREGISTER:
  620. result:='freg'+nr;
  621. R_MMREGISTER:
  622. result:='mreg'+nr;
  623. R_MMXREGISTER:
  624. result:='xreg'+nr;
  625. R_ADDRESSREGISTER:
  626. result:='areg'+nr;
  627. R_SPECIALREGISTER:
  628. result:='sreg'+nr;
  629. else
  630. begin
  631. result:='INVALID';
  632. exit;
  633. end;
  634. end;
  635. case getsubreg(r) of
  636. R_SUBNONE:
  637. ;
  638. R_SUBL:
  639. result:=result+'l';
  640. R_SUBH:
  641. result:=result+'h';
  642. R_SUBW:
  643. result:=result+'w';
  644. R_SUBD:
  645. result:=result+'d';
  646. R_SUBQ:
  647. result:=result+'q';
  648. R_SUBFS:
  649. result:=result+'fs';
  650. R_SUBFD:
  651. result:=result+'fd';
  652. R_SUBMMD:
  653. result:=result+'md';
  654. R_SUBMMS:
  655. result:=result+'ms';
  656. R_SUBMMWHOLE:
  657. result:=result+'ma';
  658. R_SUBMMX:
  659. result:=result+'mx';
  660. R_SUBMMY:
  661. result:=result+'my';
  662. R_SUBMMZ:
  663. result:=result+'mz';
  664. {$ifdef aarch64}
  665. R_SUBMM8B:
  666. result:=result+'m8b';
  667. R_SUBMM16B:
  668. result:=result+'m16b';
  669. R_SUBMM4H:
  670. result:=result+'m4h';
  671. R_SUBMM8H:
  672. result:=result+'m8h';
  673. R_SUBMM2S:
  674. result:=result+'m2s';
  675. R_SUBMM4S:
  676. result:=result+'m4s';
  677. R_SUBMM2D:
  678. result:=result+'m2d';
  679. R_SUBMMB1:
  680. result:=result+'mb1';
  681. R_SUBMMH1:
  682. result:=result+'mh1';
  683. R_SUBMMS1:
  684. result:=result+'ms1';
  685. R_SUBMMD1:
  686. result:=result+'md1';
  687. {$endif}
  688. else
  689. internalerror(200308252);
  690. end;
  691. end;
  692. function int_cgsize(const a: tcgint): tcgsize;{$ifdef USEINLINE}inline;{$endif}
  693. const
  694. size2cgsize : array[0..8] of tcgsize = (
  695. OS_NO,OS_8,OS_16,OS_NO,OS_32,OS_NO,OS_NO,OS_NO,OS_64
  696. );
  697. begin
  698. {$ifdef cpu64bitalu}
  699. if a=16 then
  700. result:=OS_128
  701. else
  702. {$endif cpu64bitalu}
  703. if a>8 then
  704. result:=OS_NO
  705. else
  706. result:=size2cgsize[a];
  707. end;
  708. function int_float_cgsize(const a: tcgint): tcgsize;
  709. begin
  710. case a of
  711. 4 :
  712. result:=OS_F32;
  713. 8 :
  714. result:=OS_F64;
  715. 10 :
  716. result:=OS_F80;
  717. 16 :
  718. result:=OS_F128;
  719. else
  720. internalerror(200603211);
  721. end;
  722. end;
  723. function float_array_cgsize(const a: tcgint): tcgsize;{$ifdef USEINLINE}inline;{$endif}
  724. begin
  725. case a of
  726. 4:
  727. result := OS_M32;
  728. 16:
  729. result := OS_M128;
  730. 32:
  731. result := OS_M256;
  732. 64:
  733. result := OS_M512;
  734. else
  735. result := int_cgsize(a);
  736. end;
  737. end;
  738. function double_array_cgsize(const a: tcgint): tcgsize;{$ifdef USEINLINE}inline;{$endif}
  739. begin
  740. case a of
  741. 8:
  742. result := OS_M64;
  743. 16:
  744. result := OS_M128;
  745. 32:
  746. result := OS_M256;
  747. 64:
  748. result := OS_M512;
  749. else
  750. result := int_cgsize(a);
  751. end;
  752. end;
  753. function tcgsize2str(cgsize: tcgsize):string;
  754. begin
  755. Str(cgsize, Result);
  756. end;
  757. function inverse_opcmp(opcmp: topcmp): topcmp;{$ifdef USEINLINE}inline;{$endif}
  758. const
  759. list: array[TOpCmp] of TOpCmp =
  760. (OC_NONE,OC_NE,OC_LTE,OC_GTE,OC_LT,OC_GT,OC_EQ,OC_A,OC_AE,
  761. OC_B,OC_BE);
  762. begin
  763. inverse_opcmp := list[opcmp];
  764. end;
  765. function swap_opcmp(opcmp: topcmp): topcmp;{$ifdef USEINLINE}inline;{$endif}
  766. const
  767. list: array[TOpCmp] of TOpCmp =
  768. (OC_NONE,OC_EQ,OC_LT,OC_GT,OC_LTE,OC_GTE,OC_NE,OC_AE,OC_A,
  769. OC_BE,OC_B);
  770. begin
  771. swap_opcmp := list[opcmp];
  772. end;
  773. function commutativeop(op: topcg): boolean;{$ifdef USEINLINE}inline;{$endif}
  774. const
  775. list: array[topcg] of boolean =
  776. (true,false,true,true,false,false,true,true,false,false,
  777. true,false,false,false,false,true,false,false);
  778. begin
  779. commutativeop := list[op];
  780. end;
  781. function realshuffle(shuffle : pmmshuffle) : boolean;
  782. var
  783. i : longint;
  784. begin
  785. realshuffle:=true;
  786. if (shuffle=nil) or (shuffle^.len<1) then
  787. realshuffle:=false
  788. else
  789. begin
  790. for i:=1 to shuffle^.len do
  791. begin
  792. if (shuffle^.shuffles[i] and $ff)<>((shuffle^.shuffles[i] and $ff00) shr 8) then
  793. exit;
  794. end;
  795. realshuffle:=false;
  796. end;
  797. end;
  798. function shufflescalar(shuffle : pmmshuffle) : boolean;
  799. begin
  800. result:=shuffle^.len=0;
  801. end;
  802. procedure removeshuffles(var shuffle : tmmshuffle);
  803. var
  804. i : longint;
  805. begin
  806. if shuffle.len=0 then
  807. exit;
  808. for i:=1 to shuffle.len do
  809. shuffle.shuffles[i]:=(shuffle.shuffles[i] and $f) or ((shuffle.shuffles[i] and $f0) shr 4);
  810. end;
  811. function is_float_cgsize(size: tcgsize): boolean;{$ifdef USEINLINE}inline;{$endif}
  812. begin
  813. result:=size in [OS_F32..OS_F128];
  814. end;
  815. procedure Initmms(var p : pmmshuffle;len : ShortInt);
  816. var
  817. i : Integer;
  818. begin
  819. Getmem(p,sizeof(tmmshuffle)+(max(len,0)-1)*2);
  820. p^.len:=len;
  821. for i:=1 to len do
  822. {$push}
  823. {$R-}
  824. p^.shuffles[i]:=i;
  825. {$pop}
  826. end;
  827. initialization
  828. Initmms(mms_movescalar,0);
  829. Initmms(mms_variable,-1);
  830. Initmms(mms_2,2);
  831. Initmms(mms_4,4);
  832. Initmms(mms_8,8);
  833. Initmms(mms_16,16);
  834. Initmms(mms_32,32);
  835. finalization
  836. Freemem(mms_movescalar);
  837. Freemem(mms_variable);
  838. Freemem(mms_2);
  839. Freemem(mms_4);
  840. Freemem(mms_8);
  841. Freemem(mms_16);
  842. Freemem(mms_32);
  843. end.