atmega324pb.pp 32 KB

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  1. unit ATmega324PB;
  2. interface
  3. var
  4. PINA: byte absolute $20; // Port A Input Pins
  5. DDRA: byte absolute $21; // Port A Data Direction Register
  6. PORTA: byte absolute $22; // Port A Data Register
  7. PINB: byte absolute $23; // Port B Input Pins
  8. DDRB: byte absolute $24; // Port B Data Direction Register
  9. PORTB: byte absolute $25; // Port B Data Register
  10. PINC: byte absolute $26; // Port C Input Pins
  11. DDRC: byte absolute $27; // Port C Data Direction Register
  12. PORTC: byte absolute $28; // Port C Data Register
  13. PIND: byte absolute $29; // Port D Input Pins
  14. DDRD: byte absolute $2A; // Port D Data Direction Register
  15. PORTD: byte absolute $2B; // Port D Data Register
  16. PINE: byte absolute $2C; // Port E Input Pins
  17. DDRE: byte absolute $2D; // Port E Data Direction Register
  18. PORTE: byte absolute $2E; // Port E Data Register
  19. TIFR0: byte absolute $35; // Timer/Counter0 Interrupt Flag register
  20. TIFR1: byte absolute $36; // Timer/Counter Interrupt Flag register
  21. TIFR2: byte absolute $37; // Timer/Counter Interrupt Flag Register
  22. TIFR3: byte absolute $38; // Timer/Counter Interrupt Flag register
  23. TIFR4: byte absolute $39; // Timer/Counter Interrupt Flag register
  24. PCIFR: byte absolute $3B; // Pin Change Interrupt Flag Register
  25. EIFR: byte absolute $3C; // External Interrupt Flag Register
  26. EIMSK: byte absolute $3D; // External Interrupt Mask Register
  27. GPIOR0: byte absolute $3E; // General Purpose IO Register 0
  28. EECR: byte absolute $3F; // EEPROM Control Register
  29. EEDR: byte absolute $40; // EEPROM Data Register
  30. EEAR: word absolute $41; // EEPROM Address Register Low Bytes
  31. EEARL: byte absolute $41; // EEPROM Address Register Low Bytes
  32. EEARH: byte absolute $42; // EEPROM Address Register Low Bytes;
  33. GTCCR: byte absolute $43; // General Timer/Counter Control Register
  34. TCCR0A: byte absolute $44; // Timer/Counter0 Control Register A
  35. TCCR0B: byte absolute $45; // Timer/Counter0 Control Register B
  36. TCNT0: byte absolute $46; // Timer/Counter0
  37. OCR0A: byte absolute $47; // Timer/Counter0 Output Compare Register
  38. OCR0B: byte absolute $48; // Timer/Counter0 Output Compare Register
  39. GPIOR1: byte absolute $4A; // General Purpose IO Register 1
  40. GPIOR2: byte absolute $4B; // General Purpose IO Register 2
  41. SPCR0: byte absolute $4C; // SPI Control Register
  42. SPSR0: byte absolute $4D; // SPI Status Register
  43. SPDR0: byte absolute $4E; // SPI Data Register
  44. ACSRB: byte absolute $4F; // Analog Comparator Control And Status Register B
  45. ACSR: byte absolute $50; // Analog Comparator Control And Status Register
  46. OCDR: byte absolute $51; // On-Chip Debug Related Register in I/O Memory
  47. SMCR: byte absolute $53; // Sleep Mode Control Register
  48. MCUSR: byte absolute $54; // MCU Status Register
  49. MCUCR: byte absolute $55; // MCU Control Register
  50. SPMCSR: byte absolute $57; // Store Program Memory Control Register
  51. SP: word absolute $5D; // Stack Pointer
  52. SPL: byte absolute $5D; // Stack Pointer
  53. SPH: byte absolute $5E; // Stack Pointer ;
  54. SREG: byte absolute $5F; // Status Register
  55. WDTCSR: byte absolute $60; // Watchdog Timer Control Register
  56. CLKPR: byte absolute $61;
  57. XFDCSR: byte absolute $62; // XOSC Failure Detection Control and Status Register
  58. PRR2: byte absolute $63; // Power Reduction Register2
  59. PRR0: byte absolute $64; // Power Reduction Register0
  60. PRR1: byte absolute $65; // Power Reduction Register1
  61. OSCCAL: byte absolute $66; // Oscillator Calibration Value
  62. PCICR: byte absolute $68; // Pin Change Interrupt Control Register
  63. EICRA: byte absolute $69; // External Interrupt Control Register A
  64. PCMSK0: byte absolute $6B; // Pin Change Mask Register 0
  65. PCMSK1: byte absolute $6C; // Pin Change Mask Register 1
  66. PCMSK2: byte absolute $6D; // Pin Change Mask Register 2
  67. TIMSK0: byte absolute $6E; // Timer/Counter0 Interrupt Mask Register
  68. TIMSK1: byte absolute $6F; // Timer/Counter1 Interrupt Mask Register
  69. TIMSK2: byte absolute $70; // Timer/Counter Interrupt Mask register
  70. TIMSK3: byte absolute $71; // Timer/Counter3 Interrupt Mask Register
  71. TIMSK4: byte absolute $72; // Timer/Counter4 Interrupt Mask Register
  72. PCMSK3: byte absolute $73; // Pin Change Mask Register 3
  73. PCMSK4: byte absolute $75; // Pin Change Mask Register 4
  74. ADC: word absolute $78; // ADC Data Register Bytes
  75. ADCL: byte absolute $78; // ADC Data Register Bytes
  76. ADCH: byte absolute $79; // ADC Data Register Bytes;
  77. ADCSRA: byte absolute $7A; // ADC Control and Status register A
  78. ADCSRB: byte absolute $7B; // ADC Control and Status register B
  79. ADMUX: byte absolute $7C; // ADC multiplexer Selection Register
  80. DIDR0: byte absolute $7E; // Digital Input Disable Register
  81. DIDR1: byte absolute $7F; // Digital Input Disable Register 1
  82. TCCR1A: byte absolute $80; // Timer/Counter1 Control Register A
  83. TCCR1B: byte absolute $81; // Timer/Counter1 Control Register B
  84. TCCR1C: byte absolute $82; // Timer/Counter1 Control Register C
  85. TCNT1: word absolute $84; // Timer/Counter1 Bytes
  86. TCNT1L: byte absolute $84; // Timer/Counter1 Bytes
  87. TCNT1H: byte absolute $85; // Timer/Counter1 Bytes;
  88. ICR1: word absolute $86; // Timer/Counter1 Input Capture Register Bytes
  89. ICR1L: byte absolute $86; // Timer/Counter1 Input Capture Register Bytes
  90. ICR1H: byte absolute $87; // Timer/Counter1 Input Capture Register Bytes;
  91. OCR1A: word absolute $88; // Timer/Counter1 Output Compare Register A Bytes
  92. OCR1AL: byte absolute $88; // Timer/Counter1 Output Compare Register A Bytes
  93. OCR1AH: byte absolute $89; // Timer/Counter1 Output Compare Register A Bytes;
  94. OCR1B: word absolute $8A; // Timer/Counter1 Output Compare Register B Bytes
  95. OCR1BL: byte absolute $8A; // Timer/Counter1 Output Compare Register B Bytes
  96. OCR1BH: byte absolute $8B; // Timer/Counter1 Output Compare Register B Bytes;
  97. TCCR3A: byte absolute $90; // Timer/Counter3 Control Register A
  98. TCCR3B: byte absolute $91; // Timer/Counter3 Control Register B
  99. TCCR3C: byte absolute $92; // Timer/Counter3 Control Register C
  100. TCNT3: word absolute $94; // Timer/Counter3 Bytes
  101. TCNT3L: byte absolute $94; // Timer/Counter3 Bytes
  102. TCNT3H: byte absolute $95; // Timer/Counter3 Bytes;
  103. ICR3: word absolute $96; // Timer/Counter3 Input Capture Register Bytes
  104. ICR3L: byte absolute $96; // Timer/Counter3 Input Capture Register Bytes
  105. ICR3H: byte absolute $97; // Timer/Counter3 Input Capture Register Bytes;
  106. OCR3A: word absolute $98; // Timer/Counter3 Output Compare Register A Bytes
  107. OCR3AL: byte absolute $98; // Timer/Counter3 Output Compare Register A Bytes
  108. OCR3AH: byte absolute $99; // Timer/Counter3 Output Compare Register A Bytes;
  109. OCR3B: word absolute $9A; // Timer/Counter3 Output Compare Register B Bytes
  110. OCR3BL: byte absolute $9A; // Timer/Counter3 Output Compare Register B Bytes
  111. OCR3BH: byte absolute $9B; // Timer/Counter3 Output Compare Register B Bytes;
  112. TCCR4A: byte absolute $A0; // Timer/Counter4 Control Register A
  113. TCCR4B: byte absolute $A1; // Timer/Counter4 Control Register B
  114. TCCR4C: byte absolute $A2; // Timer/Counter4 Control Register C
  115. TCNT4: word absolute $A4; // Timer/Counter4 Bytes
  116. TCNT4L: byte absolute $A4; // Timer/Counter4 Bytes
  117. TCNT4H: byte absolute $A5; // Timer/Counter4 Bytes;
  118. ICR4: word absolute $A6; // Timer/Counter4 Input Capture Register Bytes
  119. ICR4L: byte absolute $A6; // Timer/Counter4 Input Capture Register Bytes
  120. ICR4H: byte absolute $A7; // Timer/Counter4 Input Capture Register Bytes;
  121. OCR4A: word absolute $A8; // Timer/Counter4 Output Compare Register A Bytes
  122. OCR4AL: byte absolute $A8; // Timer/Counter4 Output Compare Register A Bytes
  123. OCR4AH: byte absolute $A9; // Timer/Counter4 Output Compare Register A Bytes;
  124. OCR4B: word absolute $AA; // Timer/Counter4 Output Compare Register B Bytes
  125. OCR4BL: byte absolute $AA; // Timer/Counter4 Output Compare Register B Bytes
  126. OCR4BH: byte absolute $AB; // Timer/Counter4 Output Compare Register B Bytes;
  127. SPCR1: byte absolute $AC; // SPI Control Register
  128. SPSR1: byte absolute $AD; // SPI Status Register
  129. SPDR1: byte absolute $AE; // SPI Data Register
  130. TCCR2A: byte absolute $B0; // Timer/Counter2 Control Register A
  131. TCCR2B: byte absolute $B1; // Timer/Counter2 Control Register B
  132. TCNT2: byte absolute $B2; // Timer/Counter2
  133. OCR2A: byte absolute $B3; // Timer/Counter2 Output Compare Register A
  134. OCR2B: byte absolute $B4; // Timer/Counter2 Output Compare Register B
  135. ASSR: byte absolute $B6; // Asynchronous Status Register
  136. TWBR0: byte absolute $B8; // TWI Bit Rate register
  137. TWSR0: byte absolute $B9; // TWI Status Register
  138. TWAR0: byte absolute $BA; // TWI (Slave) Address register
  139. TWDR0: byte absolute $BB; // TWI Data register
  140. TWCR0: byte absolute $BC; // TWI Control Register
  141. TWAMR0: byte absolute $BD; // TWI (Slave) Address Mask Register
  142. UCSR0A: byte absolute $C0; // USART Control and Status Register A
  143. UCSR0B: byte absolute $C1; // USART Control and Status Register B
  144. UCSR0C: byte absolute $C2; // USART Control and Status Register C
  145. UCSR0D: byte absolute $C3; // USART Control and Status Register D
  146. UBRR0: word absolute $C4; // USART Baud Rate Register Bytes
  147. UBRR0L: byte absolute $C4; // USART Baud Rate Register Bytes
  148. UBRR0H: byte absolute $C5; // USART Baud Rate Register Bytes;
  149. UDR0: byte absolute $C6; // USART I/O Data Register
  150. UCSR1A: byte absolute $C8; // USART Control and Status Register A
  151. UCSR1B: byte absolute $C9; // USART Control and Status Register B
  152. UCSR1C: byte absolute $CA; // USART Control and Status Register C
  153. UCSR1D: byte absolute $CB; // USART Control and Status Register D
  154. UBRR1: word absolute $CC; // USART Baud Rate Register Bytes
  155. UBRR1L: byte absolute $CC; // USART Baud Rate Register Bytes
  156. UBRR1H: byte absolute $CD; // USART Baud Rate Register Bytes;
  157. UDR1: byte absolute $CE; // USART I/O Data Register
  158. UCSR2A: byte absolute $D0; // USART Control and Status Register A
  159. UCSR2B: byte absolute $D1; // USART Control and Status Register B
  160. UCSR2C: byte absolute $D2; // USART Control and Status Register C
  161. UCSR2D: byte absolute $D3; // USART Control and Status Register D
  162. UBRR2: word absolute $D4; // USART Baud Rate Register Bytes
  163. UBRR2L: byte absolute $D4; // USART Baud Rate Register Bytes
  164. UBRR2H: byte absolute $D5; // USART Baud Rate Register Bytes;
  165. UDR2: byte absolute $D6; // USART I/O Data Register
  166. TWBR1: byte absolute $D8; // TWI Bit Rate register
  167. TWSR1: byte absolute $D9; // TWI Status Register
  168. TWAR1: byte absolute $DA; // TWI (Slave) Address register
  169. TWDR1: byte absolute $DB; // TWI Data register
  170. TWCR1: byte absolute $DC; // TWI Control Register
  171. TWAMR1: byte absolute $DD; // TWI (Slave) Address Mask Register
  172. const
  173. // Port A Data Register
  174. PA0 = $00;
  175. PA1 = $01;
  176. PA2 = $02;
  177. PA3 = $03;
  178. PA4 = $04;
  179. PA5 = $05;
  180. PA6 = $06;
  181. PA7 = $07;
  182. // Port B Data Register
  183. PB0 = $00;
  184. PB1 = $01;
  185. PB2 = $02;
  186. PB3 = $03;
  187. PB4 = $04;
  188. PB5 = $05;
  189. PB6 = $06;
  190. PB7 = $07;
  191. // Port C Data Register
  192. PC0 = $00;
  193. PC1 = $01;
  194. PC2 = $02;
  195. PC3 = $03;
  196. PC4 = $04;
  197. PC5 = $05;
  198. PC6 = $06;
  199. PC7 = $07;
  200. // Port D Data Register
  201. PD0 = $00;
  202. PD1 = $01;
  203. PD2 = $02;
  204. PD3 = $03;
  205. PD4 = $04;
  206. PD5 = $05;
  207. PD6 = $06;
  208. PD7 = $07;
  209. // Port E Data Register
  210. PE0 = $00;
  211. PE1 = $01;
  212. PE2 = $02;
  213. PE3 = $03;
  214. PE4 = $04;
  215. PE5 = $05;
  216. PE6 = $06;
  217. // Timer/Counter0 Interrupt Flag register
  218. TOV0 = $00;
  219. OCF0A = $01;
  220. OCF0B = $02;
  221. // Timer/Counter Interrupt Flag register
  222. TOV1 = $00;
  223. OCF1A = $01;
  224. OCF1B = $02;
  225. ICF1 = $05;
  226. // Timer/Counter Interrupt Flag Register
  227. TOV2 = $00;
  228. OCF2A = $01;
  229. OCF2B = $02;
  230. // Timer/Counter Interrupt Flag register
  231. TOV3 = $00;
  232. OCF3A = $01;
  233. OCF3B = $02;
  234. ICF3 = $05;
  235. // Timer/Counter Interrupt Flag register
  236. TOV4 = $00;
  237. OCF4A = $01;
  238. OCF4B = $02;
  239. ICF4 = $05;
  240. // Pin Change Interrupt Flag Register
  241. PCIF0 = $00; // Pin Change Interrupt Flags
  242. PCIF1 = $01; // Pin Change Interrupt Flags
  243. PCIF2 = $02; // Pin Change Interrupt Flags
  244. PCIF3 = $03; // Pin Change Interrupt Flags
  245. PCIF4 = $04; // Pin Change Interrupt Flags
  246. // External Interrupt Flag Register
  247. INTF0 = $00; // External Interrupt Flags
  248. INTF1 = $01; // External Interrupt Flags
  249. INTF2 = $02; // External Interrupt Flags
  250. // External Interrupt Mask Register
  251. INT0 = $00; // External Interrupt Request Enable
  252. INT1 = $01; // External Interrupt Request Enable
  253. INT2 = $02; // External Interrupt Request Enable
  254. // EEPROM Control Register
  255. EERE = $00;
  256. EEPE = $01;
  257. EEMPE = $02;
  258. EERIE = $03;
  259. EEPM0 = $04; // EEPROM Programming Mode Bits
  260. EEPM1 = $05; // EEPROM Programming Mode Bits
  261. // General Timer/Counter Control Register
  262. PSRSYNC = $00;
  263. PSRASY = $01;
  264. TSM = $07;
  265. // Timer/Counter0 Control Register A
  266. WGM00 = $00; // Waveform Generation Mode
  267. WGM01 = $01; // Waveform Generation Mode
  268. COM0B0 = $04; // Compare Match Output B Mode
  269. COM0B1 = $05; // Compare Match Output B Mode
  270. COM0A0 = $06; // Compare Match Output A Mode
  271. COM0A1 = $07; // Compare Match Output A Mode
  272. // Timer/Counter0 Control Register B
  273. CS00 = $00; // Clock Select
  274. CS01 = $01; // Clock Select
  275. CS02 = $02; // Clock Select
  276. WGM02 = $03;
  277. FOC0B = $06;
  278. FOC0A = $07;
  279. // SPI Control Register
  280. SPR0 = $00; // SPI Clock Rate Select
  281. SPR1 = $01; // SPI Clock Rate Select
  282. CPHA = $02;
  283. CPOL = $03;
  284. MSTR = $04;
  285. DORD = $05;
  286. SPE = $06;
  287. SPIE = $07;
  288. // SPI Status Register
  289. SPI2X = $00;
  290. WCOL = $06;
  291. SPIF = $07;
  292. // Analog Comparator Control And Status Register B
  293. ACOE = $00;
  294. // Analog Comparator Control And Status Register
  295. ACIS0 = $00; // Analog Comparator Interrupt Mode Select bits
  296. ACIS1 = $01; // Analog Comparator Interrupt Mode Select bits
  297. ACIC = $02;
  298. ACIE = $03;
  299. ACI = $04;
  300. ACO = $05;
  301. ACBG = $06;
  302. ACD = $07;
  303. // Sleep Mode Control Register
  304. SE = $00;
  305. SM0 = $01; // Sleep Mode Select bits
  306. SM1 = $02; // Sleep Mode Select bits
  307. SM2 = $03; // Sleep Mode Select bits
  308. // MCU Status Register
  309. PORF = $00;
  310. EXTRF = $01;
  311. BORF = $02;
  312. WDRF = $03;
  313. JTRF = $04;
  314. // MCU Control Register
  315. IVCE = $00;
  316. IVSEL = $01;
  317. PUD = $04;
  318. BODSE = $05;
  319. BODS = $06;
  320. JTD = $07;
  321. // Store Program Memory Control Register
  322. SPMEN = $00;
  323. PGERS = $01;
  324. PGWRT = $02;
  325. BLBSET = $03;
  326. RWWSRE = $04;
  327. SIGRD = $05;
  328. RWWSB = $06;
  329. SPMIE = $07;
  330. // Status Register
  331. C = $00;
  332. Z = $01;
  333. N = $02;
  334. V = $03;
  335. S = $04;
  336. H = $05;
  337. T = $06;
  338. I = $07;
  339. // Watchdog Timer Control Register
  340. WDE = $03;
  341. WDCE = $04;
  342. WDP0 = $00; // Watchdog Timer Prescaler Bits
  343. WDP1 = $01; // Watchdog Timer Prescaler Bits
  344. WDP2 = $02; // Watchdog Timer Prescaler Bits
  345. WDP3 = $05; // Watchdog Timer Prescaler Bits
  346. WDIE = $06;
  347. WDIF = $07;
  348. CLKPS0 = $00;
  349. CLKPS1 = $01;
  350. CLKPS2 = $02;
  351. CLKPS3 = $03;
  352. CLKPCE = $07;
  353. // XOSC Failure Detection Control and Status Register
  354. XFDIE = $00;
  355. XFDIF = $01;
  356. // Power Reduction Register2
  357. PRTWI1 = $00;
  358. PRSPI1 = $01;
  359. PRUSART2 = $02;
  360. PRPTC = $03;
  361. // Power Reduction Register0
  362. PRADC = $00;
  363. PRUSART0 = $01;
  364. PRSPI0 = $02;
  365. PRTIM1 = $03;
  366. PRUSART1 = $04;
  367. PRTIM0 = $05;
  368. PRTIM2 = $06;
  369. PRTWI0 = $07;
  370. // Power Reduction Register1
  371. PRTIM3 = $00;
  372. PRTIM4 = $01;
  373. // Oscillator Calibration Value
  374. OSCCAL0 = $00; // Oscillator Calibration
  375. OSCCAL1 = $01; // Oscillator Calibration
  376. OSCCAL2 = $02; // Oscillator Calibration
  377. OSCCAL3 = $03; // Oscillator Calibration
  378. OSCCAL4 = $04; // Oscillator Calibration
  379. OSCCAL5 = $05; // Oscillator Calibration
  380. OSCCAL6 = $06; // Oscillator Calibration
  381. OSCCAL7 = $07; // Oscillator Calibration
  382. // Pin Change Interrupt Control Register
  383. PCIE0 = $00; // Pin Change Interrupt Enables
  384. PCIE1 = $01; // Pin Change Interrupt Enables
  385. PCIE2 = $02; // Pin Change Interrupt Enables
  386. PCIE3 = $03; // Pin Change Interrupt Enables
  387. PCIE4 = $04; // Pin Change Interrupt Enables
  388. // External Interrupt Control Register A
  389. ISC00 = $00; // External Interrupt Sense Control Bit
  390. ISC01 = $01; // External Interrupt Sense Control Bit
  391. ISC10 = $02; // External Interrupt Sense Control Bit
  392. ISC11 = $03; // External Interrupt Sense Control Bit
  393. ISC20 = $04; // External Interrupt Sense Control Bit
  394. ISC21 = $05; // External Interrupt Sense Control Bit
  395. // Timer/Counter0 Interrupt Mask Register
  396. TOIE0 = $00;
  397. OCIE0A = $01;
  398. OCIE0B = $02;
  399. // Timer/Counter1 Interrupt Mask Register
  400. TOIE1 = $00;
  401. OCIE1A = $01;
  402. OCIE1B = $02;
  403. ICIE1 = $05;
  404. // Timer/Counter Interrupt Mask register
  405. TOIE2 = $00;
  406. OCIE2A = $01;
  407. OCIE2B = $02;
  408. // Timer/Counter3 Interrupt Mask Register
  409. TOIE3 = $00;
  410. OCIE3A = $01;
  411. OCIE3B = $02;
  412. ICIE3 = $05;
  413. // Timer/Counter4 Interrupt Mask Register
  414. TOIE4 = $00;
  415. OCIE4A = $01;
  416. OCIE4B = $02;
  417. ICIE4 = $05;
  418. // Pin Change Mask Register 4
  419. PCINT32 = $00; // Pin Change Enable Masks
  420. PCINT33 = $01; // Pin Change Enable Masks
  421. PCINT34 = $02; // Pin Change Enable Masks
  422. PCINT35 = $03; // Pin Change Enable Masks
  423. PCINT36 = $04; // Pin Change Enable Masks
  424. PCINT37 = $05; // Pin Change Enable Masks
  425. PCINT38 = $06; // Pin Change Enable Masks
  426. // ADC Control and Status register A
  427. ADPS0 = $00; // ADC Prescaler Select Bits
  428. ADPS1 = $01; // ADC Prescaler Select Bits
  429. ADPS2 = $02; // ADC Prescaler Select Bits
  430. ADIE = $03;
  431. ADIF = $04;
  432. ADATE = $05;
  433. ADSC = $06;
  434. ADEN = $07;
  435. // ADC Control and Status register B
  436. ADTS0 = $00; // ADC Auto Trigger Source bits
  437. ADTS1 = $01; // ADC Auto Trigger Source bits
  438. ADTS2 = $02; // ADC Auto Trigger Source bits
  439. ACME = $06;
  440. GPIOEN = $07;
  441. // ADC multiplexer Selection Register
  442. MUX0 = $00; // Analog Channel and Gain Selection Bits
  443. MUX1 = $01; // Analog Channel and Gain Selection Bits
  444. MUX2 = $02; // Analog Channel and Gain Selection Bits
  445. MUX3 = $03; // Analog Channel and Gain Selection Bits
  446. MUX4 = $04; // Analog Channel and Gain Selection Bits
  447. ADLAR = $05;
  448. REFS0 = $06; // Reference Selection Bits
  449. REFS1 = $07; // Reference Selection Bits
  450. // Digital Input Disable Register
  451. ADC0D = $00;
  452. ADC1D = $01;
  453. ADC2D = $02;
  454. ADC3D = $03;
  455. ADC4D = $04;
  456. ADC5D = $05;
  457. ADC6D = $06;
  458. ADC7D = $07;
  459. // Digital Input Disable Register 1
  460. AIN0D = $00;
  461. AIN1D = $01;
  462. // Timer/Counter1 Control Register A
  463. WGM10 = $00; // Pulse Width Modulator Select Bits
  464. WGM11 = $01; // Pulse Width Modulator Select Bits
  465. COM1B0 = $04; // Compare Output Mode 1B, bits
  466. COM1B1 = $05; // Compare Output Mode 1B, bits
  467. COM1A0 = $06; // Compare Output Mode 1A, bits
  468. COM1A1 = $07; // Compare Output Mode 1A, bits
  469. // Timer/Counter1 Control Register B
  470. CS10 = $00; // Clock Select1 bits
  471. CS11 = $01; // Clock Select1 bits
  472. CS12 = $02; // Clock Select1 bits
  473. ICES1 = $06;
  474. ICNC1 = $07;
  475. // Timer/Counter1 Control Register C
  476. FOC1B = $06;
  477. FOC1A = $07;
  478. // Timer/Counter3 Control Register A
  479. WGM30 = $00; // Pulse Width Modulator Select Bits
  480. WGM31 = $01; // Pulse Width Modulator Select Bits
  481. COM3B0 = $04; // Compare Output Mode 3B, bits
  482. COM3B1 = $05; // Compare Output Mode 3B, bits
  483. COM3A0 = $06; // Compare Output Mode 3A, bits
  484. COM3A1 = $07; // Compare Output Mode 3A, bits
  485. // Timer/Counter3 Control Register B
  486. CS30 = $00; // Clock Select3 bits
  487. CS31 = $01; // Clock Select3 bits
  488. CS32 = $02; // Clock Select3 bits
  489. ICES3 = $06;
  490. ICNC3 = $07;
  491. // Timer/Counter3 Control Register C
  492. FOC3B = $06;
  493. FOC3A = $07;
  494. // Timer/Counter4 Control Register A
  495. WGM40 = $00; // Pulse Width Modulator Select Bits
  496. WGM41 = $01; // Pulse Width Modulator Select Bits
  497. COM4B0 = $04; // Compare Output Mode 4B, bits
  498. COM4B1 = $05; // Compare Output Mode 4B, bits
  499. COM4A0 = $06; // Compare Output Mode 4A, bits
  500. COM4A1 = $07; // Compare Output Mode 4A, bits
  501. // Timer/Counter4 Control Register B
  502. CS40 = $00; // Clock Select4 bits
  503. CS41 = $01; // Clock Select4 bits
  504. CS42 = $02; // Clock Select4 bits
  505. ICES4 = $06;
  506. ICNC4 = $07;
  507. // Timer/Counter4 Control Register C
  508. FOC4B = $06;
  509. FOC4A = $07;
  510. // Timer/Counter2 Control Register A
  511. WGM20 = $00; // Waveform Genration Mode
  512. WGM21 = $01; // Waveform Genration Mode
  513. COM2B0 = $04; // Compare Output Mode 2B bits
  514. COM2B1 = $05; // Compare Output Mode 2B bits
  515. COM2A0 = $06; // Compare Output Mode 2A bits
  516. COM2A1 = $07; // Compare Output Mode 2A bits
  517. // Timer/Counter2 Control Register B
  518. CS20 = $00; // Clock Select bits
  519. CS21 = $01; // Clock Select bits
  520. CS22 = $02; // Clock Select bits
  521. WGM22 = $03;
  522. FOC2B = $06;
  523. FOC2A = $07;
  524. // Asynchronous Status Register
  525. TCR2BUB = $00;
  526. TCR2AUB = $01;
  527. OCR2BUB = $02;
  528. OCR2AUB = $03;
  529. TCN2UB = $04;
  530. AS2 = $05;
  531. EXCLK = $06;
  532. // TWI Status Register
  533. TWPS0 = $00; // TWI Prescaler
  534. TWPS1 = $01; // TWI Prescaler
  535. TWS03 = $03; // TWI Status
  536. TWS04 = $04; // TWI Status
  537. TWS05 = $05; // TWI Status
  538. TWS06 = $06; // TWI Status
  539. TWS07 = $07; // TWI Status
  540. // TWI (Slave) Address register
  541. TWGCE = $00;
  542. TWA0 = $01; // TWI (Slave) Address register Bits
  543. TWA1 = $02; // TWI (Slave) Address register Bits
  544. TWA2 = $03; // TWI (Slave) Address register Bits
  545. TWA3 = $04; // TWI (Slave) Address register Bits
  546. TWA4 = $05; // TWI (Slave) Address register Bits
  547. TWA5 = $06; // TWI (Slave) Address register Bits
  548. TWA6 = $07; // TWI (Slave) Address register Bits
  549. // TWI Control Register
  550. TWIE = $00;
  551. TWEN = $02;
  552. TWWC = $03;
  553. TWSTO = $04;
  554. TWSTA = $05;
  555. TWEA = $06;
  556. TWINT = $07;
  557. // TWI (Slave) Address Mask Register
  558. TWAM00 = $01;
  559. TWAM01 = $02;
  560. TWAM02 = $03;
  561. TWAM03 = $04;
  562. TWAM04 = $05;
  563. TWAM05 = $06;
  564. TWAM06 = $07;
  565. // USART Control and Status Register A
  566. MPCM = $00;
  567. U2X = $01;
  568. UPE = $02;
  569. DOR = $03;
  570. FE = $04;
  571. UDRE = $05;
  572. TXC = $06;
  573. RXC = $07;
  574. // USART Control and Status Register B
  575. TXB8 = $00;
  576. RXB8 = $01;
  577. UCSZ2 = $02;
  578. TXEN = $03;
  579. RXEN = $04;
  580. UDRIE = $05;
  581. TXCIE = $06;
  582. RXCIE = $07;
  583. // USART Control and Status Register C
  584. UCPOL = $00;
  585. UCSZ0 = $01; // Character Size
  586. UCSZ1 = $02; // Character Size
  587. USBS = $03;
  588. UPM0 = $04; // Parity Mode Bits
  589. UPM1 = $05; // Parity Mode Bits
  590. UMSEL0 = $06; // USART Mode Select
  591. UMSEL1 = $07; // USART Mode Select
  592. // USART Control and Status Register D
  593. SFDE = $05;
  594. RXS = $06;
  595. RXSIE = $07;
  596. // TWI (Slave) Address Mask Register
  597. TWAM10 = $01;
  598. TWAM11 = $02;
  599. TWAM12 = $03;
  600. TWAM13 = $04;
  601. TWAM14 = $05;
  602. TWAM15 = $06;
  603. TWAM16 = $07;
  604. implementation
  605. {$i avrcommon.inc}
  606. procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
  607. procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1
  608. procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 3 External Interrupt Request 2
  609. procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 4 Pin Change Interrupt Request 0
  610. procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 5 Pin Change Interrupt Request 1
  611. procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 6 Pin Change Interrupt Request 2
  612. procedure PCINT3_ISR; external name 'PCINT3_ISR'; // Interrupt 7 Pin Change Interrupt Request 3
  613. procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 8 Watchdog Time-out Interrupt
  614. procedure TIMER2_COMPA_ISR; external name 'TIMER2_COMPA_ISR'; // Interrupt 9 Timer/Counter2 Compare Match A
  615. procedure TIMER2_COMPB_ISR; external name 'TIMER2_COMPB_ISR'; // Interrupt 10 Timer/Counter2 Compare Match B
  616. procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 11 Timer/Counter2 Overflow
  617. procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 12 Timer/Counter1 Capture Event
  618. procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 13 Timer/Counter1 Compare Match A
  619. procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 14 Timer/Counter1 Compare Match B
  620. procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 15 Timer/Counter1 Overflow
  621. procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 16 Timer/Counter0 Compare Match A
  622. procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 17 Timer/Counter0 Compare Match B
  623. procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 18 Timer/Counter0 Overflow
  624. procedure SPI0_STC_ISR; external name 'SPI0_STC_ISR'; // Interrupt 19 SPI0 Serial Transfer Complete
  625. procedure USART0_RX_ISR; external name 'USART0_RX_ISR'; // Interrupt 20 USART0 Rx Complete
  626. procedure USART0_UDRE_ISR; external name 'USART0_UDRE_ISR'; // Interrupt 21 USART0 Data register Empty
  627. procedure USART0_TX_ISR; external name 'USART0_TX_ISR'; // Interrupt 22 USART0 Tx Complete
  628. procedure ANALOG_COMP_ISR; external name 'ANALOG_COMP_ISR'; // Interrupt 23 Analog Comparator
  629. procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 24 ADC Conversion Complete
  630. procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 25 EEPROM Ready
  631. procedure TWI0_ISR; external name 'TWI0_ISR'; // Interrupt 26 2-wire Serial Interface 0
  632. procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 27 Store Program Memory Read
  633. procedure USART1_RX_ISR; external name 'USART1_RX_ISR'; // Interrupt 28 USART1 RX complete
  634. procedure USART1_UDRE_ISR; external name 'USART1_UDRE_ISR'; // Interrupt 29 USART1 Data Register Empty
  635. procedure USART1_TX_ISR; external name 'USART1_TX_ISR'; // Interrupt 30 USART1 TX complete
  636. procedure TIMER3_CAPT_ISR; external name 'TIMER3_CAPT_ISR'; // Interrupt 31 Timer/Counter3 Capture Event
  637. procedure TIMER3_COMPA_ISR; external name 'TIMER3_COMPA_ISR'; // Interrupt 32 Timer/Counter3 Compare Match A
  638. procedure TIMER3_COMPB_ISR; external name 'TIMER3_COMPB_ISR'; // Interrupt 33 Timer/Counter3 Compare Match B
  639. procedure TIMER3_OVF_ISR; external name 'TIMER3_OVF_ISR'; // Interrupt 34 Timer/Counter3 Overflow
  640. procedure USART0_RXS_ISR; external name 'USART0_RXS_ISR'; // Interrupt 35 USART0 RX start edge detect
  641. procedure USART0_START_ISR; external name 'USART0_START_ISR'; // Interrupt 35 USART0 RX start edge detect
  642. procedure USART1_RXS_ISR; external name 'USART1_RXS_ISR'; // Interrupt 36 USART1 RX start edge detect
  643. procedure USART1_START_ISR; external name 'USART1_START_ISR'; // Interrupt 36 USART1 RX start edge detect
  644. procedure PCINT4_ISR; external name 'PCINT4_ISR'; // Interrupt 37 Pin Change Interrupt Request 4
  645. procedure XOSCFD_ISR; external name 'XOSCFD_ISR'; // Interrupt 38 Crystal failure detect
  646. procedure PTC_EOC_ISR; external name 'PTC_EOC_ISR'; // Interrupt 39 PTC end of conversion
  647. procedure PTC_WCOMP_ISR; external name 'PTC_WCOMP_ISR'; // Interrupt 40 PTC window comparator interrupt
  648. procedure SPI1_STC_ISR; external name 'SPI1_STC_ISR'; // Interrupt 41 SPI1 Serial Transfer Complete
  649. procedure TWI1_ISR; external name 'TWI1_ISR'; // Interrupt 42 2-wire Serial Interface 1
  650. procedure TIMER4_CAPT_ISR; external name 'TIMER4_CAPT_ISR'; // Interrupt 43 Timer/Counter4 Capture Event
  651. procedure TIMER4_COMPA_ISR; external name 'TIMER4_COMPA_ISR'; // Interrupt 44 Timer/Counter4 Compare Match A
  652. procedure TIMER4_COMPB_ISR; external name 'TIMER4_COMPB_ISR'; // Interrupt 45 Timer/Counter4 Compare Match B
  653. procedure TIMER4_OVF_ISR; external name 'TIMER4_OVF_ISR'; // Interrupt 46 Timer/Counter4 Overflow
  654. procedure USART2_RX_ISR; external name 'USART2_RX_ISR'; // Interrupt 47 USART2 Rx Complete
  655. procedure USART2_UDRE_ISR; external name 'USART2_UDRE_ISR'; // Interrupt 48 USART2 Data register Empty
  656. procedure USART2_TX_ISR; external name 'USART2_TX_ISR'; // Interrupt 49 USART2 Tx Complete
  657. procedure USART2_RXS_ISR; external name 'USART2_RXS_ISR'; // Interrupt 50 USART2 RX start edge detect
  658. procedure USART2_START_ISR; external name 'USART2_START_ISR'; // Interrupt 50 USART2 RX start edge detect
  659. procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';
  660. asm
  661. jmp __dtors_end
  662. jmp INT0_ISR
  663. jmp INT1_ISR
  664. jmp INT2_ISR
  665. jmp PCINT0_ISR
  666. jmp PCINT1_ISR
  667. jmp PCINT2_ISR
  668. jmp PCINT3_ISR
  669. jmp WDT_ISR
  670. jmp TIMER2_COMPA_ISR
  671. jmp TIMER2_COMPB_ISR
  672. jmp TIMER2_OVF_ISR
  673. jmp TIMER1_CAPT_ISR
  674. jmp TIMER1_COMPA_ISR
  675. jmp TIMER1_COMPB_ISR
  676. jmp TIMER1_OVF_ISR
  677. jmp TIMER0_COMPA_ISR
  678. jmp TIMER0_COMPB_ISR
  679. jmp TIMER0_OVF_ISR
  680. jmp SPI0_STC_ISR
  681. jmp USART0_RX_ISR
  682. jmp USART0_UDRE_ISR
  683. jmp USART0_TX_ISR
  684. jmp ANALOG_COMP_ISR
  685. jmp ADC_ISR
  686. jmp EE_READY_ISR
  687. jmp TWI0_ISR
  688. jmp SPM_READY_ISR
  689. jmp USART1_RX_ISR
  690. jmp USART1_UDRE_ISR
  691. jmp USART1_TX_ISR
  692. jmp TIMER3_CAPT_ISR
  693. jmp TIMER3_COMPA_ISR
  694. jmp TIMER3_COMPB_ISR
  695. jmp TIMER3_OVF_ISR
  696. jmp USART0_RXS_ISR
  697. jmp USART0_START_ISR
  698. jmp USART1_RXS_ISR
  699. jmp USART1_START_ISR
  700. jmp PCINT4_ISR
  701. jmp XOSCFD_ISR
  702. jmp PTC_EOC_ISR
  703. jmp PTC_WCOMP_ISR
  704. jmp SPI1_STC_ISR
  705. jmp TWI1_ISR
  706. jmp TIMER4_CAPT_ISR
  707. jmp TIMER4_COMPA_ISR
  708. jmp TIMER4_COMPB_ISR
  709. jmp TIMER4_OVF_ISR
  710. jmp USART2_RX_ISR
  711. jmp USART2_UDRE_ISR
  712. jmp USART2_TX_ISR
  713. jmp USART2_RXS_ISR
  714. jmp USART2_START_ISR
  715. .weak INT0_ISR
  716. .weak INT1_ISR
  717. .weak INT2_ISR
  718. .weak PCINT0_ISR
  719. .weak PCINT1_ISR
  720. .weak PCINT2_ISR
  721. .weak PCINT3_ISR
  722. .weak WDT_ISR
  723. .weak TIMER2_COMPA_ISR
  724. .weak TIMER2_COMPB_ISR
  725. .weak TIMER2_OVF_ISR
  726. .weak TIMER1_CAPT_ISR
  727. .weak TIMER1_COMPA_ISR
  728. .weak TIMER1_COMPB_ISR
  729. .weak TIMER1_OVF_ISR
  730. .weak TIMER0_COMPA_ISR
  731. .weak TIMER0_COMPB_ISR
  732. .weak TIMER0_OVF_ISR
  733. .weak SPI0_STC_ISR
  734. .weak USART0_RX_ISR
  735. .weak USART0_UDRE_ISR
  736. .weak USART0_TX_ISR
  737. .weak ANALOG_COMP_ISR
  738. .weak ADC_ISR
  739. .weak EE_READY_ISR
  740. .weak TWI0_ISR
  741. .weak SPM_READY_ISR
  742. .weak USART1_RX_ISR
  743. .weak USART1_UDRE_ISR
  744. .weak USART1_TX_ISR
  745. .weak TIMER3_CAPT_ISR
  746. .weak TIMER3_COMPA_ISR
  747. .weak TIMER3_COMPB_ISR
  748. .weak TIMER3_OVF_ISR
  749. .weak USART0_RXS_ISR
  750. .weak USART0_START_ISR
  751. .weak USART1_RXS_ISR
  752. .weak USART1_START_ISR
  753. .weak PCINT4_ISR
  754. .weak XOSCFD_ISR
  755. .weak PTC_EOC_ISR
  756. .weak PTC_WCOMP_ISR
  757. .weak SPI1_STC_ISR
  758. .weak TWI1_ISR
  759. .weak TIMER4_CAPT_ISR
  760. .weak TIMER4_COMPA_ISR
  761. .weak TIMER4_COMPB_ISR
  762. .weak TIMER4_OVF_ISR
  763. .weak USART2_RX_ISR
  764. .weak USART2_UDRE_ISR
  765. .weak USART2_TX_ISR
  766. .weak USART2_RXS_ISR
  767. .weak USART2_START_ISR
  768. .set INT0_ISR, Default_IRQ_handler
  769. .set INT1_ISR, Default_IRQ_handler
  770. .set INT2_ISR, Default_IRQ_handler
  771. .set PCINT0_ISR, Default_IRQ_handler
  772. .set PCINT1_ISR, Default_IRQ_handler
  773. .set PCINT2_ISR, Default_IRQ_handler
  774. .set PCINT3_ISR, Default_IRQ_handler
  775. .set WDT_ISR, Default_IRQ_handler
  776. .set TIMER2_COMPA_ISR, Default_IRQ_handler
  777. .set TIMER2_COMPB_ISR, Default_IRQ_handler
  778. .set TIMER2_OVF_ISR, Default_IRQ_handler
  779. .set TIMER1_CAPT_ISR, Default_IRQ_handler
  780. .set TIMER1_COMPA_ISR, Default_IRQ_handler
  781. .set TIMER1_COMPB_ISR, Default_IRQ_handler
  782. .set TIMER1_OVF_ISR, Default_IRQ_handler
  783. .set TIMER0_COMPA_ISR, Default_IRQ_handler
  784. .set TIMER0_COMPB_ISR, Default_IRQ_handler
  785. .set TIMER0_OVF_ISR, Default_IRQ_handler
  786. .set SPI0_STC_ISR, Default_IRQ_handler
  787. .set USART0_RX_ISR, Default_IRQ_handler
  788. .set USART0_UDRE_ISR, Default_IRQ_handler
  789. .set USART0_TX_ISR, Default_IRQ_handler
  790. .set ANALOG_COMP_ISR, Default_IRQ_handler
  791. .set ADC_ISR, Default_IRQ_handler
  792. .set EE_READY_ISR, Default_IRQ_handler
  793. .set TWI0_ISR, Default_IRQ_handler
  794. .set SPM_READY_ISR, Default_IRQ_handler
  795. .set USART1_RX_ISR, Default_IRQ_handler
  796. .set USART1_UDRE_ISR, Default_IRQ_handler
  797. .set USART1_TX_ISR, Default_IRQ_handler
  798. .set TIMER3_CAPT_ISR, Default_IRQ_handler
  799. .set TIMER3_COMPA_ISR, Default_IRQ_handler
  800. .set TIMER3_COMPB_ISR, Default_IRQ_handler
  801. .set TIMER3_OVF_ISR, Default_IRQ_handler
  802. .set USART0_RXS_ISR, Default_IRQ_handler
  803. .set USART0_START_ISR, Default_IRQ_handler
  804. .set USART1_RXS_ISR, Default_IRQ_handler
  805. .set USART1_START_ISR, Default_IRQ_handler
  806. .set PCINT4_ISR, Default_IRQ_handler
  807. .set XOSCFD_ISR, Default_IRQ_handler
  808. .set PTC_EOC_ISR, Default_IRQ_handler
  809. .set PTC_WCOMP_ISR, Default_IRQ_handler
  810. .set SPI1_STC_ISR, Default_IRQ_handler
  811. .set TWI1_ISR, Default_IRQ_handler
  812. .set TIMER4_CAPT_ISR, Default_IRQ_handler
  813. .set TIMER4_COMPA_ISR, Default_IRQ_handler
  814. .set TIMER4_COMPB_ISR, Default_IRQ_handler
  815. .set TIMER4_OVF_ISR, Default_IRQ_handler
  816. .set USART2_RX_ISR, Default_IRQ_handler
  817. .set USART2_UDRE_ISR, Default_IRQ_handler
  818. .set USART2_TX_ISR, Default_IRQ_handler
  819. .set USART2_RXS_ISR, Default_IRQ_handler
  820. .set USART2_START_ISR, Default_IRQ_handler
  821. end;
  822. end.