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atmega406.pp 18 KB

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  1. unit ATmega406;
  2. interface
  3. var
  4. PINA: byte absolute $20; // Port A Input Pins
  5. DDRA: byte absolute $21; // Port A Data Direction Register
  6. PORTA: byte absolute $22; // Port A Data Register
  7. PINB: byte absolute $23; // Port B Input Pins
  8. DDRB: byte absolute $24; // Port B Data Direction Register
  9. PORTB: byte absolute $25; // Port B Data Register
  10. PORTC: byte absolute $28; // Port C Data Register
  11. PIND: byte absolute $29; // Input Pins, Port D
  12. DDRD: byte absolute $2A; // Data Direction Register, Port D
  13. PORTD: byte absolute $2B; // Data Register, Port D
  14. TIFR0: byte absolute $35; // Timer/Counter Interrupt Flag register
  15. TIFR1: byte absolute $36; // Timer/Counter Interrupt Flag register
  16. PCIFR: byte absolute $3B; // Pin Change Interrupt Flag Register
  17. EIFR: byte absolute $3C; // External Interrupt Flag Register
  18. EIMSK: byte absolute $3D; // External Interrupt Mask Register
  19. GPIOR0: byte absolute $3E; // General Purpose IO Register 0
  20. EECR: byte absolute $3F; // EEPROM Control Register
  21. EEDR: byte absolute $40; // EEPROM Data Register
  22. EEAR: word absolute $41; // EEPROM Address Register Bytes
  23. EEARL: byte absolute $41; // EEPROM Address Register Bytes
  24. EEARH: byte absolute $42; // EEPROM Address Register Bytes;
  25. GTCCR: byte absolute $43; // General Timer/Counter Control Register
  26. TCCR0A: byte absolute $44; // Timer/Counter0 Control Register
  27. TCCR0B: byte absolute $45; // Timer/Counter0 Control Register
  28. TCNT0: byte absolute $46; // Timer Counter 0
  29. OCR0A: byte absolute $47; // Output compare Register A
  30. OCR0B: byte absolute $48; // Output compare Register B
  31. GPIOR1: byte absolute $4A; // General Purpose IO Register 1
  32. GPIOR2: byte absolute $4B; // General Purpose IO Register 2
  33. SMCR: byte absolute $53; // Sleep Mode Control Register
  34. MCUSR: byte absolute $54; // MCU Status Register
  35. MCUCR: byte absolute $55; // MCU Control Register
  36. SPMCSR: byte absolute $57; // Store Program Memory Control Register
  37. SP: word absolute $5D; // Stack Pointer
  38. SPL: byte absolute $5D; // Stack Pointer
  39. SPH: byte absolute $5E; // Stack Pointer ;
  40. SREG: byte absolute $5F; // Status Register
  41. WDTCSR: byte absolute $60; // Watchdog Timer Control Register
  42. WUTCSR: byte absolute $62; // Wake-up Timer Control Register
  43. PRR0: byte absolute $64; // Power Reduction Register 0
  44. FOSCCAL: byte absolute $66; // Fast Oscillator Calibration Value
  45. PCICR: byte absolute $68; // Pin Change Interrupt Control Register
  46. EICRA: byte absolute $69; // External Interrupt Control Register
  47. PCMSK0: byte absolute $6B; // Pin Change Enable Mask Register 0
  48. PCMSK1: byte absolute $6C; // Pin Change Enable Mask Register 1
  49. TIMSK0: byte absolute $6E; // Timer/Counter Interrupt Mask Register
  50. TIMSK1: byte absolute $6F; // Timer/Counter Interrupt Mask Register
  51. VADC: word absolute $78; // VADC Data Register Bytes
  52. VADCL: byte absolute $78; // VADC Data Register Bytes
  53. VADCH: byte absolute $79; // VADC Data Register Bytes;
  54. VADCSR: byte absolute $7A; // The VADC Control and Status register
  55. VADMUX: byte absolute $7C; // The VADC multiplexer Selection Register
  56. DIDR0: byte absolute $7E; // Digital Input Disable Register
  57. TCCR1B: byte absolute $81; // Timer/Counter1 Control Register B
  58. TCNT1: word absolute $84; // Timer Counter 1 Bytes
  59. TCNT1L: byte absolute $84; // Timer Counter 1 Bytes
  60. TCNT1H: byte absolute $85; // Timer Counter 1 Bytes;
  61. OCR1AL: byte absolute $88; // Output Compare Register 1A Low byte
  62. OCR1AH: byte absolute $89; // Output Compare Register 1A High byte
  63. TWBR: byte absolute $B8; // TWI Bit Rate register
  64. TWSR: byte absolute $B9; // TWI Status Register
  65. TWAR: byte absolute $BA; // TWI (Slave) Address register
  66. TWDR: byte absolute $BB; // TWI Data register
  67. TWCR: byte absolute $BC; // TWI Control Register
  68. TWAMR: byte absolute $BD; // TWI (Slave) Address Mask Register
  69. TWBCSR: byte absolute $BE; // TWI Bus Control and Status Register
  70. CCSR: byte absolute $C0; // Clock Control and Status Register
  71. BGCCR: byte absolute $D0; // Bandgap Calibration Register
  72. BGCRR: byte absolute $D1; // Bandgap Calibration of Resistor Ladder
  73. CADAC0: byte absolute $E0; // ADC Accumulate Current
  74. CADAC1: byte absolute $E1; // ADC Accumulate Current
  75. CADAC2: byte absolute $E2; // ADC Accumulate Current
  76. CADAC3: byte absolute $E3; // ADC Accumulate Current
  77. CADCSRA: byte absolute $E4; // CC-ADC Control and Status Register A
  78. CADCSRB: byte absolute $E5; // CC-ADC Control and Status Register B
  79. CADRCC: byte absolute $E6; // CC-ADC Regular Charge Current
  80. CADRDC: byte absolute $E7; // CC-ADC Regular Discharge Current
  81. CADIC: word absolute $E8; // CC-ADC Instantaneous Current
  82. CADICL: byte absolute $E8; // CC-ADC Instantaneous Current
  83. CADICH: byte absolute $E9; // CC-ADC Instantaneous Current;
  84. FCSR: byte absolute $F0;
  85. CBCR: byte absolute $F1; // Cell Balancing Control Register
  86. BPIR: byte absolute $F2; // Battery Protection Interrupt Register
  87. BPDUV: byte absolute $F3; // Battery Protection Deep Under Voltage Register
  88. BPSCD: byte absolute $F4; // Battery Protection Short-Circuit Detection Level Register
  89. BPOCD: byte absolute $F5; // Battery Protection OverCurrent Detection Level Register
  90. CBPTR: byte absolute $F6; // Current Battery Protection Timing Register
  91. BPCR: byte absolute $F7; // Battery Protection Control Register
  92. BPPLR: byte absolute $F8; // Battery Protection Parameter Lock Register
  93. const
  94. // Port A Data Register
  95. PA0 = $00;
  96. PA1 = $01;
  97. PA2 = $02;
  98. PA3 = $03;
  99. PA4 = $04;
  100. PA5 = $05;
  101. PA6 = $06;
  102. PA7 = $07;
  103. // Port B Data Register
  104. PB0 = $00;
  105. PB1 = $01;
  106. PB2 = $02;
  107. PB3 = $03;
  108. PB4 = $04;
  109. PB5 = $05;
  110. PB6 = $06;
  111. PB7 = $07;
  112. // Port C Data Register
  113. PC0 = $00;
  114. // Data Register, Port D
  115. PD0 = $00;
  116. PD1 = $01;
  117. // Timer/Counter Interrupt Flag register
  118. TOV0 = $00;
  119. OCF0A = $01;
  120. OCF0B = $02;
  121. // Timer/Counter Interrupt Flag register
  122. TOV1 = $00;
  123. OCF1A = $01;
  124. // Pin Change Interrupt Flag Register
  125. PCIF0 = $00; // Pin Change Interrupt Flags
  126. PCIF1 = $01; // Pin Change Interrupt Flags
  127. // External Interrupt Flag Register
  128. INTF0 = $00; // External Interrupt Flags
  129. INTF1 = $01; // External Interrupt Flags
  130. INTF2 = $02; // External Interrupt Flags
  131. INTF3 = $03; // External Interrupt Flags
  132. // External Interrupt Mask Register
  133. INT0 = $00; // External Interrupt Request 1 Enable
  134. INT1 = $01; // External Interrupt Request 1 Enable
  135. INT2 = $02; // External Interrupt Request 1 Enable
  136. INT3 = $03; // External Interrupt Request 1 Enable
  137. // EEPROM Control Register
  138. EERE = $00;
  139. EEPE = $01;
  140. EEMPE = $02;
  141. EERIE = $03;
  142. EEPM0 = $04; // EEPROM Programming Mode Bits
  143. EEPM1 = $05; // EEPROM Programming Mode Bits
  144. // General Timer/Counter Control Register
  145. PSRSYNC = $00;
  146. TSM = $07;
  147. // Timer/Counter0 Control Register
  148. WGM00 = $00; // Clock Select0 bits
  149. WGM01 = $01; // Clock Select0 bits
  150. COM0B0 = $04;
  151. COM0B1 = $05;
  152. COM0A0 = $06; // Force Output Compare
  153. COM0A1 = $07; // Force Output Compare
  154. // Timer/Counter0 Control Register
  155. CS00 = $00; // Clock Select0 bits
  156. CS01 = $01; // Clock Select0 bits
  157. CS02 = $02; // Clock Select0 bits
  158. WGM02 = $03;
  159. FOC0B = $06;
  160. FOC0A = $07;
  161. // Output compare Register A
  162. OCR0A0 = $00;
  163. OCR0A1 = $01;
  164. OCR0A2 = $02;
  165. OCR0A3 = $03;
  166. OCR0A4 = $04;
  167. OCR0A5 = $05;
  168. OCR0A6 = $06;
  169. OCR0A7 = $07;
  170. // Output compare Register B
  171. OCR0B0 = $00;
  172. OCR0B1 = $01;
  173. OCR0B2 = $02;
  174. OCR0B3 = $03;
  175. OCR0B4 = $04;
  176. OCR0B5 = $05;
  177. OCR0B6 = $06;
  178. OCR0B7 = $07;
  179. // Sleep Mode Control Register
  180. SE = $00;
  181. SM0 = $01; // Sleep Mode Select bits
  182. SM1 = $02; // Sleep Mode Select bits
  183. SM2 = $03; // Sleep Mode Select bits
  184. // MCU Status Register
  185. PORF = $00;
  186. EXTRF = $01;
  187. BODRF = $02;
  188. WDRF = $03;
  189. JTRF = $04;
  190. // MCU Control Register
  191. IVCE = $00;
  192. IVSEL = $01;
  193. PUD = $04;
  194. JTD = $07;
  195. // Store Program Memory Control Register
  196. SPMEN = $00;
  197. PGERS = $01;
  198. PGWRT = $02;
  199. BLBSET = $03;
  200. RWWSRE = $04;
  201. SIGRD = $05;
  202. RWWSB = $06;
  203. SPMIE = $07;
  204. // Status Register
  205. C = $00;
  206. Z = $01;
  207. N = $02;
  208. V = $03;
  209. S = $04;
  210. H = $05;
  211. T = $06;
  212. I = $07;
  213. // Watchdog Timer Control Register
  214. WDE = $03;
  215. WDCE = $04;
  216. WDP0 = $00; // Watchdog Timer Prescaler Bits
  217. WDP1 = $01; // Watchdog Timer Prescaler Bits
  218. WDP2 = $02; // Watchdog Timer Prescaler Bits
  219. WDP3 = $05; // Watchdog Timer Prescaler Bits
  220. WDIE = $06;
  221. WDIF = $07;
  222. // Wake-up Timer Control Register
  223. WUTP0 = $00; // Wake-up Timer Prescaler Bits
  224. WUTP1 = $01; // Wake-up Timer Prescaler Bits
  225. WUTP2 = $02; // Wake-up Timer Prescaler Bits
  226. WUTE = $03;
  227. WUTR = $04;
  228. WUTCF = $05;
  229. WUTIE = $06;
  230. WUTIF = $07;
  231. // Power Reduction Register 0
  232. PRVADC = $00;
  233. PRTIM0 = $01;
  234. PRTIM1 = $02;
  235. PRTWI = $03;
  236. // Pin Change Interrupt Control Register
  237. PCIE0 = $00; // Pin Change Interrupt Enables
  238. PCIE1 = $01; // Pin Change Interrupt Enables
  239. // External Interrupt Control Register
  240. ISC00 = $00; // External Interrupt Sense Control 0 Bits
  241. ISC01 = $01; // External Interrupt Sense Control 0 Bits
  242. ISC10 = $02; // External Interrupt Sense Control 1 Bits
  243. ISC11 = $03; // External Interrupt Sense Control 1 Bits
  244. ISC20 = $04; // External Interrupt Sense Control 2 Bits
  245. ISC21 = $05; // External Interrupt Sense Control 2 Bits
  246. ISC30 = $06; // External Interrupt Sense Control 3 Bits
  247. ISC31 = $07; // External Interrupt Sense Control 3 Bits
  248. // Timer/Counter Interrupt Mask Register
  249. TOIE0 = $00;
  250. OCIE0A = $01;
  251. OCIE0B = $02;
  252. // Timer/Counter Interrupt Mask Register
  253. TOIE1 = $00;
  254. OCIE1A = $01;
  255. // The VADC Control and Status register
  256. VADCCIE = $00;
  257. VADCCIF = $01;
  258. VADSC = $02;
  259. VADEN = $03;
  260. // The VADC multiplexer Selection Register
  261. VADMUX0 = $00; // Analog Channel and Gain Selection Bits
  262. VADMUX1 = $01; // Analog Channel and Gain Selection Bits
  263. VADMUX2 = $02; // Analog Channel and Gain Selection Bits
  264. VADMUX3 = $03; // Analog Channel and Gain Selection Bits
  265. // Timer/Counter1 Control Register B
  266. CS10 = $00; // Clock Select1 bits
  267. CS11 = $01; // Clock Select1 bits
  268. CS12 = $02; // Clock Select1 bits
  269. CTC1 = $03;
  270. // TWI Status Register
  271. TWPS0 = $00; // TWI Prescaler
  272. TWPS1 = $01; // TWI Prescaler
  273. TWS3 = $03; // TWI Status
  274. TWS4 = $04; // TWI Status
  275. TWS5 = $05; // TWI Status
  276. TWS6 = $06; // TWI Status
  277. TWS7 = $07; // TWI Status
  278. // TWI (Slave) Address register
  279. TWGCE = $00;
  280. TWA0 = $01; // TWI (Slave) Address register Bits
  281. TWA1 = $02; // TWI (Slave) Address register Bits
  282. TWA2 = $03; // TWI (Slave) Address register Bits
  283. TWA3 = $04; // TWI (Slave) Address register Bits
  284. TWA4 = $05; // TWI (Slave) Address register Bits
  285. TWA5 = $06; // TWI (Slave) Address register Bits
  286. TWA6 = $07; // TWI (Slave) Address register Bits
  287. // TWI Control Register
  288. TWIE = $00;
  289. TWEN = $02;
  290. TWWC = $03;
  291. TWSTO = $04;
  292. TWSTA = $05;
  293. TWEA = $06;
  294. TWINT = $07;
  295. // TWI (Slave) Address Mask Register
  296. TWAM0 = $01;
  297. TWAM1 = $02;
  298. TWAM2 = $03;
  299. TWAM3 = $04;
  300. TWAM4 = $05;
  301. TWAM5 = $06;
  302. TWAM6 = $07;
  303. // TWI Bus Control and Status Register
  304. TWBCIP = $00;
  305. TWBDT0 = $01; // TWI Bus Disconnect Time-out Period
  306. TWBDT1 = $02; // TWI Bus Disconnect Time-out Period
  307. TWBCIE = $06;
  308. TWBCIF = $07;
  309. // Clock Control and Status Register
  310. ACS = $00;
  311. XOE = $01;
  312. // Bandgap Calibration Register
  313. BGCC0 = $00; // BG Calibration of PTAT Current Bits
  314. BGCC1 = $01; // BG Calibration of PTAT Current Bits
  315. BGCC2 = $02; // BG Calibration of PTAT Current Bits
  316. BGCC3 = $03; // BG Calibration of PTAT Current Bits
  317. BGCC4 = $04; // BG Calibration of PTAT Current Bits
  318. BGCC5 = $05; // BG Calibration of PTAT Current Bits
  319. BGD = $07;
  320. // CC-ADC Control and Status Register A
  321. CADSE = $00;
  322. CADSI0 = $01; // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
  323. CADSI1 = $02; // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
  324. CADAS0 = $03; // CC_ADC Accumulate Current Select Bits
  325. CADAS1 = $04; // CC_ADC Accumulate Current Select Bits
  326. CADUB = $05;
  327. CADEN = $07;
  328. // CC-ADC Control and Status Register B
  329. CADICIF = $00;
  330. CADRCIF = $01;
  331. CADACIF = $02;
  332. CADICIE = $04;
  333. CADRCIE = $05;
  334. CADACIE = $06;
  335. PFD = $00;
  336. CFE = $01;
  337. DFE = $02;
  338. CPS = $03;
  339. PWMOPC = $04;
  340. PWMOC = $05;
  341. // Cell Balancing Control Register
  342. CBE1 = $00; // Cell Balancing Enables
  343. CBE2 = $01; // Cell Balancing Enables
  344. CBE3 = $02; // Cell Balancing Enables
  345. CBE4 = $03; // Cell Balancing Enables
  346. // Battery Protection Interrupt Register
  347. SCIE = $00;
  348. DOCIE = $01;
  349. COCIE = $02;
  350. DUVIE = $03;
  351. SCIF = $04;
  352. DOCIF = $05;
  353. COCIF = $06;
  354. DUVIF = $07;
  355. // Battery Protection Deep Under Voltage Register
  356. DUDL0 = $00;
  357. DUDL1 = $01;
  358. DUDL2 = $02;
  359. DUDL3 = $03;
  360. DUVT0 = $04;
  361. DUVT1 = $05;
  362. // Battery Protection Short-Circuit Detection Level Register
  363. SCDL0 = $00;
  364. SCDL1 = $01;
  365. SCDL2 = $02;
  366. SCDL3 = $03;
  367. // Battery Protection OverCurrent Detection Level Register
  368. CCDL0 = $00;
  369. CCDL1 = $01;
  370. CCDL2 = $02;
  371. CCDL3 = $03;
  372. DCDL0 = $04;
  373. DCDL1 = $05;
  374. DCDL2 = $06;
  375. DCDL3 = $07;
  376. // Current Battery Protection Timing Register
  377. OCPT0 = $00;
  378. OCPT1 = $01;
  379. OCPT2 = $02;
  380. OCPT3 = $03;
  381. SCPT0 = $04;
  382. SCPT1 = $05;
  383. SCPT2 = $06;
  384. SCPT3 = $07;
  385. // Battery Protection Control Register
  386. CCD = $00;
  387. DCD = $01;
  388. SCD = $02;
  389. DUVD = $03;
  390. // Battery Protection Parameter Lock Register
  391. BPPL = $00;
  392. BPPLE = $01;
  393. implementation
  394. {$i avrcommon.inc}
  395. procedure BPINT_ISR; external name 'BPINT_ISR'; // Interrupt 1 Battery Protection Interrupt
  396. procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 2 External Interrupt Request 0
  397. procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 3 External Interrupt Request 1
  398. procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 4 External Interrupt Request 2
  399. procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 5 External Interrupt Request 3
  400. procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 6 Pin Change Interrupt 0
  401. procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 7 Pin Change Interrupt 1
  402. procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 8 Watchdog Timeout Interrupt
  403. procedure WAKE_UP_ISR; external name 'WAKE_UP_ISR'; // Interrupt 9 Wakeup timer overflow
  404. procedure TIM1_COMP_ISR; external name 'TIM1_COMP_ISR'; // Interrupt 10 Timer/Counter 1 Compare Match
  405. procedure TIM1_OVF_ISR; external name 'TIM1_OVF_ISR'; // Interrupt 11 Timer/Counter 1 Overflow
  406. procedure TIM0_COMPA_ISR; external name 'TIM0_COMPA_ISR'; // Interrupt 12 Timer/Counter0 Compare A Match
  407. procedure TIM0_COMPB_ISR; external name 'TIM0_COMPB_ISR'; // Interrupt 13 Timer/Counter0 Compare B Match
  408. procedure TIM0_OVF_ISR; external name 'TIM0_OVF_ISR'; // Interrupt 14 Timer/Counter0 Overflow
  409. procedure TWI_BUS_CD_ISR; external name 'TWI_BUS_CD_ISR'; // Interrupt 15 Two-Wire Bus Connect/Disconnect
  410. procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 16 Two-Wire Serial Interface
  411. procedure VADC_ISR; external name 'VADC_ISR'; // Interrupt 17 Voltage ADC Conversion Complete
  412. procedure CCADC_CONV_ISR; external name 'CCADC_CONV_ISR'; // Interrupt 18 Coulomb Counter ADC Conversion Complete
  413. procedure CCADC_REG_CUR_ISR; external name 'CCADC_REG_CUR_ISR'; // Interrupt 19 Coloumb Counter ADC Regular Current
  414. procedure CCADC_ACC_ISR; external name 'CCADC_ACC_ISR'; // Interrupt 20 Coloumb Counter ADC Accumulator
  415. procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 21 EEPROM Ready
  416. procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 22 Store Program Memory Ready
  417. procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';
  418. asm
  419. jmp __dtors_end
  420. jmp BPINT_ISR
  421. jmp INT0_ISR
  422. jmp INT1_ISR
  423. jmp INT2_ISR
  424. jmp INT3_ISR
  425. jmp PCINT0_ISR
  426. jmp PCINT1_ISR
  427. jmp WDT_ISR
  428. jmp WAKE_UP_ISR
  429. jmp TIM1_COMP_ISR
  430. jmp TIM1_OVF_ISR
  431. jmp TIM0_COMPA_ISR
  432. jmp TIM0_COMPB_ISR
  433. jmp TIM0_OVF_ISR
  434. jmp TWI_BUS_CD_ISR
  435. jmp TWI_ISR
  436. jmp VADC_ISR
  437. jmp CCADC_CONV_ISR
  438. jmp CCADC_REG_CUR_ISR
  439. jmp CCADC_ACC_ISR
  440. jmp EE_READY_ISR
  441. jmp SPM_READY_ISR
  442. .weak BPINT_ISR
  443. .weak INT0_ISR
  444. .weak INT1_ISR
  445. .weak INT2_ISR
  446. .weak INT3_ISR
  447. .weak PCINT0_ISR
  448. .weak PCINT1_ISR
  449. .weak WDT_ISR
  450. .weak WAKE_UP_ISR
  451. .weak TIM1_COMP_ISR
  452. .weak TIM1_OVF_ISR
  453. .weak TIM0_COMPA_ISR
  454. .weak TIM0_COMPB_ISR
  455. .weak TIM0_OVF_ISR
  456. .weak TWI_BUS_CD_ISR
  457. .weak TWI_ISR
  458. .weak VADC_ISR
  459. .weak CCADC_CONV_ISR
  460. .weak CCADC_REG_CUR_ISR
  461. .weak CCADC_ACC_ISR
  462. .weak EE_READY_ISR
  463. .weak SPM_READY_ISR
  464. .set BPINT_ISR, Default_IRQ_handler
  465. .set INT0_ISR, Default_IRQ_handler
  466. .set INT1_ISR, Default_IRQ_handler
  467. .set INT2_ISR, Default_IRQ_handler
  468. .set INT3_ISR, Default_IRQ_handler
  469. .set PCINT0_ISR, Default_IRQ_handler
  470. .set PCINT1_ISR, Default_IRQ_handler
  471. .set WDT_ISR, Default_IRQ_handler
  472. .set WAKE_UP_ISR, Default_IRQ_handler
  473. .set TIM1_COMP_ISR, Default_IRQ_handler
  474. .set TIM1_OVF_ISR, Default_IRQ_handler
  475. .set TIM0_COMPA_ISR, Default_IRQ_handler
  476. .set TIM0_COMPB_ISR, Default_IRQ_handler
  477. .set TIM0_OVF_ISR, Default_IRQ_handler
  478. .set TWI_BUS_CD_ISR, Default_IRQ_handler
  479. .set TWI_ISR, Default_IRQ_handler
  480. .set VADC_ISR, Default_IRQ_handler
  481. .set CCADC_CONV_ISR, Default_IRQ_handler
  482. .set CCADC_REG_CUR_ISR, Default_IRQ_handler
  483. .set CCADC_ACC_ISR, Default_IRQ_handler
  484. .set EE_READY_ISR, Default_IRQ_handler
  485. .set SPM_READY_ISR, Default_IRQ_handler
  486. end;
  487. end.