atmega4808.pp 57 KB

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  1. unit ATmega4808;
  2. interface
  3. type
  4. TAC = object //Analog Comparator
  5. CTRLA: byte; //Control A
  6. Reserved1: byte;
  7. MUXCTRLA: byte; //Mux Control A
  8. Reserved3: byte;
  9. DACREF: byte; //Referance scale control
  10. Reserved5: byte;
  11. INTCTRL: byte; //Interrupt Control
  12. STATUS: byte; //Status
  13. const
  14. // Enable
  15. ENABLEbm = $01;
  16. // AC_HYSMODE
  17. HYSMODEmask = $06;
  18. HYSMODE_OFF = $00;
  19. HYSMODE_10mV = $02;
  20. HYSMODE_25mV = $04;
  21. HYSMODE_50mV = $06;
  22. // AC_INTMODE
  23. INTMODEmask = $30;
  24. INTMODE_BOTHEDGE = $00;
  25. INTMODE_NEGEDGE = $20;
  26. INTMODE_POSEDGE = $30;
  27. // AC_LPMODE
  28. LPMODEmask = $08;
  29. LPMODE_DIS = $00;
  30. LPMODE_EN = $08;
  31. // Output Buffer Enable
  32. OUTENbm = $40;
  33. // Run in Standby Mode
  34. RUNSTDBYbm = $80;
  35. // DAC voltage reference
  36. DATA0bm = $01;
  37. DATA1bm = $02;
  38. DATA2bm = $04;
  39. DATA3bm = $08;
  40. DATA4bm = $10;
  41. DATA5bm = $20;
  42. DATA6bm = $40;
  43. DATA7bm = $80;
  44. // Analog Comparator 0 Interrupt Enable
  45. CMPbm = $01;
  46. // Invert AC Output
  47. INVERTbm = $80;
  48. // AC_MUXNEG
  49. MUXNEGmask = $03;
  50. MUXNEG_PIN0 = $00;
  51. MUXNEG_PIN1 = $01;
  52. MUXNEG_PIN2 = $02;
  53. MUXNEG_DACREF = $03;
  54. // AC_MUXPOS
  55. MUXPOSmask = $18;
  56. MUXPOS_PIN0 = $00;
  57. MUXPOS_PIN1 = $08;
  58. MUXPOS_PIN2 = $10;
  59. MUXPOS_PIN3 = $18;
  60. // Analog Comparator State
  61. STATEbm = $10;
  62. end;
  63. TADC = object //Analog to Digital Converter
  64. CTRLA: byte; //Control A
  65. CTRLB: byte; //Control B
  66. CTRLC: byte; //Control C
  67. CTRLD: byte; //Control D
  68. CTRLE: byte; //Control E
  69. SAMPCTRL: byte; //Sample Control
  70. MUXPOS: byte; //Positive mux input
  71. Reserved7: byte;
  72. COMMAND: byte; //Command
  73. EVCTRL: byte; //Event Control
  74. INTCTRL: byte; //Interrupt Control
  75. INTFLAGS: byte; //Interrupt Flags
  76. DBGCTRL: byte; //Debug Control
  77. TEMP: byte; //Temporary Data
  78. Reserved14: byte;
  79. Reserved15: byte;
  80. RES: word; //ADC Accumulator Result
  81. WINLT: word; //Window comparator low threshold
  82. WINHT: word; //Window comparator high threshold
  83. CALIB: byte; //Calibration
  84. const
  85. // ADC_DUTYCYC
  86. DUTYCYCmask = $01;
  87. DUTYCYC_DUTY50 = $00;
  88. DUTYCYC_DUTY25 = $01;
  89. // Start Conversion Operation
  90. STCONVbm = $01;
  91. // ADC Enable
  92. ENABLEbm = $01;
  93. // ADC Freerun mode
  94. FREERUNbm = $02;
  95. // ADC_RESSEL
  96. RESSELmask = $04;
  97. RESSEL_10BIT = $00;
  98. RESSEL_8BIT = $04;
  99. // Run standby mode
  100. RUNSTBYbm = $80;
  101. // ADC_SAMPNUM
  102. SAMPNUMmask = $07;
  103. SAMPNUM_ACC1 = $00;
  104. SAMPNUM_ACC2 = $01;
  105. SAMPNUM_ACC4 = $02;
  106. SAMPNUM_ACC8 = $03;
  107. SAMPNUM_ACC16 = $04;
  108. SAMPNUM_ACC32 = $05;
  109. SAMPNUM_ACC64 = $06;
  110. // ADC_PRESC
  111. PRESCmask = $07;
  112. PRESC_DIV2 = $00;
  113. PRESC_DIV4 = $01;
  114. PRESC_DIV8 = $02;
  115. PRESC_DIV16 = $03;
  116. PRESC_DIV32 = $04;
  117. PRESC_DIV64 = $05;
  118. PRESC_DIV128 = $06;
  119. PRESC_DIV256 = $07;
  120. // ADC_REFSEL
  121. REFSELmask = $30;
  122. REFSEL_INTREF = $00;
  123. REFSEL_VDDREF = $10;
  124. REFSEL_VREFA = $20;
  125. // Sample Capacitance Selection
  126. SAMPCAPbm = $40;
  127. // ADC_ASDV
  128. ASDVmask = $10;
  129. ASDV_ASVOFF = $00;
  130. ASDV_ASVON = $10;
  131. // ADC_INITDLY
  132. INITDLYmask = $E0;
  133. INITDLY_DLY0 = $00;
  134. INITDLY_DLY16 = $20;
  135. INITDLY_DLY32 = $40;
  136. INITDLY_DLY64 = $60;
  137. INITDLY_DLY128 = $80;
  138. INITDLY_DLY256 = $A0;
  139. // Sampling Delay Selection
  140. SAMPDLY0bm = $01;
  141. SAMPDLY1bm = $02;
  142. SAMPDLY2bm = $04;
  143. SAMPDLY3bm = $08;
  144. // ADC_WINCM
  145. WINCMmask = $07;
  146. WINCM_NONE = $00;
  147. WINCM_BELOW = $01;
  148. WINCM_ABOVE = $02;
  149. WINCM_INSIDE = $03;
  150. WINCM_OUTSIDE = $04;
  151. // Debug run
  152. DBGRUNbm = $01;
  153. // Start Event Input Enable
  154. STARTEIbm = $01;
  155. // Result Ready Interrupt Enable
  156. RESRDYbm = $01;
  157. // Window Comparator Interrupt Enable
  158. WCMPbm = $02;
  159. // ADC_MUXPOS
  160. MUXPOSmask = $1F;
  161. MUXPOS_AIN0 = $00;
  162. MUXPOS_AIN1 = $01;
  163. MUXPOS_AIN2 = $02;
  164. MUXPOS_AIN3 = $03;
  165. MUXPOS_AIN4 = $04;
  166. MUXPOS_AIN5 = $05;
  167. MUXPOS_AIN6 = $06;
  168. MUXPOS_AIN7 = $07;
  169. MUXPOS_AIN8 = $08;
  170. MUXPOS_AIN9 = $09;
  171. MUXPOS_AIN10 = $0A;
  172. MUXPOS_AIN11 = $0B;
  173. MUXPOS_AIN12 = $0C;
  174. MUXPOS_AIN13 = $0D;
  175. MUXPOS_AIN14 = $0E;
  176. MUXPOS_AIN15 = $0F;
  177. MUXPOS_DACREF = $1C;
  178. MUXPOS_TEMPSENSE = $1E;
  179. MUXPOS_GND = $1F;
  180. // Sample lenght
  181. SAMPLEN0bm = $01;
  182. SAMPLEN1bm = $02;
  183. SAMPLEN2bm = $04;
  184. SAMPLEN3bm = $08;
  185. SAMPLEN4bm = $10;
  186. // Temporary
  187. TEMP0bm = $01;
  188. TEMP1bm = $02;
  189. TEMP2bm = $04;
  190. TEMP3bm = $08;
  191. TEMP4bm = $10;
  192. TEMP5bm = $20;
  193. TEMP6bm = $40;
  194. TEMP7bm = $80;
  195. end;
  196. TBOD = object //Bod interface
  197. CTRLA: byte; //Control A
  198. CTRLB: byte; //Control B
  199. Reserved2: byte;
  200. Reserved3: byte;
  201. Reserved4: byte;
  202. Reserved5: byte;
  203. Reserved6: byte;
  204. Reserved7: byte;
  205. VLMCTRLA: byte; //Voltage level monitor Control
  206. INTCTRL: byte; //Voltage level monitor interrupt Control
  207. INTFLAGS: byte; //Voltage level monitor interrupt Flags
  208. STATUS: byte; //Voltage level monitor status
  209. const
  210. // BOD_ACTIVE
  211. ACTIVEmask = $0C;
  212. ACTIVE_DIS = $00;
  213. ACTIVE_ENABLED = $04;
  214. ACTIVE_SAMPLED = $08;
  215. ACTIVE_ENWAKE = $0C;
  216. // BOD_SAMPFREQ
  217. SAMPFREQmask = $10;
  218. SAMPFREQ_1KHZ = $00;
  219. SAMPFREQ_125HZ = $10;
  220. // BOD_SLEEP
  221. SLEEPmask = $03;
  222. SLEEP_DIS = $00;
  223. SLEEP_ENABLED = $01;
  224. SLEEP_SAMPLED = $02;
  225. // BOD_LVL
  226. LVLmask = $07;
  227. LVL_BODLEVEL0 = $00;
  228. LVL_BODLEVEL2 = $02;
  229. LVL_BODLEVEL7 = $07;
  230. // BOD_VLMCFG
  231. VLMCFGmask = $06;
  232. VLMCFG_BELOW = $00;
  233. VLMCFG_ABOVE = $02;
  234. VLMCFG_CROSS = $04;
  235. // voltage level monitor interrrupt enable
  236. VLMIEbm = $01;
  237. // Voltage level monitor interrupt flag
  238. VLMIFbm = $01;
  239. // Voltage level monitor status
  240. VLMSbm = $01;
  241. // BOD_VLMLVL
  242. VLMLVLmask = $03;
  243. VLMLVL_5ABOVE = $00;
  244. VLMLVL_15ABOVE = $01;
  245. VLMLVL_25ABOVE = $02;
  246. end;
  247. TCCL = object //Configurable Custom Logic
  248. CTRLA: byte; //Control Register A
  249. SEQCTRL0: byte; //Sequential Control 0
  250. SEQCTRL1: byte; //Sequential Control 1
  251. Reserved3: byte;
  252. Reserved4: byte;
  253. INTCTRL0: byte; //Interrupt Control 0
  254. Reserved6: byte;
  255. INTFLAGS: byte; //Interrupt Flags
  256. LUT0CTRLA: byte; //LUT Control 0 A
  257. LUT0CTRLB: byte; //LUT Control 0 B
  258. LUT0CTRLC: byte; //LUT Control 0 C
  259. TRUTH0: byte; //Truth 0
  260. LUT1CTRLA: byte; //LUT Control 1 A
  261. LUT1CTRLB: byte; //LUT Control 1 B
  262. LUT1CTRLC: byte; //LUT Control 1 C
  263. TRUTH1: byte; //Truth 1
  264. LUT2CTRLA: byte; //LUT Control 2 A
  265. LUT2CTRLB: byte; //LUT Control 2 B
  266. LUT2CTRLC: byte; //LUT Control 2 C
  267. TRUTH2: byte; //Truth 2
  268. LUT3CTRLA: byte; //LUT Control 3 A
  269. LUT3CTRLB: byte; //LUT Control 3 B
  270. LUT3CTRLC: byte; //LUT Control 3 C
  271. TRUTH3: byte; //Truth 3
  272. const
  273. // Enable
  274. ENABLEbm = $01;
  275. // Run in Standby
  276. RUNSTDBYbm = $40;
  277. // CCL_INTMODE0
  278. INTMODE0mask = $03;
  279. INTMODE0_INTDISABLE = $00;
  280. INTMODE0_RISING = $01;
  281. INTMODE0_FALLING = $02;
  282. INTMODE0_BOTH = $03;
  283. // CCL_INTMODE1
  284. INTMODE1mask = $0C;
  285. INTMODE1_INTDISABLE = $00;
  286. INTMODE1_RISING = $04;
  287. INTMODE1_FALLING = $08;
  288. INTMODE1_BOTH = $0C;
  289. // CCL_INTMODE2
  290. INTMODE2mask = $30;
  291. INTMODE2_INTDISABLE = $00;
  292. INTMODE2_RISING = $10;
  293. INTMODE2_FALLING = $20;
  294. INTMODE2_BOTH = $30;
  295. // CCL_INTMODE3
  296. INTMODE3mask = $C0;
  297. INTMODE3_INTDISABLE = $00;
  298. INTMODE3_RISING = $40;
  299. INTMODE3_FALLING = $80;
  300. INTMODE3_BOTH = $C0;
  301. // Interrupt Flags
  302. INT0bm = $01;
  303. INT1bm = $02;
  304. INT2bm = $04;
  305. INT3bm = $08;
  306. // CCL_CLKSRC
  307. CLKSRCmask = $0E;
  308. CLKSRC_CLKPER = $00;
  309. CLKSRC_IN2 = $02;
  310. CLKSRC_OSC20M = $08;
  311. CLKSRC_OSCULP32K = $0A;
  312. CLKSRC_OSCULP1K = $0C;
  313. // CCL_EDGEDET
  314. EDGEDETmask = $80;
  315. EDGEDET_DIS = $00;
  316. EDGEDET_EN = $80;
  317. // CCL_FILTSEL
  318. FILTSELmask = $30;
  319. FILTSEL_DISABLE = $00;
  320. FILTSEL_SYNCH = $10;
  321. FILTSEL_FILTER = $20;
  322. // Output Enable
  323. OUTENbm = $40;
  324. // CCL_INSEL0
  325. INSEL0mask = $0F;
  326. INSEL0_MASK = $00;
  327. INSEL0_FEEDBACK = $01;
  328. INSEL0_LINK = $02;
  329. INSEL0_EVENTA = $03;
  330. INSEL0_EVENTB = $04;
  331. INSEL0_IO = $05;
  332. INSEL0_AC0 = $06;
  333. INSEL0_USART0 = $08;
  334. INSEL0_SPI0 = $09;
  335. INSEL0_TCA0 = $0A;
  336. INSEL0_TCB0 = $0C;
  337. // CCL_INSEL1
  338. INSEL1mask = $F0;
  339. INSEL1_MASK = $00;
  340. INSEL1_FEEDBACK = $10;
  341. INSEL1_LINK = $20;
  342. INSEL1_EVENTA = $30;
  343. INSEL1_EVENTB = $40;
  344. INSEL1_IO = $50;
  345. INSEL1_AC0 = $60;
  346. INSEL1_USART1 = $80;
  347. INSEL1_SPI0 = $90;
  348. INSEL1_TCA0 = $A0;
  349. INSEL1_TCB1 = $C0;
  350. // CCL_INSEL2
  351. INSEL2mask = $0F;
  352. INSEL2_MASK = $00;
  353. INSEL2_FEEDBACK = $01;
  354. INSEL2_LINK = $02;
  355. INSEL2_EVENTA = $03;
  356. INSEL2_EVENTB = $04;
  357. INSEL2_IO = $05;
  358. INSEL2_AC0 = $06;
  359. INSEL2_USART2 = $08;
  360. INSEL2_SPI0 = $09;
  361. INSEL2_TCA0 = $0A;
  362. INSEL2_TCB2 = $0C;
  363. // CCL_SEQSEL0
  364. SEQSEL0mask = $07;
  365. SEQSEL0_DISABLE = $00;
  366. SEQSEL0_DFF = $01;
  367. SEQSEL0_JK = $02;
  368. SEQSEL0_LATCH = $03;
  369. SEQSEL0_RS = $04;
  370. // CCL_SEQSEL1
  371. SEQSEL1mask = $07;
  372. SEQSEL1_DISABLE = $00;
  373. SEQSEL1_DFF = $01;
  374. SEQSEL1_JK = $02;
  375. SEQSEL1_LATCH = $03;
  376. SEQSEL1_RS = $04;
  377. end;
  378. TCLKCTRL = object //Clock controller
  379. MCLKCTRLA: byte; //MCLK Control A
  380. MCLKCTRLB: byte; //MCLK Control B
  381. MCLKLOCK: byte; //MCLK Lock
  382. MCLKSTATUS: byte; //MCLK Status
  383. Reserved4: byte;
  384. Reserved5: byte;
  385. Reserved6: byte;
  386. Reserved7: byte;
  387. Reserved8: byte;
  388. Reserved9: byte;
  389. Reserved10: byte;
  390. Reserved11: byte;
  391. Reserved12: byte;
  392. Reserved13: byte;
  393. Reserved14: byte;
  394. Reserved15: byte;
  395. OSC20MCTRLA: byte; //OSC20M Control A
  396. OSC20MCALIBA: byte; //OSC20M Calibration A
  397. OSC20MCALIBB: byte; //OSC20M Calibration B
  398. Reserved19: byte;
  399. Reserved20: byte;
  400. Reserved21: byte;
  401. Reserved22: byte;
  402. Reserved23: byte;
  403. OSC32KCTRLA: byte; //OSC32K Control A
  404. Reserved25: byte;
  405. Reserved26: byte;
  406. Reserved27: byte;
  407. XOSC32KCTRLA: byte; //XOSC32K Control A
  408. const
  409. // System clock out
  410. CLKOUTbm = $80;
  411. // CLKCTRL_CLKSEL
  412. CLKSELmask = $03;
  413. CLKSEL_OSC20M = $00;
  414. CLKSEL_OSCULP32K = $01;
  415. CLKSEL_XOSC32K = $02;
  416. CLKSEL_EXTCLK = $03;
  417. // CLKCTRL_PDIV
  418. PDIVmask = $1E;
  419. PDIV_2X = $00;
  420. PDIV_4X = $02;
  421. PDIV_8X = $04;
  422. PDIV_16X = $06;
  423. PDIV_32X = $08;
  424. PDIV_64X = $0A;
  425. PDIV_6X = $10;
  426. PDIV_10X = $12;
  427. PDIV_12X = $14;
  428. PDIV_24X = $16;
  429. PDIV_48X = $18;
  430. // Prescaler enable
  431. PENbm = $01;
  432. // lock ebable
  433. LOCKENbm = $01;
  434. // External Clock status
  435. EXTSbm = $80;
  436. // 20MHz oscillator status
  437. OSC20MSbm = $10;
  438. // 32KHz oscillator status
  439. OSC32KSbm = $20;
  440. // System Oscillator changing
  441. SOSCbm = $01;
  442. // 32.768 kHz Crystal Oscillator status
  443. XOSC32KSbm = $40;
  444. // Calibration
  445. CAL20M0bm = $01;
  446. CAL20M1bm = $02;
  447. CAL20M2bm = $04;
  448. CAL20M3bm = $08;
  449. CAL20M4bm = $10;
  450. CAL20M5bm = $20;
  451. CAL20M6bm = $40;
  452. // Lock
  453. LOCKbm = $80;
  454. // Oscillator temperature coefficient
  455. TEMPCAL20M0bm = $01;
  456. TEMPCAL20M1bm = $02;
  457. TEMPCAL20M2bm = $04;
  458. TEMPCAL20M3bm = $08;
  459. // Run standby
  460. RUNSTDBYbm = $02;
  461. // CLKCTRL_CSUT
  462. CSUTmask = $30;
  463. CSUT_1K = $00;
  464. CSUT_16K = $10;
  465. CSUT_32K = $20;
  466. CSUT_64K = $30;
  467. // Enable
  468. ENABLEbm = $01;
  469. // Select
  470. SELbm = $04;
  471. end;
  472. TCPU = object //CPU
  473. Reserved0: byte;
  474. Reserved1: byte;
  475. Reserved2: byte;
  476. Reserved3: byte;
  477. CCP: byte; //Configuration Change Protection
  478. Reserved5: byte;
  479. Reserved6: byte;
  480. Reserved7: byte;
  481. Reserved8: byte;
  482. Reserved9: byte;
  483. Reserved10: byte;
  484. Reserved11: byte;
  485. Reserved12: byte;
  486. SPL: byte; //Stack Pointer Low
  487. SPH: byte; //Stack Pointer High
  488. SREG: byte; //Status Register
  489. const
  490. // CPU_CCP
  491. CCPmask = $FF;
  492. CCP_SPM = $9D;
  493. CCP_IOREG = $D8;
  494. // Carry Flag
  495. Cbm = $01;
  496. // Half Carry Flag
  497. Hbm = $20;
  498. // Global Interrupt Enable Flag
  499. Ibm = $80;
  500. // Negative Flag
  501. Nbm = $04;
  502. // N Exclusive Or V Flag
  503. Sbm = $10;
  504. // Transfer Bit
  505. Tbm = $40;
  506. // Two's Complement Overflow Flag
  507. Vbm = $08;
  508. // Zero Flag
  509. Zbm = $02;
  510. end;
  511. TCPUINT = object //Interrupt Controller
  512. CTRLA: byte; //Control A
  513. STATUS: byte; //Status
  514. LVL0PRI: byte; //Interrupt Level 0 Priority
  515. LVL1VEC: byte; //Interrupt Level 1 Priority Vector
  516. const
  517. // Compact Vector Table
  518. CVTbm = $20;
  519. // Interrupt Vector Select
  520. IVSELbm = $40;
  521. // Round-robin Scheduling Enable
  522. LVL0RRbm = $01;
  523. // Interrupt Level Priority
  524. LVL0PRI0bm = $01;
  525. LVL0PRI1bm = $02;
  526. LVL0PRI2bm = $04;
  527. LVL0PRI3bm = $08;
  528. LVL0PRI4bm = $10;
  529. LVL0PRI5bm = $20;
  530. LVL0PRI6bm = $40;
  531. LVL0PRI7bm = $80;
  532. // Interrupt Vector with High Priority
  533. LVL1VEC0bm = $01;
  534. LVL1VEC1bm = $02;
  535. LVL1VEC2bm = $04;
  536. LVL1VEC3bm = $08;
  537. LVL1VEC4bm = $10;
  538. LVL1VEC5bm = $20;
  539. LVL1VEC6bm = $40;
  540. LVL1VEC7bm = $80;
  541. // Level 0 Interrupt Executing
  542. LVL0EXbm = $01;
  543. // Level 1 Interrupt Executing
  544. LVL1EXbm = $02;
  545. // Non-maskable Interrupt Executing
  546. NMIEXbm = $80;
  547. end;
  548. TCRCSCAN = object //CRCSCAN
  549. CTRLA: byte; //Control A
  550. CTRLB: byte; //Control B
  551. STATUS: byte; //Status
  552. const
  553. // Enable CRC scan
  554. ENABLEbm = $01;
  555. // Enable NMI Trigger
  556. NMIENbm = $02;
  557. // Reset CRC scan
  558. RESETbm = $80;
  559. // CRCSCAN_SRC
  560. SRCmask = $03;
  561. SRC_FLASH = $00;
  562. SRC_APPLICATION = $01;
  563. SRC_BOOT = $02;
  564. // CRC Busy
  565. BUSYbm = $01;
  566. // CRC Ok
  567. OKbm = $02;
  568. end;
  569. TEVSYS = object //Event System
  570. STROBE: byte; //Channel Strobe
  571. Reserved1: byte;
  572. Reserved2: byte;
  573. Reserved3: byte;
  574. Reserved4: byte;
  575. Reserved5: byte;
  576. Reserved6: byte;
  577. Reserved7: byte;
  578. Reserved8: byte;
  579. Reserved9: byte;
  580. Reserved10: byte;
  581. Reserved11: byte;
  582. Reserved12: byte;
  583. Reserved13: byte;
  584. Reserved14: byte;
  585. Reserved15: byte;
  586. CHANNEL0: byte; //Multiplexer Channel 0
  587. CHANNEL1: byte; //Multiplexer Channel 1
  588. CHANNEL2: byte; //Multiplexer Channel 2
  589. CHANNEL3: byte; //Multiplexer Channel 3
  590. CHANNEL4: byte; //Multiplexer Channel 4
  591. CHANNEL5: byte; //Multiplexer Channel 5
  592. Reserved22: byte;
  593. Reserved23: byte;
  594. Reserved24: byte;
  595. Reserved25: byte;
  596. Reserved26: byte;
  597. Reserved27: byte;
  598. Reserved28: byte;
  599. Reserved29: byte;
  600. Reserved30: byte;
  601. Reserved31: byte;
  602. USERCCLLUT0A: byte; //User CCL LUT0 Event A
  603. USERCCLLUT0B: byte; //User CCL LUT0 Event B
  604. USERCCLLUT1A: byte; //User CCL LUT1 Event A
  605. USERCCLLUT1B: byte; //User CCL LUT1 Event B
  606. USERCCLLUT2A: byte; //User CCL LUT2 Event A
  607. USERCCLLUT2B: byte; //User CCL LUT2 Event B
  608. USERCCLLUT3A: byte; //User CCL LUT3 Event A
  609. USERCCLLUT3B: byte; //User CCL LUT3 Event B
  610. USERADC0: byte; //User ADC0
  611. USEREVOUTA: byte; //User EVOUT Port A
  612. USEREVOUTB: byte; //User EVOUT Port B
  613. USEREVOUTC: byte; //User EVOUT Port C
  614. USEREVOUTD: byte; //User EVOUT Port D
  615. USEREVOUTE: byte; //User EVOUT Port E
  616. USEREVOUTF: byte; //User EVOUT Port F
  617. USERUSART0: byte; //User USART0
  618. USERUSART1: byte; //User USART1
  619. USERUSART2: byte; //User USART2
  620. USERUSART3: byte; //User USART3
  621. USERTCA0: byte; //User TCA0
  622. USERTCB0: byte; //User TCB0
  623. USERTCB1: byte; //User TCB1
  624. USERTCB2: byte; //User TCB2
  625. USERTCB3: byte; //User TCB3
  626. const
  627. // EVSYS_GENERATOR
  628. GENERATORmask = $FF;
  629. GENERATOR_OFF = $00;
  630. GENERATOR_UPDI = $01;
  631. GENERATOR_RTC_OVF = $06;
  632. GENERATOR_RTC_CMP = $07;
  633. GENERATOR_RTC_PIT0 = $08;
  634. GENERATOR_RTC_PIT1 = $09;
  635. GENERATOR_RTC_PIT2 = $0A;
  636. GENERATOR_RTC_PIT3 = $0B;
  637. GENERATOR_CCL_LUT0 = $10;
  638. GENERATOR_CCL_LUT1 = $11;
  639. GENERATOR_CCL_LUT2 = $12;
  640. GENERATOR_CCL_LUT3 = $13;
  641. GENERATOR_AC0_OUT = $20;
  642. GENERATOR_ADC0_RESRDY = $24;
  643. GENERATOR_PORT0_PIN0 = $40;
  644. GENERATOR_PORT0_PIN1 = $41;
  645. GENERATOR_PORT0_PIN2 = $42;
  646. GENERATOR_PORT0_PIN3 = $43;
  647. GENERATOR_PORT0_PIN4 = $44;
  648. GENERATOR_PORT0_PIN5 = $45;
  649. GENERATOR_PORT0_PIN6 = $46;
  650. GENERATOR_PORT0_PIN7 = $47;
  651. GENERATOR_PORT1_PIN0 = $48;
  652. GENERATOR_PORT1_PIN1 = $49;
  653. GENERATOR_PORT1_PIN2 = $4A;
  654. GENERATOR_PORT1_PIN3 = $4B;
  655. GENERATOR_PORT1_PIN4 = $4C;
  656. GENERATOR_PORT1_PIN5 = $4D;
  657. GENERATOR_PORT1_PIN6 = $4E;
  658. GENERATOR_PORT1_PIN7 = $4F;
  659. GENERATOR_USART0_XCK = $60;
  660. GENERATOR_USART1_XCK = $61;
  661. GENERATOR_USART2_XCK = $62;
  662. GENERATOR_USART3_XCK = $63;
  663. GENERATOR_SPI0_SCK = $68;
  664. GENERATOR_TCA0_OVF_LUNF = $80;
  665. GENERATOR_TCA0_HUNF = $81;
  666. GENERATOR_TCA0_CMP0 = $84;
  667. GENERATOR_TCA0_CMP1 = $85;
  668. GENERATOR_TCA0_CMP2 = $86;
  669. GENERATOR_TCB0_CAPT = $A0;
  670. GENERATOR_TCB1_CAPT = $A2;
  671. GENERATOR_TCB2_CAPT = $A4;
  672. GENERATOR_TCB3_CAPT = $A6;
  673. // EVSYS_STROBE0
  674. STROBE0mask = $FF;
  675. STROBE0_EV_STROBE_CH0 = $01;
  676. STROBE0_EV_STROBE_CH1 = $02;
  677. STROBE0_EV_STROBE_CH2 = $04;
  678. STROBE0_EV_STROBE_CH3 = $08;
  679. STROBE0_EV_STROBE_CH4 = $10;
  680. STROBE0_EV_STROBE_CH5 = $20;
  681. STROBE0_EV_STROBE_CH6 = $40;
  682. STROBE0_EV_STROBE_CH7 = $80;
  683. // EVSYS_CHANNEL
  684. CHANNELmask = $FF;
  685. CHANNEL_OFF = $00;
  686. CHANNEL_CHANNEL0 = $01;
  687. CHANNEL_CHANNEL1 = $02;
  688. CHANNEL_CHANNEL2 = $03;
  689. CHANNEL_CHANNEL3 = $04;
  690. CHANNEL_CHANNEL4 = $05;
  691. CHANNEL_CHANNEL5 = $06;
  692. end;
  693. TFUSE = object //Fuses
  694. WDTCFG: byte; //Watchdog Configuration
  695. BODCFG: byte; //BOD Configuration
  696. OSCCFG: byte; //Oscillator Configuration
  697. Reserved3: byte;
  698. Reserved4: byte;
  699. SYSCFG0: byte; //System Configuration 0
  700. SYSCFG1: byte; //System Configuration 1
  701. APPEND: byte; //Application Code Section End
  702. BOOTEND: byte; //Boot Section End
  703. const
  704. // FUSE_ACTIVE
  705. ACTIVEmask = $0C;
  706. ACTIVE_DIS = $00;
  707. ACTIVE_ENABLED = $04;
  708. ACTIVE_SAMPLED = $08;
  709. ACTIVE_ENWAKE = $0C;
  710. // FUSE_LVL
  711. LVLmask = $E0;
  712. LVL_BODLEVEL0 = $00;
  713. LVL_BODLEVEL2 = $40;
  714. LVL_BODLEVEL7 = $E0;
  715. // FUSE_SAMPFREQ
  716. SAMPFREQmask = $10;
  717. SAMPFREQ_1KHZ = $00;
  718. SAMPFREQ_125HZ = $10;
  719. // FUSE_SLEEP
  720. SLEEPmask = $03;
  721. SLEEP_DIS = $00;
  722. SLEEP_ENABLED = $01;
  723. SLEEP_SAMPLED = $02;
  724. // FUSE_FREQSEL
  725. FREQSELmask = $03;
  726. FREQSEL_16MHZ = $01;
  727. FREQSEL_20MHZ = $02;
  728. // Oscillator Lock
  729. OSCLOCKbm = $80;
  730. // FUSE_CRCSRC
  731. CRCSRCmask = $C0;
  732. CRCSRC_FLASH = $00;
  733. CRCSRC_BOOT = $40;
  734. CRCSRC_BOOTAPP = $80;
  735. CRCSRC_NOCRC = $C0;
  736. // EEPROM Save
  737. EESAVEbm = $01;
  738. // FUSE_RSTPINCFG
  739. RSTPINCFGmask = $08;
  740. RSTPINCFG_GPIO = $00;
  741. RSTPINCFG_RST = $08;
  742. // FUSE_SUT
  743. SUTmask = $07;
  744. SUT_0MS = $00;
  745. SUT_1MS = $01;
  746. SUT_2MS = $02;
  747. SUT_4MS = $03;
  748. SUT_8MS = $04;
  749. SUT_16MS = $05;
  750. SUT_32MS = $06;
  751. SUT_64MS = $07;
  752. // FUSE_PERIOD
  753. PERIODmask = $0F;
  754. PERIOD_OFF = $00;
  755. PERIOD_8CLK = $01;
  756. PERIOD_16CLK = $02;
  757. PERIOD_32CLK = $03;
  758. PERIOD_64CLK = $04;
  759. PERIOD_128CLK = $05;
  760. PERIOD_256CLK = $06;
  761. PERIOD_512CLK = $07;
  762. PERIOD_1KCLK = $08;
  763. PERIOD_2KCLK = $09;
  764. PERIOD_4KCLK = $0A;
  765. PERIOD_8KCLK = $0B;
  766. // FUSE_WINDOW
  767. WINDOWmask = $F0;
  768. WINDOW_OFF = $00;
  769. WINDOW_8CLK = $10;
  770. WINDOW_16CLK = $20;
  771. WINDOW_32CLK = $30;
  772. WINDOW_64CLK = $40;
  773. WINDOW_128CLK = $50;
  774. WINDOW_256CLK = $60;
  775. WINDOW_512CLK = $70;
  776. WINDOW_1KCLK = $80;
  777. WINDOW_2KCLK = $90;
  778. WINDOW_4KCLK = $A0;
  779. WINDOW_8KCLK = $B0;
  780. end;
  781. TGPIO = object //General Purpose IO
  782. GPIOR0: byte; //General Purpose IO Register 0
  783. GPIOR1: byte; //General Purpose IO Register 1
  784. GPIOR2: byte; //General Purpose IO Register 2
  785. GPIOR3: byte; //General Purpose IO Register 3
  786. end;
  787. TLOCKBIT = object //Lockbit
  788. LOCKBIT: byte; //Lock Bits
  789. const
  790. // LOCKBIT_LB
  791. LBmask = $FF;
  792. LB_RWLOCK = $3A;
  793. LB_NOLOCK = $C5;
  794. end;
  795. TNVMCTRL = object //Non-volatile Memory Controller
  796. CTRLA: byte; //Control A
  797. CTRLB: byte; //Control B
  798. STATUS: byte; //Status
  799. INTCTRL: byte; //Interrupt Control
  800. INTFLAGS: byte; //Interrupt Flags
  801. Reserved5: byte;
  802. DATA: word; //Data
  803. ADDR: word; //Address
  804. const
  805. // NVMCTRL_CMD
  806. CMDmask = $07;
  807. CMD_NONE = $00;
  808. CMD_PAGEWRITE = $01;
  809. CMD_PAGEERASE = $02;
  810. CMD_PAGEERASEWRITE = $03;
  811. CMD_PAGEBUFCLR = $04;
  812. CMD_CHIPERASE = $05;
  813. CMD_EEERASE = $06;
  814. CMD_FUSEWRITE = $07;
  815. // Application code write protect
  816. APCWPbm = $01;
  817. // Boot Lock
  818. BOOTLOCKbm = $02;
  819. // EEPROM Ready
  820. EEREADYbm = $01;
  821. // EEPROM busy
  822. EEBUSYbm = $02;
  823. // Flash busy
  824. FBUSYbm = $01;
  825. // Write error
  826. WRERRORbm = $04;
  827. end;
  828. TPORT = object //I/O Ports
  829. DIR: byte; //Data Direction
  830. DIRSET: byte; //Data Direction Set
  831. DIRCLR: byte; //Data Direction Clear
  832. DIRTGL: byte; //Data Direction Toggle
  833. OUT_: byte; //Output Value
  834. OUTSET: byte; //Output Value Set
  835. OUTCLR: byte; //Output Value Clear
  836. OUTTGL: byte; //Output Value Toggle
  837. IN_: byte; //Input Value
  838. INTFLAGS: byte; //Interrupt Flags
  839. PORTCTRL: byte; //Port Control
  840. Reserved11: byte;
  841. Reserved12: byte;
  842. Reserved13: byte;
  843. Reserved14: byte;
  844. Reserved15: byte;
  845. PIN0CTRL: byte; //Pin 0 Control
  846. PIN1CTRL: byte; //Pin 1 Control
  847. PIN2CTRL: byte; //Pin 2 Control
  848. PIN3CTRL: byte; //Pin 3 Control
  849. PIN4CTRL: byte; //Pin 4 Control
  850. PIN5CTRL: byte; //Pin 5 Control
  851. PIN6CTRL: byte; //Pin 6 Control
  852. PIN7CTRL: byte; //Pin 7 Control
  853. const
  854. // Pin Interrupt
  855. INT0bm = $01;
  856. INT1bm = $02;
  857. INT2bm = $04;
  858. INT3bm = $08;
  859. INT4bm = $10;
  860. INT5bm = $20;
  861. INT6bm = $40;
  862. INT7bm = $80;
  863. // Inverted I/O Enable
  864. INVENbm = $80;
  865. // PORT_ISC
  866. ISCmask = $07;
  867. ISC_INTDISABLE = $00;
  868. ISC_BOTHEDGES = $01;
  869. ISC_RISING = $02;
  870. ISC_FALLING = $03;
  871. ISC_INPUT_DISABLE = $04;
  872. ISC_LEVEL = $05;
  873. // Pullup enable
  874. PULLUPENbm = $08;
  875. // Slew Rate Limit Enable
  876. SRLbm = $01;
  877. end;
  878. TPORTMUX = object //Port Multiplexer
  879. EVSYSROUTEA: byte; //Port Multiplexer EVSYS
  880. CCLROUTEA: byte; //Port Multiplexer CCL
  881. USARTROUTEA: byte; //Port Multiplexer USART register A
  882. TWISPIROUTEA: byte; //Port Multiplexer TWI and SPI
  883. TCAROUTEA: byte; //Port Multiplexer TCA
  884. TCBROUTEA: byte; //Port Multiplexer TCB
  885. const
  886. // CCL LUT0
  887. LUT0bm = $01;
  888. // CCL LUT1
  889. LUT1bm = $02;
  890. // CCL LUT2
  891. LUT2bm = $04;
  892. // CCL LUT3
  893. LUT3bm = $08;
  894. // Event Output 0
  895. EVOUT0bm = $01;
  896. // Event Output 1
  897. EVOUT1bm = $02;
  898. // Event Output 2
  899. EVOUT2bm = $04;
  900. // Event Output 3
  901. EVOUT3bm = $08;
  902. // Event Output 4
  903. EVOUT4bm = $10;
  904. // Event Output 5
  905. EVOUT5bm = $20;
  906. // PORTMUX_TCA0
  907. TCA0mask = $07;
  908. TCA0_PORTA = $00;
  909. TCA0_PORTB = $01;
  910. TCA0_PORTC = $02;
  911. TCA0_PORTD = $03;
  912. TCA0_PORTE = $04;
  913. TCA0_PORTF = $05;
  914. // Port Multiplexer TCB0
  915. TCB0bm = $01;
  916. // Port Multiplexer TCB1
  917. TCB1bm = $02;
  918. // Port Multiplexer TCB2
  919. TCB2bm = $04;
  920. // Port Multiplexer TCB3
  921. TCB3bm = $08;
  922. // PORTMUX_SPI0
  923. SPI0mask = $03;
  924. SPI0_DEFAULT = $00;
  925. SPI0_ALT1 = $01;
  926. SPI0_ALT2 = $02;
  927. SPI0_NONE = $03;
  928. // PORTMUX_TWI0
  929. TWI0mask = $30;
  930. TWI0_DEFAULT = $00;
  931. TWI0_ALT1 = $10;
  932. TWI0_ALT2 = $20;
  933. TWI0_NONE = $30;
  934. // PORTMUX_USART0
  935. USART0mask = $03;
  936. USART0_DEFAULT = $00;
  937. USART0_ALT1 = $01;
  938. USART0_NONE = $03;
  939. // PORTMUX_USART1
  940. USART1mask = $0C;
  941. USART1_DEFAULT = $00;
  942. USART1_ALT1 = $04;
  943. USART1_NONE = $0C;
  944. // PORTMUX_USART2
  945. USART2mask = $30;
  946. USART2_DEFAULT = $00;
  947. USART2_ALT1 = $10;
  948. USART2_NONE = $30;
  949. // PORTMUX_USART3
  950. USART3mask = $C0;
  951. USART3_DEFAULT = $00;
  952. USART3_ALT1 = $40;
  953. USART3_NONE = $C0;
  954. end;
  955. TRSTCTRL = object //Reset controller
  956. RSTFR: byte; //Reset Flags
  957. SWRR: byte; //Software Reset
  958. const
  959. // Brown out detector Reset flag
  960. BORFbm = $02;
  961. // External Reset flag
  962. EXTRFbm = $04;
  963. // Power on Reset flag
  964. PORFbm = $01;
  965. // Software Reset flag
  966. SWRFbm = $10;
  967. // UPDI Reset flag
  968. UPDIRFbm = $20;
  969. // Watch dog Reset flag
  970. WDRFbm = $08;
  971. // Software reset enable
  972. SWREbm = $01;
  973. end;
  974. TRTC = object //Real-Time Counter
  975. CTRLA: byte; //Control A
  976. STATUS: byte; //Status
  977. INTCTRL: byte; //Interrupt Control
  978. INTFLAGS: byte; //Interrupt Flags
  979. TEMP: byte; //Temporary
  980. DBGCTRL: byte; //Debug control
  981. CALIB: byte; //Calibration
  982. CLKSEL: byte; //Clock Select
  983. CNT: word; //Counter
  984. PER: word; //Period
  985. CMP: word; //Compare
  986. Reserved14: byte;
  987. Reserved15: byte;
  988. PITCTRLA: byte; //PIT Control A
  989. PITSTATUS: byte; //PIT Status
  990. PITINTCTRL: byte; //PIT Interrupt Control
  991. PITINTFLAGS: byte; //PIT Interrupt Flags
  992. Reserved20: byte;
  993. PITDBGCTRL: byte; //PIT Debug control
  994. const
  995. // Error Correction Value
  996. ERROR0bm = $01;
  997. ERROR1bm = $02;
  998. ERROR2bm = $04;
  999. ERROR3bm = $08;
  1000. ERROR4bm = $10;
  1001. ERROR5bm = $20;
  1002. ERROR6bm = $40;
  1003. // Error Correction Sign Bit
  1004. SIGNbm = $80;
  1005. // RTC_CLKSEL
  1006. CLKSELmask = $03;
  1007. CLKSEL_INT32K = $00;
  1008. CLKSEL_INT1K = $01;
  1009. CLKSEL_TOSC32K = $02;
  1010. CLKSEL_EXTCLK = $03;
  1011. // Correction enable
  1012. CORRENbm = $04;
  1013. // RTC_PRESCALER
  1014. PRESCALERmask = $78;
  1015. PRESCALER_DIV1 = $00;
  1016. PRESCALER_DIV2 = $08;
  1017. PRESCALER_DIV4 = $10;
  1018. PRESCALER_DIV8 = $18;
  1019. PRESCALER_DIV16 = $20;
  1020. PRESCALER_DIV32 = $28;
  1021. PRESCALER_DIV64 = $30;
  1022. PRESCALER_DIV128 = $38;
  1023. PRESCALER_DIV256 = $40;
  1024. PRESCALER_DIV512 = $48;
  1025. PRESCALER_DIV1024 = $50;
  1026. PRESCALER_DIV2048 = $58;
  1027. PRESCALER_DIV4096 = $60;
  1028. PRESCALER_DIV8192 = $68;
  1029. PRESCALER_DIV16384 = $70;
  1030. PRESCALER_DIV32768 = $78;
  1031. // Enable
  1032. RTCENbm = $01;
  1033. // Run In Standby
  1034. RUNSTDBYbm = $80;
  1035. // Run in debug
  1036. DBGRUNbm = $01;
  1037. // Compare Match Interrupt enable
  1038. CMPbm = $02;
  1039. // Overflow Interrupt enable
  1040. OVFbm = $01;
  1041. // RTC_PERIOD
  1042. PERIODmask = $78;
  1043. PERIOD_OFF = $00;
  1044. PERIOD_CYC4 = $08;
  1045. PERIOD_CYC8 = $10;
  1046. PERIOD_CYC16 = $18;
  1047. PERIOD_CYC32 = $20;
  1048. PERIOD_CYC64 = $28;
  1049. PERIOD_CYC128 = $30;
  1050. PERIOD_CYC256 = $38;
  1051. PERIOD_CYC512 = $40;
  1052. PERIOD_CYC1024 = $48;
  1053. PERIOD_CYC2048 = $50;
  1054. PERIOD_CYC4096 = $58;
  1055. PERIOD_CYC8192 = $60;
  1056. PERIOD_CYC16384 = $68;
  1057. PERIOD_CYC32768 = $70;
  1058. // Enable
  1059. PITENbm = $01;
  1060. // Periodic Interrupt
  1061. PIbm = $01;
  1062. // CTRLA Synchronization Busy Flag
  1063. CTRLBUSYbm = $01;
  1064. // Comparator Synchronization Busy Flag
  1065. CMPBUSYbm = $08;
  1066. // Count Synchronization Busy Flag
  1067. CNTBUSYbm = $02;
  1068. // CTRLA Synchronization Busy Flag
  1069. CTRLABUSYbm = $01;
  1070. // Period Synchronization Busy Flag
  1071. PERBUSYbm = $04;
  1072. end;
  1073. TSIGROW = object //Signature row
  1074. DEVICEID0: byte; //Device ID Byte 0
  1075. DEVICEID1: byte; //Device ID Byte 1
  1076. DEVICEID2: byte; //Device ID Byte 2
  1077. SERNUM0: byte; //Serial Number Byte 0
  1078. SERNUM1: byte; //Serial Number Byte 1
  1079. SERNUM2: byte; //Serial Number Byte 2
  1080. SERNUM3: byte; //Serial Number Byte 3
  1081. SERNUM4: byte; //Serial Number Byte 4
  1082. SERNUM5: byte; //Serial Number Byte 5
  1083. SERNUM6: byte; //Serial Number Byte 6
  1084. SERNUM7: byte; //Serial Number Byte 7
  1085. SERNUM8: byte; //Serial Number Byte 8
  1086. SERNUM9: byte; //Serial Number Byte 9
  1087. Reserved13: byte;
  1088. Reserved14: byte;
  1089. Reserved15: byte;
  1090. Reserved16: byte;
  1091. Reserved17: byte;
  1092. Reserved18: byte;
  1093. Reserved19: byte;
  1094. OSCCAL32K: byte; //Oscillator Calibration for 32kHz ULP
  1095. Reserved21: byte;
  1096. Reserved22: byte;
  1097. Reserved23: byte;
  1098. OSCCAL16M0: byte; //Oscillator Calibration 16 MHz Byte 0
  1099. OSCCAL16M1: byte; //Oscillator Calibration 16 MHz Byte 1
  1100. OSCCAL20M0: byte; //Oscillator Calibration 20 MHz Byte 0
  1101. OSCCAL20M1: byte; //Oscillator Calibration 20 MHz Byte 1
  1102. Reserved28: byte;
  1103. Reserved29: byte;
  1104. Reserved30: byte;
  1105. Reserved31: byte;
  1106. TEMPSENSE0: byte; //Temperature Sensor Calibration Byte 0
  1107. TEMPSENSE1: byte; //Temperature Sensor Calibration Byte 1
  1108. OSC16ERR3V: byte; //OSC16 error at 3V
  1109. OSC16ERR5V: byte; //OSC16 error at 5V
  1110. OSC20ERR3V: byte; //OSC20 error at 3V
  1111. OSC20ERR5V: byte; //OSC20 error at 5V
  1112. Reserved38: byte;
  1113. Reserved39: byte;
  1114. Reserved40: byte;
  1115. Reserved41: byte;
  1116. Reserved42: byte;
  1117. Reserved43: byte;
  1118. Reserved44: byte;
  1119. Reserved45: byte;
  1120. Reserved46: byte;
  1121. CHECKSUM1: byte; //CRC Checksum Byte 1
  1122. end;
  1123. TSLPCTRL = object //Sleep Controller
  1124. CTRLA: byte; //Control
  1125. const
  1126. // Sleep enable
  1127. SENbm = $01;
  1128. // SLPCTRL_SMODE
  1129. SMODEmask = $06;
  1130. SMODE_IDLE = $00;
  1131. SMODE_STDBY = $02;
  1132. SMODE_PDOWN = $04;
  1133. end;
  1134. TSPI = object //Serial Peripheral Interface
  1135. CTRLA: byte; //Control A
  1136. CTRLB: byte; //Control B
  1137. INTCTRL: byte; //Interrupt Control
  1138. INTFLAGS: byte; //Interrupt Flags
  1139. DATA: byte; //Data
  1140. const
  1141. // Enable Double Speed
  1142. CLK2Xbm = $10;
  1143. // Data Order Setting
  1144. DORDbm = $40;
  1145. // Enable Module
  1146. ENABLEbm = $01;
  1147. // Master Operation Enable
  1148. MASTERbm = $20;
  1149. // SPI_PRESC
  1150. PRESCmask = $06;
  1151. PRESC_DIV4 = $00;
  1152. PRESC_DIV16 = $02;
  1153. PRESC_DIV64 = $04;
  1154. PRESC_DIV128 = $06;
  1155. // Buffer Mode Enable
  1156. BUFENbm = $80;
  1157. // Buffer Write Mode
  1158. BUFWRbm = $40;
  1159. // SPI_MODE
  1160. MODEmask = $03;
  1161. MODE_0 = $00;
  1162. MODE_1 = $01;
  1163. MODE_2 = $02;
  1164. MODE_3 = $03;
  1165. // Slave Select Disable
  1166. SSDbm = $04;
  1167. // Data Register Empty Interrupt Enable
  1168. DREIEbm = $20;
  1169. // Interrupt Enable
  1170. IEbm = $01;
  1171. // Receive Complete Interrupt Enable
  1172. RXCIEbm = $80;
  1173. // Slave Select Trigger Interrupt Enable
  1174. SSIEbm = $10;
  1175. // Transfer Complete Interrupt Enable
  1176. TXCIEbm = $40;
  1177. // Buffer Overflow
  1178. BUFOVFbm = $01;
  1179. // Data Register Empty Interrupt Flag
  1180. DREIFbm = $20;
  1181. // Receive Complete Interrupt Flag
  1182. RXCIFbm = $80;
  1183. // Slave Select Trigger Interrupt Flag
  1184. SSIFbm = $10;
  1185. // Transfer Complete Interrupt Flag
  1186. TXCIFbm = $40;
  1187. // Interrupt Flag
  1188. IFbm = $80;
  1189. // Write Collision
  1190. WRCOLbm = $40;
  1191. end;
  1192. TSYSCFG = object //System Configuration Registers
  1193. Reserved0: byte;
  1194. REVID: byte; //Revision ID
  1195. EXTBRK: byte; //External Break
  1196. Reserved3: byte;
  1197. Reserved4: byte;
  1198. Reserved5: byte;
  1199. Reserved6: byte;
  1200. Reserved7: byte;
  1201. Reserved8: byte;
  1202. Reserved9: byte;
  1203. Reserved10: byte;
  1204. Reserved11: byte;
  1205. Reserved12: byte;
  1206. Reserved13: byte;
  1207. Reserved14: byte;
  1208. Reserved15: byte;
  1209. Reserved16: byte;
  1210. Reserved17: byte;
  1211. Reserved18: byte;
  1212. Reserved19: byte;
  1213. Reserved20: byte;
  1214. Reserved21: byte;
  1215. Reserved22: byte;
  1216. Reserved23: byte;
  1217. OCDM: byte; //OCD Message Register
  1218. OCDMS: byte; //OCD Message Status
  1219. const
  1220. // External break enable
  1221. ENEXTBRKbm = $01;
  1222. // OCD Message Read
  1223. OCDMRbm = $01;
  1224. end;
  1225. TTCA_SINGLE = object //16-bit Timer/Counter Type A - Single Mode
  1226. CTRLA: byte; //Control A
  1227. CTRLB: byte; //Control B
  1228. CTRLC: byte; //Control C
  1229. CTRLD: byte; //Control D
  1230. CTRLECLR: byte; //Control E Clear
  1231. CTRLESET: byte; //Control E Set
  1232. CTRLFCLR: byte; //Control F Clear
  1233. CTRLFSET: byte; //Control F Set
  1234. Reserved8: byte;
  1235. EVCTRL: byte; //Event Control
  1236. INTCTRL: byte; //Interrupt Control
  1237. INTFLAGS: byte; //Interrupt Flags
  1238. Reserved12: byte;
  1239. Reserved13: byte;
  1240. DBGCTRL: byte; //Degbug Control
  1241. TEMP: byte; //Temporary data for 16-bit Access
  1242. Reserved16: byte;
  1243. Reserved17: byte;
  1244. Reserved18: byte;
  1245. Reserved19: byte;
  1246. Reserved20: byte;
  1247. Reserved21: byte;
  1248. Reserved22: byte;
  1249. Reserved23: byte;
  1250. Reserved24: byte;
  1251. Reserved25: byte;
  1252. Reserved26: byte;
  1253. Reserved27: byte;
  1254. Reserved28: byte;
  1255. Reserved29: byte;
  1256. Reserved30: byte;
  1257. Reserved31: byte;
  1258. CNT: word; //Count
  1259. Reserved34: byte;
  1260. Reserved35: byte;
  1261. Reserved36: byte;
  1262. Reserved37: byte;
  1263. PER: word; //Period
  1264. CMP0: word; //Compare 0
  1265. CMP1: word; //Compare 1
  1266. CMP2: word; //Compare 2
  1267. Reserved46: byte;
  1268. Reserved47: byte;
  1269. Reserved48: byte;
  1270. Reserved49: byte;
  1271. Reserved50: byte;
  1272. Reserved51: byte;
  1273. Reserved52: byte;
  1274. Reserved53: byte;
  1275. PERBUF: word; //Period Buffer
  1276. CMP0BUF: word; //Compare 0 Buffer
  1277. CMP1BUF: word; //Compare 1 Buffer
  1278. CMP2BUF: word; //Compare 2 Buffer
  1279. const
  1280. // TCA_SINGLE_CLKSEL
  1281. SINGLE_CLKSELmask = $0E;
  1282. SINGLE_CLKSEL_DIV1 = $00;
  1283. SINGLE_CLKSEL_DIV2 = $02;
  1284. SINGLE_CLKSEL_DIV4 = $04;
  1285. SINGLE_CLKSEL_DIV8 = $06;
  1286. SINGLE_CLKSEL_DIV16 = $08;
  1287. SINGLE_CLKSEL_DIV64 = $0A;
  1288. SINGLE_CLKSEL_DIV256 = $0C;
  1289. SINGLE_CLKSEL_DIV1024 = $0E;
  1290. // Module Enable
  1291. ENABLEbm = $01;
  1292. // Auto Lock Update
  1293. ALUPDbm = $08;
  1294. // Compare 0 Enable
  1295. CMP0ENbm = $10;
  1296. // Compare 1 Enable
  1297. CMP1ENbm = $20;
  1298. // Compare 2 Enable
  1299. CMP2ENbm = $40;
  1300. // TCA_SINGLE_WGMODE
  1301. SINGLE_WGMODEmask = $07;
  1302. SINGLE_WGMODE_NORMAL = $00;
  1303. SINGLE_WGMODE_FRQ = $01;
  1304. SINGLE_WGMODE_SINGLESLOPE = $03;
  1305. SINGLE_WGMODE_DSTOP = $05;
  1306. SINGLE_WGMODE_DSBOTH = $06;
  1307. SINGLE_WGMODE_DSBOTTOM = $07;
  1308. // Compare 0 Waveform Output Value
  1309. CMP0OVbm = $01;
  1310. // Compare 1 Waveform Output Value
  1311. CMP1OVbm = $02;
  1312. // Compare 2 Waveform Output Value
  1313. CMP2OVbm = $04;
  1314. // Split Mode Enable
  1315. SPLITMbm = $01;
  1316. // TCA_SINGLE_CMD
  1317. SINGLE_CMDmask = $0C;
  1318. SINGLE_CMD_NONE = $00;
  1319. SINGLE_CMD_UPDATE = $04;
  1320. SINGLE_CMD_RESTART = $08;
  1321. SINGLE_CMD_RESET = $0C;
  1322. // Direction
  1323. DIRbm = $01;
  1324. // Lock Update
  1325. LUPDbm = $02;
  1326. // Compare 0 Buffer Valid
  1327. CMP0BVbm = $02;
  1328. // Compare 1 Buffer Valid
  1329. CMP1BVbm = $04;
  1330. // Compare 2 Buffer Valid
  1331. CMP2BVbm = $08;
  1332. // Period Buffer Valid
  1333. PERBVbm = $01;
  1334. // Debug Run
  1335. DBGRUNbm = $01;
  1336. // Count on Event Input
  1337. CNTEIbm = $01;
  1338. // TCA_SINGLE_EVACT
  1339. SINGLE_EVACTmask = $06;
  1340. SINGLE_EVACT_POSEDGE = $00;
  1341. SINGLE_EVACT_ANYEDGE = $02;
  1342. SINGLE_EVACT_HIGHLVL = $04;
  1343. SINGLE_EVACT_UPDOWN = $06;
  1344. // Compare 0 Interrupt
  1345. CMP0bm = $10;
  1346. // Compare 1 Interrupt
  1347. CMP1bm = $20;
  1348. // Compare 2 Interrupt
  1349. CMP2bm = $40;
  1350. // Overflow Interrupt
  1351. OVFbm = $01;
  1352. end;
  1353. TTCA_SPLIT = object //16-bit Timer/Counter Type A - Split Mode
  1354. CTRLA: byte; //Control A
  1355. CTRLB: byte; //Control B
  1356. CTRLC: byte; //Control C
  1357. CTRLD: byte; //Control D
  1358. CTRLECLR: byte; //Control E Clear
  1359. CTRLESET: byte; //Control E Set
  1360. Reserved6: byte;
  1361. Reserved7: byte;
  1362. Reserved8: byte;
  1363. Reserved9: byte;
  1364. INTCTRL: byte; //Interrupt Control
  1365. INTFLAGS: byte; //Interrupt Flags
  1366. Reserved12: byte;
  1367. Reserved13: byte;
  1368. DBGCTRL: byte; //Degbug Control
  1369. Reserved15: byte;
  1370. Reserved16: byte;
  1371. Reserved17: byte;
  1372. Reserved18: byte;
  1373. Reserved19: byte;
  1374. Reserved20: byte;
  1375. Reserved21: byte;
  1376. Reserved22: byte;
  1377. Reserved23: byte;
  1378. Reserved24: byte;
  1379. Reserved25: byte;
  1380. Reserved26: byte;
  1381. Reserved27: byte;
  1382. Reserved28: byte;
  1383. Reserved29: byte;
  1384. Reserved30: byte;
  1385. Reserved31: byte;
  1386. LCNT: byte; //Low Count
  1387. HCNT: byte; //High Count
  1388. Reserved34: byte;
  1389. Reserved35: byte;
  1390. Reserved36: byte;
  1391. Reserved37: byte;
  1392. LPER: byte; //Low Period
  1393. HPER: byte; //High Period
  1394. LCMP0: byte; //Low Compare
  1395. HCMP0: byte; //High Compare
  1396. LCMP1: byte; //Low Compare
  1397. HCMP1: byte; //High Compare
  1398. LCMP2: byte; //Low Compare
  1399. HCMP2: byte; //High Compare
  1400. const
  1401. // TCA_SPLIT_CLKSEL
  1402. SPLIT_CLKSELmask = $0E;
  1403. SPLIT_CLKSEL_DIV1 = $00;
  1404. SPLIT_CLKSEL_DIV2 = $02;
  1405. SPLIT_CLKSEL_DIV4 = $04;
  1406. SPLIT_CLKSEL_DIV8 = $06;
  1407. SPLIT_CLKSEL_DIV16 = $08;
  1408. SPLIT_CLKSEL_DIV64 = $0A;
  1409. SPLIT_CLKSEL_DIV256 = $0C;
  1410. SPLIT_CLKSEL_DIV1024 = $0E;
  1411. // Module Enable
  1412. ENABLEbm = $01;
  1413. // High Compare 0 Enable
  1414. HCMP0ENbm = $10;
  1415. // High Compare 1 Enable
  1416. HCMP1ENbm = $20;
  1417. // High Compare 2 Enable
  1418. HCMP2ENbm = $40;
  1419. // Low Compare 0 Enable
  1420. LCMP0ENbm = $01;
  1421. // Low Compare 1 Enable
  1422. LCMP1ENbm = $02;
  1423. // Low Compare 2 Enable
  1424. LCMP2ENbm = $04;
  1425. // High Compare 0 Output Value
  1426. HCMP0OVbm = $10;
  1427. // High Compare 1 Output Value
  1428. HCMP1OVbm = $20;
  1429. // High Compare 2 Output Value
  1430. HCMP2OVbm = $40;
  1431. // Low Compare 0 Output Value
  1432. LCMP0OVbm = $01;
  1433. // Low Compare 1 Output Value
  1434. LCMP1OVbm = $02;
  1435. // Low Compare 2 Output Value
  1436. LCMP2OVbm = $04;
  1437. // Split Mode Enable
  1438. SPLITMbm = $01;
  1439. // TCA_SPLIT_CMD
  1440. SPLIT_CMDmask = $0C;
  1441. SPLIT_CMD_NONE = $00;
  1442. SPLIT_CMD_UPDATE = $04;
  1443. SPLIT_CMD_RESTART = $08;
  1444. SPLIT_CMD_RESET = $0C;
  1445. // Debug Run
  1446. DBGRUNbm = $01;
  1447. // High Underflow Interrupt Enable
  1448. HUNFbm = $02;
  1449. // Low Compare 0 Interrupt Enable
  1450. LCMP0bm = $10;
  1451. // Low Compare 1 Interrupt Enable
  1452. LCMP1bm = $20;
  1453. // Low Compare 2 Interrupt Enable
  1454. LCMP2bm = $40;
  1455. // Low Underflow Interrupt Enable
  1456. LUNFbm = $01;
  1457. end;
  1458. TTCA = record //16-bit Timer/Counter Type A
  1459. case byte of
  1460. 0: (SINGLE: TTCA_SINGLE);
  1461. 1: (SPLIT: TTCA_SPLIT);
  1462. end;
  1463. TTCB = object //16-bit Timer Type B
  1464. CTRLA: byte; //Control A
  1465. CTRLB: byte; //Control Register B
  1466. Reserved2: byte;
  1467. Reserved3: byte;
  1468. EVCTRL: byte; //Event Control
  1469. INTCTRL: byte; //Interrupt Control
  1470. INTFLAGS: byte; //Interrupt Flags
  1471. STATUS: byte; //Status
  1472. DBGCTRL: byte; //Debug Control
  1473. TEMP: byte; //Temporary Value
  1474. CNT: word; //Count
  1475. CCMP: word; //Compare or Capture
  1476. const
  1477. // TCB_CLKSEL
  1478. CLKSELmask = $06;
  1479. CLKSEL_CLKDIV1 = $00;
  1480. CLKSEL_CLKDIV2 = $02;
  1481. CLKSEL_CLKTCA = $04;
  1482. // Enable
  1483. ENABLEbm = $01;
  1484. // Run Standby
  1485. RUNSTDBYbm = $40;
  1486. // Synchronize Update
  1487. SYNCUPDbm = $10;
  1488. // Asynchronous Enable
  1489. ASYNCbm = $40;
  1490. // Pin Output Enable
  1491. CCMPENbm = $10;
  1492. // Pin Initial State
  1493. CCMPINITbm = $20;
  1494. // TCB_CNTMODE
  1495. CNTMODEmask = $07;
  1496. CNTMODE_INT = $00;
  1497. CNTMODE_TIMEOUT = $01;
  1498. CNTMODE_CAPT = $02;
  1499. CNTMODE_FRQ = $03;
  1500. CNTMODE_PW = $04;
  1501. CNTMODE_FRQPW = $05;
  1502. CNTMODE_SINGLE = $06;
  1503. CNTMODE_PWM8 = $07;
  1504. // Debug Run
  1505. DBGRUNbm = $01;
  1506. // Event Input Enable
  1507. CAPTEIbm = $01;
  1508. // Event Edge
  1509. EDGEbm = $10;
  1510. // Input Capture Noise Cancellation Filter
  1511. FILTERbm = $40;
  1512. // Capture or Timeout
  1513. CAPTbm = $01;
  1514. // Run
  1515. RUNbm = $01;
  1516. end;
  1517. TTWI = object //Two-Wire Interface
  1518. CTRLA: byte; //Control A
  1519. DUALCTRL: byte; //Dual Control
  1520. DBGCTRL: byte; //Debug Control Register
  1521. MCTRLA: byte; //Master Control A
  1522. MCTRLB: byte; //Master Control B
  1523. MSTATUS: byte; //Master Status
  1524. MBAUD: byte; //Master Baurd Rate Control
  1525. MADDR: byte; //Master Address
  1526. MDATA: byte; //Master Data
  1527. SCTRLA: byte; //Slave Control A
  1528. SCTRLB: byte; //Slave Control B
  1529. SSTATUS: byte; //Slave Status
  1530. SADDR: byte; //Slave Address
  1531. SDATA: byte; //Slave Data
  1532. SADDRMASK: byte; //Slave Address Mask
  1533. const
  1534. // FM Plus Enable
  1535. FMPENbm = $02;
  1536. // TWI_DEFAULT_SDAHOLD
  1537. DEFAULT_SDAHOLDmask = $0C;
  1538. DEFAULT_SDAHOLD_OFF = $00;
  1539. DEFAULT_SDAHOLD_50NS = $04;
  1540. DEFAULT_SDAHOLD_300NS = $08;
  1541. DEFAULT_SDAHOLD_500NS = $0C;
  1542. // TWI_DEFAULT_SDASETUP
  1543. DEFAULT_SDASETUPmask = $10;
  1544. DEFAULT_SDASETUP_4CYC = $00;
  1545. DEFAULT_SDASETUP_8CYC = $10;
  1546. // Debug Run
  1547. DBGRUNbm = $01;
  1548. // Dual Control Enable
  1549. ENABLEbm = $01;
  1550. // Quick Command Enable
  1551. QCENbm = $10;
  1552. // Read Interrupt Enable
  1553. RIENbm = $80;
  1554. // Smart Mode Enable
  1555. SMENbm = $02;
  1556. // TWI_TIMEOUT
  1557. TIMEOUTmask = $0C;
  1558. TIMEOUT_DISABLED = $00;
  1559. TIMEOUT_50US = $04;
  1560. TIMEOUT_100US = $08;
  1561. TIMEOUT_200US = $0C;
  1562. // Write Interrupt Enable
  1563. WIENbm = $40;
  1564. // TWI_ACKACT
  1565. ACKACTmask = $04;
  1566. ACKACT_ACK = $00;
  1567. ACKACT_NACK = $04;
  1568. // Flush
  1569. FLUSHbm = $08;
  1570. // TWI_MCMD
  1571. MCMDmask = $03;
  1572. MCMD_NOACT = $00;
  1573. MCMD_REPSTART = $01;
  1574. MCMD_RECVTRANS = $02;
  1575. MCMD_STOP = $03;
  1576. // Arbitration Lost
  1577. ARBLOSTbm = $08;
  1578. // Bus Error
  1579. BUSERRbm = $04;
  1580. // TWI_BUSSTATE
  1581. BUSSTATEmask = $03;
  1582. BUSSTATE_UNKNOWN = $00;
  1583. BUSSTATE_IDLE = $01;
  1584. BUSSTATE_OWNER = $02;
  1585. BUSSTATE_BUSY = $03;
  1586. // Clock Hold
  1587. CLKHOLDbm = $20;
  1588. // Read Interrupt Flag
  1589. RIFbm = $80;
  1590. // Received Acknowledge
  1591. RXACKbm = $10;
  1592. // Write Interrupt Flag
  1593. WIFbm = $40;
  1594. // Address Enable
  1595. ADDRENbm = $01;
  1596. // Address Mask
  1597. ADDRMASK0bm = $02;
  1598. ADDRMASK1bm = $04;
  1599. ADDRMASK2bm = $08;
  1600. ADDRMASK3bm = $10;
  1601. ADDRMASK4bm = $20;
  1602. ADDRMASK5bm = $40;
  1603. ADDRMASK6bm = $80;
  1604. // Address/Stop Interrupt Enable
  1605. APIENbm = $40;
  1606. // Data Interrupt Enable
  1607. DIENbm = $80;
  1608. // Stop Interrupt Enable
  1609. PIENbm = $20;
  1610. // Promiscuous Mode Enable
  1611. PMENbm = $04;
  1612. // TWI_SCMD
  1613. SCMDmask = $03;
  1614. SCMD_NOACT = $00;
  1615. SCMD_COMPTRANS = $02;
  1616. SCMD_RESPONSE = $03;
  1617. // TWI_AP
  1618. APmask = $01;
  1619. AP_STOP = $00;
  1620. AP_ADR = $01;
  1621. // Address/Stop Interrupt Flag
  1622. APIFbm = $40;
  1623. // Collision
  1624. COLLbm = $08;
  1625. // Data Interrupt Flag
  1626. DIFbm = $80;
  1627. // Read/Write Direction
  1628. DIRbm = $02;
  1629. end;
  1630. TUSART = object //Universal Synchronous and Asynchronous Receiver and Transmitter
  1631. RXDATAL: byte; //Receive Data Low Byte
  1632. RXDATAH: byte; //Receive Data High Byte
  1633. TXDATAL: byte; //Transmit Data Low Byte
  1634. TXDATAH: byte; //Transmit Data High Byte
  1635. STATUS: byte; //Status
  1636. CTRLA: byte; //Control A
  1637. CTRLB: byte; //Control B
  1638. CTRLC: byte; //Control C
  1639. BAUD: word; //Baud Rate
  1640. CTRLD: byte; //Control D
  1641. DBGCTRL: byte; //Debug Control
  1642. EVCTRL: byte; //Event Control
  1643. TXPLCTRL: byte; //IRCOM Transmitter Pulse Length Control
  1644. RXPLCTRL: byte; //IRCOM Receiver Pulse Length Control
  1645. const
  1646. // Auto-baud Error Interrupt Enable
  1647. ABEIEbm = $04;
  1648. // Data Register Empty Interrupt Enable
  1649. DREIEbm = $20;
  1650. // Loop-back Mode Enable
  1651. LBMEbm = $08;
  1652. // USART_RS485
  1653. RS485mask = $03;
  1654. RS485_OFF = $00;
  1655. RS485_EXT = $01;
  1656. RS485_INT = $02;
  1657. // Receive Complete Interrupt Enable
  1658. RXCIEbm = $80;
  1659. // Receiver Start Frame Interrupt Enable
  1660. RXSIEbm = $10;
  1661. // Transmit Complete Interrupt Enable
  1662. TXCIEbm = $40;
  1663. // Multi-processor Communication Mode
  1664. MPCMbm = $01;
  1665. // Open Drain Mode Enable
  1666. ODMEbm = $08;
  1667. // Reciever enable
  1668. RXENbm = $80;
  1669. // USART_RXMODE
  1670. RXMODEmask = $06;
  1671. RXMODE_NORMAL = $00;
  1672. RXMODE_CLK2X = $02;
  1673. RXMODE_GENAUTO = $04;
  1674. RXMODE_LINAUTO = $06;
  1675. // Start Frame Detection Enable
  1676. SFDENbm = $10;
  1677. // Transmitter Enable
  1678. TXENbm = $40;
  1679. // USART_MSPI_CMODE
  1680. MSPI_CMODEmask = $C0;
  1681. MSPI_CMODE_ASYNCHRONOUS = $00;
  1682. MSPI_CMODE_SYNCHRONOUS = $40;
  1683. MSPI_CMODE_IRCOM = $80;
  1684. MSPI_CMODE_MSPI = $C0;
  1685. // SPI Master Mode, Clock Phase
  1686. UCPHAbm = $02;
  1687. // SPI Master Mode, Data Order
  1688. UDORDbm = $04;
  1689. // USART_NORMAL_CHSIZE
  1690. NORMAL_CHSIZEmask = $07;
  1691. NORMAL_CHSIZE_5BIT = $00;
  1692. NORMAL_CHSIZE_6BIT = $01;
  1693. NORMAL_CHSIZE_7BIT = $02;
  1694. NORMAL_CHSIZE_8BIT = $03;
  1695. NORMAL_CHSIZE_9BITL = $06;
  1696. NORMAL_CHSIZE_9BITH = $07;
  1697. // USART_NORMAL_CMODE
  1698. NORMAL_CMODEmask = $C0;
  1699. NORMAL_CMODE_ASYNCHRONOUS = $00;
  1700. NORMAL_CMODE_SYNCHRONOUS = $40;
  1701. NORMAL_CMODE_IRCOM = $80;
  1702. NORMAL_CMODE_MSPI = $C0;
  1703. // USART_NORMAL_PMODE
  1704. NORMAL_PMODEmask = $30;
  1705. NORMAL_PMODE_DISABLED = $00;
  1706. NORMAL_PMODE_EVEN = $20;
  1707. NORMAL_PMODE_ODD = $30;
  1708. // USART_NORMAL_SBMODE
  1709. NORMAL_SBMODEmask = $08;
  1710. NORMAL_SBMODE_1BIT = $00;
  1711. NORMAL_SBMODE_2BIT = $08;
  1712. // USART_ABW
  1713. ABWmask = $C0;
  1714. ABW_WDW0 = $00;
  1715. ABW_WDW1 = $40;
  1716. ABW_WDW2 = $80;
  1717. ABW_WDW3 = $C0;
  1718. // Autobaud majority voter bypass
  1719. ABMBPbm = $80;
  1720. // Debug Run
  1721. DBGRUNbm = $01;
  1722. // IrDA Event Input Enable
  1723. IREIbm = $01;
  1724. // Buffer Overflow
  1725. BUFOVFbm = $40;
  1726. // Receiver Data Register
  1727. DATA8bm = $01;
  1728. // Frame Error
  1729. FERRbm = $04;
  1730. // Parity Error
  1731. PERRbm = $02;
  1732. // Receive Complete Interrupt Flag
  1733. RXCIFbm = $80;
  1734. // RX Data
  1735. DATA0bm = $01;
  1736. DATA1bm = $02;
  1737. DATA2bm = $04;
  1738. DATA3bm = $08;
  1739. DATA4bm = $10;
  1740. DATA5bm = $20;
  1741. DATA6bm = $40;
  1742. DATA7bm = $80;
  1743. // Receiver Pulse Lenght
  1744. RXPL0bm = $01;
  1745. RXPL1bm = $02;
  1746. RXPL2bm = $04;
  1747. RXPL3bm = $08;
  1748. RXPL4bm = $10;
  1749. RXPL5bm = $20;
  1750. RXPL6bm = $40;
  1751. // Break Detected Flag
  1752. BDFbm = $02;
  1753. // Data Register Empty Flag
  1754. DREIFbm = $20;
  1755. // Inconsistent Sync Field Interrupt Flag
  1756. ISFIFbm = $08;
  1757. // Receive Start Interrupt
  1758. RXSIFbm = $10;
  1759. // Transmit Interrupt Flag
  1760. TXCIFbm = $40;
  1761. // Wait For Break
  1762. WFBbm = $01;
  1763. // Transmit pulse length
  1764. TXPL0bm = $01;
  1765. TXPL1bm = $02;
  1766. TXPL2bm = $04;
  1767. TXPL3bm = $08;
  1768. TXPL4bm = $10;
  1769. TXPL5bm = $20;
  1770. TXPL6bm = $40;
  1771. TXPL7bm = $80;
  1772. end;
  1773. TUSERROW = object //User Row
  1774. USERROW0: byte; //User Row Byte 0
  1775. USERROW1: byte; //User Row Byte 1
  1776. USERROW2: byte; //User Row Byte 2
  1777. USERROW3: byte; //User Row Byte 3
  1778. USERROW4: byte; //User Row Byte 4
  1779. USERROW5: byte; //User Row Byte 5
  1780. USERROW6: byte; //User Row Byte 6
  1781. USERROW7: byte; //User Row Byte 7
  1782. USERROW8: byte; //User Row Byte 8
  1783. USERROW9: byte; //User Row Byte 9
  1784. USERROW10: byte; //User Row Byte 10
  1785. USERROW11: byte; //User Row Byte 11
  1786. USERROW12: byte; //User Row Byte 12
  1787. USERROW13: byte; //User Row Byte 13
  1788. USERROW14: byte; //User Row Byte 14
  1789. USERROW15: byte; //User Row Byte 15
  1790. USERROW16: byte; //User Row Byte 16
  1791. USERROW17: byte; //User Row Byte 17
  1792. USERROW18: byte; //User Row Byte 18
  1793. USERROW19: byte; //User Row Byte 19
  1794. USERROW20: byte; //User Row Byte 20
  1795. USERROW21: byte; //User Row Byte 21
  1796. USERROW22: byte; //User Row Byte 22
  1797. USERROW23: byte; //User Row Byte 23
  1798. USERROW24: byte; //User Row Byte 24
  1799. USERROW25: byte; //User Row Byte 25
  1800. USERROW26: byte; //User Row Byte 26
  1801. USERROW27: byte; //User Row Byte 27
  1802. USERROW28: byte; //User Row Byte 28
  1803. USERROW29: byte; //User Row Byte 29
  1804. USERROW30: byte; //User Row Byte 30
  1805. USERROW31: byte; //User Row Byte 31
  1806. USERROW32: byte; //User Row Byte 32
  1807. USERROW33: byte; //User Row Byte 33
  1808. USERROW34: byte; //User Row Byte 34
  1809. USERROW35: byte; //User Row Byte 35
  1810. USERROW36: byte; //User Row Byte 36
  1811. USERROW37: byte; //User Row Byte 37
  1812. USERROW38: byte; //User Row Byte 38
  1813. USERROW39: byte; //User Row Byte 39
  1814. USERROW40: byte; //User Row Byte 40
  1815. USERROW41: byte; //User Row Byte 41
  1816. USERROW42: byte; //User Row Byte 42
  1817. USERROW43: byte; //User Row Byte 43
  1818. USERROW44: byte; //User Row Byte 44
  1819. USERROW45: byte; //User Row Byte 45
  1820. USERROW46: byte; //User Row Byte 46
  1821. USERROW47: byte; //User Row Byte 47
  1822. USERROW48: byte; //User Row Byte 48
  1823. USERROW49: byte; //User Row Byte 49
  1824. USERROW50: byte; //User Row Byte 50
  1825. USERROW51: byte; //User Row Byte 51
  1826. USERROW52: byte; //User Row Byte 52
  1827. USERROW53: byte; //User Row Byte 53
  1828. USERROW54: byte; //User Row Byte 54
  1829. USERROW55: byte; //User Row Byte 55
  1830. USERROW56: byte; //User Row Byte 56
  1831. USERROW57: byte; //User Row Byte 57
  1832. USERROW58: byte; //User Row Byte 58
  1833. USERROW59: byte; //User Row Byte 59
  1834. USERROW60: byte; //User Row Byte 60
  1835. USERROW61: byte; //User Row Byte 61
  1836. USERROW62: byte; //User Row Byte 62
  1837. USERROW63: byte; //User Row Byte 63
  1838. end;
  1839. TVPORT = object //Virtual Ports
  1840. DIR: byte; //Data Direction
  1841. OUT_: byte; //Output Value
  1842. IN_: byte; //Input Value
  1843. INTFLAGS: byte; //Interrupt Flags
  1844. const
  1845. // Pin Interrupt
  1846. INT0bm = $01;
  1847. INT1bm = $02;
  1848. INT2bm = $04;
  1849. INT3bm = $08;
  1850. INT4bm = $10;
  1851. INT5bm = $20;
  1852. INT6bm = $40;
  1853. INT7bm = $80;
  1854. end;
  1855. TVREF = object //Voltage reference
  1856. CTRLA: byte; //Control A
  1857. CTRLB: byte; //Control B
  1858. const
  1859. // VREF_AC0REFSEL
  1860. AC0REFSELmask = $07;
  1861. AC0REFSEL_0V55 = $00;
  1862. AC0REFSEL_1V1 = $01;
  1863. AC0REFSEL_2V5 = $02;
  1864. AC0REFSEL_4V34 = $03;
  1865. AC0REFSEL_1V5 = $04;
  1866. AC0REFSEL_AVDD = $07;
  1867. // VREF_ADC0REFSEL
  1868. ADC0REFSELmask = $70;
  1869. ADC0REFSEL_0V55 = $00;
  1870. ADC0REFSEL_1V1 = $10;
  1871. ADC0REFSEL_2V5 = $20;
  1872. ADC0REFSEL_4V34 = $30;
  1873. ADC0REFSEL_1V5 = $40;
  1874. // AC0 DACREF reference enable
  1875. AC0REFENbm = $01;
  1876. // ADC0 reference enable
  1877. ADC0REFENbm = $02;
  1878. end;
  1879. TWDT = object //Watch-Dog Timer
  1880. CTRLA: byte; //Control A
  1881. STATUS: byte; //Status
  1882. const
  1883. // WDT_PERIOD
  1884. PERIODmask = $0F;
  1885. PERIOD_OFF = $00;
  1886. PERIOD_8CLK = $01;
  1887. PERIOD_16CLK = $02;
  1888. PERIOD_32CLK = $03;
  1889. PERIOD_64CLK = $04;
  1890. PERIOD_128CLK = $05;
  1891. PERIOD_256CLK = $06;
  1892. PERIOD_512CLK = $07;
  1893. PERIOD_1KCLK = $08;
  1894. PERIOD_2KCLK = $09;
  1895. PERIOD_4KCLK = $0A;
  1896. PERIOD_8KCLK = $0B;
  1897. // WDT_WINDOW
  1898. WINDOWmask = $F0;
  1899. WINDOW_OFF = $00;
  1900. WINDOW_8CLK = $10;
  1901. WINDOW_16CLK = $20;
  1902. WINDOW_32CLK = $30;
  1903. WINDOW_64CLK = $40;
  1904. WINDOW_128CLK = $50;
  1905. WINDOW_256CLK = $60;
  1906. WINDOW_512CLK = $70;
  1907. WINDOW_1KCLK = $80;
  1908. WINDOW_2KCLK = $90;
  1909. WINDOW_4KCLK = $A0;
  1910. WINDOW_8KCLK = $B0;
  1911. // Lock enable
  1912. LOCKbm = $80;
  1913. // Syncronization busy
  1914. SYNCBUSYbm = $01;
  1915. end;
  1916. const
  1917. Pin0idx = 0; Pin0bm = 1;
  1918. Pin1idx = 1; Pin1bm = 2;
  1919. Pin2idx = 2; Pin2bm = 4;
  1920. Pin3idx = 3; Pin3bm = 8;
  1921. Pin4idx = 4; Pin4bm = 16;
  1922. Pin5idx = 5; Pin5bm = 32;
  1923. Pin6idx = 6; Pin6bm = 64;
  1924. Pin7idx = 7; Pin7bm = 128;
  1925. var
  1926. VPORTA: TVPORT absolute $0000;
  1927. VPORTB: TVPORT absolute $0004;
  1928. VPORTC: TVPORT absolute $0008;
  1929. VPORTD: TVPORT absolute $000C;
  1930. VPORTE: TVPORT absolute $0010;
  1931. VPORTF: TVPORT absolute $0014;
  1932. GPIO: TGPIO absolute $001C;
  1933. CPU: TCPU absolute $0030;
  1934. RSTCTRL: TRSTCTRL absolute $0040;
  1935. SLPCTRL: TSLPCTRL absolute $0050;
  1936. CLKCTRL: TCLKCTRL absolute $0060;
  1937. BOD: TBOD absolute $0080;
  1938. VREF: TVREF absolute $00A0;
  1939. WDT: TWDT absolute $0100;
  1940. CPUINT: TCPUINT absolute $0110;
  1941. CRCSCAN: TCRCSCAN absolute $0120;
  1942. RTC: TRTC absolute $0140;
  1943. EVSYS: TEVSYS absolute $0180;
  1944. CCL: TCCL absolute $01C0;
  1945. PORTA: TPORT absolute $0400;
  1946. PORTB: TPORT absolute $0420;
  1947. PORTC: TPORT absolute $0440;
  1948. PORTD: TPORT absolute $0460;
  1949. PORTE: TPORT absolute $0480;
  1950. PORTF: TPORT absolute $04A0;
  1951. PORTMUX: TPORTMUX absolute $05E0;
  1952. ADC0: TADC absolute $0600;
  1953. AC0: TAC absolute $0680;
  1954. USART0: TUSART absolute $0800;
  1955. USART1: TUSART absolute $0820;
  1956. USART2: TUSART absolute $0840;
  1957. TWI0: TTWI absolute $08A0;
  1958. SPI0: TSPI absolute $08C0;
  1959. TCA0: TTCA absolute $0A00;
  1960. TCB0: TTCB absolute $0A80;
  1961. TCB1: TTCB absolute $0A90;
  1962. TCB2: TTCB absolute $0AA0;
  1963. SYSCFG: TSYSCFG absolute $0F00;
  1964. NVMCTRL: TNVMCTRL absolute $1000;
  1965. SIGROW: TSIGROW absolute $1100;
  1966. FUSE: TFUSE absolute $1280;
  1967. LOCKBIT: TLOCKBIT absolute $128A;
  1968. USERROW: TUSERROW absolute $1300;
  1969. implementation
  1970. {$i avrcommon.inc}
  1971. procedure CRCSCAN_NMI_ISR; external name 'CRCSCAN_NMI_ISR'; // Interrupt 1
  1972. procedure BOD_VLM_ISR; external name 'BOD_VLM_ISR'; // Interrupt 2
  1973. procedure RTC_CNT_ISR; external name 'RTC_CNT_ISR'; // Interrupt 3
  1974. procedure RTC_PIT_ISR; external name 'RTC_PIT_ISR'; // Interrupt 4
  1975. procedure CCL_CCL_ISR; external name 'CCL_CCL_ISR'; // Interrupt 5
  1976. procedure PORTA_PORT_ISR; external name 'PORTA_PORT_ISR'; // Interrupt 6
  1977. procedure TCA0_LUNF_ISR; external name 'TCA0_LUNF_ISR'; // Interrupt 7
  1978. //procedure TCA0_OVF_ISR; external name 'TCA0_OVF_ISR'; // Interrupt 7
  1979. procedure TCA0_HUNF_ISR; external name 'TCA0_HUNF_ISR'; // Interrupt 8
  1980. procedure TCA0_LCMP0_ISR; external name 'TCA0_LCMP0_ISR'; // Interrupt 9
  1981. //procedure TCA0_CMP0_ISR; external name 'TCA0_CMP0_ISR'; // Interrupt 9
  1982. procedure TCA0_LCMP1_ISR; external name 'TCA0_LCMP1_ISR'; // Interrupt 10
  1983. //procedure TCA0_CMP1_ISR; external name 'TCA0_CMP1_ISR'; // Interrupt 10
  1984. procedure TCA0_CMP2_ISR; external name 'TCA0_CMP2_ISR'; // Interrupt 11
  1985. //procedure TCA0_LCMP2_ISR; external name 'TCA0_LCMP2_ISR'; // Interrupt 11
  1986. procedure TCB0_INT_ISR; external name 'TCB0_INT_ISR'; // Interrupt 12
  1987. procedure TCB1_INT_ISR; external name 'TCB1_INT_ISR'; // Interrupt 13
  1988. procedure TWI0_TWIS_ISR; external name 'TWI0_TWIS_ISR'; // Interrupt 14
  1989. procedure TWI0_TWIM_ISR; external name 'TWI0_TWIM_ISR'; // Interrupt 15
  1990. procedure SPI0_INT_ISR; external name 'SPI0_INT_ISR'; // Interrupt 16
  1991. procedure USART0_RXC_ISR; external name 'USART0_RXC_ISR'; // Interrupt 17
  1992. procedure USART0_DRE_ISR; external name 'USART0_DRE_ISR'; // Interrupt 18
  1993. procedure USART0_TXC_ISR; external name 'USART0_TXC_ISR'; // Interrupt 19
  1994. procedure PORTD_PORT_ISR; external name 'PORTD_PORT_ISR'; // Interrupt 20
  1995. procedure AC0_AC_ISR; external name 'AC0_AC_ISR'; // Interrupt 21
  1996. procedure ADC0_RESRDY_ISR; external name 'ADC0_RESRDY_ISR'; // Interrupt 22
  1997. procedure ADC0_WCOMP_ISR; external name 'ADC0_WCOMP_ISR'; // Interrupt 23
  1998. procedure PORTC_PORT_ISR; external name 'PORTC_PORT_ISR'; // Interrupt 24
  1999. procedure TCB2_INT_ISR; external name 'TCB2_INT_ISR'; // Interrupt 25
  2000. procedure USART1_RXC_ISR; external name 'USART1_RXC_ISR'; // Interrupt 26
  2001. procedure USART1_DRE_ISR; external name 'USART1_DRE_ISR'; // Interrupt 27
  2002. procedure USART1_TXC_ISR; external name 'USART1_TXC_ISR'; // Interrupt 28
  2003. procedure PORTF_PORT_ISR; external name 'PORTF_PORT_ISR'; // Interrupt 29
  2004. procedure NVMCTRL_EE_ISR; external name 'NVMCTRL_EE_ISR'; // Interrupt 30
  2005. procedure USART2_RXC_ISR; external name 'USART2_RXC_ISR'; // Interrupt 31
  2006. procedure USART2_DRE_ISR; external name 'USART2_DRE_ISR'; // Interrupt 32
  2007. procedure USART2_TXC_ISR; external name 'USART2_TXC_ISR'; // Interrupt 33
  2008. procedure PORTB_PORT_ISR; external name 'PORTB_PORT_ISR'; // Interrupt 34
  2009. procedure PORTE_PORT_ISR; external name 'PORTE_PORT_ISR'; // Interrupt 35
  2010. procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';
  2011. asm
  2012. jmp __dtors_end
  2013. jmp CRCSCAN_NMI_ISR
  2014. jmp BOD_VLM_ISR
  2015. jmp RTC_CNT_ISR
  2016. jmp RTC_PIT_ISR
  2017. jmp CCL_CCL_ISR
  2018. jmp PORTA_PORT_ISR
  2019. jmp TCA0_LUNF_ISR
  2020. // jmp TCA0_OVF_ISR
  2021. jmp TCA0_HUNF_ISR
  2022. jmp TCA0_LCMP0_ISR
  2023. // jmp TCA0_CMP0_ISR
  2024. jmp TCA0_LCMP1_ISR
  2025. // jmp TCA0_CMP1_ISR
  2026. jmp TCA0_CMP2_ISR
  2027. // jmp TCA0_LCMP2_ISR
  2028. jmp TCB0_INT_ISR
  2029. jmp TCB1_INT_ISR
  2030. jmp TWI0_TWIS_ISR
  2031. jmp TWI0_TWIM_ISR
  2032. jmp SPI0_INT_ISR
  2033. jmp USART0_RXC_ISR
  2034. jmp USART0_DRE_ISR
  2035. jmp USART0_TXC_ISR
  2036. jmp PORTD_PORT_ISR
  2037. jmp AC0_AC_ISR
  2038. jmp ADC0_RESRDY_ISR
  2039. jmp ADC0_WCOMP_ISR
  2040. jmp PORTC_PORT_ISR
  2041. jmp TCB2_INT_ISR
  2042. jmp USART1_RXC_ISR
  2043. jmp USART1_DRE_ISR
  2044. jmp USART1_TXC_ISR
  2045. jmp PORTF_PORT_ISR
  2046. jmp NVMCTRL_EE_ISR
  2047. jmp USART2_RXC_ISR
  2048. jmp USART2_DRE_ISR
  2049. jmp USART2_TXC_ISR
  2050. jmp PORTB_PORT_ISR
  2051. jmp PORTE_PORT_ISR
  2052. .weak CRCSCAN_NMI_ISR
  2053. .weak BOD_VLM_ISR
  2054. .weak RTC_CNT_ISR
  2055. .weak RTC_PIT_ISR
  2056. .weak CCL_CCL_ISR
  2057. .weak PORTA_PORT_ISR
  2058. .weak TCA0_LUNF_ISR
  2059. // .weak TCA0_OVF_ISR
  2060. .weak TCA0_HUNF_ISR
  2061. .weak TCA0_LCMP0_ISR
  2062. // .weak TCA0_CMP0_ISR
  2063. .weak TCA0_LCMP1_ISR
  2064. // .weak TCA0_CMP1_ISR
  2065. .weak TCA0_CMP2_ISR
  2066. // .weak TCA0_LCMP2_ISR
  2067. .weak TCB0_INT_ISR
  2068. .weak TCB1_INT_ISR
  2069. .weak TWI0_TWIS_ISR
  2070. .weak TWI0_TWIM_ISR
  2071. .weak SPI0_INT_ISR
  2072. .weak USART0_RXC_ISR
  2073. .weak USART0_DRE_ISR
  2074. .weak USART0_TXC_ISR
  2075. .weak PORTD_PORT_ISR
  2076. .weak AC0_AC_ISR
  2077. .weak ADC0_RESRDY_ISR
  2078. .weak ADC0_WCOMP_ISR
  2079. .weak PORTC_PORT_ISR
  2080. .weak TCB2_INT_ISR
  2081. .weak USART1_RXC_ISR
  2082. .weak USART1_DRE_ISR
  2083. .weak USART1_TXC_ISR
  2084. .weak PORTF_PORT_ISR
  2085. .weak NVMCTRL_EE_ISR
  2086. .weak USART2_RXC_ISR
  2087. .weak USART2_DRE_ISR
  2088. .weak USART2_TXC_ISR
  2089. .weak PORTB_PORT_ISR
  2090. .weak PORTE_PORT_ISR
  2091. .set CRCSCAN_NMI_ISR, Default_IRQ_handler
  2092. .set BOD_VLM_ISR, Default_IRQ_handler
  2093. .set RTC_CNT_ISR, Default_IRQ_handler
  2094. .set RTC_PIT_ISR, Default_IRQ_handler
  2095. .set CCL_CCL_ISR, Default_IRQ_handler
  2096. .set PORTA_PORT_ISR, Default_IRQ_handler
  2097. .set TCA0_LUNF_ISR, Default_IRQ_handler
  2098. // .set TCA0_OVF_ISR, Default_IRQ_handler
  2099. .set TCA0_HUNF_ISR, Default_IRQ_handler
  2100. .set TCA0_LCMP0_ISR, Default_IRQ_handler
  2101. // .set TCA0_CMP0_ISR, Default_IRQ_handler
  2102. .set TCA0_LCMP1_ISR, Default_IRQ_handler
  2103. // .set TCA0_CMP1_ISR, Default_IRQ_handler
  2104. .set TCA0_CMP2_ISR, Default_IRQ_handler
  2105. // .set TCA0_LCMP2_ISR, Default_IRQ_handler
  2106. .set TCB0_INT_ISR, Default_IRQ_handler
  2107. .set TCB1_INT_ISR, Default_IRQ_handler
  2108. .set TWI0_TWIS_ISR, Default_IRQ_handler
  2109. .set TWI0_TWIM_ISR, Default_IRQ_handler
  2110. .set SPI0_INT_ISR, Default_IRQ_handler
  2111. .set USART0_RXC_ISR, Default_IRQ_handler
  2112. .set USART0_DRE_ISR, Default_IRQ_handler
  2113. .set USART0_TXC_ISR, Default_IRQ_handler
  2114. .set PORTD_PORT_ISR, Default_IRQ_handler
  2115. .set AC0_AC_ISR, Default_IRQ_handler
  2116. .set ADC0_RESRDY_ISR, Default_IRQ_handler
  2117. .set ADC0_WCOMP_ISR, Default_IRQ_handler
  2118. .set PORTC_PORT_ISR, Default_IRQ_handler
  2119. .set TCB2_INT_ISR, Default_IRQ_handler
  2120. .set USART1_RXC_ISR, Default_IRQ_handler
  2121. .set USART1_DRE_ISR, Default_IRQ_handler
  2122. .set USART1_TXC_ISR, Default_IRQ_handler
  2123. .set PORTF_PORT_ISR, Default_IRQ_handler
  2124. .set NVMCTRL_EE_ISR, Default_IRQ_handler
  2125. .set USART2_RXC_ISR, Default_IRQ_handler
  2126. .set USART2_DRE_ISR, Default_IRQ_handler
  2127. .set USART2_TXC_ISR, Default_IRQ_handler
  2128. .set PORTB_PORT_ISR, Default_IRQ_handler
  2129. .set PORTE_PORT_ISR, Default_IRQ_handler
  2130. end;
  2131. end.