atmega64.pp 23 KB

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  1. unit ATmega64;
  2. interface
  3. var
  4. // ANALOG_COMPARATOR
  5. SFIOR : byte absolute $00+$40; // Special Function IO Register
  6. ACSR : byte absolute $00+$28; // Analog Comparator Control And Status Register
  7. // AD_CONVERTER
  8. ADMUX : byte absolute $00+$27; // The ADC multiplexer Selection Register
  9. ADC : word absolute $00+$24; // ADC Data Register Bytes
  10. ADCL : byte absolute $00+$24; // ADC Data Register Bytes
  11. ADCH : byte absolute $00+$24+1; // ADC Data Register Bytes
  12. ADCSRA : byte absolute $00+$26; // The ADC Control and Status register A
  13. ADCSRB : byte absolute $00+$8E; // The ADC Control and Status register B
  14. // SPI
  15. SPDR : byte absolute $00+$2F; // SPI Data Register
  16. SPSR : byte absolute $00+$2E; // SPI Status Register
  17. SPCR : byte absolute $00+$2D; // SPI Control Register
  18. // TWI
  19. TWBR : byte absolute $00+$70; // TWI Bit Rate register
  20. TWCR : byte absolute $00+$74; // TWI Control Register
  21. TWSR : byte absolute $00+$71; // TWI Status Register
  22. TWDR : byte absolute $00+$73; // TWI Data register
  23. TWAR : byte absolute $00+$72; // TWI (Slave) Address register
  24. // USART0
  25. UDR0 : byte absolute $00+$2C; // USART I/O Data Register
  26. UCSR0A : byte absolute $00+$2B; // USART Control and Status Register A
  27. UCSR0B : byte absolute $00+$2A; // USART Control and Status Register B
  28. UCSR0C : byte absolute $00+$95; // USART Control and Status Register C
  29. UBRR0H : byte absolute $00+$90; // USART Baud Rate Register Hight Byte
  30. UBRR0L : byte absolute $00+$29; // USART Baud Rate Register Low Byte
  31. // USART1
  32. UDR1 : byte absolute $00+$9C; // USART I/O Data Register
  33. UCSR1A : byte absolute $00+$9B; // USART Control and Status Register A
  34. UCSR1B : byte absolute $00+$9A; // USART Control and Status Register B
  35. UCSR1C : byte absolute $00+$9D; // USART Control and Status Register C
  36. UBRR1H : byte absolute $00+$98; // USART Baud Rate Register Hight Byte
  37. UBRR1L : byte absolute $00+$99; // USART Baud Rate Register Low Byte
  38. // CPU
  39. SREG : byte absolute $00+$5F; // Status Register
  40. SP : word absolute $00+$5D; // Stack Pointer
  41. SPL : byte absolute $00+$5D; // Stack Pointer
  42. SPH : byte absolute $00+$5D+1; // Stack Pointer
  43. MCUCR : byte absolute $00+$55; // MCU Control Register
  44. MCUCSR : byte absolute $00+$54; // MCU Control And Status Register
  45. XMCRA : byte absolute $00+$6D; // External Memory Control Register A
  46. XMCRB : byte absolute $00+$6C; // External Memory Control Register B
  47. OSCCAL : byte absolute $00+$6F; // Oscillator Calibration Value
  48. XDIV : byte absolute $00+$5C; // XTAL Divide Control Register
  49. // BOOT_LOAD
  50. SPMCSR : byte absolute $00+$68; // Store Program Memory Control Register
  51. // JTAG
  52. OCDR : byte absolute $00+$42; // On-Chip Debug Related Register in I/O Memory
  53. // MISC
  54. // EXTERNAL_INTERRUPT
  55. EICRA : byte absolute $00+$6A; // External Interrupt Control Register A
  56. EICRB : byte absolute $00+$5A; // External Interrupt Control Register B
  57. EIMSK : byte absolute $00+$59; // External Interrupt Mask Register
  58. EIFR : byte absolute $00+$58; // External Interrupt Flag Register
  59. // EEPROM
  60. EEAR : word absolute $00+$3E; // EEPROM Read/Write Access Bytes
  61. EEARL : byte absolute $00+$3E; // EEPROM Read/Write Access Bytes
  62. EEARH : byte absolute $00+$3E+1; // EEPROM Read/Write Access Bytes
  63. EEDR : byte absolute $00+$3D; // EEPROM Data Register
  64. EECR : byte absolute $00+$3C; // EEPROM Control Register
  65. // PORTA
  66. PORTA : byte absolute $00+$3B; // Port A Data Register
  67. DDRA : byte absolute $00+$3A; // Port A Data Direction Register
  68. PINA : byte absolute $00+$39; // Port A Input Pins
  69. // PORTB
  70. PORTB : byte absolute $00+$38; // Port B Data Register
  71. DDRB : byte absolute $00+$37; // Port B Data Direction Register
  72. PINB : byte absolute $00+$36; // Port B Input Pins
  73. // PORTC
  74. PORTC : byte absolute $00+$35; // Port C Data Register
  75. DDRC : byte absolute $00+$34; // Port C Data Direction Register
  76. PINC : byte absolute $00+$33; // Port C Input Pins
  77. // PORTD
  78. PORTD : byte absolute $00+$32; // Port D Data Register
  79. DDRD : byte absolute $00+$31; // Port D Data Direction Register
  80. PIND : byte absolute $00+$30; // Port D Input Pins
  81. // PORTE
  82. PORTE : byte absolute $00+$23; // Data Register, Port E
  83. DDRE : byte absolute $00+$22; // Data Direction Register, Port E
  84. PINE : byte absolute $00+$21; // Input Pins, Port E
  85. // PORTF
  86. PORTF : byte absolute $00+$62; // Data Register, Port F
  87. DDRF : byte absolute $00+$61; // Data Direction Register, Port F
  88. PINF : byte absolute $00+$20; // Input Pins, Port F
  89. // PORTG
  90. PORTG : byte absolute $00+$65; // Data Register, Port G
  91. DDRG : byte absolute $00+$64; // Data Direction Register, Port G
  92. PING : byte absolute $00+$63; // Input Pins, Port G
  93. // TIMER_COUNTER_0
  94. TCCR0 : byte absolute $00+$53; // Timer/Counter Control Register
  95. TCNT0 : byte absolute $00+$52; // Timer/Counter Register
  96. OCR0 : byte absolute $00+$51; // Output Compare Register
  97. ASSR : byte absolute $00+$50; // Asynchronus Status Register
  98. TIMSK : byte absolute $00+$57; // Timer/Counter Interrupt Mask Register
  99. TIFR : byte absolute $00+$56; // Timer/Counter Interrupt Flag register
  100. // TIMER_COUNTER_1
  101. ETIMSK : byte absolute $00+$7D; // Extended Timer/Counter Interrupt Mask Register
  102. ETIFR : byte absolute $00+$7C; // Extended Timer/Counter Interrupt Flag register
  103. TCCR1A : byte absolute $00+$4F; // Timer/Counter1 Control Register A
  104. TCCR1B : byte absolute $00+$4E; // Timer/Counter1 Control Register B
  105. TCCR1C : byte absolute $00+$7A; // Timer/Counter1 Control Register C
  106. TCNT1 : word absolute $00+$4C; // Timer/Counter1 Bytes
  107. TCNT1L : byte absolute $00+$4C; // Timer/Counter1 Bytes
  108. TCNT1H : byte absolute $00+$4C+1; // Timer/Counter1 Bytes
  109. OCR1A : word absolute $00+$4A; // Timer/Counter1 Output Compare Register Bytes
  110. OCR1AL : byte absolute $00+$4A; // Timer/Counter1 Output Compare Register Bytes
  111. OCR1AH : byte absolute $00+$4A+1; // Timer/Counter1 Output Compare Register Bytes
  112. OCR1B : word absolute $00+$48; // Timer/Counter1 Output Compare Register Bytes
  113. OCR1BL : byte absolute $00+$48; // Timer/Counter1 Output Compare Register Bytes
  114. OCR1BH : byte absolute $00+$48+1; // Timer/Counter1 Output Compare Register Bytes
  115. OCR1C : word absolute $00+$78; // Timer/Counter1 Output Compare Register Bytes
  116. OCR1CL : byte absolute $00+$78; // Timer/Counter1 Output Compare Register Bytes
  117. OCR1CH : byte absolute $00+$78+1; // Timer/Counter1 Output Compare Register Bytes
  118. ICR1 : word absolute $00+$46; // Timer/Counter1 Input Capture Register Bytes
  119. ICR1L : byte absolute $00+$46; // Timer/Counter1 Input Capture Register Bytes
  120. ICR1H : byte absolute $00+$46+1; // Timer/Counter1 Input Capture Register Bytes
  121. // TIMER_COUNTER_2
  122. TCCR2 : byte absolute $00+$45; // Timer/Counter Control Register
  123. TCNT2 : byte absolute $00+$44; // Timer/Counter Register
  124. OCR2 : byte absolute $00+$43; // Output Compare Register
  125. // TIMER_COUNTER_3
  126. TCCR3A : byte absolute $00+$8B; // Timer/Counter3 Control Register A
  127. TCCR3B : byte absolute $00+$8A; // Timer/Counter3 Control Register B
  128. TCCR3C : byte absolute $00+$8C; // Timer/Counter3 Control Register C
  129. TCNT3 : word absolute $00+$88; // Timer/Counter3 Bytes
  130. TCNT3L : byte absolute $00+$88; // Timer/Counter3 Bytes
  131. TCNT3H : byte absolute $00+$88+1; // Timer/Counter3 Bytes
  132. OCR3A : word absolute $00+$86; // Timer/Counter3 Output Compare Register A Bytes
  133. OCR3AL : byte absolute $00+$86; // Timer/Counter3 Output Compare Register A Bytes
  134. OCR3AH : byte absolute $00+$86+1; // Timer/Counter3 Output Compare Register A Bytes
  135. OCR3B : word absolute $00+$84; // Timer/Counter3 Output Compare Register B Bytes
  136. OCR3BL : byte absolute $00+$84; // Timer/Counter3 Output Compare Register B Bytes
  137. OCR3BH : byte absolute $00+$84+1; // Timer/Counter3 Output Compare Register B Bytes
  138. OCR3C : word absolute $00+$82; // Timer/Counter3 Output compare Register C Bytes
  139. OCR3CL : byte absolute $00+$82; // Timer/Counter3 Output compare Register C Bytes
  140. OCR3CH : byte absolute $00+$82+1; // Timer/Counter3 Output compare Register C Bytes
  141. ICR3 : word absolute $00+$80; // Timer/Counter3 Input Capture Register Bytes
  142. ICR3L : byte absolute $00+$80; // Timer/Counter3 Input Capture Register Bytes
  143. ICR3H : byte absolute $00+$80+1; // Timer/Counter3 Input Capture Register Bytes
  144. // WATCHDOG
  145. WDTCR : byte absolute $00+$41; // Watchdog Timer Control Register
  146. const
  147. // SFIOR
  148. ACME = 3; // Analog Comparator Multiplexer Enable
  149. // ACSR
  150. ACD = 7; // Analog Comparator Disable
  151. ACBG = 6; // Analog Comparator Bandgap Select
  152. ACO = 5; // Analog Compare Output
  153. ACI = 4; // Analog Comparator Interrupt Flag
  154. ACIE = 3; // Analog Comparator Interrupt Enable
  155. ACIC = 2; // Analog Comparator Input Capture Enable
  156. ACIS = 0; // Analog Comparator Interrupt Mode Select bits
  157. // ADMUX
  158. REFS = 6; // Reference Selection Bits
  159. ADLAR = 5; // Left Adjust Result
  160. MUX = 0; // Analog Channel and Gain Selection Bits
  161. // ADCSRA
  162. ADEN = 7; // ADC Enable
  163. ADSC = 6; // ADC Start Conversion
  164. ADATE = 5; // ADC Auto Trigger Enable
  165. ADIF = 4; // ADC Interrupt Flag
  166. ADIE = 3; // ADC Interrupt Enable
  167. ADPS = 0; // ADC Prescaler Select Bits
  168. // ADCSRB
  169. ADTS = 0; // ADC Auto Trigger Source bits
  170. // SPSR
  171. SPIF = 7; // SPI Interrupt Flag
  172. WCOL = 6; // Write Collision Flag
  173. SPI2X = 0; // Double SPI Speed Bit
  174. // SPCR
  175. SPIE = 7; // SPI Interrupt Enable
  176. SPE = 6; // SPI Enable
  177. DORD = 5; // Data Order
  178. MSTR = 4; // Master/Slave Select
  179. CPOL = 3; // Clock polarity
  180. CPHA = 2; // Clock Phase
  181. SPR = 0; // SPI Clock Rate Selects
  182. // TWCR
  183. TWINT = 7; // TWI Interrupt Flag
  184. TWEA = 6; // TWI Enable Acknowledge Bit
  185. TWSTA = 5; // TWI Start Condition Bit
  186. TWSTO = 4; // TWI Stop Condition Bit
  187. TWWC = 3; // TWI Write Collition Flag
  188. TWEN = 2; // TWI Enable Bit
  189. TWIE = 0; // TWI Interrupt Enable
  190. // TWSR
  191. TWS = 3; // TWI Status
  192. TWPS = 0; // TWI Prescaler
  193. // TWAR
  194. TWA = 1; // TWI (Slave) Address register Bits
  195. TWGCE = 0; // TWI General Call Recognition Enable Bit
  196. // UCSR0A
  197. RXC0 = 7; // USART Receive Complete
  198. TXC0 = 6; // USART Transmitt Complete
  199. UDRE0 = 5; // USART Data Register Empty
  200. FE0 = 4; // Framing Error
  201. DOR0 = 3; // Data overRun
  202. UPE0 = 2; // Parity Error
  203. U2X0 = 1; // Double the USART transmission speed
  204. MPCM0 = 0; // Multi-processor Communication Mode
  205. // UCSR0B
  206. RXCIE0 = 7; // RX Complete Interrupt Enable
  207. TXCIE0 = 6; // TX Complete Interrupt Enable
  208. UDRIE0 = 5; // USART Data register Empty Interrupt Enable
  209. RXEN0 = 4; // Receiver Enable
  210. TXEN0 = 3; // Transmitter Enable
  211. UCSZ02 = 2; // Character Size
  212. RXB80 = 1; // Receive Data Bit 8
  213. TXB80 = 0; // Transmit Data Bit 8
  214. // UCSR0C
  215. UMSEL0 = 6; // USART Mode Select
  216. UPM0 = 4; // Parity Mode Bits
  217. USBS0 = 3; // Stop Bit Select
  218. UCSZ0 = 1; // Character Size
  219. UCPOL0 = 0; // Clock Polarity
  220. // UCSR1A
  221. RXC1 = 7; // USART Receive Complete
  222. TXC1 = 6; // USART Transmitt Complete
  223. UDRE1 = 5; // USART Data Register Empty
  224. FE1 = 4; // Framing Error
  225. DOR1 = 3; // Data overRun
  226. UPE1 = 2; // Parity Error
  227. U2X1 = 1; // Double the USART transmission speed
  228. MPCM1 = 0; // Multi-processor Communication Mode
  229. // UCSR1B
  230. RXCIE1 = 7; // RX Complete Interrupt Enable
  231. TXCIE1 = 6; // TX Complete Interrupt Enable
  232. UDRIE1 = 5; // USART Data register Empty Interrupt Enable
  233. RXEN1 = 4; // Receiver Enable
  234. TXEN1 = 3; // Transmitter Enable
  235. UCSZ12 = 2; // Character Size
  236. RXB81 = 1; // Receive Data Bit 8
  237. TXB81 = 0; // Transmit Data Bit 8
  238. // UCSR1C
  239. UMSEL1 = 6; // USART Mode Select
  240. UPM1 = 4; // Parity Mode Bits
  241. USBS1 = 3; // Stop Bit Select
  242. UCSZ1 = 1; // Character Size
  243. UCPOL1 = 0; // Clock Polarity
  244. // SREG
  245. I = 7; // Global Interrupt Enable
  246. T = 6; // Bit Copy Storage
  247. H = 5; // Half Carry Flag
  248. S = 4; // Sign Bit
  249. V = 3; // Two's Complement Overflow Flag
  250. N = 2; // Negative Flag
  251. Z = 1; // Zero Flag
  252. C = 0; // Carry Flag
  253. // MCUCR
  254. SRE = 7; // External SRAM Enable
  255. SRW10 = 6; // External SRAM Wait State Select
  256. SE = 5; // Sleep Enable
  257. SM = 3; // Sleep Mode Select
  258. SM2 = 2; // Sleep Mode Select
  259. IVSEL = 1; // Interrupt Vector Select
  260. IVCE = 0; // Interrupt Vector Change Enable
  261. // MCUCSR
  262. JTD = 7; // JTAG Interface Disable
  263. JTRF = 4; // JTAG Reset Flag
  264. WDRF = 3; // Watchdog Reset Flag
  265. BORF = 2; // Brown-out Reset Flag
  266. EXTRF = 1; // External Reset Flag
  267. PORF = 0; // Power-on reset flag
  268. // XMCRA
  269. SRL = 4; // Wait state page limit
  270. SRW0 = 2; // Wait state select bit lower page
  271. SRW11 = 1; // Wait state select bit upper page
  272. // XMCRB
  273. XMBK = 7; // External Memory Bus Keeper Enable
  274. XMM = 0; // External Memory High Mask
  275. // XDIV
  276. XDIVEN = 7; // XTAL Divide Enable
  277. // SPMCSR
  278. SPMIE = 7; // SPM Interrupt Enable
  279. RWWSB = 6; // Read While Write Section Busy
  280. RWWSRE = 4; // Read While Write section read enable
  281. BLBSET = 3; // Boot Lock Bit Set
  282. PGWRT = 2; // Page Write
  283. PGERS = 1; // Page Erase
  284. SPMEN = 0; // Store Program Memory Enable
  285. // OCDR
  286. // MCUCSR
  287. // SFIOR
  288. TSM = 7; // Timer/Counter Synchronization Mode
  289. PUD = 2; // Pull Up Disable
  290. PSR0 = 1; // Prescaler Reset Timer/Counter0
  291. PSR321 = 0; // Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1
  292. // EICRA
  293. ISC3 = 6; // External Interrupt Sense Control Bit
  294. ISC2 = 4; // External Interrupt Sense Control Bit
  295. ISC1 = 2; // External Interrupt Sense Control Bit
  296. ISC0 = 0; // External Interrupt Sense Control Bit
  297. // EICRB
  298. ISC7 = 6; // External Interrupt 7-4 Sense Control Bit
  299. ISC6 = 4; // External Interrupt 7-4 Sense Control Bit
  300. ISC5 = 2; // External Interrupt 7-4 Sense Control Bit
  301. ISC4 = 0; // External Interrupt 7-4 Sense Control Bit
  302. // EIMSK
  303. INT = 0; // External Interrupt Request 7 Enable
  304. // EIFR
  305. INTF = 0; // External Interrupt Flags
  306. // EECR
  307. EERIE = 3; // EEPROM Ready Interrupt Enable
  308. EEMWE = 2; // EEPROM Master Write Enable
  309. EEWE = 1; // EEPROM Write Enable
  310. EERE = 0; // EEPROM Read Enable
  311. // TCCR0
  312. FOC0 = 7; // Force Output Compare
  313. WGM00 = 6; // Waveform Generation Mode 0
  314. COM0 = 4; // Compare Match Output Modes
  315. WGM01 = 3; // Waveform Generation Mode 1
  316. CS0 = 0; // Clock Selects
  317. // ASSR
  318. AS0 = 3; // Asynchronus Timer/Counter 0
  319. TCN0UB = 2; // Timer/Counter0 Update Busy
  320. OCR0UB = 1; // Output Compare register 0 Busy
  321. TCR0UB = 0; // Timer/Counter Control Register 0 Update Busy
  322. // TIMSK
  323. OCIE0 = 1; // Timer/Counter0 Output Compare Match Interrupt register
  324. TOIE0 = 0; // Timer/Counter0 Overflow Interrupt Enable
  325. // TIFR
  326. OCF0 = 1; // Output Compare Flag 0
  327. TOV0 = 0; // Timer/Counter0 Overflow Flag
  328. // SFIOR
  329. // TIMSK
  330. TICIE1 = 5; // Timer/Counter1 Input Capture Interrupt Enable
  331. OCIE1A = 4; // Timer/Counter1 Output CompareA Match Interrupt Enable
  332. OCIE1B = 3; // Timer/Counter1 Output CompareB Match Interrupt Enable
  333. TOIE1 = 2; // Timer/Counter1 Overflow Interrupt Enable
  334. // ETIMSK
  335. OCIE1C = 0; // Timer/Counter 1, Output Compare Match C Interrupt Enable
  336. // TIFR
  337. ICF1 = 5; // Input Capture Flag 1
  338. OCF1A = 4; // Output Compare Flag 1A
  339. OCF1B = 3; // Output Compare Flag 1B
  340. TOV1 = 2; // Timer/Counter1 Overflow Flag
  341. // ETIFR
  342. OCF1C = 0; // Timer/Counter 1, Output Compare C Match Flag
  343. // SFIOR
  344. // TCCR1A
  345. COM1A = 6; // Compare Output Mode 1A, bits
  346. COM1B = 4; // Compare Output Mode 1B, bits
  347. COM1C = 2; // Compare Output Mode 1C, bits
  348. WGM1 = 0; // Waveform Generation Mode Bits
  349. // TCCR1B
  350. ICNC1 = 7; // Input Capture 1 Noise Canceler
  351. ICES1 = 6; // Input Capture 1 Edge Select
  352. CS1 = 0; // Clock Select1 bits
  353. // TCCR1C
  354. FOC1A = 7; // Force Output Compare for channel A
  355. FOC1B = 6; // Force Output Compare for channel B
  356. FOC1C = 5; // Force Output Compare for channel C
  357. // TCCR2
  358. FOC2 = 7; // Force Output Compare
  359. WGM20 = 6; // Wafeform Generation Mode
  360. COM2 = 4; // Compare Match Output Mode
  361. WGM21 = 3; // Waveform Generation Mode
  362. CS2 = 0; // Clock Select
  363. // TIFR
  364. OCF2 = 7; // Output Compare Flag 2
  365. TOV2 = 6; // Timer/Counter2 Overflow Flag
  366. // TIMSK
  367. OCIE2 = 7; //
  368. TOIE2 = 6; //
  369. // ETIMSK
  370. TICIE3 = 5; // Timer/Counter3 Input Capture Interrupt Enable
  371. OCIE3A = 4; // Timer/Counter3 Output CompareA Match Interrupt Enable
  372. OCIE3B = 3; // Timer/Counter3 Output CompareB Match Interrupt Enable
  373. TOIE3 = 2; // Timer/Counter3 Overflow Interrupt Enable
  374. OCIE3C = 1; // Timer/Counter3, Output Compare Match Interrupt Enable
  375. // ETIFR
  376. ICF3 = 5; // Input Capture Flag 1
  377. OCF3A = 4; // Output Compare Flag 1A
  378. OCF3B = 3; // Output Compare Flag 1B
  379. TOV3 = 2; // Timer/Counter3 Overflow Flag
  380. OCF3C = 1; // Timer/Counter3 Output Compare C Match Flag
  381. // SFIOR
  382. // TCCR3A
  383. COM3A = 6; // Compare Output Mode 3A, bits
  384. COM3B = 4; // Compare Output Mode 3B, bits
  385. COM3C = 2; // Compare Output Mode 3C, bits
  386. WGM3 = 0; // Waveform Generation Mode Bits
  387. // TCCR3B
  388. ICNC3 = 7; // Input Capture 3 Noise Canceler
  389. ICES3 = 6; // Input Capture 3 Edge Select
  390. CS3 = 0; // Clock Select3 bits
  391. // TCCR3C
  392. FOC3A = 7; // Force Output Compare for channel A
  393. FOC3B = 6; // Force Output Compare for channel B
  394. FOC3C = 5; // Force Output Compare for channel C
  395. // WDTCR
  396. WDCE = 4; // Watchdog Change Enable
  397. WDE = 3; // Watch Dog Enable
  398. WDP = 0; // Watch Dog Timer Prescaler bits
  399. implementation
  400. {$i avrcommon.inc}
  401. procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
  402. procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1
  403. procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 3 External Interrupt Request 2
  404. procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 4 External Interrupt Request 3
  405. procedure INT4_ISR; external name 'INT4_ISR'; // Interrupt 5 External Interrupt Request 4
  406. procedure INT5_ISR; external name 'INT5_ISR'; // Interrupt 6 External Interrupt Request 5
  407. procedure INT6_ISR; external name 'INT6_ISR'; // Interrupt 7 External Interrupt Request 6
  408. procedure INT7_ISR; external name 'INT7_ISR'; // Interrupt 8 External Interrupt Request 7
  409. procedure TIMER2_COMP_ISR; external name 'TIMER2_COMP_ISR'; // Interrupt 9 Timer/Counter2 Compare Match
  410. procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 10 Timer/Counter2 Overflow
  411. procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 11 Timer/Counter1 Capture Event
  412. procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 12 Timer/Counter1 Compare Match A
  413. procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 13 Timer/Counter Compare Match B
  414. procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 14 Timer/Counter1 Overflow
  415. procedure TIMER0_COMP_ISR; external name 'TIMER0_COMP_ISR'; // Interrupt 15 Timer/Counter0 Compare Match
  416. procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 16 Timer/Counter0 Overflow
  417. procedure SPI__STC_ISR; external name 'SPI__STC_ISR'; // Interrupt 17 SPI Serial Transfer Complete
  418. procedure USART0__RX_ISR; external name 'USART0__RX_ISR'; // Interrupt 18 USART0, Rx Complete
  419. procedure USART0__UDRE_ISR; external name 'USART0__UDRE_ISR'; // Interrupt 19 USART0 Data Register Empty
  420. procedure USART0__TX_ISR; external name 'USART0__TX_ISR'; // Interrupt 20 USART0, Tx Complete
  421. procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 21 ADC Conversion Complete
  422. procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 22 EEPROM Ready
  423. procedure ANALOG_COMP_ISR; external name 'ANALOG_COMP_ISR'; // Interrupt 23 Analog Comparator
  424. procedure TIMER1_COMPC_ISR; external name 'TIMER1_COMPC_ISR'; // Interrupt 24 Timer/Counter1 Compare Match C
  425. procedure TIMER3_CAPT_ISR; external name 'TIMER3_CAPT_ISR'; // Interrupt 25 Timer/Counter3 Capture Event
  426. procedure TIMER3_COMPA_ISR; external name 'TIMER3_COMPA_ISR'; // Interrupt 26 Timer/Counter3 Compare Match A
  427. procedure TIMER3_COMPB_ISR; external name 'TIMER3_COMPB_ISR'; // Interrupt 27 Timer/Counter3 Compare Match B
  428. procedure TIMER3_COMPC_ISR; external name 'TIMER3_COMPC_ISR'; // Interrupt 28 Timer/Counter3 Compare Match C
  429. procedure TIMER3_OVF_ISR; external name 'TIMER3_OVF_ISR'; // Interrupt 29 Timer/Counter3 Overflow
  430. procedure USART1__RX_ISR; external name 'USART1__RX_ISR'; // Interrupt 30 USART1, Rx Complete
  431. procedure USART1__UDRE_ISR; external name 'USART1__UDRE_ISR'; // Interrupt 31 USART1, Data Register Empty
  432. procedure USART1__TX_ISR; external name 'USART1__TX_ISR'; // Interrupt 32 USART1, Tx Complete
  433. procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 33 2-wire Serial Interface
  434. procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 34 Store Program Memory Read
  435. procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';
  436. asm
  437. jmp __dtors_end
  438. jmp INT0_ISR
  439. jmp INT1_ISR
  440. jmp INT2_ISR
  441. jmp INT3_ISR
  442. jmp INT4_ISR
  443. jmp INT5_ISR
  444. jmp INT6_ISR
  445. jmp INT7_ISR
  446. jmp TIMER2_COMP_ISR
  447. jmp TIMER2_OVF_ISR
  448. jmp TIMER1_CAPT_ISR
  449. jmp TIMER1_COMPA_ISR
  450. jmp TIMER1_COMPB_ISR
  451. jmp TIMER1_OVF_ISR
  452. jmp TIMER0_COMP_ISR
  453. jmp TIMER0_OVF_ISR
  454. jmp SPI__STC_ISR
  455. jmp USART0__RX_ISR
  456. jmp USART0__UDRE_ISR
  457. jmp USART0__TX_ISR
  458. jmp ADC_ISR
  459. jmp EE_READY_ISR
  460. jmp ANALOG_COMP_ISR
  461. jmp TIMER1_COMPC_ISR
  462. jmp TIMER3_CAPT_ISR
  463. jmp TIMER3_COMPA_ISR
  464. jmp TIMER3_COMPB_ISR
  465. jmp TIMER3_COMPC_ISR
  466. jmp TIMER3_OVF_ISR
  467. jmp USART1__RX_ISR
  468. jmp USART1__UDRE_ISR
  469. jmp USART1__TX_ISR
  470. jmp TWI_ISR
  471. jmp SPM_READY_ISR
  472. .weak INT0_ISR
  473. .weak INT1_ISR
  474. .weak INT2_ISR
  475. .weak INT3_ISR
  476. .weak INT4_ISR
  477. .weak INT5_ISR
  478. .weak INT6_ISR
  479. .weak INT7_ISR
  480. .weak TIMER2_COMP_ISR
  481. .weak TIMER2_OVF_ISR
  482. .weak TIMER1_CAPT_ISR
  483. .weak TIMER1_COMPA_ISR
  484. .weak TIMER1_COMPB_ISR
  485. .weak TIMER1_OVF_ISR
  486. .weak TIMER0_COMP_ISR
  487. .weak TIMER0_OVF_ISR
  488. .weak SPI__STC_ISR
  489. .weak USART0__RX_ISR
  490. .weak USART0__UDRE_ISR
  491. .weak USART0__TX_ISR
  492. .weak ADC_ISR
  493. .weak EE_READY_ISR
  494. .weak ANALOG_COMP_ISR
  495. .weak TIMER1_COMPC_ISR
  496. .weak TIMER3_CAPT_ISR
  497. .weak TIMER3_COMPA_ISR
  498. .weak TIMER3_COMPB_ISR
  499. .weak TIMER3_COMPC_ISR
  500. .weak TIMER3_OVF_ISR
  501. .weak USART1__RX_ISR
  502. .weak USART1__UDRE_ISR
  503. .weak USART1__TX_ISR
  504. .weak TWI_ISR
  505. .weak SPM_READY_ISR
  506. .set INT0_ISR, Default_IRQ_handler
  507. .set INT1_ISR, Default_IRQ_handler
  508. .set INT2_ISR, Default_IRQ_handler
  509. .set INT3_ISR, Default_IRQ_handler
  510. .set INT4_ISR, Default_IRQ_handler
  511. .set INT5_ISR, Default_IRQ_handler
  512. .set INT6_ISR, Default_IRQ_handler
  513. .set INT7_ISR, Default_IRQ_handler
  514. .set TIMER2_COMP_ISR, Default_IRQ_handler
  515. .set TIMER2_OVF_ISR, Default_IRQ_handler
  516. .set TIMER1_CAPT_ISR, Default_IRQ_handler
  517. .set TIMER1_COMPA_ISR, Default_IRQ_handler
  518. .set TIMER1_COMPB_ISR, Default_IRQ_handler
  519. .set TIMER1_OVF_ISR, Default_IRQ_handler
  520. .set TIMER0_COMP_ISR, Default_IRQ_handler
  521. .set TIMER0_OVF_ISR, Default_IRQ_handler
  522. .set SPI__STC_ISR, Default_IRQ_handler
  523. .set USART0__RX_ISR, Default_IRQ_handler
  524. .set USART0__UDRE_ISR, Default_IRQ_handler
  525. .set USART0__TX_ISR, Default_IRQ_handler
  526. .set ADC_ISR, Default_IRQ_handler
  527. .set EE_READY_ISR, Default_IRQ_handler
  528. .set ANALOG_COMP_ISR, Default_IRQ_handler
  529. .set TIMER1_COMPC_ISR, Default_IRQ_handler
  530. .set TIMER3_CAPT_ISR, Default_IRQ_handler
  531. .set TIMER3_COMPA_ISR, Default_IRQ_handler
  532. .set TIMER3_COMPB_ISR, Default_IRQ_handler
  533. .set TIMER3_COMPC_ISR, Default_IRQ_handler
  534. .set TIMER3_OVF_ISR, Default_IRQ_handler
  535. .set USART1__RX_ISR, Default_IRQ_handler
  536. .set USART1__UDRE_ISR, Default_IRQ_handler
  537. .set USART1__TX_ISR, Default_IRQ_handler
  538. .set TWI_ISR, Default_IRQ_handler
  539. .set SPM_READY_ISR, Default_IRQ_handler
  540. end;
  541. end.