m68k.inc 20 KB

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  1. {
  2. This file is part of the Free Pascal run time library.
  3. Copyright (c) 1999-2000 by Carl-Eric Codere,
  4. member of the Free Pascal development team.
  5. See the file COPYING.FPC, included in this distribution,
  6. for details about the copyright.
  7. This program is distributed in the hope that it will be useful,
  8. but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  10. **********************************************************************}
  11. {****************************************************************************
  12. m68k.inc : Processor dependent implementation of system unit
  13. For Motorola 680x0 Processor.
  14. *****************************************************************************}
  15. {****************************************************************************}
  16. { Credit where credit is due: }
  17. { -Some of the copy routines taken from the Atari dlib source code: }
  18. { Dale Schumacher (alias: Dalnefre') [email protected] }
  19. { 399 Beacon Ave. St. Paul, MN 55104,USA }
  20. { -Some of the routines taken from the freeware ATARI Sozobon C compiler }
  21. { 1988 by Sozobon, Limited. Author: Johann Ruegg (freeware) }
  22. { Thanks to all these people wherever they maybe today! }
  23. {****************************************************************************}
  24. {$IF DEFINED(FPU68881) OR DEFINED(FPUCOLDFIRE)}
  25. function GetFPCR: DWord; assembler; nostackframe;
  26. asm
  27. fmove.l fpcr,d0
  28. end;
  29. function GetFPSR: DWord; assembler; nostackframe;
  30. asm
  31. fmove.l fpsr, d0
  32. end;
  33. procedure SetFPCR(x: DWord);
  34. begin
  35. Default68kFPCR:=x;
  36. asm
  37. fmove.l x, fpcr
  38. end;
  39. end;
  40. procedure SetFPSR(x: DWord); assembler; nostackframe;
  41. asm
  42. fmove.l x, fpsr
  43. end;
  44. function GetNativeFPUControlWord: TNativeFPUControlWord;
  45. begin
  46. result:=GetFPCR;
  47. end;
  48. procedure SetNativeFPUControlWord(const cw: TNativeFPUControlWord);
  49. begin
  50. SetFPCR(cw);
  51. end;
  52. {$DEFINE FPC_SYSTEM_HAS_SYSRESETFPU}
  53. procedure SysResetFPU;
  54. begin
  55. softfloat_exception_flags:=[];
  56. SetFPCR(Default68KFPCR);
  57. SetFPSR(0);
  58. end;
  59. {$DEFINE FPC_SYSTEM_HAS_SYSINITFPU}
  60. procedure SysInitFPU;
  61. begin
  62. softfloat_exception_mask:=[float_flag_underflow,float_flag_inexact,float_flag_denormal];
  63. softfloat_exception_flags:=[];
  64. SetFPSR(0);
  65. end;
  66. {$endif}
  67. {$ifndef INTERNAL_BACKTRACE}
  68. {$define FPC_SYSTEM_HAS_GET_FRAME}
  69. function get_frame : pointer; assembler;nostackframe;
  70. asm
  71. move.l fp,d0
  72. end;
  73. {$endif not INTERNAL_BACKTRACE}
  74. {$define FPC_SYSTEM_HAS_GET_CALLER_ADDR}
  75. function get_caller_addr(framebp : pointer;addr:pointer=nil) : pointer; assembler;
  76. asm
  77. move.l framebp,d0
  78. tst.l d0
  79. beq @Lnul_address
  80. move.l d0,a0
  81. move.l 4(a0),d0
  82. @Lnul_address:
  83. end;
  84. {$define FPC_SYSTEM_HAS_GET_CALLER_FRAME}
  85. function get_caller_frame(framebp : pointer;addr:pointer=nil) : pointer; assembler;
  86. asm
  87. move.l framebp,d0
  88. tst.l d0
  89. beq @Lnul_frame
  90. move.l d0,a0
  91. move.l (a0),d0
  92. @Lnul_frame:
  93. end;
  94. {$define FPC_SYSTEM_HAS_SPTR}
  95. function Sptr : pointer; assembler;nostackframe;
  96. asm
  97. move.l sp,d0
  98. end;
  99. {$define FPC_SYSTEM_HAS_GET_PC_ADDR}
  100. function get_pc_addr : pointer;assembler;nostackframe;
  101. asm
  102. move.l (sp),d0
  103. end;
  104. {$ifndef FPC_SYSTEM_HAS_FILLCHAR}
  105. {$define FPC_SYSTEM_HAS_FILLCHAR}
  106. procedure FillChar(var x; count : longint; value : byte); assembler; register; nostackframe;
  107. asm
  108. {$ifdef VER3_0}
  109. move.l x,a0
  110. move.l count,d0
  111. clr.l d1
  112. move.b value,d1
  113. {$endif VER3_0}
  114. { a0 is x, d0 is count, d1 is value }
  115. tst.l d0 { anything to fill at all? }
  116. ble @Lquit
  117. cmp.l #32,d0 { limits were tested against real hardware on various CPU }
  118. blt @LfillByte
  119. cmp.l #128,d0 { limits were tested against real hardware on various CPU }
  120. blt @LfillWord
  121. bra @LfillDWord
  122. {$ifndef CPUM68K_HAS_DBRA}
  123. @LfillByte:
  124. {$endif}
  125. @LfillByteLoop:
  126. move.b d1,(a0)+
  127. {$ifdef CPUM68K_HAS_DBRA}
  128. @LfillByte:
  129. dbra d0,@LfillByteLoop
  130. {$else}
  131. subq.l #1,d0
  132. bne @LfillByteLoop
  133. {$endif}
  134. rts
  135. @LfillWord:
  136. move.l d2,-(sp)
  137. move.l a0,d2
  138. btst #0,d2
  139. beq @Leven
  140. subq.l #1,d0
  141. move.b d1,(a0)+
  142. @Leven:
  143. move.b d1,d2 // copy value to upper byte
  144. {$ifdef CPUCOLDFIRE}
  145. lsl.l #8,d1
  146. {$else}
  147. lsl.w #8,d1
  148. {$endif}
  149. move.b d2,d1
  150. move.l d0,d2 // adjust d0 for leftover copy
  151. bclr #0,d2
  152. sub.l d2,d0
  153. lsr.l #1,d2
  154. {$ifdef CPUM68K_HAS_DBRA}
  155. subq.l #1,d2
  156. {$endif}
  157. @LfillWordLoop:
  158. move.w d1,(a0)+
  159. {$ifdef CPUM68K_HAS_DBRA}
  160. dbra d2,@LFillWordLoop
  161. {$else}
  162. subq.l #1,d2
  163. bne @LfillWordLoop
  164. {$endif}
  165. move.l (sp)+,d2
  166. tst.l d0
  167. bne @LfillByte
  168. rts
  169. @LfillDWord:
  170. move.l d2,-(sp)
  171. move.b d1,d2 // copy value to upper bytes
  172. {$ifdef CPUCOLDFIRE}
  173. lsl.l #8,d1
  174. {$else}
  175. lsl.w #8,d1
  176. {$endif}
  177. move.b d2,d1
  178. move.w d1,d2
  179. swap d1
  180. move.w d2,d1
  181. move.l a0,d2 // do initial byte and word fill, if the address is unaligned
  182. btst #0,d2
  183. beq @Ldeven
  184. subq.l #1,d0
  185. move.b d1,(a0)+
  186. @Ldeven:
  187. move.l a0,d2
  188. btst #1,d2
  189. beq @Ldquad
  190. subq.l #2,d0
  191. move.w d1,(a0)+
  192. @Ldquad:
  193. move.l d0,d2 // adjust d0 for leftover copy
  194. {$ifdef CPUCOLDFIRE}
  195. and.l #$fffffffc,d2
  196. {$else}
  197. and.b #$fc,d2
  198. {$endif}
  199. sub.l d2,d0
  200. lsr.l #2,d2
  201. bra @LfillLongLoopStart
  202. @LfillLongLoop:
  203. move.l d1,(a0)+
  204. move.l d1,(a0)+
  205. move.l d1,(a0)+
  206. move.l d1,(a0)+
  207. subq.l #4,d2
  208. @LfillLongLoopStart:
  209. cmp.l #4,d2
  210. bgt @LfillLongLoop
  211. {$ifdef CPUM68K_HAS_DBRA}
  212. subq.l #1,d2
  213. {$endif}
  214. @LfillDWordLoop:
  215. move.l d1,(a0)+
  216. {$ifdef CPUM68K_HAS_DBRA}
  217. dbra d2,@LFillDWordLoop
  218. {$else}
  219. subq.l #1,d2
  220. bne @LfillDWordLoop
  221. {$endif}
  222. move.l (sp)+,d2
  223. tst.l d0
  224. bne @LfillByte
  225. @Lquit:
  226. end;
  227. {$endif ndef FPC_SYSTEM_HAS_FILLCHAR}
  228. {$ifdef dummy}
  229. { procedure strcopy(dstr,sstr : pointer;len : longint);[public,alias: 'STRCOPY'];}
  230. procedure strcopy; assembler;[public,alias: 'FPC_STRCOPY'];
  231. {---------------------------------------------------}
  232. { Low-level routine to copy a string to another }
  233. { string with maximum length. Never call directly! }
  234. { On Entry: }
  235. { a1.l = string to copy to }
  236. { a0.l = source string }
  237. { d0.l = maximum length of copy }
  238. { registers destroyed: a0,a1,d0,d1 }
  239. {---------------------------------------------------}
  240. asm
  241. { move.l sstr,a0
  242. move.l dstr,a1
  243. move.l len,d1 }
  244. move.l d0,d1
  245. move.b (a0)+,d0 { Get source length }
  246. and.w #$ff,d0
  247. cmp.w d1,d0 { This is a signed comparison! }
  248. ble @LM4
  249. move.b d1,d0 { If longer than maximum size of target, cut
  250. source length }
  251. @LM4:
  252. andi.l #$ff,d0 { zero extend d0-byte }
  253. move.l d0,d1 { save length to copy }
  254. move.b d0,(a1)+ { save new length }
  255. { Check if copying length is zero - if so then }
  256. { exit without copying anything. }
  257. tst.b d1
  258. beq @Lend
  259. bra @LMSTRCOPY55
  260. @LMSTRCOPY56: { 68010 Fast loop mode }
  261. move.b (a0)+,(a1)+
  262. @LMSTRCOPY55:
  263. {$ifndef CPUM68K_HAS_DBRA}
  264. sub.l #1,d1
  265. bpl @LMSTRCOPY56
  266. {$else CPUM68K_HAS_DBRA}
  267. dbra d1,@LMSTRCOPY56
  268. {$endif CPUM68K_HAS_DBRA}
  269. @Lend:
  270. end;
  271. { Concatenate Strings }
  272. { PARAMETERS ARE REVERSED COMPARED TO NORMAL! }
  273. { therefore online assembler may not parse the params as normal }
  274. procedure strconcat(s1,s2 : pointer);[public,alias: 'STRCONCAT'];
  275. begin
  276. asm
  277. move.b #255,d0
  278. move.l s1,a0 { a0 = destination }
  279. move.l s2,a1 { a1 = source }
  280. sub.b (a0),d0 { copyl:= 255 -length(s1) }
  281. move.b (a1),d6
  282. and.w #$ff,d0 { Sign flags are checked! }
  283. and.w #$ff,d6
  284. cmp.w d6,d0 { if copyl > length(s2) then }
  285. ble @Lcontinue
  286. move.b (a1),d0 { copyl:=length(s2) }
  287. @Lcontinue:
  288. move.b (a0),d6
  289. and.l #$ff,d6
  290. lea 1(a0,d6),a0 { s1[length(s1)+1] }
  291. add.l #1,a1 { s2[1] }
  292. move.b d0,d6
  293. { Check if copying length is zero - if so then }
  294. { exit without copying anything. }
  295. tst.b d6
  296. beq @Lend
  297. bra @ALoop
  298. @Loop:
  299. move.b (a1)+,(a0)+ { s1[i] := s2[i]; }
  300. @ALoop:
  301. {$ifndef CPUM68K_HAS_DBRA}
  302. sub.l #1,d6
  303. bpl @Loop
  304. {$else CPUM68K_HAS_DBRA}
  305. dbra d6,@Loop
  306. {$endif CPUM68K_HAS_DBRA}
  307. move.l s1,a0
  308. add.b d0,(a0) { change to new string length }
  309. @Lend:
  310. end ['d0','d1','a0','a1','d6'];
  311. end;
  312. { Compares strings }
  313. { DO NOT CALL directly. }
  314. { a0 = pointer to first string to compare }
  315. { a1 = pointer to second string to compare }
  316. { ALL FLAGS are set appropriately. }
  317. { ZF = strings are equal }
  318. { REGISTERS DESTROYED: a0, a1, d0, d1, d6 }
  319. procedure strcmp; assembler;[public,alias:'FPC_STRCMP'];
  320. asm
  321. move.b (a0)+,d0 { Get length of first string }
  322. move.b (a1)+,d6 { Get length of 2nd string }
  323. move.b d6,d1 { Save length of string for final compare }
  324. cmp.b d0,d6 { Get shortest string length }
  325. ble @LSTRCONCAT1
  326. move.b d0,d6 { Set length to shortest string }
  327. @LSTRCONCAT1:
  328. tst.b d6 { Both strings have a length of zero, exit }
  329. beq @LSTRCONCAT2
  330. andi.l #$ff,d6
  331. subq.l #1,d6 { subtract first attempt }
  332. { if value is -1 then don't loop and just compare lengths of }
  333. { both strings before exiting. }
  334. bmi @LSTRCONCAT2
  335. or.l d0,d0 { Make sure to set Zerfo flag to 0 }
  336. @LSTRCONCAT5:
  337. { Workaroung for GAS v.134 bug }
  338. { old: cmp.b (a1)+,(a0)+ }
  339. cmpm.b (a1)+,(a0)+
  340. @LSTRCONCAT4:
  341. dbne d6,@LSTRCONCAT5 { Repeat until not equal }
  342. bne @LSTRCONCAT3
  343. @LSTRCONCAT2:
  344. { If length of both string are equal }
  345. { Then set zero flag }
  346. cmp.b d1,d0 { Compare length - set flag if equal length strings }
  347. @LSTRCONCAT3:
  348. end;
  349. {$endif dummy}
  350. {$ifndef FPC_SYSTEM_HAS_MOVE}
  351. {$define FPC_SYSTEM_HAS_MOVE}
  352. procedure move(const source;var dest;count : longint); assembler;
  353. { base pointer+8 = source }
  354. { base pointer+12 = destination }
  355. { base pointer+16 = number of bytes to move}
  356. asm
  357. move.l count, d0 { number of bytes }
  358. ble @LMOVE5 { anything to copy at all? }
  359. move.l dest, a1 { destination }
  360. move.l source, a0 { source }
  361. {$ifdef CPUM68K_HAS_DBRA}
  362. cmpi.l #65535, d0 { check, if this is a word move }
  363. ble @LMEMSET00 { use fast dbra mode 68010+ }
  364. {$endif CPUM68K_HAS_DBRA}
  365. cmp.l a0,a1 { check copy direction }
  366. bls @LMOVE3
  367. add.l d0,a0 { move pointers to end }
  368. add.l d0,a1
  369. @LMOVE1:
  370. move.b -(a0),-(a1) { (s < d) copy loop }
  371. subq.l #1,d0
  372. bne @LMOVE1
  373. bra @LMOVE5
  374. @LMOVE3:
  375. move.b (a0)+,(a1)+ { (s >= d) copy loop }
  376. subq.l #1,d0
  377. bne @LMOVE3
  378. bra @LMOVE5
  379. {$ifdef CPUM68K_HAS_DBRA}
  380. @LMEMSET00: { use fast loop mode 68010+ }
  381. cmp.l a0,a1 { check copy direction }
  382. bls @LMOVE04
  383. add.l d0,a0 { move pointers to end }
  384. add.l d0,a1
  385. bra @LMOVE02
  386. @LMOVE01:
  387. move.b -(a0),-(a1) { (s < d) copy loop }
  388. @LMOVE02:
  389. dbra d0,@LMOVE01
  390. bra @LMOVE5
  391. @LMOVE03:
  392. move.b (a0)+,(a1)+ { (s >= d) copy loop }
  393. @LMOVE04:
  394. dbra d0,@LMOVE03
  395. {$endif CPUM68K_HAS_DBRA}
  396. { end fast loop mode }
  397. @LMOVE5:
  398. end;
  399. {$endif ndef FPC_SYSTEM_HAS_MOVE}
  400. {$ifdef CPUM68K_HAS_UNALIGNED}
  401. {$define FPC_SYSTEM_HAS_FILLWORD}
  402. procedure FillWord(var x; count : longint; value : word); assembler;
  403. asm
  404. move.l x, a0 { destination }
  405. move.w value, d1 { fill data }
  406. move.l count, d0 { number of bytes to fill }
  407. ble @LMEMSET3 { anything to fill at all? }
  408. bra @LMEMSET21
  409. @LMEMSET11:
  410. move.w d1,(a0)+
  411. @LMEMSET21:
  412. subq.l #1,d0
  413. bpl @LMEMSET11
  414. @LMEMSET3:
  415. end;
  416. {$endif}
  417. {$IFNDEF FPC_SYSTEM_HAS_INTERLOCKEDFUNCS}
  418. {$IFNDEF CPUM68K_HAS_CAS}
  419. var
  420. spinLock: byte;
  421. procedure getSpinLock; assembler; nostackframe;
  422. asm
  423. {$IFDEF CPUM68K_HAS_TAS}
  424. lea.l spinlock,a0
  425. @loop:
  426. tas (a0)
  427. bne @loop
  428. {$ENDIF}
  429. end;
  430. procedure releaseSpinLock; assembler; nostackframe;
  431. asm
  432. moveq.l #0,d0
  433. move.b d0,spinlock
  434. end;
  435. {$ENDIF}
  436. function InterLockedDecrement (var Target: longint) : longint;
  437. {$IFDEF CPUM68K_HAS_CAS}
  438. register; assembler;
  439. asm
  440. move.l (a0), d0
  441. @loop:
  442. move.l d0, d1
  443. subq.l #1, d1
  444. cas.l d0, d1, (a0)
  445. bne @loop
  446. move.l d1, d0
  447. end;
  448. {$ELSE}
  449. begin
  450. getSpinLock;
  451. Dec(Target);
  452. Result := Target;
  453. releaseSpinLock;
  454. end;
  455. {$ENDIF}
  456. function InterLockedIncrement (var Target: longint) : longint;
  457. {$IFDEF CPUM68K_HAS_CAS}
  458. register; assembler;
  459. asm
  460. move.l (a0), d0
  461. @loop:
  462. move.l d0, d1
  463. addq.l #1, d1
  464. cas.l d0, d1, (a0)
  465. bne @loop
  466. move.l d1, d0
  467. end;
  468. {$ELSE}
  469. begin
  470. getSpinLock;
  471. Inc(Target);
  472. Result := Target;
  473. releaseSpinLock;
  474. end;
  475. {$ENDIF}
  476. function InterLockedExchange (var Target: longint;Source : longint) : longint;
  477. {$IFDEF CPUM68K_HAS_CAS}
  478. register; assembler;
  479. asm
  480. move.l Source, d1
  481. move.l (a0), d0
  482. @loop:
  483. cas.l d0, d1, (a0)
  484. bne @loop
  485. end;
  486. {$ELSE}
  487. begin
  488. getSpinLock;
  489. Result := Target;
  490. Target := Source;
  491. releaseSpinLock;
  492. end;
  493. {$ENDIF}
  494. function InterLockedExchangeAdd (var Target: longint;Source : longint) : longint;
  495. {$IFDEF CPUM68K_HAS_CAS}
  496. register; assembler;
  497. asm
  498. move.l Source, a1
  499. move.l (a0), d0
  500. @loop:
  501. move.l a1, d1
  502. add.l d0, d1
  503. cas.l d0, d1, (a0)
  504. bne @loop
  505. end;
  506. {$ELSE}
  507. begin
  508. getSpinLock;
  509. Result := Target;
  510. Target := Target + Source;
  511. releaseSpinLock;
  512. end;
  513. {$ENDIF}
  514. function InterlockedCompareExchange(var Target: longint; NewValue: longint; Comperand: longint): longint;
  515. {$IFDEF CPUM68K_HAS_CAS}
  516. register; assembler;
  517. asm
  518. // Target = a0, NewValue = d0, Comperand = d1
  519. exg.l d0, d1
  520. cas.l d0, d1, (a0)
  521. end;
  522. {$ELSE}
  523. begin
  524. getSpinLock;
  525. Result := Target;
  526. if Target = Comperand then
  527. Target := NewValue;
  528. releaseSpinLock;
  529. end;
  530. {$ENDIF}
  531. {$ENDIF FPC_SYSTEM_HAS_INTERLOCKEDFUNCS}
  532. {$ifndef FPC_SYSTEM_HAS_TEST68K}
  533. procedure Test68k(var CPU: byte; var FPU: byte);
  534. begin
  535. {$warning Implement me!}
  536. CPU:=0;
  537. FPU:=0;
  538. end;
  539. {$endif}
  540. {$ifndef FPC_SYSTEM_HAS_SAR_QWORD}
  541. {$define FPC_SYSTEM_HAS_SAR_QWORD}
  542. function fpc_SarInt64(Const AValue : Int64;const Shift : Byte): Int64; [Public,Alias:'FPC_SARINT64']; compilerproc; assembler; nostackframe;
  543. asm
  544. // d0 = shift
  545. lea.l 4(sp),a0
  546. move.l d2,-(sp)
  547. move.l d0,d2
  548. {$ifndef CPUCOLDFIRE}
  549. and.w #63,d2
  550. cmp.w #32,d2
  551. {$else}
  552. and.l #63,d2
  553. cmp.l #32,d2
  554. {$endif}
  555. bge.s @longshift
  556. move.l (a0)+,d0
  557. move.l (a0),d1
  558. {$ifdef CPUM68K_HAS_ROLROR}
  559. cmp.w #1,d2
  560. beq.s @oneshift
  561. {$endif}
  562. {$ifdef CPU68000}
  563. cmp.w #16,d2
  564. beq.s @sixteenshift
  565. {$endif}
  566. move.l d3,a0
  567. move.l d4,a1
  568. move.l d0,d3
  569. moveq.l #32,d4
  570. {$ifndef CPUCOLDFIRE}
  571. sub.w d2,d4
  572. {$else}
  573. sub.l d2,d4
  574. {$endif}
  575. asr.l d2,d0
  576. lsl.l d4,d3
  577. lsr.l d2,d1
  578. or.l d3,d1
  579. move.l a0,d3
  580. move.l a1,d4
  581. bra.s @quit
  582. {$ifdef CPU68000}
  583. @sixteenshift:
  584. move.w d0,d1
  585. swap d1
  586. swap d0
  587. ext.l d0
  588. bra.s @quit
  589. {$endif}
  590. {$ifdef CPUM68K_HAS_ROLROR}
  591. @oneshift:
  592. asr.l #1,d0
  593. roxr.l #1,d1
  594. bra.s @quit
  595. {$endif}
  596. @longshift:
  597. move.l (a0),d0
  598. move.l d0,d1
  599. smi d0
  600. {$if defined(CPU68020) or defined(CPUCOLDFIRE)}
  601. extb.l d0
  602. {$else}
  603. ext.w d0
  604. ext.l d0
  605. {$endif}
  606. {$ifndef CPUCOLDFIRE}
  607. sub.w #32,d2
  608. {$else}
  609. sub.l #32,d2
  610. {$endif}
  611. asr.l d2,d1
  612. @quit:
  613. move.l (sp)+,d2
  614. end;
  615. {$endif}
  616. {$if defined(CPUM68K_HAS_BYTEREV) or defined(CPUM68K_HAS_ROLROR)}
  617. { Disabled for now, because not all cases below were tested. (KB) }
  618. {.$define FPC_SYSTEM_HAS_SWAPENDIAN}
  619. {$endif}
  620. {$if defined(FPC_SYSTEM_HAS_SWAPENDIAN)}
  621. function SwapEndian(const AValue: SmallInt): SmallInt; assembler; nostackframe;
  622. asm
  623. {$if defined(CPUM68K_HAS_ROLROR)}
  624. move.w avalue, d0
  625. ror.w #8, d0
  626. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  627. move.w avalue, d0
  628. byterev d0
  629. swap d0
  630. {$else}
  631. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  632. clr.l d0
  633. move.w avalue, d0
  634. move.w d0, d1
  635. lsr.l #8, d0
  636. lsl.l #8, d1
  637. or.l d1, d0
  638. {$endif}
  639. end;
  640. function SwapEndian(const AValue: Word): Word; assembler; nostackframe;
  641. asm
  642. {$if defined(CPUM68K_HAS_ROLROR)}
  643. move.w avalue, d0
  644. ror.w #8, d0
  645. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  646. move.w avalue, d0
  647. byterev d0
  648. swap d0
  649. {$else}
  650. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  651. clr.l d0
  652. move.w avalue, d0
  653. move.w d0, d1
  654. lsr.l #8, d0
  655. lsl.l #8, d1
  656. or.l d1, d0
  657. {$endif}
  658. end;
  659. function SwapEndian(const AValue: LongInt): LongInt; assembler; nostackframe;
  660. asm
  661. {$if defined(CPUM68K_HAS_ROLROR)}
  662. move.l avalue, d0
  663. ror.w #8, d0
  664. swap d0
  665. ror.w #8, d0
  666. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  667. move.l avalue, d0
  668. byterev d0
  669. {$else}
  670. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  671. move.l avalue, d0
  672. move.l d0, d1
  673. andi.l #$ff00ff00, d0
  674. andi.l #$00ff00ff, d1
  675. lsr.l #8, d0
  676. lsl.l #8, d1
  677. or.l d1, d0
  678. swap d0
  679. {$endif}
  680. end;
  681. function SwapEndian(const AValue: DWord): DWord; assembler; nostackframe;
  682. asm
  683. {$if defined(CPUM68K_HAS_ROLROR)}
  684. move.l avalue, d0
  685. ror.w #8, d0
  686. swap d0
  687. ror.w #8, d0
  688. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  689. move.l avalue, d0
  690. byterev d0
  691. {$else}
  692. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  693. move.l avalue, d0
  694. move.l d0, d1
  695. andi.l #$ff00ff00, d0
  696. andi.l #$00ff00ff, d1
  697. lsr.l #8, d0
  698. lsl.l #8, d1
  699. or.l d1, d0
  700. swap d0
  701. {$endif}
  702. end;
  703. function SwapEndian(const AValue: Int64): Int64; assembler; nostackframe;
  704. asm
  705. {$if defined(CPUM68K_HAS_ROLROR)}
  706. move.l avalue+4, d0
  707. ror.w #8, d0
  708. swap d0
  709. ror.w #8, d0
  710. move.l avalue, d1
  711. ror.w #8, d1
  712. swap d1
  713. ror.w #8, d1
  714. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  715. move.l avalue+4, d0
  716. move.l avalue, d1
  717. byterev d0
  718. byterev d1
  719. {$else}
  720. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  721. move.l d2, -(sp)
  722. move.l avalue+4, d0
  723. move.l d0, d1
  724. andi.l #$ff00ff00, d0
  725. andi.l #$00ff00ff, d1
  726. lsr.l #8, d0
  727. lsl.l #8, d1
  728. or.l d1, d0
  729. swap d0
  730. move.l avalue, d1
  731. move.l d1, d2
  732. andi.l #$ff00ff00, d1
  733. andi.l #$00ff00ff, d2
  734. lsr.l #8, d1
  735. lsl.l #8, d2
  736. or.l d2, d1
  737. swap d1
  738. move.l (sp)+, d2
  739. {$endif}
  740. end;
  741. function SwapEndian(const AValue: QWord): QWord; assembler; nostackframe;
  742. asm
  743. {$if defined(CPUM68K_HAS_ROLROR)}
  744. move.l avalue+4, d0
  745. ror.w #8, d0
  746. swap d0
  747. ror.w #8, d0
  748. move.l avalue, d1
  749. ror.w #8, d1
  750. swap d1
  751. ror.w #8, d1
  752. {$elseif defined(CPUM68K_HAS_BYTEREV)}
  753. move.l avalue+4, d0
  754. move.l avalue, d1
  755. byterev d0
  756. byterev d1
  757. {$else}
  758. // only ISA A/B ColdFire can end in this branch, so use long ops everywhere
  759. move.l d2, -(sp)
  760. move.l avalue+4, d0
  761. move.l d0, d1
  762. andi.l #$ff00ff00, d0
  763. andi.l #$00ff00ff, d1
  764. lsr.l #8, d0
  765. lsl.l #8, d1
  766. or.l d1, d0
  767. swap d0
  768. move.l avalue, d1
  769. move.l d1, d2
  770. andi.l #$ff00ff00, d1
  771. andi.l #$00ff00ff, d2
  772. lsr.l #8, d1
  773. lsl.l #8, d2
  774. or.l d2, d1
  775. swap d1
  776. move.l (sp)+, d2
  777. {$endif}
  778. end;
  779. {$endif FPC_SYSTEM_HAS_SWAPENDIAN}
  780. procedure fpc_cpucodeinit;
  781. begin
  782. Test68k(Test68000,Test68881);
  783. end;