cpubase.pas 20 KB

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  1. {
  2. Copyright (c) 1998-2012 by Florian Klaempfl and Peter Vreman
  3. Contains the base types for ARM64
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. { Base unit for processor information. This unit contains
  18. enumerations of registers, opcodes, sizes, and other
  19. such things which are processor specific.
  20. }
  21. unit cpubase;
  22. {$define USEINLINE}
  23. {$i fpcdefs.inc}
  24. interface
  25. uses
  26. cutils,cclasses,
  27. globtype,globals,
  28. cpuinfo,
  29. aasmbase,
  30. cgbase
  31. ;
  32. {*****************************************************************************
  33. Assembler Opcodes
  34. *****************************************************************************}
  35. type
  36. TAsmOp= {$i a64op.inc}
  37. { This should define the array of instructions as string }
  38. op2strtable=array[tasmop] of string[11];
  39. const
  40. { First value of opcode enumeration }
  41. firstop = low(tasmop);
  42. { Last value of opcode enumeration }
  43. lastop = high(tasmop);
  44. {*****************************************************************************
  45. Registers
  46. *****************************************************************************}
  47. type
  48. { Number of registers used for indexing in tables }
  49. tregisterindex=0..{$i ra64nor.inc}-1;
  50. const
  51. { Available Superregisters }
  52. {$i ra64sup.inc}
  53. R_SUBWHOLE = R_SUBQ;
  54. { Available Registers }
  55. {$i ra64con.inc}
  56. { Integer Super registers first and last }
  57. first_int_supreg = RS_X0;
  58. { xzr and sp take up a separate super register because some instructions
  59. are ambiguous otherwise }
  60. first_int_imreg = $21;
  61. { Integer Super registers first and last }
  62. first_fpu_supreg = RS_S0;
  63. first_fpu_imreg = $20;
  64. { MM Super register first and last }
  65. first_mm_supreg = RS_S0;
  66. first_mm_imreg = $20;
  67. { Required parameter alignment when calling a routine declared as
  68. stdcall and cdecl. The alignment value should be the one defined
  69. by GCC or the target ABI.
  70. The value of this constant is equal to the constant
  71. PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.
  72. }
  73. std_param_align = 4;
  74. { TODO: Calculate bsstart}
  75. regnumber_count_bsstart = 128;
  76. regnumber_table : array[tregisterindex] of tregister = (
  77. {$i ra64num.inc}
  78. );
  79. regstabs_table : array[tregisterindex] of shortint = (
  80. {$i ra64sta.inc}
  81. );
  82. regdwarf_table : array[tregisterindex] of shortint = (
  83. {$i ra64dwa.inc}
  84. );
  85. { registers which may be destroyed by calls }
  86. VOLATILE_INTREGISTERS = [RS_X0..RS_X18,RS_X30];
  87. VOLATILE_MMREGISTERS = [RS_D0..RS_D7,RS_D16..RS_D31];
  88. type
  89. totherregisterset = set of tregisterindex;
  90. {*****************************************************************************
  91. Instruction post fixes
  92. *****************************************************************************}
  93. type
  94. { ARM instructions load/store and arithmetic instructions
  95. can have several instruction post fixes which are collected
  96. in this enumeration
  97. }
  98. TOpPostfix = (PF_None,
  99. { update condition flags }
  100. PF_S,
  101. { load/store sizes }
  102. PF_B,PF_SB,PF_H,PF_SH,PF_W,PF_SW
  103. );
  104. TOpPostfixes = set of TOpPostfix;
  105. const
  106. tcgsizep2size: array[OS_NO..OS_F128] of byte =
  107. {OS_NO }
  108. (0,
  109. {OS_8,OS_16,OS_32,OS_64,OS_128,OS_S8,OS_S16,OS_S32,OS_S64,OS_S128}
  110. 0, 1, 2, 3, 4, 0, 1, 2, 3, 4,
  111. {OS_F32,OS_F64,OS_F80,OS_C64,OS_F128,}
  112. 2, 3, 0, 3, 4);
  113. oppostfix2str: array[TOpPostfix] of string[2] = ('',
  114. 's',
  115. 'b','sb','h','sh','w','sw');
  116. {*****************************************************************************
  117. Conditions
  118. *****************************************************************************}
  119. type
  120. TAsmCond=(C_None,
  121. C_EQ,C_NE,C_HS,C_LO,C_MI,C_PL,C_VS,C_VC,C_HI,C_LS,
  122. C_GE,C_LT,C_GT,C_LE,C_AL,C_NV
  123. );
  124. TAsmConds = set of TAsmCond;
  125. const
  126. cond2str : array[TAsmCond] of string[2]=('',
  127. 'eq','ne','hs','lo','mi','pl','vs','vc','hi','ls',
  128. 'ge','lt','gt','le','al','nv'
  129. );
  130. uppercond2str : array[TAsmCond] of string[2]=('',
  131. 'EQ','NE','HS','LO','MI','PL','VS','VC','HI','LS',
  132. 'GE','LT','GT','LE','AL','NV'
  133. );
  134. {*****************************************************************************
  135. Flags
  136. *****************************************************************************}
  137. type
  138. TResFlags = (F_EQ,F_NE,F_CS,F_CC,F_MI,F_PL,F_VS,F_VC,F_HI,F_LS,
  139. F_GE,F_LT,F_GT,F_LE);
  140. {*****************************************************************************
  141. Operands
  142. *****************************************************************************}
  143. taddressmode = (AM_OFFSET,AM_PREINDEXED,AM_POSTINDEXED);
  144. tshiftmode = (SM_None,
  145. { shifted register instructions. LSL can also be used for
  146. the index register of certain loads/stores }
  147. SM_LSL,SM_LSR,SM_ASR,
  148. { extended register instructions: zero/sign extension +
  149. optional shift (interpreted as LSL after extension)
  150. -- the index register of certain loads/stores can be
  151. extended via (s|u)xtw with a shiftval of either 0 or
  152. log2(transfer size of the load/store)
  153. }
  154. SM_UXTB,SM_UXTH,SM_UXTW,SM_UXTX,SM_SXTB,SM_SXTH,SM_SXTW,SM_SXTX);
  155. tupdatereg = (UR_None,UR_Update);
  156. pshifterop = ^tshifterop;
  157. tshifterop = record
  158. shiftmode : tshiftmode;
  159. shiftimm : byte;
  160. end;
  161. tspecialregflag = (srC, srX, srS, srF);
  162. tspecialregflags = set of tspecialregflag;
  163. {*****************************************************************************
  164. Constants
  165. *****************************************************************************}
  166. const
  167. max_operands = 6;
  168. maxintregs = 32;
  169. maxfpuregs = 32;
  170. maxaddrregs = 0;
  171. shiftedregmodes = [SM_LSL,SM_UXTB,SM_UXTH,SM_UXTW,SM_UXTX,SM_SXTB,SM_SXTH,SM_SXTW,SM_SXTX];
  172. extendedregmodes = [SM_LSL,SM_LSR,SM_ASR];
  173. {*****************************************************************************
  174. Operand Sizes
  175. *****************************************************************************}
  176. type
  177. topsize = (S_NO,
  178. S_B,S_W,S_L,S_BW,S_BL,S_WL,
  179. S_IS,S_IL,S_IQ,
  180. S_FS,S_FL,S_FX,S_D,S_Q,S_FV,S_FXX
  181. );
  182. {*****************************************************************************
  183. Default generic sizes
  184. *****************************************************************************}
  185. const
  186. { Defines the default address size for a processor, }
  187. OS_ADDR = OS_64;
  188. { the natural int size for a processor,
  189. has to match osuinttype/ossinttype as initialized in psystem }
  190. OS_INT = OS_64;
  191. OS_SINT = OS_S64;
  192. { the maximum float size for a processor, }
  193. OS_FLOAT = OS_F64;
  194. { the size of a vector register for a processor }
  195. OS_VECTOR = OS_M128;
  196. {*****************************************************************************
  197. Generic Register names
  198. *****************************************************************************}
  199. NR_FP = NR_X29;
  200. RS_FP = RS_X29;
  201. NR_WFP = NR_W29;
  202. RS_WFP = RS_W29;
  203. NR_LR = NR_X30;
  204. RS_LR = RS_X30;
  205. NR_WLR = NR_W30;
  206. RS_WLR = RS_W30;
  207. { Stack pointer register }
  208. NR_STACK_POINTER_REG = NR_SP;
  209. RS_STACK_POINTER_REG = RS_SP;
  210. { Frame pointer register }
  211. NR_FRAME_POINTER_REG = NR_X29;
  212. RS_FRAME_POINTER_REG = RS_X29;
  213. { Register for addressing absolute data in a position independant way,
  214. such as in PIC code. The exact meaning is ABI specific. For
  215. further information look at GCC source : PIC_OFFSET_TABLE_REGNUM
  216. }
  217. NR_PIC_OFFSET_REG = NR_X18;
  218. { Results are returned in this register (32-bit values) }
  219. NR_FUNCTION_RETURN_REG = NR_X0;
  220. RS_FUNCTION_RETURN_REG = RS_X0;
  221. { The value returned from a function is available in this register }
  222. NR_FUNCTION_RESULT_REG = NR_FUNCTION_RETURN_REG;
  223. RS_FUNCTION_RESULT_REG = RS_FUNCTION_RETURN_REG;
  224. NR_FPU_RESULT_REG = NR_NO;
  225. NR_MM_RESULT_REG = NR_D0;
  226. NR_RETURN_ADDRESS_REG = NR_FUNCTION_RETURN_REG;
  227. { Offset where the parent framepointer is pushed }
  228. PARENT_FRAMEPOINTER_OFFSET = 0;
  229. NR_DEFAULTFLAGS = NR_NZCV;
  230. RS_DEFAULTFLAGS = RS_NZCV;
  231. {*****************************************************************************
  232. GCC /ABI linking information
  233. *****************************************************************************}
  234. const
  235. { Registers which must be saved when calling a routine declared as
  236. cppdecl, cdecl, stdcall, safecall, palmossyscall. The registers
  237. saved should be the ones as defined in the target ABI and / or GCC.
  238. This value can be deduced from the CALLED_USED_REGISTERS array in the
  239. GCC source.
  240. }
  241. saved_standard_registers : array[0..9] of tsuperregister =
  242. (RS_X19,RS_X20,RS_X21,RS_X22,RS_X23,RS_X24,RS_X25,RS_X26,RS_X27,RS_X28);
  243. saved_mm_registers : array[0..7] of tsuperregister = (RS_D8,RS_D9,RS_D10,RS_D11,RS_D12,RS_D13,RS_D14,RS_D15);
  244. { this is only for the generic code which is not used for this architecture }
  245. saved_address_registers : array[0..0] of tsuperregister = (RS_INVALID);
  246. {*****************************************************************************
  247. Helpers
  248. *****************************************************************************}
  249. { Returns the tcgsize corresponding with the size of reg.}
  250. function reg_cgsize(const reg: tregister) : tcgsize;
  251. function cgsize2subreg(regtype: tregistertype; s:Tcgsize):Tsubregister;
  252. function is_calljmp(o:tasmop):boolean;{$ifdef USEINLINE}inline;{$endif USEINLINE}
  253. procedure inverse_flags(var f: TResFlags);
  254. function flags_to_cond(const f: TResFlags) : TAsmCond;
  255. function findreg_by_number(r:Tregister):tregisterindex;
  256. function std_regnum_search(const s:string):Tregister;
  257. function std_regname(r:Tregister):string;
  258. function inverse_cond(const c: TAsmCond): TAsmCond; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  259. function conditions_equal(const c1, c2: TAsmCond): boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  260. procedure shifterop_reset(var so : tshifterop); {$ifdef USEINLINE}inline;{$endif USEINLINE}
  261. function dwarf_reg(r:tregister):shortint;
  262. function is_shifter_const(d: aint; size: tcgsize): boolean;
  263. implementation
  264. uses
  265. systems,rgBase,verbose;
  266. const
  267. std_regname_table : TRegNameTable = (
  268. {$i ra64std.inc}
  269. );
  270. regnumber_index : array[tregisterindex] of tregisterindex = (
  271. {$i ra64rni.inc}
  272. );
  273. std_regname_index : array[tregisterindex] of tregisterindex = (
  274. {$i ra64sri.inc}
  275. );
  276. function cgsize2subreg(regtype: tregistertype; s:Tcgsize):Tsubregister;
  277. begin
  278. case regtype of
  279. R_INTREGISTER:
  280. begin
  281. case s of
  282. { there's only Wn and Xn }
  283. OS_64,
  284. OS_S64:
  285. cgsize2subreg:=R_SUBWHOLE;
  286. else
  287. cgsize2subreg:=R_SUBD;
  288. end;
  289. end;
  290. R_MMREGISTER:
  291. begin
  292. case s of
  293. OS_F32:
  294. cgsize2subreg:=R_SUBFS;
  295. OS_F64:
  296. cgsize2subreg:=R_SUBFD;
  297. else
  298. internalerror(2009112701);
  299. end;
  300. end;
  301. else
  302. cgsize2subreg:=R_SUBWHOLE;
  303. end;
  304. end;
  305. function reg_cgsize(const reg: tregister): tcgsize;
  306. begin
  307. case getregtype(reg) of
  308. R_INTREGISTER:
  309. case getsubreg(reg) of
  310. R_SUBD:
  311. result:=OS_32
  312. else
  313. result:=OS_64;
  314. end;
  315. R_MMREGISTER :
  316. begin
  317. case getsubreg(reg) of
  318. R_SUBFD,
  319. R_SUBWHOLE:
  320. result:=OS_F64;
  321. R_SUBFS:
  322. result:=OS_F32;
  323. else
  324. internalerror(2009112903);
  325. end;
  326. end;
  327. else
  328. internalerror(200303181);
  329. end;
  330. end;
  331. function is_calljmp(o:tasmop):boolean;{$ifdef USEINLINE}inline;{$endif USEINLINE}
  332. begin
  333. is_calljmp:= o in [A_B,A_BLR,A_RET];
  334. end;
  335. procedure inverse_flags(var f: TResFlags);
  336. const
  337. inv_flags: array[TResFlags] of TResFlags =
  338. (F_NE,F_EQ,F_CC,F_CS,F_PL,F_MI,F_VC,F_VS,F_LS,F_HI,
  339. F_LT,F_GE,F_LE,F_GT);
  340. begin
  341. f:=inv_flags[f];
  342. end;
  343. function flags_to_cond(const f: TResFlags) : TAsmCond;
  344. const
  345. flag_2_cond: array[TResFlags] of TAsmCond =
  346. (C_EQ,C_NE,C_HI,C_LO,C_MI,C_PL,C_VS,C_VC,C_HI,C_LS,
  347. C_GE,C_LT,C_GT,C_LE);
  348. begin
  349. if f>high(flag_2_cond) then
  350. internalerror(200112301);
  351. result:=flag_2_cond[f];
  352. end;
  353. function findreg_by_number(r:Tregister):tregisterindex;
  354. begin
  355. result:=rgBase.findreg_by_number_table(r,regnumber_index);
  356. end;
  357. function std_regnum_search(const s:string):Tregister;
  358. begin
  359. result:=regnumber_table[findreg_by_name_table(s,std_regname_table,std_regname_index)];
  360. end;
  361. function std_regname(r:Tregister):string;
  362. var
  363. p : tregisterindex;
  364. begin
  365. p:=findreg_by_number_table(r,regnumber_index);
  366. if p<>0 then
  367. result:=std_regname_table[p]
  368. else
  369. result:=generic_regname(r);
  370. end;
  371. procedure shifterop_reset(var so : tshifterop);{$ifdef USEINLINE}inline;{$endif USEINLINE}
  372. begin
  373. FillChar(so,sizeof(so),0);
  374. end;
  375. function inverse_cond(const c: TAsmCond): TAsmCond; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  376. const
  377. inverse: array[TAsmCond] of TAsmCond=(C_None,
  378. C_NE,C_EQ,C_LO,C_HI,C_PL,C_MI,C_VC,C_VS,C_LS,C_HI,
  379. C_LT,C_GE,C_LE,C_GT,C_None,C_None
  380. );
  381. begin
  382. result := inverse[c];
  383. end;
  384. function conditions_equal(const c1, c2: TAsmCond): boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
  385. begin
  386. result := c1 = c2;
  387. end;
  388. function dwarf_reg(r:tregister):shortint;
  389. begin
  390. result:=regdwarf_table[findreg_by_number(r)];
  391. if result=-1 then
  392. internalerror(200603251);
  393. end;
  394. function is_shifter_const(d: aint; size: tcgsize): boolean;
  395. var
  396. pattern, checkpattern: qword;
  397. patternlen, maxbits, replicatedlen: longint;
  398. rightmostone, rightmostzero, checkbit, secondrightmostbit: longint;
  399. begin
  400. result:=false;
  401. { patterns with all bits 0 or 1 cannot be represented this way }
  402. if (d=0) then
  403. exit;
  404. case size of
  405. OS_64,
  406. OS_S64:
  407. begin
  408. if d=-1 then
  409. exit;
  410. maxbits:=64;
  411. end
  412. else
  413. begin
  414. if longint(d)=-1 then
  415. exit;
  416. { we'll generate a 32 bit pattern -> ignore upper sign bits in
  417. case of negative longint value }
  418. d:=cardinal(d);
  419. maxbits:=32;
  420. end;
  421. end;
  422. { "The Logical (immediate) instructions accept a bitmask immediate value
  423. that is a 32-bit pattern or a 64-bit pattern viewed as a vector of
  424. identical elements of size e = 2, 4, 8, 16, 32 or, 64 bits. Each
  425. element contains the same sub-pattern, that is a single run of
  426. 1 to (e - 1) nonzero bits from bit 0 followed by zero bits, then
  427. rotated by 0 to (e - 1) bits." (ARMv8 ARM)
  428. Rather than generating all possible patterns and checking whether they
  429. match our constant, we check whether the lowest 2/4/8/... bits are
  430. a valid pattern, and if so whether the constant consists of a
  431. replication of this pattern. Such a valid pattern has the form of
  432. either (regexp notation)
  433. * 1+0+1*
  434. * 0+1+0* }
  435. patternlen:=2;
  436. while patternlen<=maxbits do
  437. begin
  438. { try lowest <patternlen> bits of d as pattern }
  439. if patternlen<>64 then
  440. pattern:=qword(d) and ((qword(1) shl patternlen)-1)
  441. else
  442. pattern:=qword(d);
  443. { valid pattern? If it contains too many 1<->0 transitions, larger
  444. parts of d cannot be a valid pattern either }
  445. rightmostone:=BsfQWord(pattern);
  446. rightmostzero:=BsfQWord(not(pattern));
  447. { pattern all ones or zeroes -> not a valid pattern (but larger ones
  448. can still be valid, since we have too few transitions) }
  449. if (rightmostone<patternlen) and
  450. (rightmostzero<patternlen) then
  451. begin
  452. if rightmostone>rightmostzero then
  453. begin
  454. { we have .*1*0* -> check next zero position by shifting
  455. out the existing zeroes (shr rightmostone), inverting and
  456. then again looking for the rightmost one position }
  457. checkpattern:=not(pattern);
  458. checkbit:=rightmostone;
  459. end
  460. else
  461. begin
  462. { same as above, but for .*0*1* }
  463. checkpattern:=pattern;
  464. checkbit:=rightmostzero;
  465. end;
  466. secondrightmostbit:=BsfQWord(checkpattern shr checkbit)+checkbit;
  467. { if this position is >= patternlen -> ok (1 transition),
  468. otherwise we now have 2 transitions and have to check for a
  469. third (if there is one, abort)
  470. bsf returns 255 if no 1 bit is found, so in that case it's
  471. also ok
  472. }
  473. if secondrightmostbit<patternlen then
  474. begin
  475. secondrightmostbit:=BsfQWord(not(checkpattern) shr secondrightmostbit)+secondrightmostbit;
  476. if secondrightmostbit<patternlen then
  477. exit;
  478. end;
  479. { ok, this is a valid pattern, now does d consist of a
  480. repetition of this pattern? }
  481. replicatedlen:=patternlen;
  482. checkpattern:=pattern;
  483. while replicatedlen<maxbits do
  484. begin
  485. { douplicate current pattern }
  486. checkpattern:=checkpattern or (checkpattern shl replicatedlen);
  487. replicatedlen:=replicatedlen*2;
  488. end;
  489. if qword(d)=checkpattern then
  490. begin
  491. { yes! }
  492. result:=true;
  493. exit;
  494. end;
  495. end;
  496. patternlen:=patternlen*2;
  497. end;
  498. end;
  499. end.