cgcpu.pas 66 KB

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  1. {
  2. Copyright (c) 2008 by Florian Klaempfl
  3. Member of the Free Pascal development team
  4. This unit implements the code generator for the AVR
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. unit cgcpu;
  19. {$i fpcdefs.inc}
  20. interface
  21. uses
  22. globtype,symtype,symdef,
  23. cgbase,cgutils,cgobj,
  24. aasmbase,aasmcpu,aasmtai,aasmdata,
  25. parabase,
  26. cpubase,cpuinfo,node,cg64f32,rgcpu;
  27. type
  28. { tcgavr }
  29. tcgavr = class(tcg)
  30. { true, if the next arithmetic operation should modify the flags }
  31. cgsetflags : boolean;
  32. procedure init_register_allocators;override;
  33. procedure done_register_allocators;override;
  34. function getintregister(list:TAsmList;size:Tcgsize):Tregister;override;
  35. function getaddressregister(list:TAsmList):TRegister;override;
  36. procedure a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);override;
  37. procedure a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);override;
  38. procedure a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);override;
  39. procedure a_load_reg_cgpara(list : TAsmList; size : tcgsize;r : tregister; const cgpara : tcgpara);override;
  40. procedure a_call_name(list : TAsmList;const s : string; weak: boolean);override;
  41. procedure a_call_reg(list : TAsmList;reg: tregister);override;
  42. procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister); override;
  43. procedure a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src, dst : TRegister); override;
  44. { move instructions }
  45. procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);override;
  46. procedure a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
  47. procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
  48. procedure a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
  49. { fpu move instructions }
  50. procedure a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
  51. procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
  52. procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
  53. { comparison operations }
  54. procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
  55. l : tasmlabel);override;
  56. procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
  57. procedure a_jmp_name(list : TAsmList;const s : string); override;
  58. procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
  59. procedure a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel); override;
  60. procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  61. procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
  62. procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
  63. procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
  64. procedure g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);override;
  65. procedure g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  66. procedure g_overflowcheck(list: TAsmList; const l: tlocation; def: tdef); override;
  67. procedure g_save_registers(list : TAsmList);override;
  68. procedure g_restore_registers(list : TAsmList);override;
  69. procedure a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  70. procedure fixref(list : TAsmList;var ref : treference);
  71. function normalize_ref(list : TAsmList;ref : treference;
  72. tmpreg : tregister) : treference;
  73. procedure g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);override;
  74. procedure g_stackpointer_alloc(list : TAsmList;size : longint);override;
  75. procedure emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  76. procedure a_adjust_sp(list: TAsmList; value: longint);
  77. function GetLoad(const ref : treference) : tasmop;
  78. function GetStore(const ref: treference): tasmop;
  79. procedure a_bit_scan_reg_reg(list: TAsmList; reverse: boolean; size: TCGSize; src, dst: TRegister); override;
  80. protected
  81. procedure a_op_reg_reg_internal(list: TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
  82. procedure a_op_const_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg, reghi: TRegister);
  83. end;
  84. tcg64favr = class(tcg64f32)
  85. procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  86. procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
  87. end;
  88. procedure create_codegen;
  89. const
  90. TOpCG2AsmOp: Array[topcg] of TAsmOp = (A_NONE,A_MOV,A_ADD,A_AND,A_NONE,
  91. A_NONE,A_MUL,A_MULS,A_NEG,A_COM,A_OR,
  92. A_ASR,A_LSL,A_LSR,A_SUB,A_EOR,A_ROL,A_ROR);
  93. implementation
  94. uses
  95. globals,verbose,systems,cutils,
  96. fmodule,
  97. symconst,symsym,symtable,
  98. tgobj,rgobj,
  99. procinfo,cpupi,
  100. paramgr;
  101. procedure tcgavr.init_register_allocators;
  102. begin
  103. inherited init_register_allocators;
  104. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  105. [RS_R8,RS_R9,
  106. RS_R10,RS_R11,RS_R12,RS_R13,RS_R14,RS_R15,RS_R16,RS_R17,RS_R18,RS_R19,
  107. RS_R20,RS_R21,RS_R22,RS_R23,RS_R24,RS_R25,
  108. RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7],first_int_imreg,[]);
  109. { rg[R_ADDRESSREGISTER]:=trgintcpu.create(R_ADDRESSREGISTER,R_SUBWHOLE,
  110. [RS_R26,RS_R30],first_int_imreg,[]); }
  111. end;
  112. procedure tcgavr.done_register_allocators;
  113. begin
  114. rg[R_INTREGISTER].free;
  115. // rg[R_ADDRESSREGISTER].free;
  116. inherited done_register_allocators;
  117. end;
  118. function tcgavr.getintregister(list: TAsmList; size: Tcgsize): Tregister;
  119. var
  120. tmp1,tmp2,tmp3 : TRegister;
  121. begin
  122. case size of
  123. OS_8,OS_S8:
  124. Result:=inherited getintregister(list, size);
  125. OS_16,OS_S16:
  126. begin
  127. Result:=inherited getintregister(list, OS_8);
  128. { ensure that the high register can be retrieved by
  129. GetNextReg
  130. }
  131. if inherited getintregister(list, OS_8)<>GetNextReg(Result) then
  132. internalerror(2011021331);
  133. end;
  134. OS_32,OS_S32:
  135. begin
  136. Result:=inherited getintregister(list, OS_8);
  137. tmp1:=inherited getintregister(list, OS_8);
  138. { ensure that the high register can be retrieved by
  139. GetNextReg
  140. }
  141. if tmp1<>GetNextReg(Result) then
  142. internalerror(2011021332);
  143. tmp2:=inherited getintregister(list, OS_8);
  144. { ensure that the upper register can be retrieved by
  145. GetNextReg
  146. }
  147. if tmp2<>GetNextReg(tmp1) then
  148. internalerror(2011021333);
  149. tmp3:=inherited getintregister(list, OS_8);
  150. { ensure that the upper register can be retrieved by
  151. GetNextReg
  152. }
  153. if tmp3<>GetNextReg(tmp2) then
  154. internalerror(2011021334);
  155. end;
  156. else
  157. internalerror(2011021330);
  158. end;
  159. end;
  160. function tcgavr.getaddressregister(list: TAsmList): TRegister;
  161. begin
  162. Result:=getintregister(list,OS_ADDR);
  163. end;
  164. procedure tcgavr.a_load_reg_cgpara(list : TAsmList;size : tcgsize;r : tregister;const cgpara : tcgpara);
  165. procedure load_para_loc(r : TRegister;paraloc : PCGParaLocation);
  166. var
  167. ref : treference;
  168. begin
  169. paramanager.allocparaloc(list,paraloc);
  170. case paraloc^.loc of
  171. LOC_REGISTER,LOC_CREGISTER:
  172. a_load_reg_reg(list,paraloc^.size,paraloc^.size,r,paraloc^.register);
  173. LOC_REFERENCE,LOC_CREFERENCE:
  174. begin
  175. reference_reset_base(ref,paraloc^.reference.index,paraloc^.reference.offset,2);
  176. a_load_reg_ref(list,paraloc^.size,paraloc^.size,r,ref);
  177. end;
  178. else
  179. internalerror(2002071004);
  180. end;
  181. end;
  182. var
  183. i : longint;
  184. hp : PCGParaLocation;
  185. begin
  186. { if use_push(cgpara) then
  187. begin
  188. if tcgsize2size[cgpara.Size] > 2 then
  189. begin
  190. if tcgsize2size[cgpara.Size] <> 4 then
  191. internalerror(2013031101);
  192. if cgpara.location^.Next = nil then
  193. begin
  194. if tcgsize2size[cgpara.location^.size] <> 4 then
  195. internalerror(2013031101);
  196. end
  197. else
  198. begin
  199. if tcgsize2size[cgpara.location^.size] <> 2 then
  200. internalerror(2013031101);
  201. if tcgsize2size[cgpara.location^.Next^.size] <> 2 then
  202. internalerror(2013031101);
  203. if cgpara.location^.Next^.Next <> nil then
  204. internalerror(2013031101);
  205. end;
  206. if tcgsize2size[cgpara.size]>cgpara.alignment then
  207. pushsize:=cgpara.size
  208. else
  209. pushsize:=int_cgsize(cgpara.alignment);
  210. pushsize2 := int_cgsize(tcgsize2size[pushsize] - 2);
  211. list.concat(taicpu.op_reg(A_PUSH,TCgsize2opsize[pushsize2],makeregsize(list,GetNextReg(r),pushsize2)));
  212. list.concat(taicpu.op_reg(A_PUSH,S_W,makeregsize(list,r,OS_16)));
  213. end
  214. else
  215. begin
  216. cgpara.check_simple_location;
  217. if tcgsize2size[cgpara.location^.size]>cgpara.alignment then
  218. pushsize:=cgpara.location^.size
  219. else
  220. pushsize:=int_cgsize(cgpara.alignment);
  221. list.concat(taicpu.op_reg(A_PUSH,TCgsize2opsize[pushsize],makeregsize(list,r,pushsize)));
  222. end;
  223. end
  224. else }
  225. begin
  226. if not(tcgsize2size[cgpara.Size] in [1..4]) then
  227. internalerror(2014011101);
  228. hp:=cgpara.location;
  229. for i:=1 to tcgsize2size[cgpara.Size] do
  230. begin
  231. if not(assigned(hp)) or
  232. (tcgsize2size[hp^.size]<>1) or
  233. (hp^.shiftval<>0) then
  234. internalerror(2014011102);
  235. load_para_loc(r,hp);
  236. hp:=hp^.Next;
  237. r:=GetNextReg(r);
  238. end;
  239. if assigned(hp) then
  240. internalerror(2014011103);
  241. end;
  242. end;
  243. procedure tcgavr.a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);
  244. var
  245. i : longint;
  246. hp : PCGParaLocation;
  247. begin
  248. if not(tcgsize2size[paraloc.Size] in [1..4]) then
  249. internalerror(2014011101);
  250. hp:=paraloc.location;
  251. for i:=1 to tcgsize2size[paraloc.Size] do
  252. begin
  253. if not(assigned(hp)) or
  254. (tcgsize2size[hp^.size]<>1) or
  255. (hp^.shiftval<>0) then
  256. internalerror(2014011105);
  257. case hp^.loc of
  258. LOC_REGISTER,LOC_CREGISTER:
  259. a_load_const_reg(list,hp^.size,(a shr (i-1)) and $ff,hp^.register);
  260. LOC_REFERENCE,LOC_CREFERENCE:
  261. begin
  262. list.concat(taicpu.op_const(A_PUSH,(a shr (i-1)) and $ff));
  263. end;
  264. else
  265. internalerror(2002071004);
  266. end;
  267. hp:=hp^.Next;
  268. end;
  269. if assigned(hp) then
  270. internalerror(2014011104);
  271. end;
  272. procedure tcgavr.a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);
  273. var
  274. tmpref, ref: treference;
  275. location: pcgparalocation;
  276. sizeleft: tcgint;
  277. begin
  278. location := paraloc.location;
  279. tmpref := r;
  280. sizeleft := paraloc.intsize;
  281. while assigned(location) do
  282. begin
  283. paramanager.allocparaloc(list,location);
  284. case location^.loc of
  285. LOC_REGISTER,LOC_CREGISTER:
  286. a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
  287. LOC_REFERENCE:
  288. begin
  289. reference_reset_base(ref,location^.reference.index,location^.reference.offset,paraloc.alignment);
  290. { doubles in softemu mode have a strange order of registers and references }
  291. if location^.size=OS_32 then
  292. g_concatcopy(list,tmpref,ref,4)
  293. else
  294. begin
  295. g_concatcopy(list,tmpref,ref,sizeleft);
  296. if assigned(location^.next) then
  297. internalerror(2005010710);
  298. end;
  299. end;
  300. LOC_VOID:
  301. begin
  302. // nothing to do
  303. end;
  304. else
  305. internalerror(2002081103);
  306. end;
  307. inc(tmpref.offset,tcgsize2size[location^.size]);
  308. dec(sizeleft,tcgsize2size[location^.size]);
  309. location := location^.next;
  310. end;
  311. end;
  312. procedure tcgavr.a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);
  313. var
  314. tmpreg: tregister;
  315. begin
  316. tmpreg:=getaddressregister(list);
  317. a_loadaddr_ref_reg(list,r,tmpreg);
  318. a_load_reg_cgpara(list,OS_ADDR,tmpreg,paraloc);
  319. end;
  320. procedure tcgavr.a_call_name(list : TAsmList;const s : string; weak: boolean);
  321. begin
  322. list.concat(taicpu.op_sym(A_RCALL,current_asmdata.RefAsmSymbol(s)));
  323. {
  324. the compiler does not properly set this flag anymore in pass 1, and
  325. for now we only need it after pass 2 (I hope) (JM)
  326. if not(pi_do_call in current_procinfo.flags) then
  327. internalerror(2003060703);
  328. }
  329. include(current_procinfo.flags,pi_do_call);
  330. end;
  331. procedure tcgavr.a_call_reg(list : TAsmList;reg: tregister);
  332. begin
  333. a_reg_alloc(list,NR_ZLO);
  334. a_reg_alloc(list,NR_ZHI);
  335. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZLO,reg));
  336. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZHI,GetHigh(reg)));
  337. list.concat(taicpu.op_none(A_ICALL));
  338. a_reg_dealloc(list,NR_ZLO);
  339. a_reg_dealloc(list,NR_ZHI);
  340. include(current_procinfo.flags,pi_do_call);
  341. end;
  342. procedure tcgavr.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister);
  343. begin
  344. if not(size in [OS_S8,OS_8,OS_S16,OS_16,OS_S32,OS_32]) then
  345. internalerror(2012102403);
  346. a_op_const_reg_internal(list,Op,size,a,reg,NR_NO);
  347. end;
  348. procedure tcgavr.a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src, dst : TRegister);
  349. begin
  350. if not(size in [OS_S8,OS_8,OS_S16,OS_16,OS_S32,OS_32]) then
  351. internalerror(2012102401);
  352. a_op_reg_reg_internal(list,Op,size,src,NR_NO,dst,NR_NO);
  353. end;
  354. procedure tcgavr.a_op_reg_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
  355. var
  356. countreg,
  357. tmpreg: tregister;
  358. i : integer;
  359. instr : taicpu;
  360. paraloc1,paraloc2,paraloc3 : TCGPara;
  361. l1,l2 : tasmlabel;
  362. pd : tprocdef;
  363. procedure NextSrcDst;
  364. begin
  365. if i=5 then
  366. begin
  367. dst:=dsthi;
  368. src:=srchi;
  369. end
  370. else
  371. begin
  372. dst:=GetNextReg(dst);
  373. src:=GetNextReg(src);
  374. end;
  375. end;
  376. { iterates TmpReg through all registers of dst }
  377. procedure NextTmp;
  378. begin
  379. if i=5 then
  380. tmpreg:=dsthi
  381. else
  382. tmpreg:=GetNextReg(tmpreg);
  383. end;
  384. begin
  385. case op of
  386. OP_ADD:
  387. begin
  388. list.concat(taicpu.op_reg_reg(A_ADD,dst,src));
  389. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  390. begin
  391. for i:=2 to tcgsize2size[size] do
  392. begin
  393. NextSrcDst;
  394. list.concat(taicpu.op_reg_reg(A_ADC,dst,src));
  395. end;
  396. end;
  397. end;
  398. OP_SUB:
  399. begin
  400. list.concat(taicpu.op_reg_reg(A_SUB,dst,src));
  401. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  402. begin
  403. for i:=2 to tcgsize2size[size] do
  404. begin
  405. NextSrcDst;
  406. list.concat(taicpu.op_reg_reg(A_SBC,dst,src));
  407. end;
  408. end;
  409. end;
  410. OP_NEG:
  411. begin
  412. if src<>dst then
  413. a_load_reg_reg(list,size,size,src,dst);
  414. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  415. begin
  416. tmpreg:=GetNextReg(dst);
  417. for i:=2 to tcgsize2size[size] do
  418. begin
  419. list.concat(taicpu.op_reg(A_COM,tmpreg));
  420. NextTmp;
  421. end;
  422. list.concat(taicpu.op_reg(A_NEG,dst));
  423. tmpreg:=GetNextReg(dst);
  424. for i:=2 to tcgsize2size[size] do
  425. begin
  426. list.concat(taicpu.op_reg_const(A_SBCI,dst,-1));
  427. NextTmp;
  428. end;
  429. end;
  430. end;
  431. OP_NOT:
  432. begin
  433. for i:=1 to tcgsize2size[size] do
  434. begin
  435. if src<>dst then
  436. a_load_reg_reg(list,OS_8,OS_8,src,dst);
  437. list.concat(taicpu.op_reg(A_COM,dst));
  438. NextSrcDst;
  439. end;
  440. end;
  441. OP_MUL,OP_IMUL:
  442. begin
  443. if size in [OS_8,OS_S8] then
  444. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src))
  445. else if size=OS_16 then
  446. begin
  447. pd:=search_system_proc('fpc_mul_word');
  448. paraloc1.init;
  449. paraloc2.init;
  450. paraloc3.init;
  451. paramanager.getintparaloc(pd,1,paraloc1);
  452. paramanager.getintparaloc(pd,2,paraloc2);
  453. paramanager.getintparaloc(pd,3,paraloc3);
  454. a_load_const_cgpara(list,OS_8,0,paraloc3);
  455. a_load_reg_cgpara(list,OS_16,src,paraloc2);
  456. a_load_reg_cgpara(list,OS_16,dst,paraloc1);
  457. paramanager.freecgpara(list,paraloc3);
  458. paramanager.freecgpara(list,paraloc2);
  459. paramanager.freecgpara(list,paraloc1);
  460. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  461. a_call_name(list,'FPC_MUL_WORD',false);
  462. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  463. cg.a_reg_alloc(list,NR_FUNCTION_RESULT_REG);
  464. cg.a_load_reg_reg(list,OS_16,OS_16,NR_FUNCTION_RESULT_REG,dst);
  465. paraloc3.done;
  466. paraloc2.done;
  467. paraloc1.done;
  468. end
  469. else
  470. internalerror(2011022002);
  471. end;
  472. OP_DIV,OP_IDIV:
  473. { special stuff, needs separate handling inside code }
  474. { generator }
  475. internalerror(2011022001);
  476. OP_SHR,OP_SHL,OP_SAR,OP_ROL,OP_ROR:
  477. begin
  478. current_asmdata.getjumplabel(l1);
  479. current_asmdata.getjumplabel(l2);
  480. countreg:=getintregister(list,OS_8);
  481. a_load_reg_reg(list,size,OS_8,src,countreg);
  482. list.concat(taicpu.op_reg_const(A_CPI,countreg,0));
  483. a_jmp_flags(list,F_EQ,l2);
  484. cg.a_label(list,l1);
  485. case op of
  486. OP_SHR:
  487. list.concat(taicpu.op_reg(A_LSR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  488. OP_SHL:
  489. list.concat(taicpu.op_reg(A_LSL,dst));
  490. OP_SAR:
  491. list.concat(taicpu.op_reg(A_ASR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  492. OP_ROR:
  493. begin
  494. { load carry? }
  495. if not(size in [OS_8,OS_S8]) then
  496. begin
  497. list.concat(taicpu.op_none(A_CLC));
  498. list.concat(taicpu.op_reg_const(A_SBRC,src,0));
  499. list.concat(taicpu.op_none(A_SEC));
  500. end;
  501. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  502. end;
  503. OP_ROL:
  504. begin
  505. { load carry? }
  506. if not(size in [OS_8,OS_S8]) then
  507. begin
  508. list.concat(taicpu.op_none(A_CLC));
  509. list.concat(taicpu.op_reg_const(A_SBRC,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1),7));
  510. list.concat(taicpu.op_none(A_SEC));
  511. end;
  512. list.concat(taicpu.op_reg(A_ROL,dst))
  513. end;
  514. else
  515. internalerror(2011030901);
  516. end;
  517. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  518. begin
  519. for i:=2 to tcgsize2size[size] do
  520. begin
  521. case op of
  522. OP_ROR,
  523. OP_SHR:
  524. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  525. OP_ROL,
  526. OP_SHL:
  527. list.concat(taicpu.op_reg(A_ROL,GetOffsetReg64(dst,dsthi,i-1)));
  528. OP_SAR:
  529. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  530. else
  531. internalerror(2011030902);
  532. end;
  533. end;
  534. end;
  535. a_op_const_reg(list,OP_SUB,OS_8,1,countreg);
  536. a_jmp_flags(list,F_NE,l1);
  537. // keep registers alive
  538. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  539. cg.a_label(list,l2);
  540. end;
  541. OP_AND,OP_OR,OP_XOR:
  542. begin
  543. for i:=1 to tcgsize2size[size] do
  544. begin
  545. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src));
  546. NextSrcDst;
  547. end;
  548. end;
  549. else
  550. internalerror(2011022004);
  551. end;
  552. end;
  553. procedure tcgavr.a_op_const_reg_internal(list: TAsmList; Op: TOpCG;
  554. size: TCGSize; a: tcgint; reg, reghi: TRegister);
  555. var
  556. mask : qword;
  557. shift : byte;
  558. i : byte;
  559. tmpreg : tregister;
  560. tmpreg64 : tregister64;
  561. procedure NextReg;
  562. begin
  563. if i=5 then
  564. reg:=reghi
  565. else
  566. reg:=GetNextReg(reg);
  567. end;
  568. begin
  569. mask:=$ff;
  570. shift:=0;
  571. case op of
  572. OP_OR:
  573. begin
  574. for i:=1 to tcgsize2size[size] do
  575. begin
  576. list.concat(taicpu.op_reg_const(A_ORI,reg,(a and mask) shr shift));
  577. NextReg;
  578. mask:=mask shl 8;
  579. inc(shift,8);
  580. end;
  581. end;
  582. OP_AND:
  583. begin
  584. for i:=1 to tcgsize2size[size] do
  585. begin
  586. list.concat(taicpu.op_reg_const(A_ANDI,reg,(a and mask) shr shift));
  587. NextReg;
  588. mask:=mask shl 8;
  589. inc(shift,8);
  590. end;
  591. end;
  592. OP_SUB:
  593. begin
  594. list.concat(taicpu.op_reg_const(A_SUBI,reg,a and mask));
  595. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  596. begin
  597. for i:=2 to tcgsize2size[size] do
  598. begin
  599. NextReg;
  600. mask:=mask shl 8;
  601. inc(shift,8);
  602. list.concat(taicpu.op_reg_const(A_SBCI,reg,(a and mask) shr shift));
  603. end;
  604. end;
  605. end;
  606. {OP_ADD:
  607. begin
  608. list.concat(taicpu.op_reg_const(A_SUBI,reg,(-a) and mask));
  609. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  610. begin
  611. for i:=2 to tcgsize2size[size] do
  612. begin
  613. NextReg;
  614. mask:=mask shl 8;
  615. inc(shift,8);
  616. list.concat(taicpu.op_reg_const(A_ADC,reg,(a and mask) shr shift));
  617. end;
  618. end;
  619. end; }
  620. else
  621. begin
  622. if size in [OS_64,OS_S64] then
  623. begin
  624. tmpreg64.reglo:=getintregister(list,OS_32);
  625. tmpreg64.reghi:=getintregister(list,OS_32);
  626. cg64.a_load64_const_reg(list,a,tmpreg64);
  627. cg64.a_op64_reg_reg(list,op,size,tmpreg64,joinreg64(reg,reghi));
  628. end
  629. else
  630. begin
  631. tmpreg:=getintregister(list,size);
  632. a_load_const_reg(list,size,a,tmpreg);
  633. a_op_reg_reg(list,op,size,tmpreg,reg);
  634. end;
  635. end;
  636. end;
  637. end;
  638. procedure tcgavr.a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);
  639. var
  640. mask : qword;
  641. shift : byte;
  642. i : byte;
  643. begin
  644. mask:=$ff;
  645. shift:=0;
  646. for i:=1 to tcgsize2size[size] do
  647. begin
  648. if ((qword(a) and mask) shr shift)=0 then
  649. emit_mov(list,reg,NR_R1)
  650. else
  651. list.concat(taicpu.op_reg_const(A_LDI,reg,(qword(a) and mask) shr shift));
  652. mask:=mask shl 8;
  653. inc(shift,8);
  654. reg:=GetNextReg(reg);
  655. end;
  656. end;
  657. function tcgavr.normalize_ref(list:TAsmList;ref: treference;tmpreg : tregister) : treference;
  658. procedure maybegetcpuregister(list:tasmlist;reg : tregister);
  659. begin
  660. { allocate the register only, if a cpu register is passed }
  661. if getsupreg(reg)<first_int_imreg then
  662. getcpuregister(list,reg);
  663. end;
  664. var
  665. tmpref : treference;
  666. l : tasmlabel;
  667. begin
  668. Result:=ref;
  669. if ref.addressmode<>AM_UNCHANGED then
  670. internalerror(2011021701);
  671. { Be sure to have a base register }
  672. if (ref.base=NR_NO) then
  673. begin
  674. { only symbol+offset? }
  675. if ref.index=NR_NO then
  676. exit;
  677. ref.base:=ref.index;
  678. ref.index:=NR_NO;
  679. end;
  680. if assigned(ref.symbol) or (ref.offset<>0) then
  681. begin
  682. reference_reset(tmpref,0);
  683. tmpref.symbol:=ref.symbol;
  684. tmpref.offset:=ref.offset;
  685. tmpref.refaddr:=addr_lo8;
  686. maybegetcpuregister(list,tmpreg);
  687. list.concat(taicpu.op_reg_ref(A_LDI,tmpreg,tmpref));
  688. tmpref.refaddr:=addr_hi8;
  689. maybegetcpuregister(list,GetNextReg(tmpreg));
  690. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(tmpreg),tmpref));
  691. if (ref.base<>NR_NO) then
  692. begin
  693. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
  694. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
  695. end;
  696. if (ref.index<>NR_NO) then
  697. begin
  698. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  699. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  700. end;
  701. ref.symbol:=nil;
  702. ref.offset:=0;
  703. ref.base:=tmpreg;
  704. ref.index:=NR_NO;
  705. end
  706. else if (ref.base<>NR_NO) and (ref.index<>NR_NO) then
  707. begin
  708. maybegetcpuregister(list,tmpreg);
  709. emit_mov(list,tmpreg,ref.base);
  710. maybegetcpuregister(list,GetNextReg(tmpreg));
  711. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  712. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  713. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  714. ref.base:=tmpreg;
  715. ref.index:=NR_NO;
  716. end
  717. else if (ref.base<>NR_NO) then
  718. begin
  719. maybegetcpuregister(list,tmpreg);
  720. emit_mov(list,tmpreg,ref.base);
  721. maybegetcpuregister(list,GetNextReg(tmpreg));
  722. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  723. ref.base:=tmpreg;
  724. ref.index:=NR_NO;
  725. end
  726. else if (ref.index<>NR_NO) then
  727. begin
  728. maybegetcpuregister(list,tmpreg);
  729. emit_mov(list,tmpreg,ref.index);
  730. maybegetcpuregister(list,GetNextReg(tmpreg));
  731. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
  732. ref.base:=tmpreg;
  733. ref.index:=NR_NO;
  734. end;
  735. Result:=ref;
  736. end;
  737. procedure tcgavr.a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);
  738. var
  739. href : treference;
  740. conv_done: boolean;
  741. tmpreg : tregister;
  742. i : integer;
  743. QuickRef : Boolean;
  744. begin
  745. QuickRef:=false;
  746. if not((Ref.addressmode=AM_UNCHANGED) and
  747. (Ref.symbol=nil) and
  748. ((Ref.base=NR_R28) or
  749. (Ref.base=NR_R29)) and
  750. (Ref.Index=NR_No) and
  751. (Ref.Offset in [0..64-tcgsize2size[tosize]])) and
  752. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  753. href:=normalize_ref(list,Ref,NR_R30)
  754. else
  755. begin
  756. QuickRef:=true;
  757. href:=Ref;
  758. end;
  759. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  760. internalerror(2011021307);
  761. conv_done:=false;
  762. if tosize<>fromsize then
  763. begin
  764. conv_done:=true;
  765. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  766. fromsize:=tosize;
  767. case fromsize of
  768. OS_8:
  769. begin
  770. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  771. href.addressmode:=AM_POSTINCREMENT;
  772. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  773. for i:=2 to tcgsize2size[tosize] do
  774. begin
  775. if QuickRef then
  776. inc(href.offset);
  777. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  778. href.addressmode:=AM_POSTINCREMENT
  779. else
  780. href.addressmode:=AM_UNCHANGED;
  781. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  782. end;
  783. end;
  784. OS_S8:
  785. begin
  786. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  787. href.addressmode:=AM_POSTINCREMENT;
  788. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  789. if tcgsize2size[tosize]>1 then
  790. begin
  791. tmpreg:=getintregister(list,OS_8);
  792. list.concat(taicpu.op_reg(A_CLR,tmpreg));
  793. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  794. list.concat(taicpu.op_reg(A_COM,tmpreg));
  795. for i:=2 to tcgsize2size[tosize] do
  796. begin
  797. if QuickRef then
  798. inc(href.offset);
  799. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  800. href.addressmode:=AM_POSTINCREMENT
  801. else
  802. href.addressmode:=AM_UNCHANGED;
  803. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  804. end;
  805. end;
  806. end;
  807. OS_16:
  808. begin
  809. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  810. href.addressmode:=AM_POSTINCREMENT;
  811. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  812. if QuickRef then
  813. inc(href.offset)
  814. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  815. href.addressmode:=AM_POSTINCREMENT
  816. else
  817. href.addressmode:=AM_UNCHANGED;
  818. reg:=GetNextReg(reg);
  819. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  820. for i:=3 to tcgsize2size[tosize] do
  821. begin
  822. if QuickRef then
  823. inc(href.offset);
  824. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  825. href.addressmode:=AM_POSTINCREMENT
  826. else
  827. href.addressmode:=AM_UNCHANGED;
  828. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  829. end;
  830. end;
  831. OS_S16:
  832. begin
  833. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  834. href.addressmode:=AM_POSTINCREMENT;
  835. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  836. if QuickRef then
  837. inc(href.offset)
  838. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  839. href.addressmode:=AM_POSTINCREMENT
  840. else
  841. href.addressmode:=AM_UNCHANGED;
  842. reg:=GetNextReg(reg);
  843. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  844. if tcgsize2size[tosize]>2 then
  845. begin
  846. tmpreg:=getintregister(list,OS_8);
  847. list.concat(taicpu.op_reg(A_CLR,tmpreg));
  848. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  849. list.concat(taicpu.op_reg(A_COM,tmpreg));
  850. for i:=3 to tcgsize2size[tosize] do
  851. begin
  852. if QuickRef then
  853. inc(href.offset);
  854. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  855. href.addressmode:=AM_POSTINCREMENT
  856. else
  857. href.addressmode:=AM_UNCHANGED;
  858. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  859. end;
  860. end;
  861. end;
  862. else
  863. conv_done:=false;
  864. end;
  865. end;
  866. if not conv_done then
  867. begin
  868. for i:=1 to tcgsize2size[fromsize] do
  869. begin
  870. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  871. href.addressmode:=AM_POSTINCREMENT
  872. else
  873. href.addressmode:=AM_UNCHANGED;
  874. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  875. if QuickRef then
  876. inc(href.offset);
  877. reg:=GetNextReg(reg);
  878. end;
  879. end;
  880. if not(QuickRef) then
  881. begin
  882. ungetcpuregister(list,href.base);
  883. ungetcpuregister(list,GetNextReg(href.base));
  884. end;
  885. end;
  886. procedure tcgavr.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;
  887. const Ref : treference;reg : tregister);
  888. var
  889. href : treference;
  890. conv_done: boolean;
  891. tmpreg : tregister;
  892. i : integer;
  893. QuickRef : boolean;
  894. begin
  895. QuickRef:=false;
  896. if not((Ref.addressmode=AM_UNCHANGED) and
  897. (Ref.symbol=nil) and
  898. ((Ref.base=NR_R28) or
  899. (Ref.base=NR_R29)) and
  900. (Ref.Index=NR_No) and
  901. (Ref.Offset in [0..64-tcgsize2size[fromsize]])) and
  902. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  903. href:=normalize_ref(list,Ref,NR_R30)
  904. else
  905. begin
  906. QuickRef:=true;
  907. href:=Ref;
  908. end;
  909. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  910. internalerror(2011021307);
  911. conv_done:=false;
  912. if tosize<>fromsize then
  913. begin
  914. conv_done:=true;
  915. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  916. fromsize:=tosize;
  917. case fromsize of
  918. OS_8:
  919. begin
  920. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  921. for i:=2 to tcgsize2size[tosize] do
  922. begin
  923. reg:=GetNextReg(reg);
  924. list.concat(taicpu.op_reg(A_CLR,reg));
  925. end;
  926. end;
  927. OS_S8:
  928. begin
  929. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  930. tmpreg:=reg;
  931. if tcgsize2size[tosize]>1 then
  932. begin
  933. reg:=GetNextReg(reg);
  934. list.concat(taicpu.op_reg(A_CLR,reg));
  935. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  936. list.concat(taicpu.op_reg(A_COM,reg));
  937. tmpreg:=reg;
  938. for i:=3 to tcgsize2size[tosize] do
  939. begin
  940. reg:=GetNextReg(reg);
  941. emit_mov(list,reg,tmpreg);
  942. end;
  943. end;
  944. end;
  945. OS_16:
  946. begin
  947. if not(QuickRef) then
  948. href.addressmode:=AM_POSTINCREMENT;
  949. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  950. if QuickRef then
  951. inc(href.offset);
  952. href.addressmode:=AM_UNCHANGED;
  953. reg:=GetNextReg(reg);
  954. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  955. for i:=3 to tcgsize2size[tosize] do
  956. begin
  957. reg:=GetNextReg(reg);
  958. list.concat(taicpu.op_reg(A_CLR,reg));
  959. end;
  960. end;
  961. OS_S16:
  962. begin
  963. if not(QuickRef) then
  964. href.addressmode:=AM_POSTINCREMENT;
  965. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  966. if QuickRef then
  967. inc(href.offset);
  968. href.addressmode:=AM_UNCHANGED;
  969. reg:=GetNextReg(reg);
  970. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  971. tmpreg:=reg;
  972. reg:=GetNextReg(reg);
  973. list.concat(taicpu.op_reg(A_CLR,reg));
  974. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  975. list.concat(taicpu.op_reg(A_COM,reg));
  976. tmpreg:=reg;
  977. for i:=4 to tcgsize2size[tosize] do
  978. begin
  979. reg:=GetNextReg(reg);
  980. emit_mov(list,reg,tmpreg);
  981. end;
  982. end;
  983. else
  984. conv_done:=false;
  985. end;
  986. end;
  987. if not conv_done then
  988. begin
  989. for i:=1 to tcgsize2size[fromsize] do
  990. begin
  991. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  992. href.addressmode:=AM_POSTINCREMENT
  993. else
  994. href.addressmode:=AM_UNCHANGED;
  995. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  996. if QuickRef then
  997. inc(href.offset);
  998. reg:=GetNextReg(reg);
  999. end;
  1000. end;
  1001. if not(QuickRef) then
  1002. begin
  1003. ungetcpuregister(list,href.base);
  1004. ungetcpuregister(list,GetNextReg(href.base));
  1005. end;
  1006. end;
  1007. procedure tcgavr.a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);
  1008. var
  1009. conv_done: boolean;
  1010. tmpreg : tregister;
  1011. i : integer;
  1012. begin
  1013. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  1014. internalerror(2011021310);
  1015. conv_done:=false;
  1016. if tosize<>fromsize then
  1017. begin
  1018. conv_done:=true;
  1019. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  1020. fromsize:=tosize;
  1021. case fromsize of
  1022. OS_8:
  1023. begin
  1024. emit_mov(list,reg2,reg1);
  1025. for i:=2 to tcgsize2size[tosize] do
  1026. begin
  1027. reg2:=GetNextReg(reg2);
  1028. list.concat(taicpu.op_reg(A_CLR,reg2));
  1029. end;
  1030. end;
  1031. OS_S8:
  1032. begin
  1033. emit_mov(list,reg2,reg1);
  1034. if tcgsize2size[tosize]>1 then
  1035. begin
  1036. reg2:=GetNextReg(reg2);
  1037. list.concat(taicpu.op_reg(A_CLR,reg2));
  1038. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  1039. list.concat(taicpu.op_reg(A_COM,reg2));
  1040. tmpreg:=reg2;
  1041. for i:=3 to tcgsize2size[tosize] do
  1042. begin
  1043. reg2:=GetNextReg(reg2);
  1044. emit_mov(list,reg2,tmpreg);
  1045. end;
  1046. end;
  1047. end;
  1048. OS_16:
  1049. begin
  1050. emit_mov(list,reg2,reg1);
  1051. reg1:=GetNextReg(reg1);
  1052. reg2:=GetNextReg(reg2);
  1053. emit_mov(list,reg2,reg1);
  1054. for i:=3 to tcgsize2size[tosize] do
  1055. begin
  1056. reg2:=GetNextReg(reg2);
  1057. list.concat(taicpu.op_reg(A_CLR,reg2));
  1058. end;
  1059. end;
  1060. OS_S16:
  1061. begin
  1062. emit_mov(list,reg2,reg1);
  1063. reg1:=GetNextReg(reg1);
  1064. reg2:=GetNextReg(reg2);
  1065. emit_mov(list,reg2,reg1);
  1066. if tcgsize2size[tosize]>2 then
  1067. begin
  1068. reg2:=GetNextReg(reg2);
  1069. list.concat(taicpu.op_reg(A_CLR,reg2));
  1070. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  1071. list.concat(taicpu.op_reg(A_COM,reg2));
  1072. tmpreg:=reg2;
  1073. for i:=4 to tcgsize2size[tosize] do
  1074. begin
  1075. reg2:=GetNextReg(reg2);
  1076. emit_mov(list,reg2,tmpreg);
  1077. end;
  1078. end;
  1079. end;
  1080. else
  1081. conv_done:=false;
  1082. end;
  1083. end;
  1084. if not conv_done and (reg1<>reg2) then
  1085. begin
  1086. for i:=1 to tcgsize2size[fromsize] do
  1087. begin
  1088. emit_mov(list,reg2,reg1);
  1089. reg1:=GetNextReg(reg1);
  1090. reg2:=GetNextReg(reg2);
  1091. end;
  1092. end;
  1093. end;
  1094. procedure tcgavr.a_loadfpu_reg_reg(list: TAsmList; fromsize,tosize: tcgsize; reg1, reg2: tregister);
  1095. begin
  1096. internalerror(2012010702);
  1097. end;
  1098. procedure tcgavr.a_loadfpu_ref_reg(list: TAsmList; fromsize,tosize: tcgsize; const ref: treference; reg: tregister);
  1099. begin
  1100. internalerror(2012010703);
  1101. end;
  1102. procedure tcgavr.a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference);
  1103. begin
  1104. internalerror(2012010704);
  1105. end;
  1106. { comparison operations }
  1107. procedure tcgavr.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;
  1108. cmp_op : topcmp;a : tcgint;reg : tregister;l : tasmlabel);
  1109. var
  1110. swapped : boolean;
  1111. tmpreg : tregister;
  1112. i : byte;
  1113. begin
  1114. if a=0 then
  1115. begin
  1116. swapped:=false;
  1117. { swap parameters? }
  1118. case cmp_op of
  1119. OC_GT:
  1120. begin
  1121. swapped:=true;
  1122. cmp_op:=OC_LT;
  1123. end;
  1124. OC_LTE:
  1125. begin
  1126. swapped:=true;
  1127. cmp_op:=OC_GTE;
  1128. end;
  1129. OC_BE:
  1130. begin
  1131. swapped:=true;
  1132. cmp_op:=OC_AE;
  1133. end;
  1134. OC_A:
  1135. begin
  1136. swapped:=true;
  1137. cmp_op:=OC_B;
  1138. end;
  1139. end;
  1140. if swapped then
  1141. list.concat(taicpu.op_reg_reg(A_CP,reg,NR_R1))
  1142. else
  1143. list.concat(taicpu.op_reg_reg(A_CP,NR_R1,reg));
  1144. for i:=2 to tcgsize2size[size] do
  1145. begin
  1146. reg:=GetNextReg(reg);
  1147. if swapped then
  1148. list.concat(taicpu.op_reg_reg(A_CPC,reg,NR_R1))
  1149. else
  1150. list.concat(taicpu.op_reg_reg(A_CPC,NR_R1,reg));
  1151. end;
  1152. a_jmp_cond(list,cmp_op,l);
  1153. end
  1154. else
  1155. inherited a_cmp_const_reg_label(list,size,cmp_op,a,reg,l);
  1156. end;
  1157. procedure tcgavr.a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;
  1158. cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
  1159. var
  1160. swapped : boolean;
  1161. tmpreg : tregister;
  1162. i : byte;
  1163. begin
  1164. swapped:=false;
  1165. { swap parameters? }
  1166. case cmp_op of
  1167. OC_GT:
  1168. begin
  1169. swapped:=true;
  1170. cmp_op:=OC_LT;
  1171. end;
  1172. OC_LTE:
  1173. begin
  1174. swapped:=true;
  1175. cmp_op:=OC_GTE;
  1176. end;
  1177. OC_BE:
  1178. begin
  1179. swapped:=true;
  1180. cmp_op:=OC_AE;
  1181. end;
  1182. OC_A:
  1183. begin
  1184. swapped:=true;
  1185. cmp_op:=OC_B;
  1186. end;
  1187. end;
  1188. if swapped then
  1189. begin
  1190. tmpreg:=reg1;
  1191. reg1:=reg2;
  1192. reg2:=tmpreg;
  1193. end;
  1194. list.concat(taicpu.op_reg_reg(A_CP,reg2,reg1));
  1195. for i:=2 to tcgsize2size[size] do
  1196. begin
  1197. reg1:=GetNextReg(reg1);
  1198. reg2:=GetNextReg(reg2);
  1199. list.concat(taicpu.op_reg_reg(A_CPC,reg2,reg1));
  1200. end;
  1201. a_jmp_cond(list,cmp_op,l);
  1202. end;
  1203. procedure tcgavr.a_bit_scan_reg_reg(list: TAsmList; reverse: boolean; size: TCGSize; src, dst: TRegister);
  1204. begin
  1205. Comment(V_Error,'tcgarm.a_bit_scan_reg_reg method not implemented');
  1206. end;
  1207. procedure tcgavr.a_jmp_name(list : TAsmList;const s : string);
  1208. var
  1209. ai : taicpu;
  1210. begin
  1211. ai:=taicpu.op_sym(A_JMP,current_asmdata.RefAsmSymbol(s));
  1212. ai.is_jmp:=true;
  1213. list.concat(ai);
  1214. end;
  1215. procedure tcgavr.a_jmp_always(list : TAsmList;l: tasmlabel);
  1216. var
  1217. ai : taicpu;
  1218. begin
  1219. ai:=taicpu.op_sym(A_JMP,l);
  1220. ai.is_jmp:=true;
  1221. list.concat(ai);
  1222. end;
  1223. procedure tcgavr.a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel);
  1224. var
  1225. ai : taicpu;
  1226. begin
  1227. ai:=setcondition(taicpu.op_sym(A_BRxx,l),flags_to_cond(f));
  1228. ai.is_jmp:=true;
  1229. list.concat(ai);
  1230. end;
  1231. procedure tcgavr.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
  1232. var
  1233. l : TAsmLabel;
  1234. tmpflags : TResFlags;
  1235. begin
  1236. current_asmdata.getjumplabel(l);
  1237. {
  1238. if flags_to_cond(f) then
  1239. begin
  1240. tmpflags:=f;
  1241. inverse_flags(tmpflags);
  1242. list.concat(taicpu.op_reg(A_CLR,reg));
  1243. a_jmp_flags(list,tmpflags,l);
  1244. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1245. end
  1246. else
  1247. }
  1248. begin
  1249. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1250. a_jmp_flags(list,f,l);
  1251. list.concat(taicpu.op_reg(A_CLR,reg));
  1252. end;
  1253. cg.a_label(list,l);
  1254. end;
  1255. procedure tcgavr.a_adjust_sp(list : TAsmList; value : longint);
  1256. var
  1257. i : integer;
  1258. begin
  1259. case value of
  1260. 0:
  1261. ;
  1262. -14..-1:
  1263. begin
  1264. if ((-value) mod 2)<>0 then
  1265. list.concat(taicpu.op_reg(A_PUSH,NR_R0));
  1266. for i:=1 to (-value) div 2 do
  1267. list.concat(taicpu.op_const(A_RCALL,0));
  1268. end;
  1269. 1..7:
  1270. begin
  1271. for i:=1 to value do
  1272. list.concat(taicpu.op_reg(A_POP,NR_R0));
  1273. end;
  1274. else
  1275. begin
  1276. list.concat(taicpu.op_reg_const(A_SUBI,NR_R28,lo(word(-value))));
  1277. list.concat(taicpu.op_reg_const(A_SBCI,NR_R29,hi(word(-value))));
  1278. // get SREG
  1279. list.concat(taicpu.op_reg_const(A_IN,NR_R0,NIO_SREG));
  1280. // block interrupts
  1281. list.concat(taicpu.op_none(A_CLI));
  1282. // write high SP
  1283. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_HI,NR_R29));
  1284. // release interrupts
  1285. list.concat(taicpu.op_const_reg(A_OUT,NIO_SREG,NR_R0));
  1286. // write low SP
  1287. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_LO,NR_R28));
  1288. end;
  1289. end;
  1290. end;
  1291. function tcgavr.GetLoad(const ref: treference) : tasmop;
  1292. begin
  1293. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1294. result:=A_LDS
  1295. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1296. result:=A_LDD
  1297. else
  1298. result:=A_LD;
  1299. end;
  1300. function tcgavr.GetStore(const ref: treference) : tasmop;
  1301. begin
  1302. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1303. result:=A_STS
  1304. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1305. result:=A_STD
  1306. else
  1307. result:=A_ST;
  1308. end;
  1309. procedure tcgavr.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
  1310. var
  1311. regs : tcpuregisterset;
  1312. reg : tsuperregister;
  1313. begin
  1314. if not(nostackframe) then
  1315. begin
  1316. { save int registers }
  1317. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1318. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1319. regs:=regs+[RS_R28,RS_R29];
  1320. for reg:=RS_R31 downto RS_R0 do
  1321. if reg in regs then
  1322. list.concat(taicpu.op_reg(A_PUSH,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1323. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1324. begin
  1325. list.concat(taicpu.op_reg_const(A_IN,NR_R28,NIO_SP_LO));
  1326. list.concat(taicpu.op_reg_const(A_IN,NR_R29,NIO_SP_HI));
  1327. end
  1328. else
  1329. { the framepointer cannot be omitted on avr because sp
  1330. is not a register but part of the i/o map
  1331. }
  1332. internalerror(2011021901);
  1333. a_adjust_sp(list,-localsize);
  1334. end;
  1335. end;
  1336. procedure tcgavr.g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean);
  1337. var
  1338. regs : tcpuregisterset;
  1339. reg : TSuperRegister;
  1340. LocalSize : longint;
  1341. begin
  1342. if not(nostackframe) then
  1343. begin
  1344. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1345. begin
  1346. LocalSize:=current_procinfo.calc_stackframe_size;
  1347. a_adjust_sp(list,LocalSize);
  1348. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1349. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1350. regs:=regs+[RS_R28,RS_R29];
  1351. for reg:=RS_R0 to RS_R31 do
  1352. if reg in regs then
  1353. list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1354. end
  1355. else
  1356. { the framepointer cannot be omitted on avr because sp
  1357. is not a register but part of the i/o map
  1358. }
  1359. internalerror(2011021902);
  1360. end;
  1361. list.concat(taicpu.op_none(A_RET));
  1362. end;
  1363. procedure tcgavr.a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);
  1364. var
  1365. tmpref : treference;
  1366. begin
  1367. if ref.addressmode<>AM_UNCHANGED then
  1368. internalerror(2011021701);
  1369. if assigned(ref.symbol) or (ref.offset<>0) then
  1370. begin
  1371. reference_reset(tmpref,0);
  1372. tmpref.symbol:=ref.symbol;
  1373. tmpref.offset:=ref.offset;
  1374. tmpref.refaddr:=addr_lo8;
  1375. list.concat(taicpu.op_reg_ref(A_LDI,r,tmpref));
  1376. tmpref.refaddr:=addr_hi8;
  1377. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(r),tmpref));
  1378. if (ref.base<>NR_NO) then
  1379. begin
  1380. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.base));
  1381. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.base)));
  1382. end;
  1383. if (ref.index<>NR_NO) then
  1384. begin
  1385. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1386. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1387. end;
  1388. end
  1389. else if (ref.base<>NR_NO)then
  1390. begin
  1391. emit_mov(list,r,ref.base);
  1392. emit_mov(list,GetNextReg(r),GetNextReg(ref.base));
  1393. if (ref.index<>NR_NO) then
  1394. begin
  1395. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1396. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1397. end;
  1398. end
  1399. else if (ref.index<>NR_NO) then
  1400. begin
  1401. emit_mov(list,r,ref.index);
  1402. emit_mov(list,GetNextReg(r),GetNextReg(ref.index));
  1403. end;
  1404. end;
  1405. procedure tcgavr.fixref(list : TAsmList;var ref : treference);
  1406. begin
  1407. internalerror(2011021320);
  1408. end;
  1409. procedure tcgavr.g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  1410. var
  1411. paraloc1,paraloc2,paraloc3 : TCGPara;
  1412. pd : tprocdef;
  1413. begin
  1414. pd:=search_system_proc('MOVE');
  1415. paraloc1.init;
  1416. paraloc2.init;
  1417. paraloc3.init;
  1418. paramanager.getintparaloc(pd,1,paraloc1);
  1419. paramanager.getintparaloc(pd,2,paraloc2);
  1420. paramanager.getintparaloc(pd,3,paraloc3);
  1421. a_load_const_cgpara(list,OS_SINT,len,paraloc3);
  1422. a_loadaddr_ref_cgpara(list,dest,paraloc2);
  1423. a_loadaddr_ref_cgpara(list,source,paraloc1);
  1424. paramanager.freecgpara(list,paraloc3);
  1425. paramanager.freecgpara(list,paraloc2);
  1426. paramanager.freecgpara(list,paraloc1);
  1427. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1428. a_call_name_static(list,'FPC_MOVE');
  1429. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1430. paraloc3.done;
  1431. paraloc2.done;
  1432. paraloc1.done;
  1433. end;
  1434. procedure tcgavr.g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);
  1435. var
  1436. countreg,tmpreg : tregister;
  1437. srcref,dstref : treference;
  1438. copysize,countregsize : tcgsize;
  1439. l : TAsmLabel;
  1440. i : longint;
  1441. SrcQuickRef, DestQuickRef : Boolean;
  1442. begin
  1443. if len>16 then
  1444. begin
  1445. current_asmdata.getjumplabel(l);
  1446. reference_reset(srcref,0);
  1447. reference_reset(dstref,0);
  1448. srcref.base:=NR_R30;
  1449. srcref.addressmode:=AM_POSTINCREMENT;
  1450. dstref.base:=NR_R26;
  1451. dstref.addressmode:=AM_POSTINCREMENT;
  1452. copysize:=OS_8;
  1453. if len<256 then
  1454. countregsize:=OS_8
  1455. else if len<65536 then
  1456. countregsize:=OS_16
  1457. else
  1458. internalerror(2011022007);
  1459. countreg:=getintregister(list,countregsize);
  1460. a_load_const_reg(list,countregsize,len,countreg);
  1461. a_loadaddr_ref_reg(list,source,NR_R30);
  1462. tmpreg:=getaddressregister(list);
  1463. a_loadaddr_ref_reg(list,dest,tmpreg);
  1464. { X is used for spilling code so we can load it
  1465. only by a push/pop sequence, this can be
  1466. optimized later on by the peephole optimizer
  1467. }
  1468. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1469. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1470. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1471. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1472. cg.a_label(list,l);
  1473. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1474. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1475. a_op_const_reg(list,OP_SUB,countregsize,1,countreg);
  1476. a_jmp_flags(list,F_NE,l);
  1477. // keep registers alive
  1478. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  1479. end
  1480. else
  1481. begin
  1482. SrcQuickRef:=false;
  1483. DestQuickRef:=false;
  1484. if not((source.addressmode=AM_UNCHANGED) and
  1485. (source.symbol=nil) and
  1486. ((source.base=NR_R28) or
  1487. (source.base=NR_R29)) and
  1488. (source.Index=NR_NO) and
  1489. (source.Offset in [0..64-len])) and
  1490. not((source.Base=NR_NO) and (source.Index=NR_NO)) then
  1491. srcref:=normalize_ref(list,source,NR_R30)
  1492. else
  1493. begin
  1494. SrcQuickRef:=true;
  1495. srcref:=source;
  1496. end;
  1497. if not((dest.addressmode=AM_UNCHANGED) and
  1498. (dest.symbol=nil) and
  1499. ((dest.base=NR_R28) or
  1500. (dest.base=NR_R29)) and
  1501. (dest.Index=NR_No) and
  1502. (dest.Offset in [0..64-len])) and
  1503. not((dest.Base=NR_NO) and (dest.Index=NR_NO)) then
  1504. begin
  1505. if not(SrcQuickRef) then
  1506. begin
  1507. tmpreg:=getaddressregister(list);
  1508. dstref:=normalize_ref(list,dest,tmpreg);
  1509. { X is used for spilling code so we can load it
  1510. only by a push/pop sequence, this can be
  1511. optimized later on by the peephole optimizer
  1512. }
  1513. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1514. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1515. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1516. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1517. dstref.base:=NR_R26;
  1518. end
  1519. else
  1520. dstref:=normalize_ref(list,dest,NR_R30);
  1521. end
  1522. else
  1523. begin
  1524. DestQuickRef:=true;
  1525. dstref:=dest;
  1526. end;
  1527. for i:=1 to len do
  1528. begin
  1529. if not(SrcQuickRef) and (i<len) then
  1530. srcref.addressmode:=AM_POSTINCREMENT
  1531. else
  1532. srcref.addressmode:=AM_UNCHANGED;
  1533. if not(DestQuickRef) and (i<len) then
  1534. dstref.addressmode:=AM_POSTINCREMENT
  1535. else
  1536. dstref.addressmode:=AM_UNCHANGED;
  1537. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1538. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1539. if SrcQuickRef then
  1540. inc(srcref.offset);
  1541. if DestQuickRef then
  1542. inc(dstref.offset);
  1543. end;
  1544. if not(SrcQuickRef) then
  1545. begin
  1546. ungetcpuregister(list,srcref.base);
  1547. ungetcpuregister(list,GetNextReg(srcref.base));
  1548. end;
  1549. end;
  1550. end;
  1551. procedure tcgavr.g_overflowCheck(list : TAsmList;const l : tlocation;def : tdef);
  1552. var
  1553. hl : tasmlabel;
  1554. ai : taicpu;
  1555. cond : TAsmCond;
  1556. begin
  1557. if not(cs_check_overflow in current_settings.localswitches) then
  1558. exit;
  1559. current_asmdata.getjumplabel(hl);
  1560. if not ((def.typ=pointerdef) or
  1561. ((def.typ=orddef) and
  1562. (torddef(def).ordtype in [u64bit,u16bit,u32bit,u8bit,uchar,
  1563. pasbool8,pasbool16,pasbool32,pasbool64]))) then
  1564. cond:=C_VC
  1565. else
  1566. cond:=C_CC;
  1567. ai:=Taicpu.Op_Sym(A_BRxx,hl);
  1568. ai.SetCondition(cond);
  1569. ai.is_jmp:=true;
  1570. list.concat(ai);
  1571. a_call_name(list,'FPC_OVERFLOW',false);
  1572. a_label(list,hl);
  1573. end;
  1574. procedure tcgavr.g_save_registers(list: TAsmList);
  1575. begin
  1576. { this is done by the entry code }
  1577. end;
  1578. procedure tcgavr.g_restore_registers(list: TAsmList);
  1579. begin
  1580. { this is done by the exit code }
  1581. end;
  1582. procedure tcgavr.a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  1583. var
  1584. ai1,ai2 : taicpu;
  1585. hl : TAsmLabel;
  1586. begin
  1587. ai1:=Taicpu.Op_sym(A_BRxx,l);
  1588. ai1.is_jmp:=true;
  1589. hl:=nil;
  1590. case cond of
  1591. OC_EQ:
  1592. ai1.SetCondition(C_EQ);
  1593. OC_GT:
  1594. begin
  1595. { emulate GT }
  1596. current_asmdata.getjumplabel(hl);
  1597. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1598. ai2.SetCondition(C_EQ);
  1599. ai2.is_jmp:=true;
  1600. list.concat(ai2);
  1601. ai1.SetCondition(C_GE);
  1602. end;
  1603. OC_LT:
  1604. ai1.SetCondition(C_LT);
  1605. OC_GTE:
  1606. ai1.SetCondition(C_GE);
  1607. OC_LTE:
  1608. begin
  1609. { emulate LTE }
  1610. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1611. ai2.SetCondition(C_EQ);
  1612. ai2.is_jmp:=true;
  1613. list.concat(ai2);
  1614. ai1.SetCondition(C_LT);
  1615. end;
  1616. OC_NE:
  1617. ai1.SetCondition(C_NE);
  1618. OC_BE:
  1619. begin
  1620. { emulate BE }
  1621. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1622. ai2.SetCondition(C_EQ);
  1623. ai2.is_jmp:=true;
  1624. list.concat(ai2);
  1625. ai1.SetCondition(C_LO);
  1626. end;
  1627. OC_B:
  1628. ai1.SetCondition(C_LO);
  1629. OC_AE:
  1630. ai1.SetCondition(C_SH);
  1631. OC_A:
  1632. begin
  1633. { emulate A (unsigned GT) }
  1634. current_asmdata.getjumplabel(hl);
  1635. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1636. ai2.SetCondition(C_EQ);
  1637. ai2.is_jmp:=true;
  1638. list.concat(ai2);
  1639. ai1.SetCondition(C_SH);
  1640. end;
  1641. else
  1642. internalerror(2011082501);
  1643. end;
  1644. list.concat(ai1);
  1645. if assigned(hl) then
  1646. a_label(list,hl);
  1647. end;
  1648. procedure tcgavr.g_stackpointer_alloc(list: TAsmList; size: longint);
  1649. begin
  1650. internalerror(201201071);
  1651. end;
  1652. procedure tcgavr.g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);
  1653. begin
  1654. internalerror(2011021324);
  1655. end;
  1656. procedure tcgavr.emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  1657. var
  1658. instr: taicpu;
  1659. begin
  1660. instr:=taicpu.op_reg_reg(A_MOV,reg2,reg1);
  1661. list.Concat(instr);
  1662. { Notify the register allocator that we have written a move instruction so
  1663. it can try to eliminate it. }
  1664. add_move_instruction(instr);
  1665. end;
  1666. procedure tcg64favr.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
  1667. begin
  1668. if not(size in [OS_S64,OS_64]) then
  1669. internalerror(2012102402);
  1670. tcgavr(cg).a_op_reg_reg_internal(list,Op,size,regsrc.reglo,regsrc.reghi,regdst.reglo,regdst.reghi);
  1671. end;
  1672. procedure tcg64favr.a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);
  1673. begin
  1674. tcgavr(cg).a_op_const_reg_internal(list,Op,size,value,reg.reglo,reg.reghi);
  1675. end;
  1676. procedure create_codegen;
  1677. begin
  1678. cg:=tcgavr.create;
  1679. cg64:=tcg64favr.create;
  1680. end;
  1681. end.