cpuinfo.pas 33 KB

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  1. {
  2. Copyright (c) 1998-2002 by the Free Pascal development team
  3. Basic Processor information for the ARM
  4. See the file COPYING.FPC, included in this distribution,
  5. for details about the copyright.
  6. This program is distributed in the hope that it will be useful,
  7. but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  9. **********************************************************************}
  10. Unit CPUInfo;
  11. Interface
  12. uses
  13. globtype;
  14. Type
  15. bestreal = double;
  16. ts32real = single;
  17. ts64real = double;
  18. ts80real = type extended;
  19. ts128real = type extended;
  20. ts64comp = comp;
  21. pbestreal=^bestreal;
  22. { possible supported processors for this target }
  23. tcputype =
  24. (cpu_none,
  25. cpu_armv3,
  26. cpu_armv4,
  27. cpu_armv4t,
  28. cpu_armv5,
  29. cpu_armv5t,
  30. cpu_armv5te,
  31. cpu_armv5tej,
  32. cpu_armv6,
  33. cpu_armv6k,
  34. cpu_armv6t2,
  35. cpu_armv6z,
  36. cpu_armv7,
  37. cpu_armv7a,
  38. cpu_armv7r,
  39. cpu_armv7m,
  40. cpu_armv7em
  41. );
  42. Const
  43. cpu_arm = [cpu_none,cpu_armv3,cpu_armv4,cpu_armv4t,cpu_armv5];
  44. cpu_thumb = [];
  45. cpu_thumb2 = [cpu_armv7m];
  46. Type
  47. tfputype =
  48. (fpu_none,
  49. fpu_soft,
  50. fpu_libgcc,
  51. fpu_fpa,
  52. fpu_fpa10,
  53. fpu_fpa11,
  54. fpu_vfpv2,
  55. fpu_vfpv3,
  56. fpu_vfpv3_d16,
  57. fpu_fpv4_s16
  58. );
  59. tcontrollertype =
  60. (ct_none,
  61. { Phillips }
  62. ct_lpc2114,
  63. ct_lpc2124,
  64. ct_lpc2194,
  65. ct_lpc1754,
  66. ct_lpc1756,
  67. ct_lpc1758,
  68. ct_lpc1764,
  69. ct_lpc1766,
  70. ct_lpc1768,
  71. { ATMEL }
  72. ct_at91sam7s256,
  73. ct_at91sam7se256,
  74. ct_at91sam7x256,
  75. ct_at91sam7xc256,
  76. { STMicroelectronics }
  77. ct_stm32f100x4, // LD&MD value line, 4=16,6=32,8=64,b=128
  78. ct_stm32f100x6,
  79. ct_stm32f100x8,
  80. ct_stm32f100xB,
  81. ct_stm32f100xC, // HD value line, r=512,d=384,c=256
  82. ct_stm32f100xD,
  83. ct_stm32f100xE,
  84. ct_stm32f101x4, // LD Access line, 4=16,6=32
  85. ct_stm32f101x6,
  86. ct_stm32f101x8, // MD Access line, 8=64,B=128
  87. ct_stm32f101xB,
  88. ct_stm32f101xC, // HD Access line, C=256,D=384,E=512
  89. ct_stm32f101xD,
  90. ct_stm32f101xE,
  91. ct_stm32f101xF, // XL Access line, F=768,G=1M
  92. ct_stm32f101xG,
  93. ct_stm32f102x4, // LD usb access line, 4=16,6=32
  94. ct_stm32f102x6,
  95. ct_stm32f102x8, // MD usb access line, 8=64,B=128
  96. ct_stm32f102xB,
  97. ct_stm32f103x4, // LD performance line, 4=16,6=32
  98. ct_stm32f103x6,
  99. ct_stm32f103x8, // MD performance line, 8=64,B=128
  100. ct_stm32f103xB,
  101. ct_stm32f103xC, // HD performance line, C=256,D=384,E=512
  102. ct_stm32f103xD,
  103. ct_stm32f103xE,
  104. ct_stm32f103xF, // XL performance line, F=768,G=1M
  105. ct_stm32f103xG,
  106. ct_stm32f107x8, // MD and HD connectivity line, 8=64,B=128,C=256
  107. ct_stm32f107xB,
  108. ct_stm32f107xC,
  109. { TI - Fury Class - 64 K Flash, 16 K SRAM Devices }
  110. ct_lm3s1110,
  111. ct_lm3s1133,
  112. ct_lm3s1138,
  113. ct_lm3s1150,
  114. ct_lm3s1162,
  115. ct_lm3s1165,
  116. ct_lm3s1166,
  117. ct_lm3s2110,
  118. ct_lm3s2139,
  119. ct_lm3s6100,
  120. ct_lm3s6110,
  121. { TI - Fury Class - 128K Flash, 32K SRAM devices }
  122. ct_lm3s1601,
  123. ct_lm3s1608,
  124. ct_lm3s1620,
  125. ct_lm3s1635,
  126. ct_lm3s1636,
  127. ct_lm3s1637,
  128. ct_lm3s1651,
  129. ct_lm3s2601,
  130. ct_lm3s2608,
  131. ct_lm3s2620,
  132. ct_lm3s2637,
  133. ct_lm3s2651,
  134. ct_lm3s6610,
  135. ct_lm3s6611,
  136. ct_lm3s6618,
  137. ct_lm3s6633,
  138. ct_lm3s6637,
  139. ct_lm3s8630,
  140. { TI - Fury Class - 256K Flash, 64K SRAM devices }
  141. ct_lm3s1911,
  142. ct_lm3s1918,
  143. ct_lm3s1937,
  144. ct_lm3s1958,
  145. ct_lm3s1960,
  146. ct_lm3s1968,
  147. ct_lm3s1969,
  148. ct_lm3s2911,
  149. ct_lm3s2918,
  150. ct_lm3s2919,
  151. ct_lm3s2939,
  152. ct_lm3s2948,
  153. ct_lm3s2950,
  154. ct_lm3s2965,
  155. ct_lm3s6911,
  156. ct_lm3s6918,
  157. ct_lm3s6938,
  158. ct_lm3s6950,
  159. ct_lm3s6952,
  160. ct_lm3s6965,
  161. ct_lm3s8930,
  162. ct_lm3s8933,
  163. ct_lm3s8938,
  164. ct_lm3s8962,
  165. ct_lm3s8970,
  166. ct_lm3s8971,
  167. { TI - Tempest Tempest - 256 K Flash, 64 K SRAM }
  168. ct_lm3s5951,
  169. ct_lm3s5956,
  170. ct_lm3s1b21,
  171. ct_lm3s2b93,
  172. ct_lm3s5b91,
  173. ct_lm3s9b81,
  174. ct_lm3s9b90,
  175. ct_lm3s9b92,
  176. ct_lm3s9b95,
  177. ct_lm3s9b96,
  178. { SAMSUNG }
  179. ct_sc32442b,
  180. // generic Thumb2 target
  181. ct_thumb2bare
  182. );
  183. Const
  184. {# Size of native extended floating point type }
  185. extended_size = 12;
  186. {# Size of a multimedia register }
  187. mmreg_size = 16;
  188. { target cpu string (used by compiler options) }
  189. target_cpu_string = 'arm';
  190. { calling conventions supported by the code generator }
  191. supported_calling_conventions : tproccalloptions = [
  192. pocall_internproc,
  193. pocall_safecall,
  194. pocall_stdcall,
  195. { same as stdcall only different name mangling }
  196. pocall_cdecl,
  197. { same as stdcall only different name mangling }
  198. pocall_cppdecl,
  199. { same as stdcall but floating point numbers are handled like equal sized integers }
  200. pocall_softfloat,
  201. { same as stdcall (requires that all const records are passed by
  202. reference, but that's already done for stdcall) }
  203. pocall_mwpascal,
  204. { used for interrupt handling }
  205. pocall_interrupt
  206. ];
  207. cputypestr : array[tcputype] of string[8] = ('',
  208. 'ARMV3',
  209. 'ARMV4',
  210. 'ARMV4T',
  211. 'ARMV5',
  212. 'ARMV5T',
  213. 'ARMV5TE',
  214. 'ARMV5TEJ',
  215. 'ARMV6',
  216. 'ARMV6K',
  217. 'ARMV6T2',
  218. 'ARMV6Z',
  219. 'ARMV7',
  220. 'ARMV7A',
  221. 'ARMV7R',
  222. 'ARMV7M',
  223. 'ARMV7EM'
  224. );
  225. fputypestr : array[tfputype] of string[9] = ('',
  226. 'SOFT',
  227. 'LIBGCC',
  228. 'FPA',
  229. 'FPA10',
  230. 'FPA11',
  231. 'VFPV2',
  232. 'VFPV3',
  233. 'VFPV3_D16',
  234. 'FPV4_S16'
  235. );
  236. { We know that there are fields after sramsize
  237. but we don't care about this warning }
  238. {$WARN 3177 OFF}
  239. embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
  240. ((
  241. controllertypestr:'';
  242. controllerunitstr:'';
  243. flashbase:0;
  244. flashsize:0;
  245. srambase:0;
  246. sramsize:0
  247. ),
  248. (
  249. controllertypestr:'LPC2114';
  250. controllerunitstr:'LPC21x4';
  251. flashbase:$00000000;
  252. flashsize:$00040000;
  253. srambase:$40000000;
  254. sramsize:$00004000
  255. ),
  256. (
  257. controllertypestr:'LPC2124';
  258. controllerunitstr:'LPC21x4';
  259. flashbase:$00000000;
  260. flashsize:$00040000;
  261. srambase:$40000000;
  262. sramsize:$00004000
  263. ),
  264. (
  265. controllertypestr:'LPC2194';
  266. controllerunitstr:'LPC21x4';
  267. flashbase:$00000000;
  268. flashsize:$00040000;
  269. srambase:$40000000;
  270. sramsize:$00004000
  271. ),
  272. (
  273. controllertypestr:'LPC1754';
  274. controllerunitstr:'LPC1754';
  275. flashbase:$00000000;
  276. flashsize:$00020000;
  277. srambase:$10000000;
  278. sramsize:$00004000
  279. ),
  280. (
  281. controllertypestr:'LPC1756';
  282. controllerunitstr:'LPC1756';
  283. flashbase:$00000000;
  284. flashsize:$00040000;
  285. srambase:$10000000;
  286. sramsize:$00004000
  287. ),
  288. (
  289. controllertypestr:'LPC1758';
  290. controllerunitstr:'LPC1758';
  291. flashbase:$00000000;
  292. flashsize:$00080000;
  293. srambase:$10000000;
  294. sramsize:$00008000
  295. ),
  296. (
  297. controllertypestr:'LPC1764';
  298. controllerunitstr:'LPC1764';
  299. flashbase:$00000000;
  300. flashsize:$00020000;
  301. srambase:$10000000;
  302. sramsize:$00004000
  303. ),
  304. (
  305. controllertypestr:'LPC1766';
  306. controllerunitstr:'LPC1766';
  307. flashbase:$00000000;
  308. flashsize:$00040000;
  309. srambase:$10000000;
  310. sramsize:$00008000
  311. ),
  312. (
  313. controllertypestr:'LPC1768';
  314. controllerunitstr:'LPC1768';
  315. flashbase:$00000000;
  316. flashsize:$00080000;
  317. srambase:$10000000;
  318. sramsize:$00008000
  319. ),
  320. (
  321. controllertypestr:'AT91SAM7S256';
  322. controllerunitstr:'AT91SAM7x256';
  323. flashbase:$00000000;
  324. flashsize:$00040000;
  325. srambase:$00200000;
  326. sramsize:$00010000
  327. ),
  328. (
  329. controllertypestr:'AT91SAM7SE256';
  330. controllerunitstr:'AT91SAM7x256';
  331. flashbase:$00000000;
  332. flashsize:$00040000;
  333. srambase:$00200000;
  334. sramsize:$00010000
  335. ),
  336. (
  337. controllertypestr:'AT91SAM7X256';
  338. controllerunitstr:'AT91SAM7x256';
  339. flashbase:$00000000;
  340. flashsize:$00040000;
  341. srambase:$00200000;
  342. sramsize:$00010000
  343. ),
  344. (
  345. controllertypestr:'AT91SAM7XC256';
  346. controllerunitstr:'AT91SAM7x256';
  347. flashbase:$00000000;
  348. flashsize:$00040000;
  349. srambase:$00200000;
  350. sramsize:$00010000
  351. ),
  352. { STM32F1 series }
  353. (controllertypestr:'STM32F100X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
  354. (controllertypestr:'STM32F100X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001000),
  355. (controllertypestr:'STM32F100X8'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002000),
  356. (controllertypestr:'STM32F100XB'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00002000),
  357. (controllertypestr:'STM32F100XC'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00006000),
  358. (controllertypestr:'STM32F100XD'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$00008000),
  359. (controllertypestr:'STM32F100XE'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00008000),
  360. (controllertypestr:'STM32F101X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
  361. (controllertypestr:'STM32F101X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001800),
  362. (controllertypestr:'STM32F101X8'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002800),
  363. (controllertypestr:'STM32F101XB'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00004000),
  364. (controllertypestr:'STM32F101XC'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00008000),
  365. (controllertypestr:'STM32F101XD'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$0000C000),
  366. (controllertypestr:'STM32F101XE'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$0000C000),
  367. (controllertypestr:'STM32F101XF'; controllerunitstr:'STM32F10X_XL'; flashbase:$08000000; flashsize:$000C0000; srambase:$20000000; sramsize:$00014000),
  368. (controllertypestr:'STM32F101XG'; controllerunitstr:'STM32F10X_XL'; flashbase:$08000000; flashsize:$00100000; srambase:$20000000; sramsize:$00014000),
  369. (controllertypestr:'STM32F102X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
  370. (controllertypestr:'STM32F102X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00001800),
  371. (controllertypestr:'STM32F102X8'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00002800),
  372. (controllertypestr:'STM32F102XB'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00004000),
  373. (controllertypestr:'STM32F103X4'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00004000; srambase:$20000000; sramsize:$00001000),
  374. (controllertypestr:'STM32F103X6'; controllerunitstr:'STM32F10X_LD'; flashbase:$08000000; flashsize:$00008000; srambase:$20000000; sramsize:$00002800),
  375. (controllertypestr:'STM32F103X8'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00005000),
  376. (controllertypestr:'STM32F103XB'; controllerunitstr:'STM32F10X_MD'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00005000),
  377. (controllertypestr:'STM32F103XC'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$0000C000),
  378. (controllertypestr:'STM32F103XD'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00060000; srambase:$20000000; sramsize:$00010000),
  379. (controllertypestr:'STM32F103XE'; controllerunitstr:'STM32F10X_HD'; flashbase:$08000000; flashsize:$00080000; srambase:$20000000; sramsize:$00010000),
  380. (controllertypestr:'STM32F103XF'; controllerunitstr:'STM32F10X_XL'; flashbase:$08000000; flashsize:$000C0000; srambase:$20000000; sramsize:$00018000),
  381. (controllertypestr:'STM32F103XG'; controllerunitstr:'STM32F10X_XL'; flashbase:$08000000; flashsize:$00100000; srambase:$20000000; sramsize:$00018000),
  382. (controllertypestr:'STM32F107X8'; controllerunitstr:'STM32F10X_CONN'; flashbase:$08000000; flashsize:$00010000; srambase:$20000000; sramsize:$00010000),
  383. (controllertypestr:'STM32F107XB'; controllerunitstr:'STM32F10X_CONN'; flashbase:$08000000; flashsize:$00020000; srambase:$20000000; sramsize:$00010000),
  384. (controllertypestr:'STM32F107XC'; controllerunitstr:'STM32F10X_CONN'; flashbase:$08000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
  385. { TI - 64 K Flash, 16 K SRAM Devices }
  386. // ct_lm3s1110,
  387. (
  388. controllertypestr:'LM3S1110';
  389. controllerunitstr:'LM3FURY';
  390. flashbase:$00000000;
  391. flashsize:$00010000;
  392. srambase:$20000000;
  393. sramsize:$00004000
  394. ),
  395. // ct_lm3s1133,
  396. (
  397. controllertypestr:'LM3S1133';
  398. controllerunitstr:'LM3FURY';
  399. flashbase:$00000000;
  400. flashsize:$00010000;
  401. srambase:$20000000;
  402. sramsize:$00004000
  403. ),
  404. // ct_lm3s1138,
  405. (
  406. controllertypestr:'LM3S1138';
  407. controllerunitstr:'LM3FURY';
  408. flashbase:$00000000;
  409. flashsize:$00010000;
  410. srambase:$20000000;
  411. sramsize:$00004000
  412. ),
  413. // ct_lm3s1150,
  414. (
  415. controllertypestr:'LM3S1150';
  416. controllerunitstr:'LM3FURY';
  417. flashbase:$00000000;
  418. flashsize:$00010000;
  419. srambase:$20000000;
  420. sramsize:$00004000
  421. ),
  422. // ct_lm3s1162,
  423. (
  424. controllertypestr:'LM3S1162';
  425. controllerunitstr:'LM3FURY';
  426. flashbase:$00000000;
  427. flashsize:$00010000;
  428. srambase:$20000000;
  429. sramsize:$00004000
  430. ),
  431. // ct_lm3s1165,
  432. (
  433. controllertypestr:'LM3S1165';
  434. controllerunitstr:'LM3FURY';
  435. flashbase:$00000000;
  436. flashsize:$00010000;
  437. srambase:$20000000;
  438. sramsize:$00004000
  439. ),
  440. // ct_lm3s1166,
  441. (
  442. controllertypestr:'LM3S1166';
  443. controllerunitstr:'LM3FURY';
  444. flashbase:$00000000;
  445. flashsize:$00010000;
  446. srambase:$20000000;
  447. sramsize:$00004000
  448. ),
  449. // ct_lm3s2110,
  450. (
  451. controllertypestr:'LM3S2110';
  452. controllerunitstr:'LM3FURY';
  453. flashbase:$00000000;
  454. flashsize:$00010000;
  455. srambase:$20000000;
  456. sramsize:$00004000
  457. ),
  458. // ct_lm3s2139,
  459. (
  460. controllertypestr:'LM3S2139';
  461. controllerunitstr:'LM3FURY';
  462. flashbase:$00000000;
  463. flashsize:$00010000;
  464. srambase:$20000000;
  465. sramsize:$00004000
  466. ),
  467. // ct_lm3s6100,
  468. (
  469. controllertypestr:'LM3S6100';
  470. controllerunitstr:'LM3FURY';
  471. flashbase:$00000000;
  472. flashsize:$00010000;
  473. srambase:$20000000;
  474. sramsize:$00004000
  475. ),
  476. // ct_lm3s6110,
  477. (
  478. controllertypestr:'LM3S6110';
  479. controllerunitstr:'LM3FURY';
  480. flashbase:$00000000;
  481. flashsize:$00010000;
  482. srambase:$20000000;
  483. sramsize:$00004000
  484. ),
  485. { TI - 128K Flash, 32K SRAM devices }
  486. // ct_lm3s1601,
  487. (
  488. controllertypestr:'LM3S1601';
  489. controllerunitstr:'LM3FURY';
  490. flashbase:$00000000;
  491. flashsize:$00020000;
  492. srambase:$20000000;
  493. sramsize:$00008000
  494. ),
  495. // ct_lm3s1608,
  496. (
  497. controllertypestr:'LM3S1608';
  498. controllerunitstr:'LM3FURY';
  499. flashbase:$00000000;
  500. flashsize:$00020000;
  501. srambase:$20000000;
  502. sramsize:$00008000
  503. ),
  504. // ct_lm3s1620,
  505. (
  506. controllertypestr:'LM3S1620';
  507. controllerunitstr:'LM3FURY';
  508. flashbase:$00000000;
  509. flashsize:$00020000;
  510. srambase:$20000000;
  511. sramsize:$00008000
  512. ),
  513. // ct_lm3s1635,
  514. (
  515. controllertypestr:'LM3S1635';
  516. controllerunitstr:'LM3FURY';
  517. flashbase:$00000000;
  518. flashsize:$00020000;
  519. srambase:$20000000;
  520. sramsize:$00008000
  521. ),
  522. // ct_lm3s1636,
  523. (
  524. controllertypestr:'LM3S1636';
  525. controllerunitstr:'LM3FURY';
  526. flashbase:$00000000;
  527. flashsize:$00020000;
  528. srambase:$20000000;
  529. sramsize:$00008000
  530. ),
  531. // ct_lm3s1637,
  532. (
  533. controllertypestr:'LM3S1637';
  534. controllerunitstr:'LM3FURY';
  535. flashbase:$00000000;
  536. flashsize:$00020000;
  537. srambase:$20000000;
  538. sramsize:$00008000
  539. ),
  540. // ct_lm3s1651,
  541. (
  542. controllertypestr:'LM3S1651';
  543. controllerunitstr:'LM3FURY';
  544. flashbase:$00000000;
  545. flashsize:$00020000;
  546. srambase:$20000000;
  547. sramsize:$00008000
  548. ),
  549. // ct_lm3s2601,
  550. (
  551. controllertypestr:'LM3S2601';
  552. controllerunitstr:'LM3FURY';
  553. flashbase:$00000000;
  554. flashsize:$00020000;
  555. srambase:$20000000;
  556. sramsize:$00008000
  557. ),
  558. // ct_lm3s2608,
  559. (
  560. controllertypestr:'LM3S2608';
  561. controllerunitstr:'LM3FURY';
  562. flashbase:$00000000;
  563. flashsize:$00020000;
  564. srambase:$20000000;
  565. sramsize:$00008000
  566. ),
  567. // ct_lm3s2620,
  568. (
  569. controllertypestr:'LM3S2620';
  570. controllerunitstr:'LM3FURY';
  571. flashbase:$00000000;
  572. flashsize:$00020000;
  573. srambase:$20000000;
  574. sramsize:$00008000
  575. ),
  576. // ct_lm3s2637,
  577. (
  578. controllertypestr:'LM3S2637';
  579. controllerunitstr:'LM3FURY';
  580. flashbase:$00000000;
  581. flashsize:$00020000;
  582. srambase:$20000000;
  583. sramsize:$00008000
  584. ),
  585. // ct_lm3s2651,
  586. (
  587. controllertypestr:'LM3S2651';
  588. controllerunitstr:'LM3FURY';
  589. flashbase:$00000000;
  590. flashsize:$00020000;
  591. srambase:$20000000;
  592. sramsize:$00008000
  593. ),
  594. // ct_lm3s6610,
  595. (
  596. controllertypestr:'LM3S6610';
  597. controllerunitstr:'LM3FURY';
  598. flashbase:$00000000;
  599. flashsize:$00020000;
  600. srambase:$20000000;
  601. sramsize:$00008000
  602. ),
  603. // ct_lm3s6611,
  604. (
  605. controllertypestr:'LM3S6611';
  606. controllerunitstr:'LM3FURY';
  607. flashbase:$00000000;
  608. flashsize:$00020000;
  609. srambase:$20000000;
  610. sramsize:$00008000
  611. ),
  612. // ct_lm3s6618,
  613. (
  614. controllertypestr:'LM3S6618';
  615. controllerunitstr:'LM3FURY';
  616. flashbase:$00000000;
  617. flashsize:$00020000;
  618. srambase:$20000000;
  619. sramsize:$00008000
  620. ),
  621. // ct_lm3s6633,
  622. (
  623. controllertypestr:'LM3S6633';
  624. controllerunitstr:'LM3FURY';
  625. flashbase:$00000000;
  626. flashsize:$00020000;
  627. srambase:$20000000;
  628. sramsize:$00008000
  629. ),
  630. // ct_lm3s6637,
  631. (
  632. controllertypestr:'LM3S6637';
  633. controllerunitstr:'LM3FURY';
  634. flashbase:$00000000;
  635. flashsize:$00020000;
  636. srambase:$20000000;
  637. sramsize:$00008000
  638. ),
  639. // ct_lm3s8630,
  640. (
  641. controllertypestr:'LM3S8630';
  642. controllerunitstr:'LM3FURY';
  643. flashbase:$00000000;
  644. flashsize:$00020000;
  645. srambase:$20000000;
  646. sramsize:$00008000
  647. ),
  648. { TI - 256K Flash, 64K SRAM devices }
  649. // ct_lm3s1911,
  650. (
  651. controllertypestr:'LM3S1911';
  652. controllerunitstr:'LM3FURY';
  653. flashbase:$00000000;
  654. flashsize:$00040000;
  655. srambase:$20000000;
  656. sramsize:$00010000
  657. ),
  658. // ct_lm3s1918,
  659. (
  660. controllertypestr:'LM3S1918';
  661. controllerunitstr:'LM3FURY';
  662. flashbase:$00000000;
  663. flashsize:$00040000;
  664. srambase:$20000000;
  665. sramsize:$00010000
  666. ),
  667. // ct_lm3s1937,
  668. (
  669. controllertypestr:'LM3S1937';
  670. controllerunitstr:'LM3FURY';
  671. flashbase:$00000000;
  672. flashsize:$00040000;
  673. srambase:$20000000;
  674. sramsize:$00010000
  675. ),
  676. // ct_lm3s1958,
  677. (
  678. controllertypestr:'LM3S1958';
  679. controllerunitstr:'LM3FURY';
  680. flashbase:$00000000;
  681. flashsize:$00040000;
  682. srambase:$20000000;
  683. sramsize:$00010000
  684. ),
  685. // ct_lm3s1960,
  686. (
  687. controllertypestr:'LM3S1960';
  688. controllerunitstr:'LM3FURY';
  689. flashbase:$00000000;
  690. flashsize:$00040000;
  691. srambase:$20000000;
  692. sramsize:$00010000
  693. ),
  694. // ct_lm3s1968,
  695. (
  696. controllertypestr:'LM3S1968';
  697. controllerunitstr:'LM3FURY';
  698. flashbase:$00000000;
  699. flashsize:$00040000;
  700. srambase:$20000000;
  701. sramsize:$00010000
  702. ),
  703. // ct_lm3s1969,
  704. (
  705. controllertypestr:'LM3S1969';
  706. controllerunitstr:'LM3FURY';
  707. flashbase:$00000000;
  708. flashsize:$00040000;
  709. srambase:$20000000;
  710. sramsize:$00010000
  711. ),
  712. // ct_lm3s2911,
  713. (
  714. controllertypestr:'LM3S2911';
  715. controllerunitstr:'LM3FURY';
  716. flashbase:$00000000;
  717. flashsize:$00040000;
  718. srambase:$20000000;
  719. sramsize:$00010000
  720. ),
  721. // ct_lm3s2918,
  722. (
  723. controllertypestr:'LM3S2918';
  724. controllerunitstr:'LM3FURY';
  725. flashbase:$00000000;
  726. flashsize:$00040000;
  727. srambase:$20000000;
  728. sramsize:$00010000
  729. ),
  730. // ct_lm3s2919,
  731. (
  732. controllertypestr:'LM3S2919';
  733. controllerunitstr:'LM3FURY';
  734. flashbase:$00000000;
  735. flashsize:$00040000;
  736. srambase:$20000000;
  737. sramsize:$00010000
  738. ),
  739. // ct_lm3s2939,
  740. (
  741. controllertypestr:'LM3S2939';
  742. controllerunitstr:'LM3FURY';
  743. flashbase:$00000000;
  744. flashsize:$00040000;
  745. srambase:$20000000;
  746. sramsize:$00010000
  747. ),
  748. // ct_lm3s2948,
  749. (
  750. controllertypestr:'LM3S2948';
  751. controllerunitstr:'LM3FURY';
  752. flashbase:$00000000;
  753. flashsize:$00040000;
  754. srambase:$20000000;
  755. sramsize:$00010000
  756. ),
  757. // ct_lm3s2950,
  758. (
  759. controllertypestr:'LM3S2950';
  760. controllerunitstr:'LM3FURY';
  761. flashbase:$00000000;
  762. flashsize:$00040000;
  763. srambase:$20000000;
  764. sramsize:$00010000
  765. ),
  766. // ct_lm3s2965,
  767. (
  768. controllertypestr:'LM3S2965';
  769. controllerunitstr:'LM3FURY';
  770. flashbase:$00000000;
  771. flashsize:$00040000;
  772. srambase:$20000000;
  773. sramsize:$00010000
  774. ),
  775. // ct_lm3s6911,
  776. (
  777. controllertypestr:'LM3S6911';
  778. controllerunitstr:'LM3FURY';
  779. flashbase:$00000000;
  780. flashsize:$00040000;
  781. srambase:$20000000;
  782. sramsize:$00010000
  783. ),
  784. // ct_lm3s6918,
  785. (
  786. controllertypestr:'LM3S6918';
  787. controllerunitstr:'LM3FURY';
  788. flashbase:$00000000;
  789. flashsize:$00040000;
  790. srambase:$20000000;
  791. sramsize:$00010000
  792. ),
  793. // ct_lm3s6938,
  794. (
  795. controllertypestr:'LM3S6938';
  796. controllerunitstr:'LM3FURY';
  797. flashbase:$00000000;
  798. flashsize:$00040000;
  799. srambase:$20000000;
  800. sramsize:$00010000
  801. ),
  802. // ct_lm3s6950,
  803. (
  804. controllertypestr:'LM3S6950';
  805. controllerunitstr:'LM3FURY';
  806. flashbase:$00000000;
  807. flashsize:$00040000;
  808. srambase:$20000000;
  809. sramsize:$00010000
  810. ),
  811. // ct_lm3s6952,
  812. (
  813. controllertypestr:'LM3S6952';
  814. controllerunitstr:'LM3FURY';
  815. flashbase:$00000000;
  816. flashsize:$00040000;
  817. srambase:$20000000;
  818. sramsize:$00010000
  819. ),
  820. // ct_lm3s6965,
  821. (
  822. controllertypestr:'LM3S6965';
  823. controllerunitstr:'LM3FURY';
  824. flashbase:$00000000;
  825. flashsize:$00040000;
  826. srambase:$20000000;
  827. sramsize:$00010000
  828. ),
  829. // ct_lm3s8930,
  830. (
  831. controllertypestr:'LM3S8930';
  832. controllerunitstr:'LM3FURY';
  833. flashbase:$00000000;
  834. flashsize:$00040000;
  835. srambase:$20000000;
  836. sramsize:$00010000
  837. ),
  838. // ct_lm3s8933,
  839. (
  840. controllertypestr:'LM3S8933';
  841. controllerunitstr:'LM3FURY';
  842. flashbase:$00000000;
  843. flashsize:$00040000;
  844. srambase:$20000000;
  845. sramsize:$00010000
  846. ),
  847. // ct_lm3s8938,
  848. (
  849. controllertypestr:'LM3S8938';
  850. controllerunitstr:'LM3FURY';
  851. flashbase:$00000000;
  852. flashsize:$00040000;
  853. srambase:$20000000;
  854. sramsize:$00010000
  855. ),
  856. // ct_lm3s8962,
  857. (
  858. controllertypestr:'LM3S8962';
  859. controllerunitstr:'LM3FURY';
  860. flashbase:$00000000;
  861. flashsize:$00040000;
  862. srambase:$20000000;
  863. sramsize:$00010000
  864. ),
  865. // ct_lm3s8970,
  866. (
  867. controllertypestr:'LM3S8970';
  868. controllerunitstr:'LM3FURY';
  869. flashbase:$00000000;
  870. flashsize:$00040000;
  871. srambase:$20000000;
  872. sramsize:$00010000
  873. ),
  874. // ct_lm3s8971,
  875. (
  876. controllertypestr:'LM3S8971';
  877. controllerunitstr:'LM3FURY';
  878. flashbase:$00000000;
  879. flashsize:$00040000;
  880. srambase:$20000000;
  881. sramsize:$00010000
  882. ),
  883. { TI - Tempest parts - 256 K Flash, 64 K SRAM }
  884. // ct_lm3s5951,
  885. (
  886. controllertypestr:'LM3S5951';
  887. controllerunitstr:'LM3TEMPEST';
  888. flashbase:$00000000;
  889. flashsize:$00040000;
  890. srambase:$20000000;
  891. sramsize:$00010000
  892. ),
  893. // ct_lm3s5956,
  894. (
  895. controllertypestr:'LM3S5956';
  896. controllerunitstr:'LM3TEMPEST';
  897. flashbase:$00000000;
  898. flashsize:$00040000;
  899. srambase:$20000000;
  900. sramsize:$00010000
  901. ),
  902. // ct_lm3s1b21,
  903. (
  904. controllertypestr:'LM3S1B21';
  905. controllerunitstr:'LM3TEMPEST';
  906. flashbase:$00000000;
  907. flashsize:$00040000;
  908. srambase:$20000000;
  909. sramsize:$00010000
  910. ),
  911. // ct_lm3s2b93,
  912. (
  913. controllertypestr:'LM3S2B93';
  914. controllerunitstr:'LM3TEMPEST';
  915. flashbase:$00000000;
  916. flashsize:$00040000;
  917. srambase:$20000000;
  918. sramsize:$00010000
  919. ),
  920. // ct_lm3s5b91,
  921. (
  922. controllertypestr:'LM3S5B91';
  923. controllerunitstr:'LM3TEMPEST';
  924. flashbase:$00000000;
  925. flashsize:$00040000;
  926. srambase:$20000000;
  927. sramsize:$00010000
  928. ),
  929. // ct_lm3s9b81,
  930. (
  931. controllertypestr:'LM3S9B81';
  932. controllerunitstr:'LM3TEMPEST';
  933. flashbase:$00000000;
  934. flashsize:$00040000;
  935. srambase:$20000000;
  936. sramsize:$00010000
  937. ),
  938. // ct_lm3s9b90,
  939. (
  940. controllertypestr:'LM3S9B90';
  941. controllerunitstr:'LM3TEMPEST';
  942. flashbase:$00000000;
  943. flashsize:$00040000;
  944. srambase:$20000000;
  945. sramsize:$00010000
  946. ),
  947. // ct_lm3s9b92,
  948. (
  949. controllertypestr:'LM3S9B92';
  950. controllerunitstr:'LM3TEMPEST';
  951. flashbase:$00000000;
  952. flashsize:$00040000;
  953. srambase:$20000000;
  954. sramsize:$00010000
  955. ),
  956. // ct_lm3s9b95,
  957. (
  958. controllertypestr:'LM3S9B95';
  959. controllerunitstr:'LM3TEMPEST';
  960. flashbase:$00000000;
  961. flashsize:$00040000;
  962. srambase:$20000000;
  963. sramsize:$00010000
  964. ),
  965. // ct_lm3s9b96,
  966. (
  967. controllertypestr:'LM3S9B96';
  968. controllerunitstr:'LM3TEMPEST';
  969. flashbase:$00000000;
  970. flashsize:$00040000;
  971. srambase:$20000000;
  972. sramsize:$00010000
  973. ),
  974. //ct_SC32442b,
  975. (
  976. controllertypestr:'SC32442B';
  977. controllerunitstr:'sc32442b';
  978. flashbase:$00000000;
  979. flashsize:$00000000;
  980. srambase:$00000000;
  981. sramsize:$08000000
  982. ),
  983. // bare bones Thumb2
  984. (
  985. controllertypestr:'THUMB2_BARE';
  986. controllerunitstr:'THUMB2_BARE';
  987. flashbase:$00000000;
  988. flashsize:$00100000;
  989. srambase:$20000000;
  990. sramsize:$00100000
  991. )
  992. );
  993. vfp_scalar = [fpu_vfpv2,fpu_vfpv3,fpu_vfpv3_d16,fpu_fpv4_s16];
  994. { Supported optimizations, only used for information }
  995. supported_optimizerswitches = genericlevel1optimizerswitches+
  996. genericlevel2optimizerswitches+
  997. genericlevel3optimizerswitches-
  998. { no need to write info about those }
  999. [cs_opt_level1,cs_opt_level2,cs_opt_level3]+
  1000. [cs_opt_regvar,cs_opt_loopunroll,cs_opt_tailrecursion,
  1001. cs_opt_stackframe,cs_opt_nodecse,cs_opt_reorder_fields,cs_opt_fastmath];
  1002. level1optimizerswitches = genericlevel1optimizerswitches;
  1003. level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
  1004. [cs_opt_regvar,cs_opt_stackframe,cs_opt_tailrecursion,cs_opt_nodecse];
  1005. level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [cs_opt_scheduler{,cs_opt_loopunroll}];
  1006. level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
  1007. type
  1008. tcpuflags =
  1009. (CPUARM_HAS_BX, { CPU supports the BX instruction }
  1010. CPUARM_HAS_BLX, { CPU supports the BLX rX instruction }
  1011. CPUARM_HAS_BLX_LABEL, { CPU supports the BLX <label> instruction }
  1012. CPUARM_HAS_CLZ, { CPU supports the CLZ instruction }
  1013. CPUARM_HAS_EDSP, { CPU supports the PLD,STRD,LDRD,MCRR and MRRC instructions }
  1014. CPUARM_HAS_REV, { CPU supports the REV instruction }
  1015. CPUARM_HAS_RBIT, { CPU supports the RBIT instruction }
  1016. CPUARM_HAS_LDREX,
  1017. CPUARM_HAS_IDIV
  1018. );
  1019. const
  1020. cpu_capabilities : array[tcputype] of set of tcpuflags =
  1021. ( { cpu_none } [],
  1022. { cpu_armv3 } [],
  1023. { cpu_armv4 } [],
  1024. { cpu_armv4t } [CPUARM_HAS_BX],
  1025. { cpu_armv5 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ],
  1026. { cpu_armv5t } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ],
  1027. { cpu_armv5te } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP],
  1028. { cpu_armv5tej } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP],
  1029. { cpu_armv6 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  1030. { cpu_armv6k } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  1031. { cpu_armv6t2 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX],
  1032. { cpu_armv6z } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_LDREX],
  1033. { the identifier armv7 is should not be used, it is considered being equal to armv7a }
  1034. { cpu_armv7 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX],
  1035. { cpu_armv7a } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX],
  1036. { cpu_armv7r } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX],
  1037. { cpu_armv7m } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV],
  1038. { cpu_armv7em } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV]
  1039. );
  1040. Implementation
  1041. end.