popt386.pas 99 KB

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  1. {
  2. $Id$
  3. Copyright (c) 1998-2000 by Florian Klaempfl and Jonas Maebe
  4. This unit contains the peephole optimizer.
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. Unit POpt386;
  19. {$i defines.inc}
  20. Interface
  21. Uses Aasm;
  22. Procedure PeepHoleOptPass1(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  23. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  24. Implementation
  25. Uses
  26. globtype,systems,
  27. globals,verbose,hcodegen,
  28. {$ifdef finaldestdebug}
  29. cobjects,
  30. {$endif finaldestdebug}
  31. cpubase,cpuasm,DAOpt386,tgeni386;
  32. Function RegUsedAfterInstruction(Reg: TRegister; p: Pai; Var UsedRegs: TRegSet): Boolean;
  33. Begin
  34. reg := reg32(reg);
  35. UpdateUsedRegs(UsedRegs, Pai(p^.Next));
  36. RegUsedAfterInstruction :=
  37. (Reg in UsedRegs) and
  38. (not(getNextInstruction(p,p)) or
  39. not(regLoadedWithNewValue(reg,false,p)));
  40. End;
  41. function doFpuLoadStoreOpt(asmL: paasmoutput; var p: pai): boolean;
  42. { returns true if a "continue" should be done after this optimization }
  43. var hp1, hp2: pai;
  44. begin
  45. doFpuLoadStoreOpt := false;
  46. if (paicpu(p)^.oper[0].typ = top_ref) and
  47. getNextInstruction(p, hp1) and
  48. (hp1^.typ = ait_instruction) and
  49. (((paicpu(hp1)^.opcode = A_FLD) and
  50. (paicpu(p)^.opcode = A_FSTP)) or
  51. ((paicpu(p)^.opcode = A_FISTP) and
  52. (paicpu(hp1)^.opcode = A_FILD))) and
  53. (paicpu(hp1)^.oper[0].typ = top_ref) and
  54. (paicpu(hp1)^.opsize = Paicpu(p)^.opsize) and
  55. refsEqual(paicpu(p)^.oper[0].ref^, paicpu(hp1)^.oper[0].ref^) then
  56. begin
  57. if getNextInstruction(hp1, hp2) and
  58. (hp2^.typ = ait_instruction) and
  59. ((paicpu(hp2)^.opcode = A_LEAVE) or
  60. (paicpu(hp2)^.opcode = A_RET)) and
  61. (paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) and
  62. (paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) and
  63. (paicpu(p)^.oper[0].ref^.Index = R_NO) then
  64. begin
  65. asmL^.remove(p);
  66. asmL^.remove(hp1);
  67. dispose(p, done);
  68. dispose(hp1, done);
  69. p := hp2;
  70. removeLastDeallocForFuncRes(asmL, p);
  71. doFPULoadStoreOpt := true;
  72. end
  73. else
  74. { fst can't store an extended value! }
  75. if (paicpu(p)^.opsize <> S_FX) and
  76. (paicpu(p)^.opsize <> S_IQ) then
  77. begin
  78. if (paicpu(p)^.opcode = A_FSTP) then
  79. paicpu(p)^.opcode := A_FST
  80. else Paicpu(p)^.opcode := A_FIST;
  81. asmL^.remove(hp1);
  82. dispose(hp1, done)
  83. end
  84. end;
  85. end;
  86. Procedure PeepHoleOptPass1(Asml: PAasmOutput; BlockStart, BlockEnd: Pai);
  87. {First pass of peepholeoptimizations}
  88. Var
  89. l,l1 : longint;
  90. p,hp1,hp2 : pai;
  91. hp3,hp4: pai;
  92. TmpRef: TReference;
  93. UsedRegs, TmpUsedRegs: TRegSet;
  94. TmpBool1, TmpBool2: Boolean;
  95. Function SkipLabels(hp: Pai; var hp2: pai): boolean;
  96. {skips all labels and returns the next "real" instruction}
  97. Begin
  98. While assigned(hp^.next) and
  99. (pai(hp^.next)^.typ In SkipInstr + [ait_label,ait_align]) Do
  100. hp := pai(hp^.next);
  101. If assigned(hp^.next) Then
  102. Begin
  103. SkipLabels := True;
  104. hp2 := pai(hp^.next)
  105. End
  106. Else
  107. Begin
  108. hp2 := hp;
  109. SkipLabels := False
  110. End;
  111. End;
  112. Procedure GetFinalDestination(AsmL: PAAsmOutput; hp: paicpu);
  113. {traces sucessive jumps to their final destination and sets it, e.g.
  114. je l1 je l3
  115. <code> <code>
  116. l1: becomes l1:
  117. je l2 je l3
  118. <code> <code>
  119. l2: l2:
  120. jmp l3 jmp l3}
  121. Var p1, p2: pai;
  122. l: pasmlabel;
  123. Function FindAnyLabel(hp: pai; var l: pasmlabel): Boolean;
  124. Begin
  125. FindAnyLabel := false;
  126. While assigned(hp^.next) and
  127. (pai(hp^.next)^.typ In (SkipInstr+[ait_align])) Do
  128. hp := pai(hp^.next);
  129. If assigned(hp^.next) and
  130. (pai(hp^.next)^.typ = ait_label) Then
  131. Begin
  132. FindAnyLabel := true;
  133. l := pai_label(hp^.next)^.l;
  134. End
  135. End;
  136. Begin
  137. If (pasmlabel(hp^.oper[0].sym)^.labelnr >= LoLab) and
  138. (pasmlabel(hp^.oper[0].sym)^.labelnr <= HiLab) and {range check, a jump can go past an assembler block!}
  139. Assigned(LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj) Then
  140. Begin
  141. p1 := LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj; {the jump's destination}
  142. SkipLabels(p1,p1);
  143. If (pai(p1)^.typ = ait_instruction) and
  144. (paicpu(p1)^.is_jmp) Then
  145. If { the next instruction after the label where the jump hp arrives}
  146. { is unconditional or of the same type as hp, so continue }
  147. (paicpu(p1)^.condition in [C_None,hp^.condition]) or
  148. { the next instruction after the label where the jump hp arrives}
  149. { is the opposite of hp (so this one is never taken), but after }
  150. { that one there is a branch that will be taken, so perform a }
  151. { little hack: set p1 equal to this instruction (that's what the}
  152. { last SkipLabels is for, only works with short bool evaluation)}
  153. ((paicpu(p1)^.condition = inverse_cond[hp^.condition]) and
  154. SkipLabels(p1,p2) and
  155. (p2^.typ = ait_instruction) and
  156. (paicpu(p2)^.is_jmp) and
  157. (paicpu(p2)^.condition in [C_None,hp^.condition]) and
  158. SkipLabels(p1,p1)) Then
  159. Begin
  160. GetFinalDestination(asml, paicpu(p1));
  161. Dec(pasmlabel(hp^.oper[0].sym)^.refs);
  162. hp^.oper[0].sym:=paicpu(p1)^.oper[0].sym;
  163. inc(pasmlabel(hp^.oper[0].sym)^.refs);
  164. End
  165. Else
  166. If (paicpu(p1)^.condition = inverse_cond[hp^.condition]) then
  167. if not FindAnyLabel(p1,l) then
  168. begin
  169. {$ifdef finaldestdebug}
  170. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  171. strpnew('previous label inserted'))));
  172. {$endif finaldestdebug}
  173. getlabel(l);
  174. insertllitem(asml,p1,p1^.next,new(pai_label,init(l)));
  175. dec(pasmlabel(paicpu(hp)^.oper[0].sym)^.refs);
  176. hp^.oper[0].sym := l;
  177. inc(l^.refs);
  178. { this won't work, since the new label isn't in the labeltable }
  179. { so it will fail the rangecheck. Labeltable should become a }
  180. { hashtable to support this: }
  181. { GetFinalDestination(asml, hp); }
  182. end
  183. else
  184. begin
  185. {$ifdef finaldestdebug}
  186. insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
  187. strpnew('next label reused'))));
  188. {$endif finaldestdebug}
  189. inc(l^.refs);
  190. hp^.oper[0].sym := l;
  191. GetFinalDestination(asml, hp);
  192. end;
  193. End;
  194. End;
  195. Function DoSubAddOpt(var p: Pai): Boolean;
  196. Begin
  197. DoSubAddOpt := False;
  198. If GetLastInstruction(p, hp1) And
  199. (hp1^.typ = ait_instruction) And
  200. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) then
  201. Case Paicpu(hp1)^.opcode Of
  202. A_DEC:
  203. If (Paicpu(hp1)^.oper[0].typ = top_reg) And
  204. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) Then
  205. Begin
  206. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+1);
  207. AsmL^.Remove(hp1);
  208. Dispose(hp1, Done)
  209. End;
  210. A_SUB:
  211. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  212. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  213. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  214. Begin
  215. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+Paicpu(hp1)^.oper[0].val);
  216. AsmL^.Remove(hp1);
  217. Dispose(hp1, Done)
  218. End;
  219. A_ADD:
  220. If (Paicpu(hp1)^.oper[0].typ = top_const) And
  221. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  222. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  223. Begin
  224. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  225. AsmL^.Remove(hp1);
  226. Dispose(hp1, Done);
  227. If (Paicpu(p)^.oper[0].val = 0) Then
  228. Begin
  229. hp1 := Pai(p^.next);
  230. AsmL^.Remove(p);
  231. Dispose(p, Done);
  232. If Not GetLastInstruction(hp1, p) Then
  233. p := hp1;
  234. DoSubAddOpt := True;
  235. End
  236. End;
  237. End;
  238. End;
  239. Begin
  240. P := BlockStart;
  241. UsedRegs := [];
  242. While (P <> BlockEnd) Do
  243. Begin
  244. UpDateUsedRegs(UsedRegs, Pai(p^.next));
  245. Case P^.Typ Of
  246. ait_instruction:
  247. Begin
  248. { Handle Jmp Optimizations }
  249. if Paicpu(p)^.is_jmp then
  250. begin
  251. {the following if-block removes all code between a jmp and the next label,
  252. because it can never be executed}
  253. If (paicpu(p)^.opcode = A_JMP) Then
  254. Begin
  255. While GetNextInstruction(p, hp1) and
  256. ((hp1^.typ <> ait_label) or
  257. { skip unused labels, they're not referenced anywhere }
  258. labelCanBeSkipped(pai_label(hp1))) Do
  259. If not(hp1^.typ in ([ait_label,ait_align]+skipinstr)) Then
  260. Begin
  261. AsmL^.Remove(hp1);
  262. Dispose(hp1, done);
  263. End
  264. else break;
  265. End;
  266. If GetNextInstruction(p, hp1) then
  267. Begin
  268. if FindLabel(pasmlabel(paicpu(p)^.oper[0].sym), hp1) then
  269. Begin
  270. hp2:=pai(hp1^.next);
  271. asml^.remove(p);
  272. dispose(p,done);
  273. p:=hp2;
  274. continue;
  275. end
  276. Else
  277. Begin
  278. if hp1^.typ = ait_label then
  279. SkipLabels(hp1,hp1);
  280. If (pai(hp1)^.typ=ait_instruction) and
  281. (paicpu(hp1)^.opcode=A_JMP) and
  282. GetNextInstruction(hp1, hp2) And
  283. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym), hp2)
  284. Then
  285. Begin
  286. if paicpu(p)^.opcode=A_Jcc then
  287. paicpu(p)^.condition:=inverse_cond[paicpu(p)^.condition]
  288. else
  289. begin
  290. If (LabDif <> 0) Then
  291. GetFinalDestination(asml, paicpu(p));
  292. p:=pai(p^.next);
  293. continue;
  294. end;
  295. Dec(pai_label(hp2)^.l^.refs);
  296. paicpu(p)^.oper[0].sym:=paicpu(hp1)^.oper[0].sym;
  297. Inc(paicpu(p)^.oper[0].sym^.refs);
  298. asml^.remove(hp1);
  299. dispose(hp1,done);
  300. If (LabDif <> 0) Then
  301. GetFinalDestination(asml, paicpu(p));
  302. end
  303. else
  304. If (LabDif <> 0) Then
  305. GetFinalDestination(asml, paicpu(p));
  306. end;
  307. end;
  308. end
  309. else
  310. { All other optimizes }
  311. begin
  312. For l := 0 to 2 Do
  313. If (Paicpu(p)^.oper[l].typ = top_ref) Then
  314. With Paicpu(p)^.oper[l].ref^ Do
  315. Begin
  316. If (base = R_NO) And
  317. (index <> R_NO) And
  318. (scalefactor in [0,1])
  319. Then
  320. Begin
  321. base := index;
  322. index := R_NO
  323. End
  324. End;
  325. Case Paicpu(p)^.opcode Of
  326. A_AND:
  327. Begin
  328. If (Paicpu(p)^.oper[0].typ = top_const) And
  329. (Paicpu(p)^.oper[1].typ = top_reg) And
  330. GetNextInstruction(p, hp1) And
  331. (Pai(hp1)^.typ = ait_instruction) And
  332. (Paicpu(hp1)^.opcode = A_AND) And
  333. (Paicpu(hp1)^.oper[0].typ = top_const) And
  334. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  335. (Paicpu(hp1)^.oper[1].reg = Paicpu(hp1)^.oper[1].reg)
  336. Then
  337. {change "and const1, reg; and const2, reg" to "and (const1 and const2), reg"}
  338. Begin
  339. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val And Paicpu(hp1)^.oper[0].val);
  340. AsmL^.Remove(hp1);
  341. Dispose(hp1, Done)
  342. End
  343. Else
  344. {change "and x, reg; jxx" to "test x, reg", if reg is deallocated before the
  345. jump, but only if it's a conditional jump (PFV) }
  346. If (Paicpu(p)^.oper[1].typ = top_reg) And
  347. GetNextInstruction(p, hp1) And
  348. (hp1^.typ = ait_instruction) And
  349. (Paicpu(hp1)^.is_jmp) and
  350. (Paicpu(hp1)^.opcode<>A_JMP) and
  351. Not(Paicpu(p)^.oper[1].reg in UsedRegs) Then
  352. Paicpu(p)^.opcode := A_TEST;
  353. End;
  354. A_CMP:
  355. Begin
  356. If (Paicpu(p)^.oper[0].typ = top_const) And
  357. (Paicpu(p)^.oper[1].typ in [top_reg,top_ref]) And
  358. (Paicpu(p)^.oper[0].val = 0) Then
  359. If GetNextInstruction(p, hp1) And
  360. (hp1^.typ = ait_instruction) And
  361. (Paicpu(hp1)^.is_jmp) and
  362. (paicpu(hp1)^.opcode=A_Jcc) and
  363. (paicpu(hp1)^.condition in [C_LE,C_BE]) and
  364. GetNextInstruction(hp1,hp2) and
  365. (hp2^.typ = ait_instruction) and
  366. (Paicpu(hp2)^.opcode = A_DEC) And
  367. OpsEqual(Paicpu(hp2)^.oper[0],Paicpu(p)^.oper[1]) And
  368. GetNextInstruction(hp2, hp3) And
  369. (hp3^.typ = ait_instruction) and
  370. (Paicpu(hp3)^.is_jmp) and
  371. (Paicpu(hp3)^.opcode = A_JMP) And
  372. GetNextInstruction(hp3, hp4) And
  373. FindLabel(PAsmLabel(paicpu(hp1)^.oper[0].sym),hp4)
  374. Then
  375. Begin
  376. Paicpu(hp2)^.Opcode := A_SUB;
  377. Paicpu(hp2)^.Loadoper(1,Paicpu(hp2)^.oper[0]);
  378. Paicpu(hp2)^.LoadConst(0,1);
  379. Paicpu(hp2)^.ops:=2;
  380. Paicpu(hp3)^.Opcode := A_Jcc;
  381. Case paicpu(hp1)^.condition of
  382. C_LE: Paicpu(hp3)^.condition := C_GE;
  383. C_BE: Paicpu(hp3)^.condition := C_AE;
  384. End;
  385. AsmL^.Remove(p);
  386. AsmL^.Remove(hp1);
  387. Dispose(p, Done);
  388. Dispose(hp1, Done);
  389. p := hp2;
  390. continue;
  391. End
  392. Else
  393. {change "cmp $0, %reg" to "test %reg, %reg"}
  394. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  395. Begin
  396. Paicpu(p)^.opcode := A_TEST;
  397. Paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  398. End;
  399. End;
  400. A_FLD:
  401. Begin
  402. If (Paicpu(p)^.oper[0].typ = top_reg) And
  403. GetNextInstruction(p, hp1) And
  404. (hp1^.typ = Ait_Instruction) And
  405. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  406. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  407. (Paicpu(hp1)^.oper[0].reg = R_ST) And
  408. (Paicpu(hp1)^.oper[1].reg = R_ST1) Then
  409. { change to
  410. fld reg fxxx reg,st
  411. fxxxp st, st1 (hp1)
  412. Remark: non commutative operations must be reversed!
  413. }
  414. begin
  415. Case Paicpu(hp1)^.opcode Of
  416. A_FMULP,A_FADDP,
  417. A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  418. begin
  419. Case Paicpu(hp1)^.opcode Of
  420. A_FADDP: Paicpu(hp1)^.opcode := A_FADD;
  421. A_FMULP: Paicpu(hp1)^.opcode := A_FMUL;
  422. A_FSUBP: Paicpu(hp1)^.opcode := A_FSUBR;
  423. A_FSUBRP: Paicpu(hp1)^.opcode := A_FSUB;
  424. A_FDIVP: Paicpu(hp1)^.opcode := A_FDIVR;
  425. A_FDIVRP: Paicpu(hp1)^.opcode := A_FDIV;
  426. End;
  427. Paicpu(hp1)^.oper[0].reg := Paicpu(p)^.oper[0].reg;
  428. Paicpu(hp1)^.oper[1].reg := R_ST;
  429. AsmL^.Remove(p);
  430. Dispose(p, Done);
  431. p := hp1;
  432. Continue;
  433. end;
  434. end;
  435. end
  436. else
  437. If (Paicpu(p)^.oper[0].typ = top_ref) And
  438. GetNextInstruction(p, hp2) And
  439. (hp2^.typ = Ait_Instruction) And
  440. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  441. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  442. (Paicpu(p)^.opsize in [S_FS, S_FL]) And
  443. (Paicpu(hp2)^.oper[0].reg = R_ST) And
  444. (Paicpu(hp2)^.oper[1].reg = R_ST1) Then
  445. If GetLastInstruction(p, hp1) And
  446. (hp1^.typ = Ait_Instruction) And
  447. ((Paicpu(hp1)^.opcode = A_FLD) Or
  448. (Paicpu(hp1)^.opcode = A_FST)) And
  449. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  450. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  451. RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^) Then
  452. If ((Paicpu(hp2)^.opcode = A_FMULP) Or
  453. (Paicpu(hp2)^.opcode = A_FADDP)) Then
  454. { change to
  455. fld/fst mem1 (hp1) fld/fst mem1
  456. fld mem1 (p) fadd/
  457. faddp/ fmul st, st
  458. fmulp st, st1 (hp2) }
  459. Begin
  460. AsmL^.Remove(p);
  461. Dispose(p, Done);
  462. p := hp1;
  463. If (Paicpu(hp2)^.opcode = A_FADDP) Then
  464. Paicpu(hp2)^.opcode := A_FADD
  465. Else
  466. Paicpu(hp2)^.opcode := A_FMUL;
  467. Paicpu(hp2)^.oper[1].reg := R_ST;
  468. End
  469. Else
  470. { change to
  471. fld/fst mem1 (hp1) fld/fst mem1
  472. fld mem1 (p) fld st}
  473. Begin
  474. Paicpu(p)^.changeopsize(S_FL);
  475. Paicpu(p)^.loadreg(0,R_ST);
  476. End
  477. Else
  478. Begin
  479. Case Paicpu(hp2)^.opcode Of
  480. A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  481. { change to
  482. fld/fst mem1 (hp1) fld/fst mem1
  483. fld mem2 (p) fxxx mem2
  484. fxxxp st, st1 (hp2) }
  485. Begin
  486. Case Paicpu(hp2)^.opcode Of
  487. A_FADDP: Paicpu(p)^.opcode := A_FADD;
  488. A_FMULP: Paicpu(p)^.opcode := A_FMUL;
  489. A_FSUBP: Paicpu(p)^.opcode := A_FSUBR;
  490. A_FSUBRP: Paicpu(p)^.opcode := A_FSUB;
  491. A_FDIVP: Paicpu(p)^.opcode := A_FDIVR;
  492. A_FDIVRP: Paicpu(p)^.opcode := A_FDIV;
  493. End;
  494. AsmL^.Remove(hp2);
  495. Dispose(hp2, Done)
  496. End
  497. End
  498. End
  499. End;
  500. A_FSTP,A_FISTP:
  501. if doFpuLoadStoreOpt(asmL,p) then
  502. continue;
  503. A_IMUL:
  504. {changes certain "imul const, %reg"'s to lea sequences}
  505. Begin
  506. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  507. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  508. (Paicpu(p)^.opsize = S_L) Then
  509. If (Paicpu(p)^.oper[0].val = 1) Then
  510. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  511. {remove "imul $1, reg"}
  512. Begin
  513. hp1 := Pai(p^.Next);
  514. AsmL^.Remove(p);
  515. Dispose(p, Done);
  516. p := hp1;
  517. Continue;
  518. End
  519. Else
  520. {change "imul $1, reg1, reg2" to "mov reg1, reg2"}
  521. Begin
  522. hp1 := New(Paicpu, Op_Reg_Reg(A_MOV, S_L, Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[2].reg));
  523. InsertLLItem(AsmL, p^.previous, p^.next, hp1);
  524. Dispose(p, Done);
  525. p := hp1;
  526. End
  527. Else If
  528. ((Paicpu(p)^.oper[2].typ = Top_Reg) or
  529. (Paicpu(p)^.oper[2].typ = Top_None)) And
  530. (aktoptprocessor < ClassP6) And
  531. (Paicpu(p)^.oper[0].val <= 12) And
  532. Not(CS_LittleSize in aktglobalswitches) And
  533. (Not(GetNextInstruction(p, hp1)) Or
  534. {GetNextInstruction(p, hp1) And}
  535. Not((Pai(hp1)^.typ = ait_instruction) And
  536. ((paicpu(hp1)^.opcode=A_Jcc) and
  537. (paicpu(hp1)^.condition in [C_O,C_NO]))))
  538. Then
  539. Begin
  540. Reset_reference(tmpref);
  541. Case Paicpu(p)^.oper[0].val Of
  542. 3: Begin
  543. {imul 3, reg1, reg2 to
  544. lea (reg1,reg1,2), reg2
  545. imul 3, reg1 to
  546. lea (reg1,reg1,2), reg1}
  547. TmpRef.base := Paicpu(p)^.oper[1].reg;
  548. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  549. TmpRef.ScaleFactor := 2;
  550. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  551. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  552. Else
  553. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  554. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  555. Dispose(p, Done);
  556. p := hp1;
  557. End;
  558. 5: Begin
  559. {imul 5, reg1, reg2 to
  560. lea (reg1,reg1,4), reg2
  561. imul 5, reg1 to
  562. lea (reg1,reg1,4), reg1}
  563. TmpRef.base := Paicpu(p)^.oper[1].reg;
  564. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  565. TmpRef.ScaleFactor := 4;
  566. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  567. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  568. Else
  569. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  570. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  571. Dispose(p, Done);
  572. p := hp1;
  573. End;
  574. 6: Begin
  575. {imul 6, reg1, reg2 to
  576. lea (,reg1,2), reg2
  577. lea (reg2,reg1,4), reg2
  578. imul 6, reg1 to
  579. lea (reg1,reg1,2), reg1
  580. add reg1, reg1}
  581. If (aktoptprocessor <= Class386)
  582. Then
  583. Begin
  584. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  585. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  586. Then
  587. Begin
  588. TmpRef.base := Paicpu(p)^.oper[2].reg;
  589. TmpRef.ScaleFactor := 4;
  590. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  591. End
  592. Else
  593. Begin
  594. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  595. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  596. End;
  597. InsertLLItem(AsmL,p, p^.next, hp1);
  598. Reset_reference(tmpref);
  599. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  600. TmpRef.ScaleFactor := 2;
  601. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  602. Then
  603. Begin
  604. TmpRef.base := R_NO;
  605. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
  606. Paicpu(p)^.oper[2].reg));
  607. End
  608. Else
  609. Begin
  610. TmpRef.base := Paicpu(p)^.oper[1].reg;
  611. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  612. End;
  613. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  614. Dispose(p, Done);
  615. p := Pai(hp1^.next);
  616. End
  617. End;
  618. 9: Begin
  619. {imul 9, reg1, reg2 to
  620. lea (reg1,reg1,8), reg2
  621. imul 9, reg1 to
  622. lea (reg1,reg1,8), reg1}
  623. TmpRef.base := Paicpu(p)^.oper[1].reg;
  624. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  625. TmpRef.ScaleFactor := 8;
  626. If (Paicpu(p)^.oper[2].typ = Top_None) Then
  627. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
  628. Else
  629. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  630. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  631. Dispose(p, Done);
  632. p := hp1;
  633. End;
  634. 10: Begin
  635. {imul 10, reg1, reg2 to
  636. lea (reg1,reg1,4), reg2
  637. add reg2, reg2
  638. imul 10, reg1 to
  639. lea (reg1,reg1,4), reg1
  640. add reg1, reg1}
  641. If (aktoptprocessor <= Class386) Then
  642. Begin
  643. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  644. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  645. Paicpu(p)^.oper[2].reg,Paicpu(p)^.oper[2].reg))
  646. Else
  647. hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
  648. Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
  649. InsertLLItem(AsmL,p, p^.next, hp1);
  650. TmpRef.base := Paicpu(p)^.oper[1].reg;
  651. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  652. TmpRef.ScaleFactor := 4;
  653. If (Paicpu(p)^.oper[2].typ = Top_Reg)
  654. Then
  655. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg))
  656. Else
  657. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  658. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  659. Dispose(p, Done);
  660. p := Pai(hp1^.next);
  661. End
  662. End;
  663. 12: Begin
  664. {imul 12, reg1, reg2 to
  665. lea (,reg1,4), reg2
  666. lea (,reg1,8) reg2
  667. imul 12, reg1 to
  668. lea (reg1,reg1,2), reg1
  669. lea (,reg1,4), reg1}
  670. If (aktoptprocessor <= Class386)
  671. Then
  672. Begin
  673. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  674. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  675. Begin
  676. TmpRef.base := Paicpu(p)^.oper[2].reg;
  677. TmpRef.ScaleFactor := 8;
  678. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  679. End
  680. Else
  681. Begin
  682. TmpRef.base := R_NO;
  683. TmpRef.ScaleFactor := 4;
  684. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  685. End;
  686. InsertLLItem(AsmL,p, p^.next, hp1);
  687. Reset_reference(tmpref);
  688. TmpRef.Index := Paicpu(p)^.oper[1].reg;
  689. If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
  690. Begin
  691. TmpRef.base := R_NO;
  692. TmpRef.ScaleFactor := 4;
  693. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
  694. End
  695. Else
  696. Begin
  697. TmpRef.base := Paicpu(p)^.oper[1].reg;
  698. TmpRef.ScaleFactor := 2;
  699. hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  700. End;
  701. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  702. Dispose(p, Done);
  703. p := Pai(hp1^.next);
  704. End
  705. End
  706. End;
  707. End;
  708. End;
  709. A_LEA:
  710. Begin
  711. {removes seg register prefixes from LEA operations, as they
  712. don't do anything}
  713. Paicpu(p)^.oper[0].ref^.Segment := R_NO;
  714. {changes "lea (%reg1), %reg2" into "mov %reg1, %reg2"}
  715. If (Paicpu(p)^.oper[0].ref^.Base In [R_EAX..R_EDI]) And
  716. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  717. (Not(Assigned(Paicpu(p)^.oper[0].ref^.Symbol))) Then
  718. If (Paicpu(p)^.oper[0].ref^.Base <> Paicpu(p)^.oper[1].reg)
  719. and (Paicpu(p)^.oper[0].ref^.Offset = 0)
  720. Then
  721. Begin
  722. hp1 := New(Paicpu, op_reg_reg(A_MOV, S_L,Paicpu(p)^.oper[0].ref^.Base,
  723. Paicpu(p)^.oper[1].reg));
  724. InsertLLItem(AsmL,p^.previous,p^.next, hp1);
  725. Dispose(p, Done);
  726. p := hp1;
  727. Continue;
  728. End
  729. Else
  730. if (Paicpu(p)^.oper[0].ref^.Offset = 0) then
  731. Begin
  732. hp1 := Pai(p^.Next);
  733. AsmL^.Remove(p);
  734. Dispose(p, Done);
  735. p := hp1;
  736. Continue;
  737. End
  738. else
  739. with Paicpu(p)^.oper[0].ref^ do
  740. if (Base = Paicpu(p)^.oper[1].reg) then
  741. begin
  742. l := offset+offsetfixup;
  743. case l of
  744. 1,-1:
  745. begin
  746. if l = 1 then
  747. paicpu(p)^.opcode := A_INC
  748. else paicpu(p)^.opcode := A_DEC;
  749. paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
  750. paicpu(p)^.ops := 1;
  751. end;
  752. else
  753. begin
  754. paicpu(p)^.opcode := A_ADD;
  755. paicpu(p)^.loadconst(0,offset+offsetfixup);
  756. end;
  757. end;
  758. end;
  759. End;
  760. A_MOV:
  761. Begin
  762. TmpUsedRegs := UsedRegs;
  763. If (Paicpu(p)^.oper[1].typ = top_reg) And
  764. (Paicpu(p)^.oper[1].reg In [R_EAX, R_EBX, R_EDX, R_EDI]) And
  765. GetNextInstruction(p, hp1) And
  766. (Pai(hp1)^.typ = ait_instruction) And
  767. (Paicpu(hp1)^.opcode = A_MOV) And
  768. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  769. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  770. Then
  771. {we have "mov x, %treg; mov %treg, y}
  772. If not(RegUsedAfterInstruction(Paicpu(p)^.oper[1].reg, hp1, TmpUsedRegs)) then
  773. {we've got "mov x, %treg; mov %treg, y; with %treg is not used after }
  774. Case Paicpu(p)^.oper[0].typ Of
  775. top_reg:
  776. Begin
  777. { change "mov %reg, %treg; mov %treg, y"
  778. to "mov %reg, y" }
  779. Paicpu(p)^.LoadOper(1,Paicpu(hp1)^.oper[1]);
  780. AsmL^.Remove(hp1);
  781. Dispose(hp1, Done);
  782. continue;
  783. End;
  784. top_ref:
  785. If (Paicpu(hp1)^.oper[1].typ = top_reg) Then
  786. Begin
  787. { change "mov mem, %treg; mov %treg, %reg"
  788. to "mov mem, %reg" }
  789. Paicpu(p)^.Loadoper(1,Paicpu(hp1)^.oper[1]);
  790. AsmL^.Remove(hp1);
  791. Dispose(hp1, Done);
  792. continue;
  793. End;
  794. End
  795. Else
  796. Else
  797. {Change "mov %reg1, %reg2; xxx %reg2, ???" to
  798. "mov %reg1, %reg2; xxx %reg1, ???" to avoid a write/read
  799. penalty}
  800. If (Paicpu(p)^.oper[0].typ = top_reg) And
  801. (Paicpu(p)^.oper[1].typ = top_reg) And
  802. GetNextInstruction(p,hp1) And
  803. (Pai(hp1)^.typ = ait_instruction) And
  804. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  805. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
  806. Then
  807. {we have "mov %reg1, %reg2; XXX %reg2, ???"}
  808. Begin
  809. If ((Paicpu(hp1)^.opcode = A_OR) Or
  810. (Paicpu(hp1)^.opcode = A_TEST)) And
  811. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  812. (Paicpu(hp1)^.oper[0].reg = Paicpu(hp1)^.oper[1].reg)
  813. Then
  814. {we have "mov %reg1, %reg2; test/or %reg2, %reg2"}
  815. Begin
  816. TmpUsedRegs := UsedRegs;
  817. { reg1 will be used after the first instruction, }
  818. { so update the allocation info }
  819. allocRegBetween(asmL,paicpu(p)^.oper[0].reg,p,hp1);
  820. If GetNextInstruction(hp1, hp2) And
  821. (hp2^.typ = ait_instruction) And
  822. paicpu(hp2)^.is_jmp and
  823. Not(RegUsedAfterInstruction(Paicpu(hp1)^.oper[0].reg, hp1, TmpUsedRegs))
  824. Then
  825. {change "mov %reg1, %reg2; test/or %reg2, %reg2; jxx" to
  826. "test %reg1, %reg1; jxx"}
  827. Begin
  828. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  829. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  830. AsmL^.Remove(p);
  831. Dispose(p, done);
  832. p := hp1;
  833. continue
  834. End
  835. Else
  836. {change "mov %reg1, %reg2; test/or %reg2, %reg2" to
  837. "mov %reg1, %reg2; test/or %reg1, %reg1"}
  838. Begin
  839. Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
  840. Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
  841. End;
  842. End
  843. { Else
  844. If (Paicpu(p^.next)^.opcode
  845. In [A_PUSH, A_OR, A_XOR, A_AND, A_TEST])}
  846. {change "mov %reg1, %reg2; push/or/xor/... %reg2, ???" to
  847. "mov %reg1, %reg2; push/or/xor/... %reg1, ???"}
  848. End
  849. Else
  850. {leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
  851. x >= RetOffset) as it doesn't do anything (it writes either to a
  852. parameter or to the temporary storage room for the function
  853. result)}
  854. If GetNextInstruction(p, hp1) And
  855. (Pai(hp1)^.typ = ait_instruction)
  856. Then
  857. If ((Paicpu(hp1)^.opcode = A_LEAVE) Or
  858. (Paicpu(hp1)^.opcode = A_RET)) And
  859. (Paicpu(p)^.oper[1].typ = top_ref) And
  860. (Paicpu(p)^.oper[1].ref^.base = procinfo^.FramePointer) And
  861. (Paicpu(p)^.oper[1].ref^.offset >= procinfo^.Return_Offset) And
  862. (Paicpu(p)^.oper[1].ref^.index = R_NO) And
  863. (Paicpu(p)^.oper[0].typ = top_reg)
  864. Then
  865. Begin
  866. AsmL^.Remove(p);
  867. Dispose(p, done);
  868. p := hp1;
  869. RemoveLastDeallocForFuncRes(asmL,p);
  870. End
  871. Else
  872. If (Paicpu(p)^.oper[0].typ = top_reg) And
  873. (Paicpu(p)^.oper[1].typ = top_ref) And
  874. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) And
  875. (Paicpu(hp1)^.opcode = A_CMP) And
  876. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  877. RefsEqual(Paicpu(p)^.oper[1].ref^, Paicpu(hp1)^.oper[1].ref^) Then
  878. {change "mov reg1, mem1; cmp x, mem1" to "mov reg, mem1; cmp x, reg1"}
  879. begin
  880. Paicpu(hp1)^.loadreg(1,Paicpu(p)^.oper[0].reg);
  881. allocRegBetween(asmL,paicpu(p)^.oper[0].reg,p,hp1);
  882. end;
  883. { Next instruction is also a MOV ? }
  884. If GetNextInstruction(p, hp1) And
  885. (pai(hp1)^.typ = ait_instruction) and
  886. (Paicpu(hp1)^.opcode = A_MOV) and
  887. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize)
  888. Then
  889. Begin
  890. If (Paicpu(hp1)^.oper[0].typ = Paicpu(p)^.oper[1].typ) and
  891. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[0].typ)
  892. Then
  893. {mov reg1, mem1 or mov mem1, reg1
  894. mov mem2, reg2 mov reg2, mem2}
  895. Begin
  896. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  897. {mov reg1, mem1 or mov mem1, reg1
  898. mov mem2, reg1 mov reg2, mem1}
  899. Begin
  900. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[1]) Then
  901. { Removes the second statement from
  902. mov reg1, mem1/reg2
  903. mov mem1/reg2, reg1 }
  904. Begin
  905. if (paicpu(p)^.oper[0].typ = top_reg) then
  906. AllocRegBetween(asmL,paicpu(p)^.oper[0].reg,p,hp1);
  907. AsmL^.remove(hp1);
  908. Dispose(hp1,done);
  909. End
  910. Else
  911. Begin
  912. TmpUsedRegs := UsedRegs;
  913. UpdateUsedRegs(TmpUsedRegs, Pai(hp1^.next));
  914. If (Paicpu(p)^.oper[0].typ = top_reg) And
  915. { mov reg1, mem1
  916. mov mem2, reg1 }
  917. GetNextInstruction(hp1, hp2) And
  918. (hp2^.typ = ait_instruction) And
  919. (Paicpu(hp2)^.opcode = A_CMP) And
  920. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  921. (Paicpu(hp2)^.oper[0].typ = TOp_Ref) And
  922. (Paicpu(hp2)^.oper[1].typ = TOp_Reg) And
  923. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(p)^.oper[1].ref^) And
  924. (Paicpu(hp2)^.oper[1].reg = Paicpu(p)^.oper[0].reg) And
  925. Not(RegUsedAfterInstruction(Paicpu(p)^.oper[0].reg, hp2, TmpUsedRegs)) Then
  926. { change to
  927. mov reg1, mem1 mov reg1, mem1
  928. mov mem2, reg1 cmp reg1, mem2
  929. cmp mem1, reg1 }
  930. Begin
  931. AsmL^.Remove(hp2);
  932. Dispose(hp2, Done);
  933. Paicpu(hp1)^.opcode := A_CMP;
  934. Paicpu(hp1)^.loadref(1,newreference(Paicpu(hp1)^.oper[0].ref^));
  935. Paicpu(hp1)^.loadreg(0,Paicpu(p)^.oper[0].reg);
  936. End;
  937. End;
  938. End
  939. Else
  940. Begin
  941. tmpUsedRegs := UsedRegs;
  942. If GetNextInstruction(hp1, hp2) And
  943. (Paicpu(p)^.oper[0].typ = top_ref) And
  944. (Paicpu(p)^.oper[1].typ = top_reg) And
  945. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  946. (Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  947. (Paicpu(hp1)^.oper[1].typ = top_ref) And
  948. (Pai(hp2)^.typ = ait_instruction) And
  949. (Paicpu(hp2)^.opcode = A_MOV) And
  950. (Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
  951. (Paicpu(hp2)^.oper[1].typ = top_reg) And
  952. (Paicpu(hp2)^.oper[0].typ = top_ref) And
  953. RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(hp1)^.oper[1].ref^) Then
  954. If not regInRef(Paicpu(hp2)^.oper[1].reg,Paicpu(hp2)^.oper[0].ref^) and
  955. (Paicpu(p)^.oper[1].reg in [R_DI,R_EDI]) and
  956. not(RegUsedAfterInstruction(R_EDI,hp1,tmpUsedRegs)) Then
  957. { mov mem1, %edi
  958. mov %edi, mem2
  959. mov mem2, reg2
  960. to:
  961. mov mem1, reg2
  962. mov reg2, mem2}
  963. Begin
  964. Paicpu(p)^.Loadoper(1,Paicpu(hp2)^.oper[1]);
  965. Paicpu(hp1)^.loadoper(0,Paicpu(hp2)^.oper[1]);
  966. AsmL^.Remove(hp2);
  967. Dispose(hp2,Done);
  968. End
  969. Else
  970. If (Paicpu(p)^.oper[1].reg <> Paicpu(hp2)^.oper[1].reg) And
  971. not(RegInRef(Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[0].ref^)) And
  972. not(RegInRef(Paicpu(hp2)^.oper[1].reg,Paicpu(hp2)^.oper[0].ref^))
  973. Then
  974. { mov mem1, reg1 mov mem1, reg1
  975. mov reg1, mem2 mov reg1, mem2
  976. mov mem2, reg2 mov mem2, reg1
  977. to: to:
  978. mov mem1, reg1 mov mem1, reg1
  979. mov mem1, reg2 mov reg1, mem2
  980. mov reg1, mem2
  981. or (if mem1 depends on reg1
  982. and/or if mem2 depends on reg2)
  983. to:
  984. mov mem1, reg1
  985. mov reg1, mem2
  986. mov reg1, reg2
  987. }
  988. Begin
  989. Paicpu(hp1)^.LoadRef(0,newreference(Paicpu(p)^.oper[0].ref^));
  990. Paicpu(hp1)^.LoadReg(1,Paicpu(hp2)^.oper[1].reg);
  991. Paicpu(hp2)^.LoadRef(1,newreference(Paicpu(hp2)^.oper[0].ref^));
  992. Paicpu(hp2)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  993. allocRegBetween(asmL,paicpu(p)^.oper[1].reg,p,hp2);
  994. if (paicpu(p)^.oper[0].ref^.base in (usableregs+[R_EDI])) then
  995. allocRegBetween(asmL,paicpu(p)^.oper[0].ref^.base,p,hp2);
  996. if (paicpu(p)^.oper[0].ref^.index in (usableregs+[R_EDI])) then
  997. allocRegBetween(asmL,paicpu(p)^.oper[0].ref^.index,p,hp2);
  998. End
  999. Else
  1000. If (Paicpu(hp1)^.Oper[0].reg <> Paicpu(hp2)^.Oper[1].reg) Then
  1001. begin
  1002. Paicpu(hp2)^.LoadReg(0,Paicpu(hp1)^.Oper[0].reg);
  1003. allocRegBetween(asmL,paicpu(p)^.oper[1].reg,p,hp2);
  1004. end
  1005. else
  1006. begin
  1007. asmL^.Remove(hp2);
  1008. dispose(hp2, done);
  1009. end
  1010. End;
  1011. End
  1012. Else
  1013. (* {movl [mem1],reg1
  1014. movl [mem1],reg2
  1015. to:
  1016. movl [mem1],reg1
  1017. movl reg1,reg2 }
  1018. If (Paicpu(p)^.oper[0].typ = top_ref) and
  1019. (Paicpu(p)^.oper[1].typ = top_reg) and
  1020. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1021. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1022. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1023. RefsEqual(TReference(Paicpu(p)^.oper[0]^),Paicpu(hp1)^.oper[0]^.ref^) and
  1024. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.base) and
  1025. (Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.index) then
  1026. Paicpu(hp1)^.LoadReg(0,Paicpu(p)^.oper[1].reg)
  1027. Else*)
  1028. { movl const1,[mem1]
  1029. movl [mem1],reg1
  1030. to:
  1031. movl const1,reg1
  1032. movl reg1,[mem1] }
  1033. If (Paicpu(p)^.oper[0].typ = top_const) and
  1034. (Paicpu(p)^.oper[1].typ = top_ref) and
  1035. (Paicpu(hp1)^.oper[0].typ = top_ref) and
  1036. (Paicpu(hp1)^.oper[1].typ = top_reg) and
  1037. (Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
  1038. RefsEqual(Paicpu(hp1)^.oper[0].ref^,Paicpu(p)^.oper[1].ref^) then
  1039. Begin
  1040. allocregbetween(asml,Paicpu(hp1)^.oper[1].reg,p,hp1);
  1041. { allocregbetween doesn't insert this because at }
  1042. { this time, no regalloc info is available in }
  1043. { the optinfo field, so do it manually (JM) }
  1044. hp2 := new(paiRegalloc,alloc(Paicpu(hp1)^.oper[1].reg));
  1045. insertllitem(asml,p^.previous,p,hp2);
  1046. Paicpu(hp1)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1047. Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[1].ref^));
  1048. Paicpu(p)^.LoadReg(1,Paicpu(hp1)^.oper[0].reg);
  1049. End
  1050. End;
  1051. End;
  1052. A_MOVZX:
  1053. Begin
  1054. {removes superfluous And's after movzx's}
  1055. If (Paicpu(p)^.oper[1].typ = top_reg) And
  1056. GetNextInstruction(p, hp1) And
  1057. (Pai(hp1)^.typ = ait_instruction) And
  1058. (Paicpu(hp1)^.opcode = A_AND) And
  1059. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1060. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1061. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1062. Then
  1063. Case Paicpu(p)^.opsize Of
  1064. S_BL, S_BW:
  1065. If (Paicpu(hp1)^.oper[0].val = $ff) Then
  1066. Begin
  1067. AsmL^.Remove(hp1);
  1068. Dispose(hp1, Done);
  1069. End;
  1070. S_WL:
  1071. If (Paicpu(hp1)^.oper[0].val = $ffff) Then
  1072. Begin
  1073. AsmL^.Remove(hp1);
  1074. Dispose(hp1, Done);
  1075. End;
  1076. End;
  1077. {changes some movzx constructs to faster synonims (all examples
  1078. are given with eax/ax, but are also valid for other registers)}
  1079. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1080. If (Paicpu(p)^.oper[0].typ = top_reg) Then
  1081. Case Paicpu(p)^.opsize of
  1082. S_BW:
  1083. Begin
  1084. If (Paicpu(p)^.oper[0].reg = Reg16ToReg8(Paicpu(p)^.oper[1].reg)) And
  1085. Not(CS_LittleSize In aktglobalswitches)
  1086. Then
  1087. {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
  1088. Begin
  1089. Paicpu(p)^.opcode := A_AND;
  1090. Paicpu(p)^.changeopsize(S_W);
  1091. Paicpu(p)^.LoadConst(0,$ff);
  1092. End
  1093. Else
  1094. If GetNextInstruction(p, hp1) And
  1095. (Pai(hp1)^.typ = ait_instruction) And
  1096. (Paicpu(hp1)^.opcode = A_AND) And
  1097. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1098. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1099. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1100. Then
  1101. {Change "movzbw %reg1, %reg2; andw $const, %reg2"
  1102. to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
  1103. Begin
  1104. Paicpu(p)^.opcode := A_MOV;
  1105. Paicpu(p)^.changeopsize(S_W);
  1106. Paicpu(p)^.LoadReg(0,Reg8ToReg16(Paicpu(p)^.oper[0].reg));
  1107. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1108. End;
  1109. End;
  1110. S_BL:
  1111. Begin
  1112. If (Paicpu(p)^.oper[0].reg = Reg32ToReg8(Paicpu(p)^.oper[1].reg)) And
  1113. Not(CS_LittleSize in aktglobalswitches)
  1114. Then
  1115. {Change "movzbl %al, %eax" to "andl $0x0ffh, %eax"}
  1116. Begin
  1117. Paicpu(p)^.opcode := A_AND;
  1118. Paicpu(p)^.changeopsize(S_L);
  1119. Paicpu(p)^.loadconst(0,$ff)
  1120. End
  1121. Else
  1122. If GetNextInstruction(p, hp1) And
  1123. (Pai(hp1)^.typ = ait_instruction) And
  1124. (Paicpu(hp1)^.opcode = A_AND) And
  1125. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1126. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1127. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1128. Then
  1129. {Change "movzbl %reg1, %reg2; andl $const, %reg2"
  1130. to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
  1131. Begin
  1132. Paicpu(p)^.opcode := A_MOV;
  1133. Paicpu(p)^.changeopsize(S_L);
  1134. Paicpu(p)^.LoadReg(0,Reg8ToReg32(Paicpu(p)^.oper[0].reg));
  1135. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1136. End
  1137. End;
  1138. S_WL:
  1139. Begin
  1140. If (Paicpu(p)^.oper[0].reg = Reg32ToReg16(Paicpu(p)^.oper[1].reg)) And
  1141. Not(CS_LittleSize In aktglobalswitches)
  1142. Then
  1143. {Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax"}
  1144. Begin
  1145. Paicpu(p)^.opcode := A_AND;
  1146. Paicpu(p)^.changeopsize(S_L);
  1147. Paicpu(p)^.LoadConst(0,$ffff);
  1148. End
  1149. Else
  1150. If GetNextInstruction(p, hp1) And
  1151. (Pai(hp1)^.typ = ait_instruction) And
  1152. (Paicpu(hp1)^.opcode = A_AND) And
  1153. (Paicpu(hp1)^.oper[0].typ = top_const) And
  1154. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1155. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
  1156. Then
  1157. {Change "movzwl %reg1, %reg2; andl $const, %reg2"
  1158. to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
  1159. Begin
  1160. Paicpu(p)^.opcode := A_MOV;
  1161. Paicpu(p)^.changeopsize(S_L);
  1162. Paicpu(p)^.LoadReg(0,Reg16ToReg32(Paicpu(p)^.oper[0].reg));
  1163. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1164. End;
  1165. End;
  1166. End
  1167. Else
  1168. If (Paicpu(p)^.oper[0].typ = top_ref) Then
  1169. Begin
  1170. If GetNextInstruction(p, hp1) And
  1171. (Pai(hp1)^.typ = ait_instruction) And
  1172. (Paicpu(hp1)^.opcode = A_AND) And
  1173. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1174. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1175. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
  1176. Begin
  1177. Paicpu(p)^.opcode := A_MOV;
  1178. Case Paicpu(p)^.opsize Of
  1179. S_BL:
  1180. Begin
  1181. Paicpu(p)^.changeopsize(S_L);
  1182. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1183. End;
  1184. S_WL:
  1185. Begin
  1186. Paicpu(p)^.changeopsize(S_L);
  1187. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
  1188. End;
  1189. S_BW:
  1190. Begin
  1191. Paicpu(p)^.changeopsize(S_W);
  1192. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
  1193. End;
  1194. End;
  1195. End;
  1196. End;
  1197. End;
  1198. A_POP:
  1199. Begin
  1200. if target_info.target=target_i386_go32v2 then
  1201. begin
  1202. { Transform a series of pop/pop/pop/push/push/push to }
  1203. { 'movl x(%esp),%reg' for go32v2 (not for the rest, }
  1204. { because I'm not sure whether they can cope with }
  1205. { 'movl x(%esp),%reg' with x > 0, I believe we had }
  1206. { such a problem when using esp as frame pointer (JM) }
  1207. if (Paicpu(p)^.oper[0].typ = top_reg) then
  1208. begin
  1209. hp1 := p;
  1210. hp2 := p;
  1211. l := 0;
  1212. while getNextInstruction(hp1,hp1) and
  1213. (hp1^.typ = ait_instruction) and
  1214. (paicpu(hp1)^.opcode = A_POP) and
  1215. (paicpu(hp1)^.oper[0].typ = top_reg) do
  1216. begin
  1217. hp2 := hp1;
  1218. inc(l,4);
  1219. end;
  1220. getLastInstruction(p,hp3);
  1221. l1 := 0;
  1222. while (hp2 <> hp3) and
  1223. assigned(hp1) and
  1224. (hp1^.typ = ait_instruction) and
  1225. (paicpu(hp1)^.opcode = A_PUSH) and
  1226. (paicpu(hp1)^.oper[0].typ = top_reg) and
  1227. (paicpu(hp1)^.oper[0].reg = paicpu(hp2)^.oper[0].reg) do
  1228. begin
  1229. { change it to a two op operation }
  1230. paicpu(hp2)^.oper[1].typ:=top_none;
  1231. paicpu(hp2)^.ops:=2;
  1232. paicpu(hp2)^.opcode := A_MOV;
  1233. paicpu(hp2)^.Loadoper(1,paicpu(hp1)^.oper[0]);
  1234. reset_reference(tmpref);
  1235. tmpRef.base := stack_pointer;
  1236. tmpRef.offset := l;
  1237. paicpu(hp2)^.loadRef(0,newReference(tmpRef));
  1238. hp4 := hp1;
  1239. getNextInstruction(hp1,hp1);
  1240. asmL^.remove(hp4);
  1241. dispose(hp4,done);
  1242. getLastInstruction(hp2,hp2);
  1243. dec(l,4);
  1244. inc(l1);
  1245. end;
  1246. if l <> -4 then
  1247. begin
  1248. inc(l,4);
  1249. for l1 := l1 downto 1 do
  1250. begin
  1251. getNextInstruction(hp2,hp2);
  1252. dec(paicpu(hp2)^.oper[0].ref^.offset,l);
  1253. end
  1254. end
  1255. end
  1256. end
  1257. else
  1258. begin
  1259. if (Paicpu(p)^.oper[0].typ = top_reg) And
  1260. GetNextInstruction(p, hp1) And
  1261. (pai(hp1)^.typ=ait_instruction) and
  1262. (Paicpu(hp1)^.opcode=A_PUSH) and
  1263. (Paicpu(hp1)^.oper[0].typ = top_reg) And
  1264. (Paicpu(hp1)^.oper[0].reg=Paicpu(p)^.oper[0].reg) then
  1265. Begin
  1266. { change it to a two op operation }
  1267. Paicpu(p)^.oper[1].typ:=top_none;
  1268. Paicpu(p)^.ops:=2;
  1269. Paicpu(p)^.opcode := A_MOV;
  1270. Paicpu(p)^.Loadoper(1,Paicpu(p)^.oper[0]);
  1271. Reset_reference(tmpref);
  1272. TmpRef.base := R_ESP;
  1273. Paicpu(p)^.LoadRef(0,newReference(TmpRef));
  1274. AsmL^.Remove(hp1);
  1275. Dispose(hp1, Done)
  1276. End;
  1277. end;
  1278. end;
  1279. A_PUSH:
  1280. Begin
  1281. If (Paicpu(p)^.opsize = S_W) And
  1282. (Paicpu(p)^.oper[0].typ = Top_Const) And
  1283. GetNextInstruction(p, hp1) And
  1284. (Pai(hp1)^.typ = ait_instruction) And
  1285. (Paicpu(hp1)^.opcode = A_PUSH) And
  1286. (Paicpu(hp1)^.oper[0].typ = Top_Const) And
  1287. (Paicpu(hp1)^.opsize = S_W) Then
  1288. Begin
  1289. Paicpu(p)^.changeopsize(S_L);
  1290. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val shl 16 + word(Paicpu(hp1)^.oper[0].val));
  1291. AsmL^.Remove(hp1);
  1292. Dispose(hp1, Done)
  1293. End;
  1294. End;
  1295. A_SHL, A_SAL:
  1296. Begin
  1297. If (Paicpu(p)^.oper[0].typ = Top_Const) And
  1298. (Paicpu(p)^.oper[1].typ = Top_Reg) And
  1299. (Paicpu(p)^.opsize = S_L) And
  1300. (Paicpu(p)^.oper[0].val <= 3)
  1301. {Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement}
  1302. Then
  1303. Begin
  1304. TmpBool1 := True; {should we check the next instruction?}
  1305. TmpBool2 := False; {have we found an add/sub which could be
  1306. integrated in the lea?}
  1307. Reset_reference(tmpref);
  1308. TmpRef.index := Paicpu(p)^.oper[1].reg;
  1309. TmpRef.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1310. While TmpBool1 And
  1311. GetNextInstruction(p, hp1) And
  1312. (Pai(hp1)^.typ = ait_instruction) And
  1313. ((Paicpu(hp1)^.opcode = A_ADD) Or
  1314. (Paicpu(hp1)^.opcode = A_SUB)) And
  1315. (Paicpu(hp1)^.oper[1].typ = Top_Reg) And
  1316. (Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Do
  1317. Begin
  1318. TmpBool1 := False;
  1319. If (Paicpu(hp1)^.oper[0].typ = Top_Const)
  1320. Then
  1321. Begin
  1322. TmpBool1 := True;
  1323. TmpBool2 := True;
  1324. If Paicpu(hp1)^.opcode = A_ADD Then
  1325. Inc(TmpRef.offset, Paicpu(hp1)^.oper[0].val)
  1326. Else
  1327. Dec(TmpRef.offset, Paicpu(hp1)^.oper[0].val);
  1328. AsmL^.Remove(hp1);
  1329. Dispose(hp1, Done);
  1330. End
  1331. Else
  1332. If (Paicpu(hp1)^.oper[0].typ = Top_Reg) And
  1333. (Paicpu(hp1)^.opcode = A_ADD) And
  1334. (TmpRef.base = R_NO) Then
  1335. Begin
  1336. TmpBool1 := True;
  1337. TmpBool2 := True;
  1338. TmpRef.base := Paicpu(hp1)^.oper[0].reg;
  1339. AsmL^.Remove(hp1);
  1340. Dispose(hp1, Done);
  1341. End;
  1342. End;
  1343. If TmpBool2 Or
  1344. ((aktoptprocessor < ClassP6) And
  1345. (Paicpu(p)^.oper[0].val <= 3) And
  1346. Not(CS_LittleSize in aktglobalswitches))
  1347. Then
  1348. Begin
  1349. If Not(TmpBool2) And
  1350. (Paicpu(p)^.oper[0].val = 1)
  1351. Then
  1352. Begin
  1353. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1354. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg))
  1355. End
  1356. Else hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
  1357. Paicpu(p)^.oper[1].reg));
  1358. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1359. Dispose(p, Done);
  1360. p := hp1;
  1361. End;
  1362. End
  1363. Else
  1364. If (aktoptprocessor < ClassP6) And
  1365. (Paicpu(p)^.oper[0].typ = top_const) And
  1366. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1367. If (Paicpu(p)^.oper[0].val = 1)
  1368. Then
  1369. {changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
  1370. but faster on a 486, and pairable in both U and V pipes on the Pentium
  1371. (unlike shl, which is only pairable in the U pipe)}
  1372. Begin
  1373. hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
  1374. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1375. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1376. Dispose(p, done);
  1377. p := hp1;
  1378. End
  1379. Else If (Paicpu(p)^.opsize = S_L) and
  1380. (Paicpu(p)^.oper[0].val<= 3) Then
  1381. {changes "shl $2, %reg" to "lea (,%reg,4), %reg"
  1382. "shl $3, %reg" to "lea (,%reg,8), %reg}
  1383. Begin
  1384. Reset_reference(tmpref);
  1385. TmpRef.index := Paicpu(p)^.oper[1].reg;
  1386. TmpRef.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
  1387. hp1 := new(Paicpu,op_ref_reg(A_LEA,S_L,newReference(TmpRef), Paicpu(p)^.oper[1].reg));
  1388. InsertLLItem(AsmL,p^.previous, p^.next, hp1);
  1389. Dispose(p, done);
  1390. p := hp1;
  1391. End
  1392. End;
  1393. A_SAR, A_SHR:
  1394. {changes the code sequence
  1395. shr/sar const1, x
  1396. shl const2, x
  1397. to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
  1398. Begin
  1399. If GetNextInstruction(p, hp1) And
  1400. (pai(hp1)^.typ = ait_instruction) and
  1401. (Paicpu(hp1)^.opcode = A_SHL) and
  1402. (Paicpu(p)^.oper[0].typ = top_const) and
  1403. (Paicpu(hp1)^.oper[0].typ = top_const) and
  1404. (Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
  1405. (Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[1].typ) And
  1406. OpsEqual(Paicpu(hp1)^.oper[1], Paicpu(p)^.oper[1])
  1407. Then
  1408. If (Paicpu(p)^.oper[0].val > Paicpu(hp1)^.oper[0].val) And
  1409. Not(CS_LittleSize In aktglobalswitches)
  1410. Then
  1411. { shr/sar const1, %reg
  1412. shl const2, %reg
  1413. with const1 > const2 }
  1414. Begin
  1415. Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
  1416. Paicpu(hp1)^.opcode := A_AND;
  1417. l := (1 shl (Paicpu(hp1)^.oper[0].val)) - 1;
  1418. Case Paicpu(p)^.opsize Of
  1419. S_L: Paicpu(hp1)^.LoadConst(0,l Xor longint(-1));
  1420. S_B: Paicpu(hp1)^.LoadConst(0,l Xor $ff);
  1421. S_W: Paicpu(hp1)^.LoadConst(0,l Xor $ffff);
  1422. End;
  1423. End
  1424. Else
  1425. If (Paicpu(p)^.oper[0].val<Paicpu(hp1)^.oper[0].val) And
  1426. Not(CS_LittleSize In aktglobalswitches)
  1427. Then
  1428. { shr/sar const1, %reg
  1429. shl const2, %reg
  1430. with const1 < const2 }
  1431. Begin
  1432. Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val-Paicpu(p)^.oper[0].val);
  1433. Paicpu(p)^.opcode := A_AND;
  1434. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1435. Case Paicpu(p)^.opsize Of
  1436. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1437. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1438. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1439. End;
  1440. End
  1441. Else
  1442. { shr/sar const1, %reg
  1443. shl const2, %reg
  1444. with const1 = const2 }
  1445. if (Paicpu(p)^.oper[0].val = Paicpu(hp1)^.oper[0].val) then
  1446. Begin
  1447. Paicpu(p)^.opcode := A_AND;
  1448. l := (1 shl (Paicpu(p)^.oper[0].val))-1;
  1449. Case Paicpu(p)^.opsize Of
  1450. S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
  1451. S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
  1452. S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
  1453. End;
  1454. AsmL^.remove(hp1);
  1455. dispose(hp1, done);
  1456. End;
  1457. End;
  1458. A_SETcc :
  1459. { changes
  1460. setcc (funcres) setcc reg
  1461. movb (funcres), reg to leave/ret
  1462. leave/ret }
  1463. Begin
  1464. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1465. GetNextInstruction(p, hp1) And
  1466. GetNextInstruction(hp1, hp2) And
  1467. (hp2^.typ = ait_instruction) And
  1468. ((Paicpu(hp2)^.opcode = A_LEAVE) or
  1469. (Paicpu(hp2)^.opcode = A_RET)) And
  1470. (Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
  1471. (Paicpu(p)^.oper[0].ref^.Index = R_NO) And
  1472. (Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) And
  1473. (hp1^.typ = ait_instruction) And
  1474. (Paicpu(hp1)^.opcode = A_MOV) And
  1475. (Paicpu(hp1)^.opsize = S_B) And
  1476. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1477. RefsEqual(Paicpu(hp1)^.oper[0].ref^, Paicpu(p)^.oper[0].ref^) Then
  1478. Begin
  1479. Paicpu(p)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
  1480. AsmL^.Remove(hp1);
  1481. Dispose(hp1, Done)
  1482. End
  1483. End;
  1484. A_SUB:
  1485. { * change "subl $2, %esp; pushw x" to "pushl x"}
  1486. { * change "sub/add const1, reg" or "dec reg" followed by
  1487. "sub const2, reg" to one "sub ..., reg" }
  1488. Begin
  1489. If (Paicpu(p)^.oper[0].typ = top_const) And
  1490. (Paicpu(p)^.oper[1].typ = top_reg) Then
  1491. If (Paicpu(p)^.oper[0].val = 2) And
  1492. (Paicpu(p)^.oper[1].reg = R_ESP) and
  1493. { Don't do the sub/push optimization if the sub }
  1494. { comes from setting up the stack frame (JM) }
  1495. (not getLastInstruction(p,hp1) or
  1496. (hp1^.typ <> ait_instruction) or
  1497. (paicpu(hp1)^.opcode <> A_MOV) or
  1498. (paicpu(hp1)^.oper[0].typ <> top_reg) or
  1499. (paicpu(hp1)^.oper[0].reg <> R_ESP) or
  1500. (paicpu(hp1)^.oper[1].typ <> top_reg) or
  1501. (paicpu(hp1)^.oper[1].reg <> R_EBP)) then
  1502. Begin
  1503. hp1 := Pai(p^.next);
  1504. While Assigned(hp1) And
  1505. (Pai(hp1)^.typ In [ait_instruction]+SkipInstr) And
  1506. not regReadByInstruction(R_ESP,hp1) and
  1507. not regModifiedByInstruction(R_ESP,hp1) do
  1508. hp1 := Pai(hp1^.next);
  1509. If Assigned(hp1) And
  1510. (Pai(hp1)^.typ = ait_instruction) And
  1511. (Paicpu(hp1)^.opcode = A_PUSH) And
  1512. (Paicpu(hp1)^.opsize = S_W)
  1513. Then
  1514. Begin
  1515. Paicpu(hp1)^.changeopsize(S_L);
  1516. if Paicpu(hp1)^.oper[0].typ=top_reg then
  1517. Paicpu(hp1)^.LoadReg(0,Reg16ToReg32(Paicpu(hp1)^.oper[0].reg));
  1518. hp1 := Pai(p^.next);
  1519. AsmL^.Remove(p);
  1520. Dispose(p, Done);
  1521. p := hp1;
  1522. Continue
  1523. End;
  1524. If DoSubAddOpt(p) Then continue;
  1525. End
  1526. Else If DoSubAddOpt(p) Then Continue
  1527. End;
  1528. A_XOR:
  1529. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1530. (Paicpu(p)^.oper[1].typ = top_reg) And
  1531. (Paicpu(p)^.oper[0].reg = Paicpu(p)^.oper[1].reg) then
  1532. { temporarily change this to 'mov reg,0' to make it easier }
  1533. { for the CSE. Will be changed back in pass 2 }
  1534. begin
  1535. paicpu(p)^.opcode := A_MOV;
  1536. paicpu(p)^.loadconst(0,0);
  1537. end;
  1538. End;
  1539. end; { if is_jmp }
  1540. End;
  1541. { ait_label:
  1542. Begin
  1543. If labelCanBeSkipped(pai_label(p))
  1544. Then
  1545. Begin
  1546. hp1 := Pai(p^.next);
  1547. AsmL^.Remove(p);
  1548. Dispose(p, Done);
  1549. p := hp1;
  1550. Continue
  1551. End;
  1552. End;}
  1553. End;
  1554. p:=pai(p^.next);
  1555. end;
  1556. end;
  1557. function isFoldableArithOp(hp1: paicpu; reg: tregister): boolean;
  1558. begin
  1559. IsFoldableArithOp := False;
  1560. case hp1^.opcode of
  1561. A_ADD,A_SUB,A_OR,A_XOR,A_AND,A_SHL,A_SHR,A_SAR:
  1562. isFoldableArithOp :=
  1563. (paicpu(hp1)^.oper[0].typ in [top_reg,top_const]) and
  1564. (paicpu(hp1)^.oper[1].typ = top_reg) and
  1565. (paicpu(hp1)^.oper[1].reg = reg);
  1566. A_INC,A_DEC:
  1567. isFoldableArithOp :=
  1568. (paicpu(hp1)^.oper[0].typ = top_reg) and
  1569. (paicpu(hp1)^.oper[0].reg = reg);
  1570. end;
  1571. end;
  1572. Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
  1573. function CanBeCMOV(p : pai) : boolean;
  1574. begin
  1575. CanBeCMOV:=assigned(p) and (p^.typ=ait_instruction) and
  1576. (paicpu(p)^.opcode=A_MOV) and
  1577. (paicpu(p)^.opsize in [S_L,S_W]) and
  1578. (paicpu(p)^.oper[0].typ in [top_reg,top_ref]) and
  1579. (paicpu(p)^.oper[1].typ in [top_reg,top_ref]);
  1580. end;
  1581. var
  1582. p,hp1,hp2: pai;
  1583. {$ifdef USECMOV}
  1584. l : longint;
  1585. condition : tasmcond;
  1586. hp3: pai;
  1587. {$endif USECMOV}
  1588. UsedRegs, TmpUsedRegs: TRegSet;
  1589. Begin
  1590. P := BlockStart;
  1591. UsedRegs := [];
  1592. While (P <> BlockEnd) Do
  1593. Begin
  1594. UpdateUsedRegs(UsedRegs, Pai(p^.next));
  1595. Case P^.Typ Of
  1596. Ait_Instruction:
  1597. Begin
  1598. Case Paicpu(p)^.opcode Of
  1599. A_CALL:
  1600. If (AktOptProcessor < ClassP6) And
  1601. GetNextInstruction(p, hp1) And
  1602. (hp1^.typ = ait_instruction) And
  1603. (paicpu(hp1)^.opcode = A_JMP) Then
  1604. Begin
  1605. Inc(paicpu(hp1)^.oper[0].sym^.refs);
  1606. hp2 := New(Paicpu,op_sym(A_PUSH,S_L,paicpu(hp1)^.oper[0].sym));
  1607. InsertLLItem(AsmL, p^.previous, p, hp2);
  1608. Paicpu(p)^.opcode := A_JMP;
  1609. AsmL^.Remove(hp1);
  1610. Dispose(hp1, Done)
  1611. End;
  1612. {$ifdef USECMOV}
  1613. A_Jcc:
  1614. if (aktspecificoptprocessor=ClassP6) then
  1615. begin
  1616. { check for
  1617. jCC xxx
  1618. <several movs>
  1619. xxx:
  1620. }
  1621. l:=0;
  1622. GetNextInstruction(p, hp1);
  1623. while assigned(hp1) And
  1624. CanBeCMOV(hp1) do
  1625. begin
  1626. inc(l);
  1627. GetNextInstruction(hp1,hp1);
  1628. end;
  1629. if assigned(hp1) then
  1630. begin
  1631. if FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym),hp1) then
  1632. begin
  1633. if (l<=4) and (l>0) then
  1634. begin
  1635. condition:=inverse_cond[paicpu(p)^.condition];
  1636. GetNextInstruction(p,hp1);
  1637. asml^.remove(p);
  1638. dispose(p,done);
  1639. p:=hp1;
  1640. repeat
  1641. paicpu(hp1)^.opcode:=A_CMOVcc;
  1642. paicpu(hp1)^.condition:=condition;
  1643. GetNextInstruction(hp1,hp1);
  1644. until not(assigned(hp1)) or
  1645. not(CanBeCMOV(hp1));
  1646. asml^.remove(hp1);
  1647. dispose(hp1,done);
  1648. continue;
  1649. end;
  1650. end
  1651. else
  1652. begin
  1653. { check further for
  1654. jCC xxx
  1655. <several movs>
  1656. jmp yyy
  1657. xxx:
  1658. <several movs>
  1659. yyy:
  1660. }
  1661. { hp2 points to jmp xxx }
  1662. hp2:=hp1;
  1663. { skip hp1 to xxx }
  1664. GetNextInstruction(hp1, hp1);
  1665. if assigned(hp2) and
  1666. assigned(hp1) and
  1667. (l<=3) and
  1668. (hp2^.typ=ait_instruction) and
  1669. (paicpu(hp2)^.is_jmp) and
  1670. (paicpu(hp2)^.condition=C_None) and
  1671. FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym),hp1) then
  1672. begin
  1673. l:=0;
  1674. while assigned(hp1) And
  1675. CanBeCMOV(hp1) do
  1676. begin
  1677. inc(l);
  1678. GetNextInstruction(hp1, hp1);
  1679. end;
  1680. end;
  1681. {
  1682. if assigned(hp1) and
  1683. FindLabel(PAsmLabel(paicpu(hp2)^.oper[0].sym),hp1) then
  1684. begin
  1685. condition:=inverse_cond[paicpu(p)^.condition];
  1686. GetNextInstruction(p,hp1);
  1687. asml^.remove(p);
  1688. dispose(p,done);
  1689. p:=hp1;
  1690. repeat
  1691. paicpu(hp1)^.opcode:=A_CMOVcc;
  1692. paicpu(hp1)^.condition:=condition;
  1693. GetNextInstruction(hp1,hp1);
  1694. until not(assigned(hp1)) or
  1695. not(CanBeCMOV(hp1));
  1696. hp2:=hp1^.next;
  1697. condition:=inverse_cond[condition];
  1698. asml^.remove(hp1^.next)
  1699. dispose(hp1^.next,done);
  1700. asml^.remove(hp1);
  1701. dispose(hp1,done);
  1702. continue;
  1703. end;
  1704. }
  1705. end;
  1706. end;
  1707. end;
  1708. {$endif USECMOV}
  1709. A_FSTP,A_FISTP:
  1710. if doFpuLoadStoreOpt(asmL,p) then
  1711. continue;
  1712. A_IMUL:
  1713. begin
  1714. if ((paicpu(p)^.oper[0].typ = top_const) or
  1715. (paicpu(p)^.oper[0].typ = top_symbol)) and
  1716. (paicpu(p)^.oper[1].typ = top_reg) and
  1717. ((paicpu(p)^.oper[2].typ = top_none) or
  1718. ((paicpu(p)^.oper[2].typ = top_reg) and
  1719. (paicpu(p)^.oper[2].reg = paicpu(p)^.oper[1].reg))) and
  1720. getLastInstruction(p,hp1) and
  1721. (hp1^.typ = ait_instruction) and
  1722. (paicpu(hp1)^.opcode = A_MOV) and
  1723. (paicpu(hp1)^.oper[0].typ = top_reg) and
  1724. (paicpu(hp1)^.oper[1].typ = top_reg) and
  1725. (paicpu(hp1)^.oper[1].reg = paicpu(p)^.oper[1].reg) then
  1726. { change "mov reg1,reg2; imul y,reg2" to "imul y,reg1,reg2" }
  1727. begin
  1728. paicpu(p)^.ops := 3;
  1729. paicpu(p)^.loadreg(1,paicpu(hp1)^.oper[0].reg);
  1730. paicpu(p)^.loadreg(2,paicpu(hp1)^.oper[1].reg);
  1731. asmL^.remove(hp1);
  1732. dispose(hp1,done);
  1733. end;
  1734. end;
  1735. A_MOV:
  1736. Begin
  1737. If (Paicpu(p)^.oper[0].typ = top_reg) And
  1738. (Paicpu(p)^.oper[1].typ = top_reg) And
  1739. GetNextInstruction(p, hp1) And
  1740. (hp1^.typ = ait_Instruction) And
  1741. ((Paicpu(hp1)^.opcode = A_MOV) or
  1742. (Paicpu(hp1)^.opcode = A_MOVZX) or
  1743. (Paicpu(hp1)^.opcode = A_MOVSX)) And
  1744. (Paicpu(hp1)^.oper[0].typ = top_ref) And
  1745. (Paicpu(hp1)^.oper[1].typ = top_reg) And
  1746. ((Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Or
  1747. (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg)) And
  1748. (Reg32(Paicpu(hp1)^.oper[1].reg) = Paicpu(p)^.oper[1].reg) Then
  1749. {mov reg1, reg2
  1750. mov/zx/sx (reg2, ..), reg2 to mov/zx/sx (reg1, ..), reg2}
  1751. Begin
  1752. If (Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Then
  1753. Paicpu(hp1)^.oper[0].ref^.Base := Paicpu(p)^.oper[0].reg;
  1754. If (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg) Then
  1755. Paicpu(hp1)^.oper[0].ref^.Index := Paicpu(p)^.oper[0].reg;
  1756. AsmL^.Remove(p);
  1757. Dispose(p, Done);
  1758. p := hp1;
  1759. Continue;
  1760. End
  1761. Else If (Paicpu(p)^.oper[0].typ = top_ref) And
  1762. GetNextInstruction(p,hp1) And
  1763. (hp1^.typ = ait_instruction) And
  1764. IsFoldableArithOp(paicpu(hp1),Paicpu(p)^.oper[1].reg) And
  1765. GetNextInstruction(hp1,hp2) And
  1766. (hp2^.typ = ait_instruction) And
  1767. (Paicpu(hp2)^.opcode = A_MOV) And
  1768. (Paicpu(hp2)^.oper[0].typ = top_reg) And
  1769. (Paicpu(hp2)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
  1770. (Paicpu(hp2)^.oper[1].typ = top_ref) Then
  1771. Begin
  1772. TmpUsedRegs := UsedRegs;
  1773. UpdateUsedRegs(TmpUsedRegs,Pai(hp1^.next));
  1774. If (RefsEqual(Paicpu(hp2)^.oper[1].ref^, Paicpu(p)^.oper[0].ref^) And
  1775. Not(RegUsedAfterInstruction(Paicpu(p)^.oper[1].reg,
  1776. hp2, TmpUsedRegs)))
  1777. Then
  1778. { change mov (ref), reg }
  1779. { add/sub/or/... reg2/$const, reg }
  1780. { mov reg, (ref) }
  1781. { # release reg }
  1782. { to add/sub/or/... reg2/$const, (ref) }
  1783. Begin
  1784. case paicpu(hp1)^.opcode of
  1785. A_INC,A_DEC:
  1786. paicpu(hp1)^.LoadRef(0,newreference(Paicpu(p)^.oper[0].ref^))
  1787. else
  1788. paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[0].ref^));
  1789. end;
  1790. AsmL^.Remove(p);
  1791. AsmL^.Remove(hp2);
  1792. Dispose(p,done);
  1793. Dispose(hp2,Done);
  1794. p := hp1
  1795. End;
  1796. End
  1797. else if (Paicpu(p)^.oper[0].typ = Top_Const) And
  1798. (Paicpu(p)^.oper[0].val = 0) And
  1799. (Paicpu(p)^.oper[1].typ = Top_Reg) Then
  1800. { change "mov $0, %reg" into "xor %reg, %reg" }
  1801. Begin
  1802. Paicpu(p)^.opcode := A_XOR;
  1803. Paicpu(p)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
  1804. End
  1805. End;
  1806. A_MOVZX:
  1807. Begin
  1808. If (Paicpu(p)^.oper[1].typ = top_reg) Then
  1809. If (Paicpu(p)^.oper[0].typ = top_reg)
  1810. Then
  1811. Case Paicpu(p)^.opsize of
  1812. S_BL:
  1813. Begin
  1814. If IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1815. Not(CS_LittleSize in aktglobalswitches) And
  1816. (aktoptprocessor = ClassP5)
  1817. Then
  1818. {Change "movzbl %reg1, %reg2" to
  1819. "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
  1820. PentiumMMX}
  1821. Begin
  1822. hp1 := New(Paicpu, op_reg_reg(A_XOR, S_L,
  1823. Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
  1824. InsertLLItem(AsmL,p^.previous, p, hp1);
  1825. Paicpu(p)^.opcode := A_MOV;
  1826. Paicpu(p)^.changeopsize(S_B);
  1827. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1828. End;
  1829. End;
  1830. End
  1831. Else
  1832. If (Paicpu(p)^.oper[0].typ = top_ref) And
  1833. (Paicpu(p)^.oper[0].ref^.base <> Paicpu(p)^.oper[1].reg) And
  1834. (Paicpu(p)^.oper[0].ref^.index <> Paicpu(p)^.oper[1].reg) And
  1835. Not(CS_LittleSize in aktglobalswitches) And
  1836. IsGP32Reg(Paicpu(p)^.oper[1].reg) And
  1837. (aktoptprocessor = ClassP5) And
  1838. (Paicpu(p)^.opsize = S_BL)
  1839. Then
  1840. {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
  1841. Pentium and PentiumMMX}
  1842. Begin
  1843. hp1 := New(Paicpu,op_reg_reg(A_XOR, S_L, Paicpu(p)^.oper[1].reg,
  1844. Paicpu(p)^.oper[1].reg));
  1845. Paicpu(p)^.opcode := A_MOV;
  1846. Paicpu(p)^.changeopsize(S_B);
  1847. Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
  1848. InsertLLItem(AsmL,p^.previous, p, hp1);
  1849. End;
  1850. End;
  1851. A_TEST, A_OR:
  1852. {removes the line marked with (x) from the sequence
  1853. And/or/xor/add/sub/... $x, %y
  1854. test/or %y, %y (x)
  1855. j(n)z _Label
  1856. as the first instruction already adjusts the ZF}
  1857. Begin
  1858. If OpsEqual(Paicpu(p)^.oper[0],Paicpu(p)^.oper[1]) Then
  1859. If GetLastInstruction(p, hp1) And
  1860. (pai(hp1)^.typ = ait_instruction) Then
  1861. Case Paicpu(hp1)^.opcode Of
  1862. A_ADD, A_SUB, A_OR, A_XOR, A_AND{, A_SHL, A_SHR}:
  1863. Begin
  1864. If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
  1865. Begin
  1866. hp1 := pai(p^.next);
  1867. asml^.remove(p);
  1868. dispose(p, done);
  1869. p := pai(hp1);
  1870. continue
  1871. End;
  1872. End;
  1873. A_DEC, A_INC, A_NEG:
  1874. Begin
  1875. If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[0]) Then
  1876. Begin
  1877. Case Paicpu(hp1)^.opcode Of
  1878. A_DEC, A_INC:
  1879. {replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag}
  1880. Begin
  1881. Case Paicpu(hp1)^.opcode Of
  1882. A_DEC: Paicpu(hp1)^.opcode := A_SUB;
  1883. A_INC: Paicpu(hp1)^.opcode := A_ADD;
  1884. End;
  1885. Paicpu(hp1)^.Loadoper(1,Paicpu(hp1)^.oper[0]);
  1886. Paicpu(hp1)^.LoadConst(0,1);
  1887. Paicpu(hp1)^.ops:=2;
  1888. End
  1889. End;
  1890. hp1 := pai(p^.next);
  1891. asml^.remove(p);
  1892. dispose(p, done);
  1893. p := pai(hp1);
  1894. continue
  1895. End;
  1896. End
  1897. End
  1898. End;
  1899. End;
  1900. End;
  1901. End;
  1902. p := Pai(p^.next)
  1903. End;
  1904. End;
  1905. End.
  1906. {
  1907. $Log$
  1908. Revision 1.13 2000-10-02 13:01:29 jonas
  1909. * fixed bug regarding removal of "test/or reg,reg": apparently, shr/shl
  1910. doesn't set the zero flag according to the contents of the register
  1911. after the shift :( (mergfed from fixes branch)
  1912. Revision 1.12 2000/09/24 15:06:23 peter
  1913. * use defines.inc
  1914. Revision 1.11 2000/09/18 11:28:36 jonas
  1915. * fixed web bug 1133 (merged from fixes branch)
  1916. Revision 1.10 2000/08/18 10:09:13 jonas
  1917. * fix for web bug1099 (merged from fixes branch)
  1918. Revision 1.9 2000/08/05 13:33:08 peter
  1919. * $ifdef go32v2 -> target_info.target=go32v2
  1920. Revision 1.8 2000/08/05 10:35:51 jonas
  1921. * readded l1 variable (between ifdef go32v2 to avoid hints/notes)
  1922. Revision 1.7 2000/08/04 22:00:52 peter
  1923. * merges from fixes
  1924. Revision 1.6 2000/07/31 08:44:05 jonas
  1925. - removed imul support from -dfoldarithops since "imull [reg32],[mem32]"
  1926. doesn't exist (merged from fixes branch)
  1927. Revision 1.5 2000/07/28 13:56:23 jonas
  1928. * fixed bug in shr/shl optimization when -Og is used (merged from fixes
  1929. branch)
  1930. Revision 1.4 2000/07/21 15:19:55 jonas
  1931. * daopt386: changes to getnextinstruction/getlastinstruction so they
  1932. ignore labels who have is_addr set
  1933. + daopt386/csopt386: remove loads of registers which are overwritten
  1934. before their contents are used (especially usefull for removing superfluous
  1935. maybe_loadesi outputs and push/pops transformed by below optimization
  1936. + popt386: transform pop/pop/pop/.../push/push/push to sequences of
  1937. 'movl x(%esp),%reg' (only active when compiling a go32v2 compiler
  1938. currently because I don't know whether it's safe to do this under Win32/
  1939. Linux (because of problems we had when using esp as frame pointer on
  1940. those os'es)
  1941. Revision 1.3 2000/07/14 05:11:49 michael
  1942. + Patch to 1.1
  1943. Revision 1.2 2000/07/13 11:32:45 michael
  1944. + removed logs
  1945. }