aasmcpu.pas 70 KB

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  1. {
  2. Copyright (c) 2003 by Florian Klaempfl
  3. Contains the assembler object for the ARM
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit aasmcpu;
  18. {$i fpcdefs.inc}
  19. interface
  20. uses
  21. cclasses,globtype,globals,verbose,
  22. aasmbase,aasmtai,
  23. ogbase,
  24. symtype,
  25. cpubase,cpuinfo,cgbase,cgutils;
  26. const
  27. { "mov reg,reg" source operand number }
  28. O_MOV_SOURCE = 1;
  29. { "mov reg,reg" source operand number }
  30. O_MOV_DEST = 0;
  31. { Operand types }
  32. OT_NONE = $00000000;
  33. OT_BITS8 = $00000001; { size, and other attributes, of the operand }
  34. OT_BITS16 = $00000002;
  35. OT_BITS32 = $00000004;
  36. OT_BITS64 = $00000008; { FPU only }
  37. OT_BITS80 = $00000010;
  38. OT_FAR = $00000020; { this means 16:16 or 16:32, like in CALL/JMP }
  39. OT_NEAR = $00000040;
  40. OT_SHORT = $00000080;
  41. OT_BITSTINY = $00000100; { fpu constant }
  42. OT_BITSSHIFTER =
  43. $00000200;
  44. OT_SIZE_MASK = $000003FF; { all the size attributes }
  45. OT_NON_SIZE = longint(not OT_SIZE_MASK);
  46. OT_SIGNED = $00000100; { the operand need to be signed -128-127 }
  47. OT_TO = $00000200; { operand is followed by a colon }
  48. { reverse effect in FADD, FSUB &c }
  49. OT_COLON = $00000400;
  50. OT_SHIFTEROP = $00000800;
  51. OT_REGISTER = $00001000;
  52. OT_IMMEDIATE = $00002000;
  53. OT_REGLIST = $00008000;
  54. OT_IMM8 = $00002001;
  55. OT_IMM24 = $00002002;
  56. OT_IMM32 = $00002004;
  57. OT_IMM64 = $00002008;
  58. OT_IMM80 = $00002010;
  59. OT_IMMTINY = $00002100;
  60. OT_IMMSHIFTER= $00002200;
  61. OT_IMMEDIATE24 = OT_IMM24;
  62. OT_SHIFTIMM = OT_SHIFTEROP or OT_IMMSHIFTER;
  63. OT_SHIFTIMMEDIATE = OT_SHIFTIMM;
  64. OT_IMMEDIATESHIFTER = OT_IMMSHIFTER;
  65. OT_IMMEDIATEFPU = OT_IMMTINY;
  66. OT_REGMEM = $00200000; { for r/m, ie EA, operands }
  67. OT_REGNORM = $00201000; { 'normal' reg, qualifies as EA }
  68. OT_REG8 = $00201001;
  69. OT_REG16 = $00201002;
  70. OT_REG32 = $00201004;
  71. OT_REG64 = $00201008;
  72. OT_VREG = $00201010; { vector register }
  73. OT_MEMORY = $00204000; { register number in 'basereg' }
  74. OT_MEM8 = $00204001;
  75. OT_MEM16 = $00204002;
  76. OT_MEM32 = $00204004;
  77. OT_MEM64 = $00204008;
  78. OT_MEM80 = $00204010;
  79. { word/byte load/store }
  80. OT_AM2 = $00010000;
  81. { misc ld/st operations }
  82. OT_AM3 = $00020000;
  83. { multiple ld/st operations }
  84. OT_AM4 = $00040000;
  85. { co proc. ld/st operations }
  86. OT_AM5 = $00080000;
  87. OT_AMMASK = $000f0000;
  88. OT_MEMORYAM2 = OT_MEMORY or OT_AM2;
  89. OT_MEMORYAM3 = OT_MEMORY or OT_AM3;
  90. OT_MEMORYAM4 = OT_MEMORY or OT_AM4;
  91. OT_MEMORYAM5 = OT_MEMORY or OT_AM5;
  92. OT_FPUREG = $01000000; { floating point stack registers }
  93. OT_REG_SMASK = $00070000; { special register operands: these may be treated differently }
  94. { a mask for the following }
  95. OT_MEM_OFFS = $00604000; { special type of EA }
  96. { simple [address] offset }
  97. OT_ONENESS = $00800000; { special type of immediate operand }
  98. { so UNITY == IMMEDIATE | ONENESS }
  99. OT_UNITY = $00802000; { for shift/rotate instructions }
  100. instabentries = {$i armnop.inc}
  101. maxinfolen = 5;
  102. IF_NONE = $00000000;
  103. IF_ARMMASK = $000F0000;
  104. IF_ARM7 = $00070000;
  105. IF_FPMASK = $00F00000;
  106. IF_FPA = $00100000;
  107. { if the instruction can change in a second pass }
  108. IF_PASS2 = longint($80000000);
  109. type
  110. TInsTabCache=array[TasmOp] of longint;
  111. PInsTabCache=^TInsTabCache;
  112. tinsentry = record
  113. opcode : tasmop;
  114. ops : byte;
  115. optypes : array[0..3] of longint;
  116. code : array[0..maxinfolen] of char;
  117. flags : longint;
  118. end;
  119. pinsentry=^tinsentry;
  120. const
  121. InsTab : array[0..instabentries-1] of TInsEntry={$i armtab.inc}
  122. var
  123. InsTabCache : PInsTabCache;
  124. type
  125. taicpu = class(tai_cpu_abstract)
  126. oppostfix : TOpPostfix;
  127. roundingmode : troundingmode;
  128. procedure loadshifterop(opidx:longint;const so:tshifterop);
  129. procedure loadregset(opidx:longint;const s:tcpuregisterset);
  130. constructor op_none(op : tasmop);
  131. constructor op_reg(op : tasmop;_op1 : tregister);
  132. constructor op_const(op : tasmop;_op1 : longint);
  133. constructor op_reg_reg(op : tasmop;_op1,_op2 : tregister);
  134. constructor op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
  135. constructor op_reg_const(op:tasmop; _op1: tregister; _op2: aint);
  136. constructor op_ref_regset(op:tasmop; _op1: treference; _op2: tcpuregisterset);
  137. constructor op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
  138. constructor op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: aint);
  139. constructor op_reg_reg_sym_ofs(op : tasmop;_op1,_op2 : tregister; _op3: tasmsymbol;_op3ofs: longint);
  140. constructor op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister; const _op3: treference);
  141. constructor op_reg_reg_shifterop(op : tasmop;_op1,_op2 : tregister;_op3 : tshifterop);
  142. { SFM/LFM }
  143. constructor op_reg_const_ref(op : tasmop;_op1 : tregister;_op2 : aint;_op3 : treference);
  144. { *M*LL }
  145. constructor op_reg_reg_reg_reg(op : tasmop;_op1,_op2,_op3,_op4 : tregister);
  146. { this is for Jmp instructions }
  147. constructor op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
  148. constructor op_sym(op : tasmop;_op1 : tasmsymbol);
  149. constructor op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
  150. constructor op_reg_sym_ofs(op : tasmop;_op1 : tregister;_op2:tasmsymbol;_op2ofs : longint);
  151. constructor op_sym_ofs_ref(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  152. function is_same_reg_move(regtype: Tregistertype):boolean; override;
  153. function spilling_get_operation_type(opnr: longint): topertype;override;
  154. { assembler }
  155. public
  156. { the next will reset all instructions that can change in pass 2 }
  157. procedure ResetPass1;
  158. procedure ResetPass2;
  159. function CheckIfValid:boolean;
  160. function GetString:string;
  161. function Pass1(objdata:TObjData):longint;override;
  162. procedure Pass2(objdata:TObjData);override;
  163. protected
  164. procedure ppuloadoper(ppufile:tcompilerppufile;var o:toper);override;
  165. procedure ppuwriteoper(ppufile:tcompilerppufile;const o:toper);override;
  166. procedure ppubuildderefimploper(var o:toper);override;
  167. procedure ppuderefoper(var o:toper);override;
  168. private
  169. { next fields are filled in pass1, so pass2 is faster }
  170. inssize : shortint;
  171. insoffset : longint;
  172. LastInsOffset : longint; { need to be public to be reset }
  173. insentry : PInsEntry;
  174. function InsEnd:longint;
  175. procedure create_ot(objdata:TObjData);
  176. function Matches(p:PInsEntry):longint;
  177. function calcsize(p:PInsEntry):shortint;
  178. procedure gencode(objdata:TObjData);
  179. function NeedAddrPrefix(opidx:byte):boolean;
  180. procedure Swapoperands;
  181. function FindInsentry(objdata:TObjData):boolean;
  182. end;
  183. tai_align = class(tai_align_abstract)
  184. { nothing to add }
  185. end;
  186. function spilling_create_load(const ref:treference;r:tregister): tai;
  187. function spilling_create_store(r:tregister; const ref:treference): tai;
  188. function setoppostfix(i : taicpu;pf : toppostfix) : taicpu;
  189. function setroundingmode(i : taicpu;rm : troundingmode) : taicpu;
  190. function setcondition(i : taicpu;c : tasmcond) : taicpu;
  191. { inserts pc relative symbols at places where they are reachable }
  192. procedure insertpcrelativedata(list,listtoinsert : taasmoutput);
  193. procedure InitAsm;
  194. procedure DoneAsm;
  195. implementation
  196. uses
  197. cutils,rgobj,itcpugas;
  198. procedure taicpu.loadshifterop(opidx:longint;const so:tshifterop);
  199. begin
  200. allocate_oper(opidx+1);
  201. with oper[opidx]^ do
  202. begin
  203. if typ<>top_shifterop then
  204. begin
  205. clearop(opidx);
  206. new(shifterop);
  207. end;
  208. shifterop^:=so;
  209. typ:=top_shifterop;
  210. if assigned(add_reg_instruction_hook) then
  211. add_reg_instruction_hook(self,shifterop^.rs);
  212. end;
  213. end;
  214. procedure taicpu.loadregset(opidx:longint;const s:tcpuregisterset);
  215. var
  216. i : byte;
  217. begin
  218. allocate_oper(opidx+1);
  219. with oper[opidx]^ do
  220. begin
  221. if typ<>top_regset then
  222. clearop(opidx);
  223. new(regset);
  224. regset^:=s;
  225. typ:=top_regset;
  226. for i:=RS_R0 to RS_R15 do
  227. begin
  228. if assigned(add_reg_instruction_hook) and (i in regset^) then
  229. add_reg_instruction_hook(self,newreg(R_INTREGISTER,i,R_SUBWHOLE));
  230. end;
  231. end;
  232. end;
  233. {*****************************************************************************
  234. taicpu Constructors
  235. *****************************************************************************}
  236. constructor taicpu.op_none(op : tasmop);
  237. begin
  238. inherited create(op);
  239. end;
  240. constructor taicpu.op_reg(op : tasmop;_op1 : tregister);
  241. begin
  242. inherited create(op);
  243. ops:=1;
  244. loadreg(0,_op1);
  245. end;
  246. constructor taicpu.op_const(op : tasmop;_op1 : longint);
  247. begin
  248. inherited create(op);
  249. ops:=1;
  250. loadconst(0,aint(_op1));
  251. end;
  252. constructor taicpu.op_reg_reg(op : tasmop;_op1,_op2 : tregister);
  253. begin
  254. inherited create(op);
  255. ops:=2;
  256. loadreg(0,_op1);
  257. loadreg(1,_op2);
  258. end;
  259. constructor taicpu.op_reg_const(op:tasmop; _op1: tregister; _op2: aint);
  260. begin
  261. inherited create(op);
  262. ops:=2;
  263. loadreg(0,_op1);
  264. loadconst(1,aint(_op2));
  265. end;
  266. constructor taicpu.op_ref_regset(op:tasmop; _op1: treference; _op2: tcpuregisterset);
  267. begin
  268. inherited create(op);
  269. ops:=2;
  270. loadref(0,_op1);
  271. loadregset(1,_op2);
  272. end;
  273. constructor taicpu.op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
  274. begin
  275. inherited create(op);
  276. ops:=2;
  277. loadreg(0,_op1);
  278. loadref(1,_op2);
  279. end;
  280. constructor taicpu.op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
  281. begin
  282. inherited create(op);
  283. ops:=3;
  284. loadreg(0,_op1);
  285. loadreg(1,_op2);
  286. loadreg(2,_op3);
  287. end;
  288. constructor taicpu.op_reg_reg_reg_reg(op : tasmop;_op1,_op2,_op3,_op4 : tregister);
  289. begin
  290. inherited create(op);
  291. ops:=4;
  292. loadreg(0,_op1);
  293. loadreg(1,_op2);
  294. loadreg(2,_op3);
  295. loadreg(3,_op4);
  296. end;
  297. constructor taicpu.op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: aint);
  298. begin
  299. inherited create(op);
  300. ops:=3;
  301. loadreg(0,_op1);
  302. loadreg(1,_op2);
  303. loadconst(2,aint(_op3));
  304. end;
  305. constructor taicpu.op_reg_const_ref(op : tasmop;_op1 : tregister;_op2 : aint;_op3 : treference);
  306. begin
  307. inherited create(op);
  308. ops:=3;
  309. loadreg(0,_op1);
  310. loadconst(1,_op2);
  311. loadref(2,_op3);
  312. end;
  313. constructor taicpu.op_reg_reg_sym_ofs(op : tasmop;_op1,_op2 : tregister; _op3: tasmsymbol;_op3ofs: longint);
  314. begin
  315. inherited create(op);
  316. ops:=3;
  317. loadreg(0,_op1);
  318. loadreg(1,_op2);
  319. loadsymbol(0,_op3,_op3ofs);
  320. end;
  321. constructor taicpu.op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister; const _op3: treference);
  322. begin
  323. inherited create(op);
  324. ops:=3;
  325. loadreg(0,_op1);
  326. loadreg(1,_op2);
  327. loadref(2,_op3);
  328. end;
  329. constructor taicpu.op_reg_reg_shifterop(op : tasmop;_op1,_op2 : tregister;_op3 : tshifterop);
  330. begin
  331. inherited create(op);
  332. ops:=3;
  333. loadreg(0,_op1);
  334. loadreg(1,_op2);
  335. loadshifterop(2,_op3);
  336. end;
  337. constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
  338. begin
  339. inherited create(op);
  340. condition:=cond;
  341. ops:=1;
  342. loadsymbol(0,_op1,0);
  343. end;
  344. constructor taicpu.op_sym(op : tasmop;_op1 : tasmsymbol);
  345. begin
  346. inherited create(op);
  347. ops:=1;
  348. loadsymbol(0,_op1,0);
  349. end;
  350. constructor taicpu.op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
  351. begin
  352. inherited create(op);
  353. ops:=1;
  354. loadsymbol(0,_op1,_op1ofs);
  355. end;
  356. constructor taicpu.op_reg_sym_ofs(op : tasmop;_op1 : tregister;_op2:tasmsymbol;_op2ofs : longint);
  357. begin
  358. inherited create(op);
  359. ops:=2;
  360. loadreg(0,_op1);
  361. loadsymbol(1,_op2,_op2ofs);
  362. end;
  363. constructor taicpu.op_sym_ofs_ref(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  364. begin
  365. inherited create(op);
  366. ops:=2;
  367. loadsymbol(0,_op1,_op1ofs);
  368. loadref(1,_op2);
  369. end;
  370. function taicpu.is_same_reg_move(regtype: Tregistertype):boolean;
  371. begin
  372. { allow the register allocator to remove unnecessary moves }
  373. result:=(((opcode=A_MOV) and (regtype = R_INTREGISTER)) or
  374. ((opcode=A_MVF) and (regtype = R_FPUREGISTER))
  375. ) and
  376. (condition=C_None) and
  377. (ops=2) and
  378. (oper[0]^.typ=top_reg) and
  379. (oper[1]^.typ=top_reg) and
  380. (oper[0]^.reg=oper[1]^.reg);
  381. end;
  382. function spilling_create_load(const ref:treference;r:tregister): tai;
  383. begin
  384. case getregtype(r) of
  385. R_INTREGISTER :
  386. result:=taicpu.op_reg_ref(A_LDR,r,ref);
  387. R_FPUREGISTER :
  388. { use lfm because we don't know the current internal format
  389. and avoid exceptions
  390. }
  391. result:=taicpu.op_reg_const_ref(A_LFM,r,1,ref);
  392. else
  393. internalerror(200401041);
  394. end;
  395. end;
  396. function spilling_create_store(r:tregister; const ref:treference): tai;
  397. begin
  398. case getregtype(r) of
  399. R_INTREGISTER :
  400. result:=taicpu.op_reg_ref(A_STR,r,ref);
  401. R_FPUREGISTER :
  402. { use sfm because we don't know the current internal format
  403. and avoid exceptions
  404. }
  405. result:=taicpu.op_reg_const_ref(A_SFM,r,1,ref);
  406. else
  407. internalerror(200401041);
  408. end;
  409. end;
  410. function taicpu.spilling_get_operation_type(opnr: longint): topertype;
  411. begin
  412. case opcode of
  413. A_ADC,A_ADD,A_AND,
  414. A_EOR,A_CLZ,
  415. A_LDR,A_LDRB,A_LDRBT,A_LDRH,A_LDRSB,
  416. A_LDRSH,A_LDRT,
  417. A_MOV,A_MVN,A_MLA,A_MUL,
  418. A_ORR,A_RSB,A_RSC,A_SBC,A_SUB,
  419. A_SWP,A_SWPB,
  420. A_LDF,A_FLT,A_FIX,
  421. A_ADF,A_DVF,A_FDV,A_FML,
  422. A_RFS,A_RFC,A_RDF,
  423. A_RMF,A_RPW,A_RSF,A_SUF,A_ABS,A_ACS,A_ASN,A_ATN,A_COS,
  424. A_EXP,A_LOG,A_LGN,A_MVF,A_MNF,A_FRD,A_MUF,A_POL,A_RND,A_SIN,A_SQT,A_TAN,
  425. A_LFM:
  426. if opnr=0 then
  427. result:=operand_write
  428. else
  429. result:=operand_read;
  430. A_BIC,A_BKPT,A_B,A_BL,A_BLX,A_BX,
  431. A_CMN,A_CMP,A_TEQ,A_TST,
  432. A_CMF,A_CMFE,A_WFS,A_CNF:
  433. result:=operand_read;
  434. A_SMLAL,A_UMLAL:
  435. if opnr in [0,1] then
  436. result:=operand_readwrite
  437. else
  438. result:=operand_read;
  439. A_SMULL,A_UMULL:
  440. if opnr in [0,1] then
  441. result:=operand_write
  442. else
  443. result:=operand_read;
  444. A_STR,A_STRB,A_STRBT,
  445. A_STRH,A_STRT,A_STF,A_SFM:
  446. { important is what happens with the involved registers }
  447. if opnr=0 then
  448. result := operand_read
  449. else
  450. { check for pre/post indexed }
  451. result := operand_read;
  452. else
  453. internalerror(200403151);
  454. end;
  455. end;
  456. procedure BuildInsTabCache;
  457. var
  458. i : longint;
  459. begin
  460. new(instabcache);
  461. FillChar(instabcache^,sizeof(tinstabcache),$ff);
  462. i:=0;
  463. while (i<InsTabEntries) do
  464. begin
  465. if InsTabCache^[InsTab[i].Opcode]=-1 then
  466. InsTabCache^[InsTab[i].Opcode]:=i;
  467. inc(i);
  468. end;
  469. end;
  470. procedure InitAsm;
  471. begin
  472. if not assigned(instabcache) then
  473. BuildInsTabCache;
  474. end;
  475. procedure DoneAsm;
  476. begin
  477. if assigned(instabcache) then
  478. begin
  479. dispose(instabcache);
  480. instabcache:=nil;
  481. end;
  482. end;
  483. function setoppostfix(i : taicpu;pf : toppostfix) : taicpu;
  484. begin
  485. i.oppostfix:=pf;
  486. result:=i;
  487. end;
  488. function setroundingmode(i : taicpu;rm : troundingmode) : taicpu;
  489. begin
  490. i.roundingmode:=rm;
  491. result:=i;
  492. end;
  493. function setcondition(i : taicpu;c : tasmcond) : taicpu;
  494. begin
  495. i.condition:=c;
  496. result:=i;
  497. end;
  498. procedure insertpcrelativedata(list,listtoinsert : taasmoutput);
  499. var
  500. curpos : longint;
  501. lastpos : longint;
  502. curop : longint;
  503. curtai : tai;
  504. curdatatai,hp : tai;
  505. curdata : taasmoutput;
  506. l : tasmlabel;
  507. begin
  508. curdata:=taasmoutput.create;
  509. lastpos:=-1;
  510. curpos:=0;
  511. curtai:=tai(list.first);
  512. while assigned(curtai) do
  513. begin
  514. { instruction? }
  515. if curtai.typ=ait_instruction then
  516. begin
  517. { walk through all operand of the instruction }
  518. for curop:=0 to taicpu(curtai).ops-1 do
  519. begin
  520. { reference? }
  521. if (taicpu(curtai).oper[curop]^.typ=top_ref) then
  522. begin
  523. { pc relative symbol? }
  524. curdatatai:=tai(taicpu(curtai).oper[curop]^.ref^.symboldata);
  525. if assigned(curdatatai) then
  526. begin
  527. { if yes, insert till next symbol }
  528. repeat
  529. hp:=tai(curdatatai.next);
  530. listtoinsert.remove(curdatatai);
  531. curdata.concat(curdatatai);
  532. curdatatai:=hp;
  533. until (curdatatai=nil) or (curdatatai.typ=ait_label);
  534. if lastpos=-1 then
  535. lastpos:=curpos;
  536. end;
  537. end;
  538. end;
  539. inc(curpos);
  540. end;
  541. { split only at real instructions else the test below fails }
  542. if ((curpos-lastpos)>1016) and (curtai.typ=ait_instruction) and
  543. (
  544. { don't split loads of pc to lr and the following move }
  545. not(
  546. (taicpu(curtai).opcode=A_MOV) and
  547. (taicpu(curtai).oper[0]^.typ=top_reg) and
  548. (taicpu(curtai).oper[0]^.reg=NR_R14) and
  549. (taicpu(curtai).oper[1]^.typ=top_reg) and
  550. (taicpu(curtai).oper[1]^.reg=NR_PC)
  551. )
  552. ) then
  553. begin
  554. lastpos:=curpos;
  555. hp:=tai(curtai.next);
  556. objectlibrary.getjumplabel(l);
  557. curdata.insert(taicpu.op_sym(A_B,l));
  558. curdata.concat(tai_label.create(l));
  559. list.insertlistafter(curtai,curdata);
  560. curtai:=hp;
  561. end
  562. else
  563. curtai:=tai(curtai.next);
  564. end;
  565. list.concatlist(curdata);
  566. curdata.free;
  567. end;
  568. (*
  569. Floating point instruction format information, taken from the linux kernel
  570. ARM Floating Point Instruction Classes
  571. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  572. |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
  573. |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|1|0| o f f s e t | CPDT (copro 2)
  574. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  575. |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
  576. |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
  577. |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
  578. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  579. CPDT data transfer instructions
  580. LDF, STF, LFM (copro 2), SFM (copro 2)
  581. CPDO dyadic arithmetic instructions
  582. ADF, MUF, SUF, RSF, DVF, RDF,
  583. POW, RPW, RMF, FML, FDV, FRD, POL
  584. CPDO monadic arithmetic instructions
  585. MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
  586. SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
  587. CPRT joint arithmetic/data transfer instructions
  588. FIX (arithmetic followed by load/store)
  589. FLT (load/store followed by arithmetic)
  590. CMF, CNF CMFE, CNFE (comparisons)
  591. WFS, RFS (write/read floating point status register)
  592. WFC, RFC (write/read floating point control register)
  593. cond condition codes
  594. P pre/post index bit: 0 = postindex, 1 = preindex
  595. U up/down bit: 0 = stack grows down, 1 = stack grows up
  596. W write back bit: 1 = update base register (Rn)
  597. L load/store bit: 0 = store, 1 = load
  598. Rn base register
  599. Rd destination/source register
  600. Fd floating point destination register
  601. Fn floating point source register
  602. Fm floating point source register or floating point constant
  603. uv transfer length (TABLE 1)
  604. wx register count (TABLE 2)
  605. abcd arithmetic opcode (TABLES 3 & 4)
  606. ef destination size (rounding precision) (TABLE 5)
  607. gh rounding mode (TABLE 6)
  608. j dyadic/monadic bit: 0 = dyadic, 1 = monadic
  609. i constant bit: 1 = constant (TABLE 6)
  610. */
  611. /*
  612. TABLE 1
  613. +-------------------------+---+---+---------+---------+
  614. | Precision | u | v | FPSR.EP | length |
  615. +-------------------------+---+---+---------+---------+
  616. | Single | 0 | 0 | x | 1 words |
  617. | Double | 1 | 1 | x | 2 words |
  618. | Extended | 1 | 1 | x | 3 words |
  619. | Packed decimal | 1 | 1 | 0 | 3 words |
  620. | Expanded packed decimal | 1 | 1 | 1 | 4 words |
  621. +-------------------------+---+---+---------+---------+
  622. Note: x = don't care
  623. */
  624. /*
  625. TABLE 2
  626. +---+---+---------------------------------+
  627. | w | x | Number of registers to transfer |
  628. +---+---+---------------------------------+
  629. | 0 | 1 | 1 |
  630. | 1 | 0 | 2 |
  631. | 1 | 1 | 3 |
  632. | 0 | 0 | 4 |
  633. +---+---+---------------------------------+
  634. */
  635. /*
  636. TABLE 3: Dyadic Floating Point Opcodes
  637. +---+---+---+---+----------+-----------------------+-----------------------+
  638. | a | b | c | d | Mnemonic | Description | Operation |
  639. +---+---+---+---+----------+-----------------------+-----------------------+
  640. | 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm |
  641. | 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm |
  642. | 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm |
  643. | 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn |
  644. | 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm |
  645. | 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn |
  646. | 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm |
  647. | 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn |
  648. | 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) |
  649. | 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm |
  650. | 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm |
  651. | 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn |
  652. | 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) |
  653. | 1 | 1 | 0 | 1 | | undefined instruction | trap |
  654. | 1 | 1 | 1 | 0 | | undefined instruction | trap |
  655. | 1 | 1 | 1 | 1 | | undefined instruction | trap |
  656. +---+---+---+---+----------+-----------------------+-----------------------+
  657. Note: POW, RPW, POL are deprecated, and are available for backwards
  658. compatibility only.
  659. */
  660. /*
  661. TABLE 4: Monadic Floating Point Opcodes
  662. +---+---+---+---+----------+-----------------------+-----------------------+
  663. | a | b | c | d | Mnemonic | Description | Operation |
  664. +---+---+---+---+----------+-----------------------+-----------------------+
  665. | 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm |
  666. | 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm |
  667. | 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) |
  668. | 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) |
  669. | 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) |
  670. | 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) |
  671. | 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) |
  672. | 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm |
  673. | 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) |
  674. | 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) |
  675. | 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) |
  676. | 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) |
  677. | 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) |
  678. | 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) |
  679. | 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) |
  680. | 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) |
  681. +---+---+---+---+----------+-----------------------+-----------------------+
  682. Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are
  683. available for backwards compatibility only.
  684. */
  685. /*
  686. TABLE 5
  687. +-------------------------+---+---+
  688. | Rounding Precision | e | f |
  689. +-------------------------+---+---+
  690. | IEEE Single precision | 0 | 0 |
  691. | IEEE Double precision | 0 | 1 |
  692. | IEEE Extended precision | 1 | 0 |
  693. | undefined (trap) | 1 | 1 |
  694. +-------------------------+---+---+
  695. */
  696. /*
  697. TABLE 5
  698. +---------------------------------+---+---+
  699. | Rounding Mode | g | h |
  700. +---------------------------------+---+---+
  701. | Round to nearest (default) | 0 | 0 |
  702. | Round toward plus infinity | 0 | 1 |
  703. | Round toward negative infinity | 1 | 0 |
  704. | Round toward zero | 1 | 1 |
  705. +---------------------------------+---+---+
  706. *)
  707. function taicpu.GetString:string;
  708. var
  709. i : longint;
  710. s : string;
  711. addsize : boolean;
  712. begin
  713. s:='['+gas_op2str[opcode];
  714. for i:=0 to ops-1 do
  715. begin
  716. with oper[i]^ do
  717. begin
  718. if i=0 then
  719. s:=s+' '
  720. else
  721. s:=s+',';
  722. { type }
  723. addsize:=false;
  724. if (ot and OT_VREG)=OT_VREG then
  725. s:=s+'vreg'
  726. else
  727. if (ot and OT_FPUREG)=OT_FPUREG then
  728. s:=s+'fpureg'
  729. else
  730. if (ot and OT_REGISTER)=OT_REGISTER then
  731. begin
  732. s:=s+'reg';
  733. addsize:=true;
  734. end
  735. else
  736. if (ot and OT_REGLIST)=OT_REGLIST then
  737. begin
  738. s:=s+'reglist';
  739. addsize:=false;
  740. end
  741. else
  742. if (ot and OT_IMMEDIATE)=OT_IMMEDIATE then
  743. begin
  744. s:=s+'imm';
  745. addsize:=true;
  746. end
  747. else
  748. if (ot and OT_MEMORY)=OT_MEMORY then
  749. begin
  750. s:=s+'mem';
  751. addsize:=true;
  752. if (ot and OT_AM2)<>0 then
  753. s:=s+' am2 ';
  754. end
  755. else
  756. s:=s+'???';
  757. { size }
  758. if addsize then
  759. begin
  760. if (ot and OT_BITS8)<>0 then
  761. s:=s+'8'
  762. else
  763. if (ot and OT_BITS16)<>0 then
  764. s:=s+'24'
  765. else
  766. if (ot and OT_BITS32)<>0 then
  767. s:=s+'32'
  768. else
  769. if (ot and OT_BITSSHIFTER)<>0 then
  770. s:=s+'shifter'
  771. else
  772. s:=s+'??';
  773. { signed }
  774. if (ot and OT_SIGNED)<>0 then
  775. s:=s+'s';
  776. end;
  777. end;
  778. end;
  779. GetString:=s+']';
  780. end;
  781. procedure taicpu.ResetPass1;
  782. begin
  783. { we need to reset everything here, because the choosen insentry
  784. can be invalid for a new situation where the previously optimized
  785. insentry is not correct }
  786. InsEntry:=nil;
  787. InsSize:=0;
  788. LastInsOffset:=-1;
  789. end;
  790. procedure taicpu.ResetPass2;
  791. begin
  792. { we are here in a second pass, check if the instruction can be optimized }
  793. if assigned(InsEntry) and
  794. ((InsEntry^.flags and IF_PASS2)<>0) then
  795. begin
  796. InsEntry:=nil;
  797. InsSize:=0;
  798. end;
  799. LastInsOffset:=-1;
  800. end;
  801. function taicpu.CheckIfValid:boolean;
  802. begin
  803. end;
  804. function taicpu.Pass1(objdata:TObjData):longint;
  805. var
  806. ldr2op : array[PF_B..PF_T] of tasmop = (
  807. A_LDRB,A_LDRSB,A_LDRBT,A_LDRH,A_LDRSH,A_LDRT);
  808. str2op : array[PF_B..PF_T] of tasmop = (
  809. A_STRB,A_None,A_STRBT,A_STRH,A_None,A_STRT);
  810. begin
  811. Pass1:=0;
  812. { Save the old offset and set the new offset }
  813. InsOffset:=ObjData.CurrObjSec.Size;
  814. { Error? }
  815. if (Insentry=nil) and (InsSize=-1) then
  816. exit;
  817. { set the file postion }
  818. aktfilepos:=fileinfo;
  819. { tranlate LDR+postfix to complete opcode }
  820. if (opcode=A_LDR) and (oppostfix<>PF_None) then
  821. begin
  822. if (oppostfix in [low(ldr2op)..high(ldr2op)]) then
  823. opcode:=ldr2op[oppostfix]
  824. else
  825. internalerror(2005091001);
  826. if opcode=A_None then
  827. internalerror(2005091004);
  828. { postfix has been added to opcode }
  829. oppostfix:=PF_None;
  830. end
  831. else if (opcode=A_STR) and (oppostfix<>PF_None) then
  832. begin
  833. if (oppostfix in [low(str2op)..high(str2op)]) then
  834. opcode:=str2op[oppostfix]
  835. else
  836. internalerror(2005091002);
  837. if opcode=A_None then
  838. internalerror(2005091003);
  839. { postfix has been added to opcode }
  840. oppostfix:=PF_None;
  841. end;
  842. { Get InsEntry }
  843. if FindInsEntry(objdata) then
  844. begin
  845. InsSize:=4;
  846. LastInsOffset:=InsOffset;
  847. Pass1:=InsSize;
  848. exit;
  849. end;
  850. LastInsOffset:=-1;
  851. end;
  852. procedure taicpu.Pass2(objdata:TObjData);
  853. begin
  854. { error in pass1 ? }
  855. if insentry=nil then
  856. exit;
  857. aktfilepos:=fileinfo;
  858. { Generate the instruction }
  859. GenCode(objdata);
  860. end;
  861. procedure taicpu.ppuloadoper(ppufile:tcompilerppufile;var o:toper);
  862. begin
  863. end;
  864. procedure taicpu.ppuwriteoper(ppufile:tcompilerppufile;const o:toper);
  865. begin
  866. end;
  867. procedure taicpu.ppubuildderefimploper(var o:toper);
  868. begin
  869. end;
  870. procedure taicpu.ppuderefoper(var o:toper);
  871. begin
  872. end;
  873. function taicpu.InsEnd:longint;
  874. begin
  875. end;
  876. procedure taicpu.create_ot(objdata:TObjData);
  877. var
  878. i,l,relsize : longint;
  879. dummy : byte;
  880. currsym : TObjSymbol;
  881. begin
  882. if ops=0 then
  883. exit;
  884. { update oper[].ot field }
  885. for i:=0 to ops-1 do
  886. with oper[i]^ do
  887. begin
  888. case typ of
  889. top_regset:
  890. begin
  891. ot:=OT_REGLIST;
  892. end;
  893. top_reg :
  894. begin
  895. case getregtype(reg) of
  896. R_INTREGISTER:
  897. ot:=OT_REG32 or OT_SHIFTEROP;
  898. R_FPUREGISTER:
  899. ot:=OT_FPUREG;
  900. else
  901. internalerror(2005090901);
  902. end;
  903. end;
  904. top_ref :
  905. begin
  906. if ref^.refaddr=addr_no then
  907. begin
  908. { create ot field }
  909. { we should get the size here dependend on the
  910. instruction }
  911. if (ot and OT_SIZE_MASK)=0 then
  912. ot:=OT_MEMORY or OT_BITS32
  913. else
  914. ot:=OT_MEMORY or (ot and OT_SIZE_MASK);
  915. if (ref^.base=NR_NO) and (ref^.index=NR_NO) then
  916. ot:=ot or OT_MEM_OFFS;
  917. { if we need to fix a reference, we do it here }
  918. { pc relative addressing }
  919. if (ref^.base=NR_NO) and
  920. (ref^.index=NR_NO) and
  921. (ref^.shiftmode=SM_None)
  922. { at least we should check if the destination symbol
  923. is in a text section }
  924. { and
  925. (ref^.symbol^.owner="text") } then
  926. ref^.base:=NR_PC;
  927. { determine possible address modes }
  928. if (ref^.base<>NR_NO) and
  929. (
  930. (
  931. (ref^.index=NR_NO) and
  932. (ref^.shiftmode=SM_None) and
  933. (ref^.offset>=-4097) and
  934. (ref^.offset<=4097)
  935. ) or
  936. (
  937. (ref^.shiftmode=SM_None) and
  938. (ref^.offset=0)
  939. ) or
  940. (
  941. (ref^.index<>NR_NO) and
  942. (ref^.shiftmode<>SM_None) and
  943. (ref^.shiftimm<=31) and
  944. (ref^.offset=0)
  945. )
  946. ) then
  947. ot:=ot or OT_AM2;
  948. if (ref^.index<>NR_NO) and
  949. (oppostfix in [PF_IA,PF_IB,PF_DA,PF_DB,PF_FD,PF_FA,PF_ED,PF_EA]) and
  950. (
  951. (ref^.base=NR_NO) and
  952. (ref^.shiftmode=SM_None) and
  953. (ref^.offset=0)
  954. ) then
  955. ot:=ot or OT_AM4;
  956. end
  957. else
  958. begin
  959. l:=ref^.offset;
  960. currsym:=ObjData.symbolref(ref^.symbol);
  961. if assigned(currsym) then
  962. inc(l,currsym.address);
  963. relsize:=(InsOffset+2)-l;
  964. if (relsize<-33554428) or (relsize>33554428) then
  965. ot:=OT_IMM32
  966. else
  967. ot:=OT_IMM24;
  968. end;
  969. end;
  970. top_local :
  971. begin
  972. { we should get the size here dependend on the
  973. instruction }
  974. if (ot and OT_SIZE_MASK)=0 then
  975. ot:=OT_MEMORY or OT_BITS32
  976. else
  977. ot:=OT_MEMORY or (ot and OT_SIZE_MASK);
  978. end;
  979. top_const :
  980. begin
  981. ot:=OT_IMMEDIATE;
  982. if is_shifter_const(val,dummy) then
  983. ot:=OT_IMMSHIFTER
  984. else
  985. ot:=OT_IMM32
  986. end;
  987. top_none :
  988. begin
  989. { generated when there was an error in the
  990. assembler reader. It never happends when generating
  991. assembler }
  992. end;
  993. top_shifterop:
  994. begin
  995. ot:=OT_SHIFTEROP;
  996. end;
  997. else
  998. internalerror(200402261);
  999. end;
  1000. end;
  1001. end;
  1002. function taicpu.Matches(p:PInsEntry):longint;
  1003. { * IF_SM stands for Size Match: any operand whose size is not
  1004. * explicitly specified by the template is `really' intended to be
  1005. * the same size as the first size-specified operand.
  1006. * Non-specification is tolerated in the input instruction, but
  1007. * _wrong_ specification is not.
  1008. *
  1009. * IF_SM2 invokes Size Match on only the first _two_ operands, for
  1010. * three-operand instructions such as SHLD: it implies that the
  1011. * first two operands must match in size, but that the third is
  1012. * required to be _unspecified_.
  1013. *
  1014. * IF_SB invokes Size Byte: operands with unspecified size in the
  1015. * template are really bytes, and so no non-byte specification in
  1016. * the input instruction will be tolerated. IF_SW similarly invokes
  1017. * Size Word, and IF_SD invokes Size Doubleword.
  1018. *
  1019. * (The default state if neither IF_SM nor IF_SM2 is specified is
  1020. * that any operand with unspecified size in the template is
  1021. * required to have unspecified size in the instruction too...)
  1022. }
  1023. var
  1024. i,j,asize,oprs : longint;
  1025. siz : array[0..3] of longint;
  1026. begin
  1027. Matches:=100;
  1028. writeln(getstring,'---');
  1029. { Check the opcode and operands }
  1030. if (p^.opcode<>opcode) or (p^.ops<>ops) then
  1031. begin
  1032. Matches:=0;
  1033. exit;
  1034. end;
  1035. { Check that no spurious colons or TOs are present }
  1036. for i:=0 to p^.ops-1 do
  1037. if (oper[i]^.ot and (not p^.optypes[i]) and (OT_COLON or OT_TO))<>0 then
  1038. begin
  1039. Matches:=0;
  1040. exit;
  1041. end;
  1042. { Check that the operand flags all match up }
  1043. for i:=0 to p^.ops-1 do
  1044. begin
  1045. if ((p^.optypes[i] and (not oper[i]^.ot)) or
  1046. ((p^.optypes[i] and OT_SIZE_MASK) and
  1047. ((p^.optypes[i] xor oper[i]^.ot) and OT_SIZE_MASK)))<>0 then
  1048. begin
  1049. if ((p^.optypes[i] and (not oper[i]^.ot) and OT_NON_SIZE) or
  1050. (oper[i]^.ot and OT_SIZE_MASK))<>0 then
  1051. begin
  1052. Matches:=0;
  1053. exit;
  1054. end
  1055. else
  1056. Matches:=1;
  1057. end;
  1058. end;
  1059. { check postfixes:
  1060. the existance of a certain postfix requires a
  1061. particular code }
  1062. { update condition flags
  1063. or floating point single }
  1064. if (oppostfix=PF_S) and
  1065. not(p^.code[0] in [#$04]) then
  1066. begin
  1067. Matches:=0;
  1068. exit;
  1069. end;
  1070. { floating point size }
  1071. if (oppostfix in [PF_D,PF_E,PF_P,PF_EP]) and
  1072. not(p^.code[0] in []) then
  1073. begin
  1074. Matches:=0;
  1075. exit;
  1076. end;
  1077. { multiple load/store address modes }
  1078. if (oppostfix in [PF_IA,PF_IB,PF_DA,PF_DB,PF_FD,PF_FA,PF_ED,PF_EA]) and
  1079. not(p^.code[0] in [
  1080. // ldr,str,ldrb,strb
  1081. #$17,
  1082. // stm,ldm
  1083. #$26
  1084. ]) then
  1085. begin
  1086. Matches:=0;
  1087. exit;
  1088. end;
  1089. { we shouldn't see any opsize prefixes here }
  1090. if (oppostfix in [PF_B,PF_SB,PF_BT,PF_H,PF_SH,PF_T]) then
  1091. begin
  1092. Matches:=0;
  1093. exit;
  1094. end;
  1095. if (roundingmode<>RM_None) and not(p^.code[0] in []) then
  1096. begin
  1097. Matches:=0;
  1098. exit;
  1099. end;
  1100. { Check operand sizes }
  1101. { as default an untyped size can get all the sizes, this is different
  1102. from nasm, but else we need to do a lot checking which opcodes want
  1103. size or not with the automatic size generation }
  1104. asize:=longint($ffffffff);
  1105. (*
  1106. if (p^.flags and IF_SB)<>0 then
  1107. asize:=OT_BITS8
  1108. else if (p^.flags and IF_SW)<>0 then
  1109. asize:=OT_BITS16
  1110. else if (p^.flags and IF_SD)<>0 then
  1111. asize:=OT_BITS32;
  1112. if (p^.flags and IF_ARMASK)<>0 then
  1113. begin
  1114. siz[0]:=0;
  1115. siz[1]:=0;
  1116. siz[2]:=0;
  1117. if (p^.flags and IF_AR0)<>0 then
  1118. siz[0]:=asize
  1119. else if (p^.flags and IF_AR1)<>0 then
  1120. siz[1]:=asize
  1121. else if (p^.flags and IF_AR2)<>0 then
  1122. siz[2]:=asize;
  1123. end
  1124. else
  1125. begin
  1126. { we can leave because the size for all operands is forced to be
  1127. the same
  1128. but not if IF_SB IF_SW or IF_SD is set PM }
  1129. if asize=-1 then
  1130. exit;
  1131. siz[0]:=asize;
  1132. siz[1]:=asize;
  1133. siz[2]:=asize;
  1134. end;
  1135. if (p^.flags and (IF_SM or IF_SM2))<>0 then
  1136. begin
  1137. if (p^.flags and IF_SM2)<>0 then
  1138. oprs:=2
  1139. else
  1140. oprs:=p^.ops;
  1141. for i:=0 to oprs-1 do
  1142. if ((p^.optypes[i] and OT_SIZE_MASK) <> 0) then
  1143. begin
  1144. for j:=0 to oprs-1 do
  1145. siz[j]:=p^.optypes[i] and OT_SIZE_MASK;
  1146. break;
  1147. end;
  1148. end
  1149. else
  1150. oprs:=2;
  1151. { Check operand sizes }
  1152. for i:=0 to p^.ops-1 do
  1153. begin
  1154. if ((p^.optypes[i] and OT_SIZE_MASK)=0) and
  1155. ((oper[i]^.ot and OT_SIZE_MASK and (not siz[i]))<>0) and
  1156. { Immediates can always include smaller size }
  1157. ((oper[i]^.ot and OT_IMMEDIATE)=0) and
  1158. (((p^.optypes[i] and OT_SIZE_MASK) or siz[i])<(oper[i]^.ot and OT_SIZE_MASK)) then
  1159. Matches:=2;
  1160. end;
  1161. *)
  1162. end;
  1163. function taicpu.calcsize(p:PInsEntry):shortint;
  1164. begin
  1165. result:=4;
  1166. end;
  1167. function taicpu.NeedAddrPrefix(opidx:byte):boolean;
  1168. begin
  1169. end;
  1170. procedure taicpu.Swapoperands;
  1171. begin
  1172. end;
  1173. function taicpu.FindInsentry(objdata:TObjData):boolean;
  1174. var
  1175. i : longint;
  1176. begin
  1177. result:=false;
  1178. { Things which may only be done once, not when a second pass is done to
  1179. optimize }
  1180. if (Insentry=nil) or ((InsEntry^.flags and IF_PASS2)<>0) then
  1181. begin
  1182. { create the .ot fields }
  1183. create_ot(objdata);
  1184. { set the file postion }
  1185. aktfilepos:=fileinfo;
  1186. end
  1187. else
  1188. begin
  1189. { we've already an insentry so it's valid }
  1190. result:=true;
  1191. exit;
  1192. end;
  1193. { Lookup opcode in the table }
  1194. InsSize:=-1;
  1195. i:=instabcache^[opcode];
  1196. if i=-1 then
  1197. begin
  1198. Message1(asmw_e_opcode_not_in_table,gas_op2str[opcode]);
  1199. exit;
  1200. end;
  1201. insentry:=@instab[i];
  1202. while (insentry^.opcode=opcode) do
  1203. begin
  1204. if matches(insentry)=100 then
  1205. begin
  1206. result:=true;
  1207. exit;
  1208. end;
  1209. inc(i);
  1210. insentry:=@instab[i];
  1211. end;
  1212. Message1(asmw_e_invalid_opcode_and_operands,GetString);
  1213. { No instruction found, set insentry to nil and inssize to -1 }
  1214. insentry:=nil;
  1215. inssize:=-1;
  1216. end;
  1217. procedure taicpu.gencode(objdata:TObjData);
  1218. var
  1219. bytes : dword;
  1220. i_field : byte;
  1221. procedure setshifterop(op : byte);
  1222. begin
  1223. case oper[op]^.typ of
  1224. top_const:
  1225. begin
  1226. i_field:=1;
  1227. bytes:=bytes or (oper[op]^.val and $fff);
  1228. end;
  1229. top_reg:
  1230. begin
  1231. i_field:=0;
  1232. bytes:=bytes or (getsupreg(oper[op]^.reg) shl 16);
  1233. { does a real shifter op follow? }
  1234. if (op+1<=op) and (oper[op+1]^.typ=top_shifterop) then
  1235. begin
  1236. end;
  1237. end;
  1238. else
  1239. internalerror(2005091103);
  1240. end;
  1241. end;
  1242. begin
  1243. bytes:=$0;
  1244. { evaluate and set condition code }
  1245. { condition code allowed? }
  1246. { setup rest of the instruction }
  1247. case insentry^.code[0] of
  1248. #$08:
  1249. begin
  1250. { set instruction code }
  1251. bytes:=bytes or (ord(insentry^.code[1]) shl 26);
  1252. bytes:=bytes or (ord(insentry^.code[2]) shl 21);
  1253. { set destination }
  1254. bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
  1255. { create shifter op }
  1256. setshifterop(1);
  1257. { set i field }
  1258. bytes:=bytes or (i_field shl 25);
  1259. { set s if necessary }
  1260. if oppostfix=PF_S then
  1261. bytes:=bytes or (1 shl 20);
  1262. end;
  1263. #$ff:
  1264. internalerror(2005091101);
  1265. else
  1266. internalerror(2005091102);
  1267. end;
  1268. { we're finished, write code }
  1269. objdata.writebytes(bytes,sizeof(bytes));
  1270. end;
  1271. end.
  1272. {$ifdef dummy}
  1273. (*
  1274. static void gencode (long segment, long offset, int bits,
  1275. insn *ins, char *codes, long insn_end)
  1276. {
  1277. int has_S_code; /* S - setflag */
  1278. int has_B_code; /* B - setflag */
  1279. int has_T_code; /* T - setflag */
  1280. int has_W_code; /* ! => W flag */
  1281. int has_F_code; /* ^ => S flag */
  1282. int keep;
  1283. unsigned char c;
  1284. unsigned char bytes[4];
  1285. long data, size;
  1286. static int cc_code[] = /* bit pattern of cc */
  1287. { /* order as enum in */
  1288. 0x0E, 0x03, 0x02, 0x00, /* nasm.h */
  1289. 0x0A, 0x0C, 0x08, 0x0D,
  1290. 0x09, 0x0B, 0x04, 0x01,
  1291. 0x05, 0x07, 0x06,
  1292. };
  1293. (*
  1294. #ifdef DEBUG
  1295. static char *CC[] =
  1296. { /* condition code names */
  1297. "AL", "CC", "CS", "EQ",
  1298. "GE", "GT", "HI", "LE",
  1299. "LS", "LT", "MI", "NE",
  1300. "PL", "VC", "VS", "",
  1301. "S"
  1302. };
  1303. *)
  1304. has_S_code = (ins->condition & C_SSETFLAG);
  1305. has_B_code = (ins->condition & C_BSETFLAG);
  1306. has_T_code = (ins->condition & C_TSETFLAG);
  1307. has_W_code = (ins->condition & C_EXSETFLAG);
  1308. has_F_code = (ins->condition & C_FSETFLAG);
  1309. ins->condition = (ins->condition & 0x0F);
  1310. (*
  1311. if (rt_debug)
  1312. {
  1313. printf ("gencode: instruction: %s%s", insn_names[ins->opcode],
  1314. CC[ins->condition & 0x0F]);
  1315. if (has_S_code)
  1316. printf ("S");
  1317. if (has_B_code)
  1318. printf ("B");
  1319. if (has_T_code)
  1320. printf ("T");
  1321. if (has_W_code)
  1322. printf ("!");
  1323. if (has_F_code)
  1324. printf ("^");
  1325. printf ("\n");
  1326. c = *codes;
  1327. printf (" (%d) decode - '0x%02X'\n", ins->operands, c);
  1328. bytes[0] = 0xB;
  1329. bytes[1] = 0xE;
  1330. bytes[2] = 0xE;
  1331. bytes[3] = 0xF;
  1332. }
  1333. *)
  1334. // First condition code in upper nibble
  1335. if (ins->condition < C_NONE)
  1336. {
  1337. c = cc_code[ins->condition] << 4;
  1338. }
  1339. else
  1340. {
  1341. c = cc_code[C_AL] << 4; // is often ALWAYS but not always
  1342. }
  1343. switch (keep = *codes)
  1344. {
  1345. case 1:
  1346. // B, BL
  1347. ++codes;
  1348. c |= *codes++;
  1349. bytes[0] = c;
  1350. if (ins->oprs[0].segment != segment)
  1351. {
  1352. // fais une relocation
  1353. c = 1;
  1354. data = 0; // Let the linker locate ??
  1355. }
  1356. else
  1357. {
  1358. c = 0;
  1359. data = ins->oprs[0].offset - (offset + 8);
  1360. if (data % 4)
  1361. {
  1362. errfunc (ERR_NONFATAL, "offset not aligned on 4 bytes");
  1363. }
  1364. }
  1365. if (data >= 0x1000)
  1366. {
  1367. errfunc (ERR_NONFATAL, "too long offset");
  1368. }
  1369. data = data >> 2;
  1370. bytes[1] = (data >> 16) & 0xFF;
  1371. bytes[2] = (data >> 8) & 0xFF;
  1372. bytes[3] = (data ) & 0xFF;
  1373. if (c == 1)
  1374. {
  1375. // out (offset, segment, &bytes[0], OUT_RAWDATA+1, NO_SEG, NO_SEG);
  1376. out (offset, segment, &bytes[0], OUT_REL3ADR+4, ins->oprs[0].segment, NO_SEG);
  1377. }
  1378. else
  1379. {
  1380. out (offset, segment, &bytes[0], OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1381. }
  1382. return;
  1383. case 2:
  1384. // SWI
  1385. ++codes;
  1386. c |= *codes++;
  1387. bytes[0] = c;
  1388. data = ins->oprs[0].offset;
  1389. bytes[1] = (data >> 16) & 0xFF;
  1390. bytes[2] = (data >> 8) & 0xFF;
  1391. bytes[3] = (data) & 0xFF;
  1392. out (offset, segment, &bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1393. return;
  1394. case 3:
  1395. // BX
  1396. ++codes;
  1397. c |= *codes++;
  1398. bytes[0] = c;
  1399. bytes[1] = *codes++;
  1400. bytes[2] = *codes++;
  1401. bytes[3] = *codes++;
  1402. c = regval (&ins->oprs[0],1);
  1403. if (c == 15) // PC
  1404. {
  1405. errfunc (ERR_WARNING, "'BX' with R15 has undefined behaviour");
  1406. }
  1407. else if (c > 15)
  1408. {
  1409. errfunc (ERR_NONFATAL, "Illegal register specified for 'BX'");
  1410. }
  1411. bytes[3] |= (c & 0x0F);
  1412. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1413. return;
  1414. case 4: // AND Rd,Rn,Rm
  1415. case 5: // AND Rd,Rn,Rm,<shift>Rs
  1416. case 6: // AND Rd,Rn,Rm,<shift>imm
  1417. case 7: // AND Rd,Rn,<shift>imm
  1418. ++codes;
  1419. #ifdef DEBUG
  1420. if (rt_debug)
  1421. {
  1422. printf (" decode - '0x%02X'\n", keep);
  1423. printf (" code - '0x%02X'\n", (unsigned char) ( *codes));
  1424. }
  1425. #endif
  1426. bytes[0] = c | *codes;
  1427. ++codes;
  1428. bytes[1] = *codes;
  1429. if (has_S_code)
  1430. bytes[1] |= 0x10;
  1431. c = regval (&ins->oprs[1],1);
  1432. // Rn in low nibble
  1433. bytes[1] |= c;
  1434. // Rd in high nibble
  1435. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1436. if (keep != 7)
  1437. {
  1438. // Rm in low nibble
  1439. bytes[3] = regval (&ins->oprs[2],1);
  1440. }
  1441. // Shifts if any
  1442. if (keep == 5 || keep == 6)
  1443. {
  1444. // Shift in bytes 2 and 3
  1445. if (keep == 5)
  1446. {
  1447. // Rs
  1448. c = regval (&ins->oprs[3],1);
  1449. bytes[2] |= c;
  1450. c = 0x10; // Set bit 4 in byte[3]
  1451. }
  1452. if (keep == 6)
  1453. {
  1454. c = (ins->oprs[3].offset) & 0x1F;
  1455. // #imm
  1456. bytes[2] |= c >> 1;
  1457. if (c & 0x01)
  1458. {
  1459. bytes[3] |= 0x80;
  1460. }
  1461. c = 0; // Clr bit 4 in byte[3]
  1462. }
  1463. // <shift>
  1464. c |= shiftval (&ins->oprs[3]) << 5;
  1465. bytes[3] |= c;
  1466. }
  1467. // reg,reg,imm
  1468. if (keep == 7)
  1469. {
  1470. int shimm;
  1471. shimm = imm_shift (ins->oprs[2].offset);
  1472. if (shimm == -1)
  1473. {
  1474. errfunc (ERR_NONFATAL, "cannot create that constant");
  1475. }
  1476. bytes[3] = shimm & 0xFF;
  1477. bytes[2] |= (shimm & 0xF00) >> 8;
  1478. }
  1479. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1480. return;
  1481. case 8: // MOV Rd,Rm
  1482. case 9: // MOV Rd,Rm,<shift>Rs
  1483. case 0xA: // MOV Rd,Rm,<shift>imm
  1484. case 0xB: // MOV Rd,<shift>imm
  1485. ++codes;
  1486. #ifdef DEBUG
  1487. if (rt_debug)
  1488. {
  1489. printf (" decode - '0x%02X'\n", keep);
  1490. printf (" code - '0x%02X'\n", (unsigned char) ( *codes));
  1491. }
  1492. #endif
  1493. bytes[0] = c | *codes;
  1494. ++codes;
  1495. bytes[1] = *codes;
  1496. if (has_S_code)
  1497. bytes[1] |= 0x10;
  1498. // Rd in high nibble
  1499. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1500. if (keep != 0x0B)
  1501. {
  1502. // Rm in low nibble
  1503. bytes[3] = regval (&ins->oprs[1],1);
  1504. }
  1505. // Shifts if any
  1506. if (keep == 0x09 || keep == 0x0A)
  1507. {
  1508. // Shift in bytes 2 and 3
  1509. if (keep == 0x09)
  1510. {
  1511. // Rs
  1512. c = regval (&ins->oprs[2],1);
  1513. bytes[2] |= c;
  1514. c = 0x10; // Set bit 4 in byte[3]
  1515. }
  1516. if (keep == 0x0A)
  1517. {
  1518. c = (ins->oprs[2].offset) & 0x1F;
  1519. // #imm
  1520. bytes[2] |= c >> 1;
  1521. if (c & 0x01)
  1522. {
  1523. bytes[3] |= 0x80;
  1524. }
  1525. c = 0; // Clr bit 4 in byte[3]
  1526. }
  1527. // <shift>
  1528. c |= shiftval (&ins->oprs[2]) << 5;
  1529. bytes[3] |= c;
  1530. }
  1531. // reg,imm
  1532. if (keep == 0x0B)
  1533. {
  1534. int shimm;
  1535. shimm = imm_shift (ins->oprs[1].offset);
  1536. if (shimm == -1)
  1537. {
  1538. errfunc (ERR_NONFATAL, "cannot create that constant");
  1539. }
  1540. bytes[3] = shimm & 0xFF;
  1541. bytes[2] |= (shimm & 0xF00) >> 8;
  1542. }
  1543. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1544. return;
  1545. case 0xC: // CMP Rn,Rm
  1546. case 0xD: // CMP Rn,Rm,<shift>Rs
  1547. case 0xE: // CMP Rn,Rm,<shift>imm
  1548. case 0xF: // CMP Rn,<shift>imm
  1549. ++codes;
  1550. bytes[0] = c | *codes++;
  1551. bytes[1] = *codes;
  1552. // Implicit S code
  1553. bytes[1] |= 0x10;
  1554. c = regval (&ins->oprs[0],1);
  1555. // Rn in low nibble
  1556. bytes[1] |= c;
  1557. // No destination
  1558. bytes[2] = 0;
  1559. if (keep != 0x0B)
  1560. {
  1561. // Rm in low nibble
  1562. bytes[3] = regval (&ins->oprs[1],1);
  1563. }
  1564. // Shifts if any
  1565. if (keep == 0x0D || keep == 0x0E)
  1566. {
  1567. // Shift in bytes 2 and 3
  1568. if (keep == 0x0D)
  1569. {
  1570. // Rs
  1571. c = regval (&ins->oprs[2],1);
  1572. bytes[2] |= c;
  1573. c = 0x10; // Set bit 4 in byte[3]
  1574. }
  1575. if (keep == 0x0E)
  1576. {
  1577. c = (ins->oprs[2].offset) & 0x1F;
  1578. // #imm
  1579. bytes[2] |= c >> 1;
  1580. if (c & 0x01)
  1581. {
  1582. bytes[3] |= 0x80;
  1583. }
  1584. c = 0; // Clr bit 4 in byte[3]
  1585. }
  1586. // <shift>
  1587. c |= shiftval (&ins->oprs[2]) << 5;
  1588. bytes[3] |= c;
  1589. }
  1590. // reg,imm
  1591. if (keep == 0x0F)
  1592. {
  1593. int shimm;
  1594. shimm = imm_shift (ins->oprs[1].offset);
  1595. if (shimm == -1)
  1596. {
  1597. errfunc (ERR_NONFATAL, "cannot create that constant");
  1598. }
  1599. bytes[3] = shimm & 0xFF;
  1600. bytes[2] |= (shimm & 0xF00) >> 8;
  1601. }
  1602. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1603. return;
  1604. case 0x10: // MRS Rd,<psr>
  1605. ++codes;
  1606. bytes[0] = c | *codes++;
  1607. bytes[1] = *codes++;
  1608. // Rd
  1609. c = regval (&ins->oprs[0],1);
  1610. bytes[2] = c << 4;
  1611. bytes[3] = 0;
  1612. c = ins->oprs[1].basereg;
  1613. if (c == R_CPSR || c == R_SPSR)
  1614. {
  1615. if (c == R_SPSR)
  1616. {
  1617. bytes[1] |= 0x40;
  1618. }
  1619. }
  1620. else
  1621. {
  1622. errfunc (ERR_NONFATAL, "CPSR or SPSR expected");
  1623. }
  1624. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  1625. return;
  1626. case 0x11: // MSR <psr>,Rm
  1627. case 0x12: // MSR <psrf>,Rm
  1628. case 0x13: // MSR <psrf>,#expression
  1629. ++codes;
  1630. bytes[0] = c | *codes++;
  1631. bytes[1] = *codes++;
  1632. bytes[2] = *codes;
  1633. if (keep == 0x11 || keep == 0x12)
  1634. {
  1635. // Rm
  1636. c = regval (&ins->oprs[1],1);
  1637. bytes[3] = c;
  1638. }
  1639. else
  1640. {
  1641. int shimm;
  1642. shimm = imm_shift (ins->oprs[1].offset);
  1643. if (shimm == -1)
  1644. {
  1645. errfunc (ERR_NONFATAL, "cannot create that constant");
  1646. }
  1647. bytes[3] = shimm & 0xFF;
  1648. bytes[2] |= (shimm & 0xF00) >> 8;
  1649. }
  1650. c = ins->oprs[0].basereg;
  1651. if ( keep == 0x11)
  1652. {
  1653. if ( c == R_CPSR || c == R_SPSR)
  1654. {
  1655. if ( c== R_SPSR)
  1656. {
  1657. bytes[1] |= 0x40;
  1658. }
  1659. }
  1660. else
  1661. {
  1662. errfunc (ERR_NONFATAL, "CPSR or SPSR expected");
  1663. }
  1664. }
  1665. else
  1666. {
  1667. if ( c == R_CPSR_FLG || c == R_SPSR_FLG)
  1668. {
  1669. if ( c== R_SPSR_FLG)
  1670. {
  1671. bytes[1] |= 0x40;
  1672. }
  1673. }
  1674. else
  1675. {
  1676. errfunc (ERR_NONFATAL, "CPSR_flg or SPSR_flg expected");
  1677. }
  1678. }
  1679. break;
  1680. case 0x14: // MUL Rd,Rm,Rs
  1681. case 0x15: // MULA Rd,Rm,Rs,Rn
  1682. ++codes;
  1683. bytes[0] = c | *codes++;
  1684. bytes[1] = *codes++;
  1685. bytes[3] = *codes;
  1686. // Rd
  1687. bytes[1] |= regval (&ins->oprs[0],1);
  1688. if (has_S_code)
  1689. bytes[1] |= 0x10;
  1690. // Rm
  1691. bytes[3] |= regval (&ins->oprs[1],1);
  1692. // Rs
  1693. bytes[2] = regval (&ins->oprs[2],1);
  1694. if (keep == 0x15)
  1695. {
  1696. bytes[2] |= regval (&ins->oprs[3],1) << 4;
  1697. }
  1698. break;
  1699. case 0x16: // SMLAL RdHi,RdLo,Rm,Rs
  1700. ++codes;
  1701. bytes[0] = c | *codes++;
  1702. bytes[1] = *codes++;
  1703. bytes[3] = *codes;
  1704. // RdHi
  1705. bytes[1] |= regval (&ins->oprs[1],1);
  1706. if (has_S_code)
  1707. bytes[1] |= 0x10;
  1708. // RdLo
  1709. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1710. // Rm
  1711. bytes[3] |= regval (&ins->oprs[2],1);
  1712. // Rs
  1713. bytes[2] |= regval (&ins->oprs[3],1);
  1714. break;
  1715. case 0x17: // LDR Rd, expression
  1716. ++codes;
  1717. bytes[0] = c | *codes++;
  1718. bytes[1] = *codes++;
  1719. // Rd
  1720. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1721. if (has_B_code)
  1722. bytes[1] |= 0x40;
  1723. if (has_T_code)
  1724. {
  1725. errfunc (ERR_NONFATAL, "'T' not allowed in pre-index mode");
  1726. }
  1727. if (has_W_code)
  1728. {
  1729. errfunc (ERR_NONFATAL, "'!' not allowed");
  1730. }
  1731. // Rn - implicit R15
  1732. bytes[1] |= 0xF;
  1733. if (ins->oprs[1].segment != segment)
  1734. {
  1735. errfunc (ERR_NONFATAL, "label not in same segment");
  1736. }
  1737. data = ins->oprs[1].offset - (offset + 8);
  1738. if (data < 0)
  1739. {
  1740. data = -data;
  1741. }
  1742. else
  1743. {
  1744. bytes[1] |= 0x80;
  1745. }
  1746. if (data >= 0x1000)
  1747. {
  1748. errfunc (ERR_NONFATAL, "too long offset");
  1749. }
  1750. bytes[2] |= ((data & 0xF00) >> 8);
  1751. bytes[3] = data & 0xFF;
  1752. break;
  1753. case 0x18: // LDR Rd, [Rn]
  1754. ++codes;
  1755. bytes[0] = c | *codes++;
  1756. bytes[1] = *codes++;
  1757. // Rd
  1758. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1759. if (has_B_code)
  1760. bytes[1] |= 0x40;
  1761. if (has_T_code)
  1762. {
  1763. bytes[1] |= 0x20; // write-back
  1764. }
  1765. else
  1766. {
  1767. bytes[0] |= 0x01; // implicit pre-index mode
  1768. }
  1769. if (has_W_code)
  1770. {
  1771. bytes[1] |= 0x20; // write-back
  1772. }
  1773. // Rn
  1774. c = regval (&ins->oprs[1],1);
  1775. bytes[1] |= c;
  1776. if (c == 0x15) // R15
  1777. data = -8;
  1778. else
  1779. data = 0;
  1780. if (data < 0)
  1781. {
  1782. data = -data;
  1783. }
  1784. else
  1785. {
  1786. bytes[1] |= 0x80;
  1787. }
  1788. bytes[2] |= ((data & 0xF00) >> 8);
  1789. bytes[3] = data & 0xFF;
  1790. break;
  1791. case 0x19: // LDR Rd, [Rn,#expression]
  1792. case 0x20: // LDR Rd, [Rn,Rm]
  1793. case 0x21: // LDR Rd, [Rn,Rm,shift]
  1794. ++codes;
  1795. bytes[0] = c | *codes++;
  1796. bytes[1] = *codes++;
  1797. // Rd
  1798. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1799. if (has_B_code)
  1800. bytes[1] |= 0x40;
  1801. // Rn
  1802. c = regval (&ins->oprs[1],1);
  1803. bytes[1] |= c;
  1804. if (ins->oprs[ins->operands-1].bracket) // FIXME: Bracket on last operand -> pre-index <--
  1805. {
  1806. bytes[0] |= 0x01; // pre-index mode
  1807. if (has_W_code)
  1808. {
  1809. bytes[1] |= 0x20;
  1810. }
  1811. if (has_T_code)
  1812. {
  1813. errfunc (ERR_NONFATAL, "'T' not allowed in pre-index mode");
  1814. }
  1815. }
  1816. else
  1817. {
  1818. if (has_T_code) // Forced write-back in post-index mode
  1819. {
  1820. bytes[1] |= 0x20;
  1821. }
  1822. if (has_W_code)
  1823. {
  1824. errfunc (ERR_NONFATAL, "'!' not allowed in post-index mode");
  1825. }
  1826. }
  1827. if (keep == 0x19)
  1828. {
  1829. data = ins->oprs[2].offset;
  1830. if (data < 0)
  1831. {
  1832. data = -data;
  1833. }
  1834. else
  1835. {
  1836. bytes[1] |= 0x80;
  1837. }
  1838. if (data >= 0x1000)
  1839. {
  1840. errfunc (ERR_NONFATAL, "too long offset");
  1841. }
  1842. bytes[2] |= ((data & 0xF00) >> 8);
  1843. bytes[3] = data & 0xFF;
  1844. }
  1845. else
  1846. {
  1847. if (ins->oprs[2].minus == 0)
  1848. {
  1849. bytes[1] |= 0x80;
  1850. }
  1851. c = regval (&ins->oprs[2],1);
  1852. bytes[3] = c;
  1853. if (keep == 0x21)
  1854. {
  1855. c = ins->oprs[3].offset;
  1856. if (c > 0x1F)
  1857. {
  1858. errfunc (ERR_NONFATAL, "too large shiftvalue");
  1859. c = c & 0x1F;
  1860. }
  1861. bytes[2] |= c >> 1;
  1862. if (c & 0x01)
  1863. {
  1864. bytes[3] |= 0x80;
  1865. }
  1866. bytes[3] |= shiftval (&ins->oprs[3]) << 5;
  1867. }
  1868. }
  1869. break;
  1870. case 0x22: // LDRH Rd, expression
  1871. ++codes;
  1872. bytes[0] = c | 0x01; // Implicit pre-index
  1873. bytes[1] = *codes++;
  1874. // Rd
  1875. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1876. // Rn - implicit R15
  1877. bytes[1] |= 0xF;
  1878. if (ins->oprs[1].segment != segment)
  1879. {
  1880. errfunc (ERR_NONFATAL, "label not in same segment");
  1881. }
  1882. data = ins->oprs[1].offset - (offset + 8);
  1883. if (data < 0)
  1884. {
  1885. data = -data;
  1886. }
  1887. else
  1888. {
  1889. bytes[1] |= 0x80;
  1890. }
  1891. if (data >= 0x100)
  1892. {
  1893. errfunc (ERR_NONFATAL, "too long offset");
  1894. }
  1895. bytes[3] = *codes++;
  1896. bytes[2] |= ((data & 0xF0) >> 4);
  1897. bytes[3] |= data & 0xF;
  1898. break;
  1899. case 0x23: // LDRH Rd, Rn
  1900. ++codes;
  1901. bytes[0] = c | 0x01; // Implicit pre-index
  1902. bytes[1] = *codes++;
  1903. // Rd
  1904. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1905. // Rn
  1906. c = regval (&ins->oprs[1],1);
  1907. bytes[1] |= c;
  1908. if (c == 0x15) // R15
  1909. data = -8;
  1910. else
  1911. data = 0;
  1912. if (data < 0)
  1913. {
  1914. data = -data;
  1915. }
  1916. else
  1917. {
  1918. bytes[1] |= 0x80;
  1919. }
  1920. if (data >= 0x100)
  1921. {
  1922. errfunc (ERR_NONFATAL, "too long offset");
  1923. }
  1924. bytes[3] = *codes++;
  1925. bytes[2] |= ((data & 0xF0) >> 4);
  1926. bytes[3] |= data & 0xF;
  1927. break;
  1928. case 0x24: // LDRH Rd, Rn, expression
  1929. case 0x25: // LDRH Rd, Rn, Rm
  1930. ++codes;
  1931. bytes[0] = c;
  1932. bytes[1] = *codes++;
  1933. // Rd
  1934. bytes[2] = regval (&ins->oprs[0],1) << 4;
  1935. // Rn
  1936. c = regval (&ins->oprs[1],1);
  1937. bytes[1] |= c;
  1938. if (ins->oprs[ins->operands-1].bracket) // FIXME: Bracket on last operand -> pre-index <--
  1939. {
  1940. bytes[0] |= 0x01; // pre-index mode
  1941. if (has_W_code)
  1942. {
  1943. bytes[1] |= 0x20;
  1944. }
  1945. }
  1946. else
  1947. {
  1948. if (has_W_code)
  1949. {
  1950. errfunc (ERR_NONFATAL, "'!' not allowed in post-index mode");
  1951. }
  1952. }
  1953. bytes[3] = *codes++;
  1954. if (keep == 0x24)
  1955. {
  1956. data = ins->oprs[2].offset;
  1957. if (data < 0)
  1958. {
  1959. data = -data;
  1960. }
  1961. else
  1962. {
  1963. bytes[1] |= 0x80;
  1964. }
  1965. if (data >= 0x100)
  1966. {
  1967. errfunc (ERR_NONFATAL, "too long offset");
  1968. }
  1969. bytes[2] |= ((data & 0xF0) >> 4);
  1970. bytes[3] |= data & 0xF;
  1971. }
  1972. else
  1973. {
  1974. if (ins->oprs[2].minus == 0)
  1975. {
  1976. bytes[1] |= 0x80;
  1977. }
  1978. c = regval (&ins->oprs[2],1);
  1979. bytes[3] |= c;
  1980. }
  1981. break;
  1982. case 0x26: // LDM/STM Rn, {reg-list}
  1983. ++codes;
  1984. bytes[0] = c;
  1985. bytes[0] |= ( *codes >> 4) & 0xF;
  1986. bytes[1] = ( *codes << 4) & 0xF0;
  1987. ++codes;
  1988. if (has_W_code)
  1989. {
  1990. bytes[1] |= 0x20;
  1991. }
  1992. if (has_F_code)
  1993. {
  1994. bytes[1] |= 0x40;
  1995. }
  1996. // Rn
  1997. bytes[1] |= regval (&ins->oprs[0],1);
  1998. data = ins->oprs[1].basereg;
  1999. bytes[2] = ((data >> 8) & 0xFF);
  2000. bytes[3] = (data & 0xFF);
  2001. break;
  2002. case 0x27: // SWP Rd, Rm, [Rn]
  2003. ++codes;
  2004. bytes[0] = c;
  2005. bytes[0] |= *codes++;
  2006. bytes[1] = regval (&ins->oprs[2],1);
  2007. if (has_B_code)
  2008. {
  2009. bytes[1] |= 0x40;
  2010. }
  2011. bytes[2] = regval (&ins->oprs[0],1) << 4;
  2012. bytes[3] = *codes++;
  2013. bytes[3] |= regval (&ins->oprs[1],1);
  2014. break;
  2015. default:
  2016. errfunc (ERR_FATAL, "unknown decoding of instruction");
  2017. bytes[0] = c;
  2018. // And a fix nibble
  2019. ++codes;
  2020. bytes[0] |= *codes++;
  2021. if ( *codes == 0x01) // An I bit
  2022. {
  2023. }
  2024. if ( *codes == 0x02) // An I bit
  2025. {
  2026. }
  2027. ++codes;
  2028. }
  2029. out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
  2030. }
  2031. *)
  2032. {$endif dummy
  2033. }