mk20d5.pp 59 KB

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  1. unit mk20d5;
  2. interface
  3. {$PACKRECORDS 2}
  4. {$GOTO ON}
  5. {$MODESWITCH ADVANCEDRECORDS}
  6. // ** ###################################################################
  7. // ** Compilers: ARM Compiler
  8. // ** Freescale C/C++ for Embedded ARM
  9. // ** GNU C Compiler
  10. // ** IAR ANSI C/C++ Compiler for ARM
  11. // **
  12. // ** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
  13. // ** K20P32M50SF0RM Rev. 1, Oct 2011
  14. // ** K20P48M50SF0RM Rev. 1, Oct 2011
  15. // **
  16. // ** Version: rev. 2.0, 2012-03-19
  17. // **
  18. // ** Abstract:
  19. // ** CMSIS Peripheral Access Layer for MK20D5
  20. // **
  21. // ** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
  22. // **
  23. // ** http: www.freescale.com
  24. // ** mail: [email protected]
  25. // **
  26. // ** Revisions:
  27. // ** - rev. 1.0 (2011-12-15)
  28. // ** Initial version
  29. // ** - rev. 2.0 (2012-03-19)
  30. // ** PDB Peripheral register structure updated.
  31. // ** DMA Registers and bits for unsupported DMA channels removed.
  32. // **
  33. // ** ###################################################################
  34. // *
  35. // * @file MK20D5.h
  36. // * @version 2.0
  37. // * @date 2012-03-19
  38. // CMSIS Peripheral Access Layer for MK20D5
  39. // *
  40. // * CMSIS Peripheral Access Layer for MK20D5
  41. // * Memory map major version (memory maps with equal major version number are
  42. // * compatible)
  43. // * Memory map minor version
  44. // Macro to access a single bit of a peripheral register (bit band region
  45. // * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
  46. // * @param Reg Register to access.
  47. // * @param Bit Bit number to access.
  48. // * @return Value of the targeted bit in the bit band region.
  49. // ----------------------------------------------------------------------------
  50. // -- Interrupt vector numbers
  51. // ----------------------------------------------------------------------------
  52. // *
  53. // * Interrupt Number Definitions
  54. type
  55. TIRQn_Enum = (
  56. NonMaskableInt_IRQn = -14, // *< Non Maskable Interrupt
  57. MemoryManagement_IRQn = -12, // *< Cortex-M4 Memory Management Interrupt
  58. BusFault_IRQn = -11, // *< Cortex-M4 Bus Fault Interrupt
  59. UsageFault_IRQn = -10, // *< Cortex-M4 Usage Fault Interrupt
  60. SVCall_IRQn = -5, // *< Cortex-M4 SV Call Interrupt
  61. DebugMonitor_IRQn = -4, // *< Cortex-M4 Debug Monitor Interrupt
  62. PendSV_IRQn = -2, // *< Cortex-M4 Pend SV Interrupt
  63. SysTick_IRQn = -1, // *< Cortex-M4 System Tick Interrupt
  64. DMA0_IRQn = 0, // *< DMA channel 0 transfer complete interrupt
  65. DMA1_IRQn = 1, // *< DMA channel 1 transfer complete interrupt
  66. DMA2_IRQn = 2, // *< DMA channel 2 transfer complete interrupt
  67. DMA3_IRQn = 3, // *< DMA channel 3 transfer complete interrupt
  68. DMA_Error_IRQn = 4, // *< DMA error interrupt
  69. RESERVED21_IRQn = 5, // *< Reserved interrupt 21
  70. FTFL_IRQn = 6, // *< FTFL interrupt
  71. Read_Collision_IRQn = 7, // *< Read collision interrupt
  72. LVD_LVW_IRQn = 8, // *< Low Voltage Detect, Low Voltage Warning
  73. LLW_IRQn = 9, // *< Low Leakage Wakeup
  74. Watchdog_IRQn = 10, // *< WDOG interrupt
  75. I2C0_IRQn = 11, // *< I2C0 interrupt
  76. SPI0_IRQn = 12, // *< SPI0 interrupt
  77. I2S0_Tx_IRQn = 13, // *< I2S0 transmit interrupt
  78. I2S0_Rx_IRQn = 14, // *< I2S0 receive interrupt
  79. UART0_LON_IRQn = 15, // *< UART0 LON interrupt
  80. UART0_RX_TX_IRQn = 16, // *< UART0 receive/transmit interrupt
  81. UART0_ERR_IRQn = 17, // *< UART0 error interrupt
  82. UART1_RX_TX_IRQn = 18, // *< UART1 receive/transmit interrupt
  83. UART1_ERR_IRQn = 19, // *< UART1 error interrupt
  84. UART2_RX_TX_IRQn = 20, // *< UART2 receive/transmit interrupt
  85. UART2_ERR_IRQn = 21, // *< UART2 error interrupt
  86. ADC0_IRQn = 22, // *< ADC0 interrupt
  87. CMP0_IRQn = 23, // *< CMP0 interrupt
  88. CMP1_IRQn = 24, // *< CMP1 interrupt
  89. FTM0_IRQn = 25, // *< FTM0 fault, overflow and channels interrupt
  90. FTM1_IRQn = 26, // *< FTM1 fault, overflow and channels interrupt
  91. CMT_IRQn = 27, // *< CMT interrupt
  92. RTC_IRQn = 28, // *< RTC interrupt
  93. RTC_Seconds_IRQn = 29, // *< RTC seconds interrupt
  94. PIT0_IRQn = 30, // *< PIT timer channel 0 interrupt
  95. PIT1_IRQn = 31, // *< PIT timer channel 1 interrupt
  96. PIT2_IRQn = 32, // *< PIT timer channel 2 interrupt
  97. PIT3_IRQn = 33, // *< PIT timer channel 3 interrupt
  98. PDB0_IRQn = 34, // *< PDB0 interrupt
  99. USB0_IRQn = 35, // *< USB0 interrupt
  100. USBDCD_IRQn = 36, // *< USBDCD interrupt
  101. TSI0_IRQn = 37, // *< TSI0 interrupt
  102. MCG_IRQn = 38, // *< MCG interrupt
  103. LPTimer_IRQn = 39, // *< LPTimer interrupt
  104. PORTA_IRQn = 40, // *< Port A interrupt
  105. PORTB_IRQn = 41, // *< Port B interrupt
  106. PORTC_IRQn = 42, // *< Port C interrupt
  107. PORTD_IRQn = 43, // *< Port D interrupt
  108. PORTE_IRQn = 44, // *< Port E interrupt
  109. SWI_IRQn = 45 // *< Software interrupt
  110. );
  111. TADC_Registers = record
  112. SC1 : array[0..1] of longword; // *< ADC status and control registers 1, array offset: 0x0, array step: 0x4
  113. CFG1 : longword; // *< ADC configuration register 1, offset: 0x8
  114. CFG2 : longword; // *< Configuration register 2, offset: 0xC
  115. R : array[0..1] of longword; // *< ADC data result register, array offset: 0x10, array step: 0x4
  116. CV1 : longword; // *< Compare value registers, offset: 0x18
  117. CV2 : longword; // *< Compare value registers, offset: 0x1C
  118. SC2 : longword; // *< Status and control register 2, offset: 0x20
  119. SC3 : longword; // *< Status and control register 3, offset: 0x24
  120. OFS : longword; // *< ADC offset correction register, offset: 0x28
  121. PG : longword; // *< ADC plus-side gain register, offset: 0x2C
  122. MG : longword; // *< ADC minus-side gain register, offset: 0x30
  123. CLPD : longword; // *< ADC plus-side general calibration value register, offset: 0x34
  124. CLPS : longword; // *< ADC plus-side general calibration value register, offset: 0x38
  125. CLP4 : longword; // *< ADC plus-side general calibration value register, offset: 0x3C
  126. CLP3 : longword; // *< ADC plus-side general calibration value register, offset: 0x40
  127. CLP2 : longword; // *< ADC plus-side general calibration value register, offset: 0x44
  128. CLP1 : longword; // *< ADC plus-side general calibration value register, offset: 0x48
  129. CLP0 : longword; // *< ADC plus-side general calibration value register, offset: 0x4C
  130. RESERVED_0 : array[0..3] of byte;
  131. CLMD : longword; // *< ADC minus-side general calibration value register, offset: 0x54
  132. CLMS : longword; // *< ADC minus-side general calibration value register, offset: 0x58
  133. CLM4 : longword; // *< ADC minus-side general calibration value register, offset: 0x5C
  134. CLM3 : longword; // *< ADC minus-side general calibration value register, offset: 0x60
  135. CLM2 : longword; // *< ADC minus-side general calibration value register, offset: 0x64
  136. CLM1 : longword; // *< ADC minus-side general calibration value register, offset: 0x68
  137. CLM0 : longword; // *< ADC minus-side general calibration value register, offset: 0x6C
  138. end;
  139. const
  140. ADC0_BASE = $4003B000;
  141. var
  142. ADC0 : TADC_Registers absolute ADC0_BASE;
  143. type
  144. TCMP_Registers = record
  145. CR0 : byte; // *< CMP Control Register 0, offset: 0x0
  146. CR1 : byte; // *< CMP Control Register 1, offset: 0x1
  147. FPR : byte; // *< CMP Filter Period Register, offset: 0x2
  148. SCR : byte; // *< CMP Status and Control Register, offset: 0x3
  149. DACCR : byte; // *< DAC Control Register, offset: 0x4
  150. MUXCR : byte; // *< MUX Control Register, offset: 0x5
  151. end;
  152. const
  153. CMP0_BASE = $40073000;
  154. var
  155. CMP0 : TCMP_Registers absolute CMP0_BASE;
  156. const
  157. CMP1_BASE = $40073008;
  158. var
  159. CMP1 : TCMP_Registers absolute CMP1_BASE;
  160. type
  161. TCMT_Registers = record
  162. CGH1 : byte; // *< CMT Carrier Generator High Data Register 1, offset: 0x0
  163. CGL1 : byte; // *< CMT Carrier Generator Low Data Register 1, offset: 0x1
  164. CGH2 : byte; // *< CMT Carrier Generator High Data Register 2, offset: 0x2
  165. CGL2 : byte; // *< CMT Carrier Generator Low Data Register 2, offset: 0x3
  166. OC : byte; // *< CMT Output Control Register, offset: 0x4
  167. MSC : byte; // *< CMT Modulator Status and Control Register, offset: 0x5
  168. CMD1 : byte; // *< CMT Modulator Data Register Mark High, offset: 0x6
  169. CMD2 : byte; // *< CMT Modulator Data Register Mark Low, offset: 0x7
  170. CMD3 : byte; // *< CMT Modulator Data Register Space High, offset: 0x8
  171. CMD4 : byte; // *< CMT Modulator Data Register Space Low, offset: 0x9
  172. PPS : byte; // *< CMT Primary Prescaler Register, offset: 0xA
  173. DMA : byte; // *< CMT Direct Memory Access, offset: 0xB
  174. end;
  175. const
  176. CMT_BASE = $40062000;
  177. var
  178. CMT : TCMT_Registers absolute CMT_BASE;
  179. type
  180. TCRC_Registers = record
  181. CRC :longword; // *< CRC Data Register, offset: 0x0
  182. GPOLY :longword; // *< CRC Polynomial Register, offset: 0x4
  183. CTRL :longword; // *< CRC Control Register, offset: 0x8
  184. end;
  185. const
  186. CRC_BASE = $40032000;
  187. var
  188. CRC0 : TCRC_Registers absolute CRC_BASE;
  189. type
  190. TDMA_TCD = record
  191. SADDR : longword; // *< TCD Source Address, array offset: 0x1000, array step: 0x20
  192. SOFF : word; // *< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20
  193. ATTR : word; // *< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20
  194. NBYTES_MLNO: longword; // *< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20
  195. SLAST : longword; // *< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20
  196. DADDR : longword; // *< TCD Destination Address, array offset: 0x1010, array step: 0x20
  197. DOFF : word; // *< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20
  198. CITER_ELINKNO: word; // *< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20
  199. DLAST_SGA : longword; // *< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20
  200. CSR : word; // *< TCD Control and Status, array offset: 0x101C, array step: 0x20
  201. BITER_ELINKNO : word; // *< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20
  202. end;
  203. TDMA_Registers = record
  204. CR : longword; // *< Control Register, offset: 0x0
  205. ES : longword; // *< Error Status Register, offset: 0x4
  206. RESERVED_0 : array[0..3] of byte;
  207. ERQ : longword; // *< Enable Request Register, offset: 0xC
  208. RESERVED_1 : array[0..3] of byte;
  209. EEI : longword; // *< Enable Error Interrupt Register, offset: 0x14
  210. CEEI : byte; // *< Clear Enable Error Interrupt Register, offset: 0x18
  211. SEEI : byte; // *< Set Enable Error Interrupt Register, offset: 0x19
  212. CERQ : byte; // *< Clear Enable Request Register, offset: 0x1A
  213. SERQ : byte; // *< Set Enable Request Register, offset: 0x1B
  214. CDNE : byte; // *< Clear DONE Status Bit Register, offset: 0x1C
  215. SSRT : byte; // *< Set START Bit Register, offset: 0x1D
  216. CERR : byte; // *< Clear Error Register, offset: 0x1E
  217. CINT : byte; // *< Clear Interrupt Request Register, offset: 0x1F
  218. RESERVED_2 : array[0..3] of byte;
  219. INT : longword; // *< Interrupt Request Register, offset: 0x24
  220. RESERVED_3 : array[0..3] of byte;
  221. ERR : longword; // *< Error Register, offset: 0x2C
  222. RESERVED_4 : array[0..3] of byte;
  223. HRS : longword; // *< Hardware Request Status Register, offset: 0x34
  224. RESERVED_5 : array[0..199] of byte;
  225. DCHPRI3 : byte; // *< Channel n Priority Register, offset: 0x100
  226. DCHPRI2 : byte; // *< Channel n Priority Register, offset: 0x101
  227. DCHPRI1 : byte; // *< Channel n Priority Register, offset: 0x102
  228. DCHPRI0 : byte; // *< Channel n Priority Register, offset: 0x103
  229. RESERVED_6 : array[0..3835] of byte;
  230. TCD : array[0..3] of TDMA_TCD;
  231. end;
  232. const
  233. DMA_BASE = $40008000;
  234. var
  235. DMA0 : TDMA_Registers absolute DMA_BASE;
  236. type
  237. TDMAMUX_Registers = record
  238. CHCFG : array[0..15] of byte; // *< Channel Configuration Register, array offset: 0x0, array step: 0x1
  239. end;
  240. const
  241. DMAMUX_BASE = $40021000;
  242. var
  243. DMAMUX : TDMAMUX_Registers absolute DMAMUX_BASE;
  244. type
  245. TEWM_Registers = record
  246. CTRL : byte; // *< Control Register, offset: 0x0
  247. SERV : byte; // *< Service Register, offset: 0x1
  248. CMPL : byte; // *< Compare Low Register, offset: 0x2
  249. CMPH : byte; // *< Compare High Register, offset: 0x3
  250. end;
  251. const
  252. EWM_BASE = $40061000;
  253. var
  254. EWM : TEWM_Registers absolute EWM_BASE;
  255. type
  256. TFMC_TAG_WAY = record
  257. TAGVD : array[0..1] of longword; // *< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4
  258. RESERVED_0 : array[0..23] of byte;
  259. end;
  260. TFMC_DATAW0S = record
  261. DATAW0S : longword; // *< Cache Data Storage, array offset: 0x204, array step: 0x8
  262. RESERVED_0 : array[0..3] of byte;
  263. end;
  264. TFMC_DATAW1S = record
  265. DATAW1S : longword; // *< Cache Data Storage, array offset: 0x244, array step: 0x8
  266. RESERVED_0 : array[0..3] of byte;
  267. end;
  268. TFMC_DATAW2S = record
  269. DATAW2S : longword; // *< Cache Data Storage, array offset: 0x284, array step: 0x8
  270. RESERVED_0 : array[0..3] of byte;
  271. end;
  272. TFMC_DATAW3S = record
  273. DATAW3S : longword; // *< Cache Data Storage, array offset: 0x2C4, array step: 0x8
  274. RESERVED_0 : array[0..3] of byte;
  275. end;
  276. TFMC_Registers = record
  277. PFAPR : longword; // *< Flash Access Protection Register, offset: 0x0
  278. PFB0CR : longword; // *< Flash Control Register, offset: 0x4
  279. RESERVED_0 : array[0..247] of byte;
  280. TAG_WAY : array[0..3] of TFMC_TAG_WAY;
  281. RESERVED_1 : array[0..131] of byte;
  282. DATAW0S : array[0..1] of TFMC_DATAW0S;
  283. RESERVED_2 : array[0..47] of byte;
  284. DATAW1S : array[0..1] of TFMC_DATAW1S;
  285. RESERVED_3 : array[0..47] of byte;
  286. DATAW2S : array[0..1] of TFMC_DATAW2S;
  287. RESERVED_4 : array[0..47] of byte;
  288. DATAW3S : array[0..1] of TFMC_DATAW3S;
  289. end;
  290. const
  291. FMC_BASE = $4001F000;
  292. var
  293. FMC : TFMC_Registers absolute FMC_BASE;
  294. type
  295. TFTFL_Registers = record
  296. FSTAT : byte; // *< Flash Status Register, offset: 0x0
  297. FCNFG : byte; // *< Flash Configuration Register, offset: 0x1
  298. FSEC : byte; // *< Flash Security Register, offset: 0x2
  299. FOPT : byte; // *< Flash Option Register, offset: 0x3
  300. FCCOB3 : byte; // *< Flash Common Command Object Registers, offset: 0x4
  301. FCCOB2 : byte; // *< Flash Common Command Object Registers, offset: 0x5
  302. FCCOB1 : byte; // *< Flash Common Command Object Registers, offset: 0x6
  303. FCCOB0 : byte; // *< Flash Common Command Object Registers, offset: 0x7
  304. FCCOB7 : byte; // *< Flash Common Command Object Registers, offset: 0x8
  305. FCCOB6 : byte; // *< Flash Common Command Object Registers, offset: 0x9
  306. FCCOB5 : byte; // *< Flash Common Command Object Registers, offset: 0xA
  307. FCCOB4 : byte; // *< Flash Common Command Object Registers, offset: 0xB
  308. FCCOBB : byte; // *< Flash Common Command Object Registers, offset: 0xC
  309. FCCOBA : byte; // *< Flash Common Command Object Registers, offset: 0xD
  310. FCCOB9 : byte; // *< Flash Common Command Object Registers, offset: 0xE
  311. FCCOB8 : byte; // *< Flash Common Command Object Registers, offset: 0xF
  312. FPROT3 : byte; // *< Program Flash Protection Registers, offset: 0x10
  313. FPROT2 : byte; // *< Program Flash Protection Registers, offset: 0x11
  314. FPROT1 : byte; // *< Program Flash Protection Registers, offset: 0x12
  315. FPROT0 : byte; // *< Program Flash Protection Registers, offset: 0x13
  316. RESERVED_0 : array[0..1] of byte;
  317. FEPROT : byte; // *< EEPROM Protection Register, offset: 0x16
  318. FDPROT : byte; // *< Data Flash Protection Register, offset: 0x17
  319. end;
  320. const
  321. FTFL_BASE = $40020000;
  322. var
  323. FTFL : TFTFL_Registers absolute FTFL_BASE;
  324. type
  325. TFTM_CONTROLS= record
  326. CnSC : longword; // *< Channel (n) Status and Control, array offset: 0xC, array step: 0x8
  327. CnV : longword; // *< Channel (n) Value, array offset: 0x10, array step: 0x8
  328. end;
  329. TFTM_Registers = record
  330. SC : longword; // *< Status and Control, offset: 0x0
  331. CNT : longword; // *< Counter, offset: 0x4
  332. &MOD : longword; // *< Modulo, offset: 0x8
  333. CONTROLS : array[0..7] of TFTM_CONTROLS;
  334. CNTIN : longword; // *< Counter Initial Value, offset: 0x4C
  335. STATUS : longword; // *< Capture and Compare Status, offset: 0x50
  336. MODE : longword; // *< Features Mode Selection, offset: 0x54
  337. SYNC : longword; // *< Synchronization, offset: 0x58
  338. OUTINIT : longword; // *< Initial State for Channels Output, offset: 0x5C
  339. OUTMASK : longword; // *< Output Mask, offset: 0x60
  340. COMBINE : longword; // *< Function for Linked Channels, offset: 0x64
  341. DEADTIME : longword; // *< Deadtime Insertion Control, offset: 0x68
  342. EXTTRIG : longword; // *< FTM External Trigger, offset: 0x6C
  343. POL : longword; // *< Channels Polarity, offset: 0x70
  344. FMS : longword; // *< Fault Mode Status, offset: 0x74
  345. FILTER : longword; // *< Input Capture Filter Control, offset: 0x78
  346. FLTCTRL : longword; // *< Fault Control, offset: 0x7C
  347. QDCTRL : longword; // *< Quadrature Decoder Control and Status, offset: 0x80
  348. CONF : longword; // *< Configuration, offset: 0x84
  349. FLTPOL : longword; // *< FTM Fault Input Polarity, offset: 0x88
  350. SYNCONF : longword; // *< Synchronization Configuration, offset: 0x8C
  351. INVCTRL : longword; // *< FTM Inverting Control, offset: 0x90
  352. SWOCTRL : longword; // *< FTM Software Output Control, offset: 0x94
  353. PWMLOAD : longword; // *< FTM PWM Load, offset: 0x98
  354. end;
  355. const
  356. FTM0_BASE = $40038000;
  357. var
  358. FTM0 : TFTM_Registers absolute FTM0_BASE;
  359. const
  360. FTM1_BASE = $40039000;
  361. var
  362. FTM1 : TFTM_Registers absolute FTM1_BASE;
  363. type
  364. TGPIO_Registers = record
  365. PDOR : longword; // *< Port Data Output Register, offset: 0x0
  366. PSOR : longword; // *< Port Set Output Register, offset: 0x4
  367. PCOR : longword; // *< Port Clear Output Register, offset: 0x8
  368. PTOR : longword; // *< Port Toggle Output Register, offset: 0xC
  369. PDIR : longword; // *< Port Data Input Register, offset: 0x10
  370. PDDR : longword; // *< Port Data Direction Register, offset: 0x14
  371. end;
  372. const
  373. PTA_BASE = $400FF000;
  374. var
  375. PTA : TGPIO_Registers absolute PTA_BASE;
  376. const
  377. PTB_BASE = $400FF040;
  378. var
  379. PTB : TGPIO_Registers absolute PTB_BASE;
  380. const
  381. PTC_BASE = $400FF080;
  382. var
  383. PTC : TGPIO_Registers absolute PTC_BASE;
  384. const
  385. PTD_BASE = $400FF0C0;
  386. var
  387. PTD : TGPIO_Registers absolute PTD_BASE;
  388. const
  389. PTE_BASE = $400FF100;
  390. var
  391. PTE : TGPIO_Registers absolute PTE_BASE;
  392. type
  393. TI2C_Registers = record
  394. A1 : byte; // *< I2C Address Register 1, offset: 0x0
  395. F : byte; // *< I2C Frequency Divider register, offset: 0x1
  396. C1 : byte; // *< I2C Control Register 1, offset: 0x2
  397. S : byte; // *< I2C Status Register, offset: 0x3
  398. D : byte; // *< I2C Data I/O register, offset: 0x4
  399. C2 : byte; // *< I2C Control Register 2, offset: 0x5
  400. FLT : byte; // *< I2C Programmable Input Glitch Filter register, offset: 0x6
  401. RA : byte; // *< I2C Range Address register, offset: 0x7
  402. SMB : byte; // *< I2C SMBus Control and Status register, offset: 0x8
  403. A2 : byte; // *< I2C Address Register 2, offset: 0x9
  404. SLTH : byte; // *< I2C SCL Low Timeout Register High, offset: 0xA
  405. SLTL : byte; // *< I2C SCL Low Timeout Register Low, offset: 0xB
  406. end;
  407. const
  408. I2C0_BASE = $40066000;
  409. var
  410. I2C0 : TI2C_Registers absolute I2C0_BASE;
  411. type
  412. TI2S_Registers = record
  413. TCSR : longword; // *< SAI Transmit Control Register, offset: 0x0
  414. TCR1 : longword; // *< SAI Transmit Configuration 1 Register, offset: 0x4
  415. TCR2 : longword; // *< SAI Transmit Configuration 2 Register, offset: 0x8
  416. TCR3 : longword; // *< SAI Transmit Configuration 3 Register, offset: 0xC
  417. TCR4 : longword; // *< SAI Transmit Configuration 4 Register, offset: 0x10
  418. TCR5 : longword; // *< SAI Transmit Configuration 5 Register, offset: 0x14
  419. RESERVED_0 : array[0..7] of byte;
  420. TDR : array[0..1] of longword; // *< SAI Transmit Data Register, array offset: 0x20, array step: 0x4
  421. RESERVED_1 : array[0..23] of byte;
  422. TFR : array[0..1] of longword; // *< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4
  423. RESERVED_2 : array[0..23] of byte;
  424. TMR : longword; // *< SAI Transmit Mask Register, offset: 0x60
  425. RESERVED_3 : array[0..27] of byte;
  426. RCSR : longword; // *< SAI Receive Control Register, offset: 0x80
  427. RCR1 : longword; // *< SAI Receive Configuration 1 Register, offset: 0x84
  428. RCR2 : longword; // *< SAI Receive Configuration 2 Register, offset: 0x88
  429. RCR3 : longword; // *< SAI Receive Configuration 3 Register, offset: 0x8C
  430. RCR4 : longword; // *< SAI Receive Configuration 4 Register, offset: 0x90
  431. RCR5 : longword; // *< SAI Receive Configuration 5 Register, offset: 0x94
  432. RESERVED_4 : array[0..7] of byte;
  433. RDR : array[0..1] of longword; // *< SAI Receive Data Register, array offset: 0xA0, array step: 0x4
  434. RESERVED_5 : array[0..23] of byte;
  435. RFR : array[0..1] of longword; // *< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4
  436. RESERVED_6 : array[0..23] of byte;
  437. RMR : longword; // *< SAI Receive Mask Register, offset: 0xE0
  438. RESERVED_7 : array[0..27] of byte;
  439. MCR : longword; // *< SAI MCLK Control Register, offset: 0x100
  440. MDR : longword; // *< MCLK Divide Register, offset: 0x104
  441. end;
  442. const
  443. I2S0_BASE = $4002F000;
  444. var
  445. I2S0 : TI2S_Registers absolute I2S0_BASE;
  446. type
  447. TLLWU_Registers = record
  448. PE1 : byte; // *< LLWU Pin Enable 1 Register, offset: 0x0
  449. PE2 : byte; // *< LLWU Pin Enable 2 Register, offset: 0x1
  450. PE3 : byte; // *< LLWU Pin Enable 3 Register, offset: 0x2
  451. PE4 : byte; // *< LLWU Pin Enable 4 Register, offset: 0x3
  452. ME : byte; // *< LLWU Module Enable Register, offset: 0x4
  453. F1 : byte; // *< LLWU Flag 1 Register, offset: 0x5
  454. F2 : byte; // *< LLWU Flag 2 Register, offset: 0x6
  455. F3 : byte; // *< LLWU Flag 3 Register, offset: 0x7
  456. FILT1 : byte; // *< LLWU Pin Filter 1 Register, offset: 0x8
  457. FILT2 : byte; // *< LLWU Pin Filter 2 Register, offset: 0x9
  458. RST : byte; // *< LLWU Reset Enable Register, offset: 0xA
  459. end;
  460. const
  461. LLWU_BASE = $4007C000;
  462. var
  463. LLWU : TLLWU_Registers absolute LLWU_BASE;
  464. type
  465. TLPTMR_Registers = record
  466. CSR : longword; // *< Low Power Timer Control Status Register, offset: 0x0
  467. PSR : longword; // *< Low Power Timer Prescale Register, offset: 0x4
  468. CMR : longword; // *< Low Power Timer Compare Register, offset: 0x8
  469. CNR : longword; // *< Low Power Timer Counter Register, offset: 0xC
  470. end;
  471. const
  472. LPTMR0_BASE = $40040000;
  473. var
  474. LPTMR0 : TLPTMR_Registers absolute LPTMR0_BASE;
  475. type
  476. TMCG_Registers = record
  477. C1 : byte; // *< MCG Control 1 Register, offset: 0x0
  478. C2 : byte; // *< MCG Control 2 Register, offset: 0x1
  479. C3 : byte; // *< MCG Control 3 Register, offset: 0x2
  480. C4 : byte; // *< MCG Control 4 Register, offset: 0x3
  481. C5 : byte; // *< MCG Control 5 Register, offset: 0x4
  482. C6 : byte; // *< MCG Control 6 Register, offset: 0x5
  483. S : byte; // *< MCG Status Register, offset: 0x6
  484. RESERVED_0 : array[0..0] of byte;
  485. SC : byte; // *< MCG Status and Control Register, offset: 0x8
  486. RESERVED_1 : array[0..0] of byte;
  487. ATCVH : byte; // *< MCG Auto Trim Compare Value High Register, offset: 0xA
  488. ATCVL : byte; // *< MCG Auto Trim Compare Value Low Register, offset: 0xB
  489. C7 : byte; // *< MCG Control 7 Register, offset: 0xC
  490. C8 : byte; // *< MCG Control 8 Register, offset: 0xD
  491. end;
  492. const
  493. MCG_BASE = $40064000;
  494. var
  495. MCG : TMCG_Registers absolute MCG_BASE;
  496. type
  497. TNV_Registers = record
  498. BACKKEY3 : byte; // *< Backdoor Comparison Key 3., offset: 0x0
  499. BACKKEY2 : byte; // *< Backdoor Comparison Key 2., offset: 0x1
  500. BACKKEY1 : byte; // *< Backdoor Comparison Key 1., offset: 0x2
  501. BACKKEY0 : byte; // *< Backdoor Comparison Key 0., offset: 0x3
  502. BACKKEY7 : byte; // *< Backdoor Comparison Key 7., offset: 0x4
  503. BACKKEY6 : byte; // *< Backdoor Comparison Key 6., offset: 0x5
  504. BACKKEY5 : byte; // *< Backdoor Comparison Key 5., offset: 0x6
  505. BACKKEY4 : byte; // *< Backdoor Comparison Key 4., offset: 0x7
  506. FPROT3 : byte; // *< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8
  507. FPROT2 : byte; // *< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9
  508. FPROT1 : byte; // *< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA
  509. FPROT0 : byte; // *< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB
  510. FSEC : byte; // *< Non-volatile Flash Security Register, offset: 0xC
  511. FOPT : byte; // *< Non-volatile Flash Option Register, offset: 0xD
  512. FEPROT : byte; // *< Non-volatile EERAM Protection Register, offset: 0xE
  513. FDPROT : byte; // *< Non-volatile D-Flash Protection Register, offset: 0xF
  514. end;
  515. const
  516. FTFL_FlashConfig_BASE = $400;
  517. var
  518. FTFL_FlashConfig : TNV_Registers absolute FTFL_FlashConfig_BASE;
  519. type
  520. TOSC_Registers = record
  521. CR : byte; // *< OSC Control Register, offset: 0x0
  522. end;
  523. const
  524. OSC0_BASE = $40065000;
  525. var
  526. OSC0 : TOSC_Registers absolute OSC0_BASE;
  527. type
  528. TPDB_CH = record
  529. C1 : longword; // *< Channel n Control Register 1, array offset: 0x10, array step: 0x10
  530. S : longword; // *< Channel n Status Register, array offset: 0x14, array step: 0x10
  531. DLY : array[0..1] of longword; // *< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4
  532. end;
  533. TPDB_Registers = record
  534. SC : longword; // *< Status and Control Register, offset: 0x0
  535. &MOD : longword; // *< Modulus Register, offset: 0x4
  536. CNT : longword; // *< Counter Register, offset: 0x8
  537. IDLY : longword; // *< Interrupt Delay Register, offset: 0xC
  538. CH : array[0..0] of TPDB_CH;
  539. RESERVED_0 : array[0..367] of byte;
  540. POEN : longword; // *< Pulse-Out n Enable Register, offset: 0x190
  541. PODLY : array[0..1] of longword; // *< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4
  542. end;
  543. const
  544. PDB0_BASE = $40036000;
  545. var
  546. PDB0 : TPDB_Registers absolute PDB0_BASE;
  547. type
  548. TPIT_CHANNEL = record
  549. LDVAL : longword; // *< Timer Load Value Register, array offset: 0x100, array step: 0x10
  550. CVAL : longword; // *< Current Timer Value Register, array offset: 0x104, array step: 0x10
  551. TCTRL : longword; // *< Timer Control Register, array offset: 0x108, array step: 0x10
  552. TFLG : longword; // *< Timer Flag Register, array offset: 0x10C, array step: 0x10
  553. end;
  554. TPIT_Registers = record
  555. MCR : longword; // *< PIT Module Control Register, offset: 0x0
  556. RESERVED_0 : array[0..251] of byte;
  557. CHANNEL : array[0..3] of TPIT_CHANNEL;
  558. end;
  559. const
  560. PIT_BASE = $40037000;
  561. var
  562. PIT : TPIT_Registers absolute PIT_BASE;
  563. type
  564. TPMC_Registers = record
  565. LVDSC1 : byte; // *< Low Voltage Detect Status and Control 1 Register, offset: 0x0
  566. LVDSC2 : byte; // *< Low Voltage Detect Status and Control 2 Register, offset: 0x1
  567. REGSC : byte; // *< Regulator Status and Control Register, offset: 0x2
  568. end;
  569. const
  570. PMC_BASE = $4007D000;
  571. var
  572. PMC : TPMC_Registers absolute PMC_BASE;
  573. type
  574. TPORT_Registers = record
  575. PCR : array[0..31] of longword; // *< Pin Control Register n, array offset: 0x0, array step: 0x4
  576. GPCLR : longword; // *< Global Pin Control Low Register, offset: 0x80
  577. GPCHR : longword; // *< Global Pin Control High Register, offset: 0x84
  578. RESERVED_0 : array[0..23] of byte;
  579. ISFR : longword; // *< Interrupt Status Flag Register, offset: 0xA0
  580. RESERVED_1 : array[0..27] of byte;
  581. DFER : longword; // *< Digital Filter Enable Register, offset: 0xC0
  582. DFCR : longword; // *< Digital Filter Clock Register, offset: 0xC4
  583. DFWR : longword; // *< Digital Filter Width Register, offset: 0xC8
  584. end;
  585. const
  586. PORTA_BASE = $40049000;
  587. var
  588. PORTA : TPORT_Registers absolute PORTA_BASE;
  589. const
  590. PORTB_BASE = $4004A000;
  591. var
  592. PORTB : TPORT_Registers absolute PORTB_BASE;
  593. const
  594. PORTC_BASE = $4004B000;
  595. var
  596. PORTC : TPORT_Registers absolute PORTC_BASE;
  597. const
  598. PORTD_BASE = $4004C000;
  599. var
  600. PORTD : TPORT_Registers absolute PORTD_BASE;
  601. const
  602. PORTE_BASE = $4004D000;
  603. var
  604. PORTE : TPORT_Registers absolute PORTE_BASE;
  605. type
  606. TRCM_Registers = record
  607. SRS0 : byte; // *< System Reset Status Register 0, offset: 0x0
  608. SRS1 : byte; // *< System Reset Status Register 1, offset: 0x1
  609. RESERVED_0 : array[0..1] of byte;
  610. RPFC : byte; // *< Reset Pin Filter Control Register, offset: 0x4
  611. RPFW : byte; // *< Reset Pin Filter Width Register, offset: 0x5
  612. RESERVED_1 : array[0..0] of byte;
  613. MR : byte; // *< Mode Register, offset: 0x7
  614. end;
  615. const
  616. RCM_BASE = $4007F000;
  617. var
  618. RCM : TRCM_Registers absolute RCM_BASE;
  619. type
  620. TRFSYS_Registers = record
  621. REG : array[0..7] of longword; // *< Register file register, array offset: 0x0, array step: 0x4
  622. end;
  623. const
  624. RFSYS_BASE = $40041000;
  625. var
  626. RFSYS : TRFSYS_Registers absolute RFSYS_BASE;
  627. type
  628. TRFVBAT_Registers = record
  629. REG : array[0..7] of longword; // *< VBAT register file register, array offset: 0x0, array step: 0x4
  630. end;
  631. const
  632. RFVBAT_BASE = $4003E000;
  633. var
  634. RFVBAT : TRFVBAT_Registers absolute RFVBAT_BASE;
  635. type
  636. TRTC_Registers = record
  637. TSR : longword; // *< RTC Time Seconds Register, offset: 0x0
  638. TPR : longword; // *< RTC Time Prescaler Register, offset: 0x4
  639. TAR : longword; // *< RTC Time Alarm Register, offset: 0x8
  640. TCR : longword; // *< RTC Time Compensation Register, offset: 0xC
  641. CR : longword; // *< RTC Control Register, offset: 0x10
  642. SR : longword; // *< RTC Status Register, offset: 0x14
  643. LR : longword; // *< RTC Lock Register, offset: 0x18
  644. IER : longword; // *< RTC Interrupt Enable Register, offset: 0x1C
  645. RESERVED_0 : array[0..2015] of byte;
  646. WAR : longword; // *< RTC Write Access Register, offset: 0x800
  647. RAR : longword; // *< RTC Read Access Register, offset: 0x804
  648. end;
  649. const
  650. RTC_BASE = $4003D000;
  651. var
  652. RTC : TRTC_Registers absolute RTC_BASE;
  653. type
  654. TSIM_Registers = record
  655. SOPT1 : longword; // *< System Options Register 1, offset: 0x0
  656. SOPT1CFG : longword; // *< SOPT1 Configuration Register, offset: 0x4
  657. RESERVED_0 : array[0..4091] of byte;
  658. SOPT2 : longword; // *< System Options Register 2, offset: 0x1004
  659. RESERVED_1 : array[0..3] of byte;
  660. SOPT4 : longword; // *< System Options Register 4, offset: 0x100C
  661. SOPT5 : longword; // *< System Options Register 5, offset: 0x1010
  662. RESERVED_2 : array[0..3] of byte;
  663. SOPT7 : longword; // *< System Options Register 7, offset: 0x1018
  664. RESERVED_3 : array[0..7] of byte;
  665. SDID : longword; // *< System Device Identification Register, offset: 0x1024
  666. RESERVED_4 : array[0..11] of byte;
  667. SCGC4 : longword; // *< System Clock Gating Control Register 4, offset: 0x1034
  668. SCGC5 : longword; // *< System Clock Gating Control Register 5, offset: 0x1038
  669. SCGC6 : longword; // *< System Clock Gating Control Register 6, offset: 0x103C
  670. SCGC7 : longword; // *< System Clock Gating Control Register 7, offset: 0x1040
  671. CLKDIV1 : longword; // *< System Clock Divider Register 1, offset: 0x1044
  672. CLKDIV2 : longword; // *< System Clock Divider Register 2, offset: 0x1048
  673. FCFG1 : longword; // *< Flash Configuration Register 1, offset: 0x104C
  674. FCFG2 : longword; // *< Flash Configuration Register 2, offset: 0x1050
  675. UIDH : longword; // *< Unique Identification Register High, offset: 0x1054
  676. UIDMH : longword; // *< Unique Identification Register Mid-High, offset: 0x1058
  677. UIDML : longword; // *< Unique Identification Register Mid Low, offset: 0x105C
  678. UIDL : longword; // *< Unique Identification Register Low, offset: 0x1060
  679. end;
  680. const
  681. SIM_BASE = $40047000;
  682. var
  683. SIM : TSIM_Registers absolute SIM_BASE;
  684. type
  685. TSMC_Registers = record
  686. PMPROT : byte; // *< Power Mode Protection Register, offset: 0x0
  687. PMCTRL : byte; // *< Power Mode Control Register, offset: 0x1
  688. VLLSCTRL : byte; // *< VLLS Control Register, offset: 0x2
  689. PMSTAT : byte; // *< Power Mode Status Register, offset: 0x3
  690. end;
  691. const
  692. SMC_BASE = $4007E000;
  693. var
  694. SMC : TSMC_Registers absolute SMC_BASE;
  695. type
  696. TSPI_Registers = record
  697. MCR : longword; // *< DSPI Module Configuration Register, offset: 0x0
  698. RESERVED_0 : array[0..3] of byte;
  699. TCR : longword; // *< DSPI Transfer Count Register, offset: 0x8
  700. CTAR : array[0..1] of longword; // *< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4
  701. RESERVED_1 : array[0..23] of byte;
  702. SR : longword; // *< DSPI Status Register, offset: 0x2C
  703. RSER : longword; // *< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30
  704. PUSHR : longword; // *< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34
  705. POPR : longword; // *< DSPI POP RX FIFO Register, offset: 0x38
  706. TXFR0 : longword; // *< DSPI Transmit FIFO Registers, offset: 0x3C
  707. TXFR1 : longword; // *< DSPI Transmit FIFO Registers, offset: 0x40
  708. TXFR2 : longword; // *< DSPI Transmit FIFO Registers, offset: 0x44
  709. TXFR3 : longword; // *< DSPI Transmit FIFO Registers, offset: 0x48
  710. RESERVED_2 : array[0..47] of byte;
  711. RXFR0 : longword; // *< DSPI Receive FIFO Registers, offset: 0x7C
  712. RXFR1 : longword; // *< DSPI Receive FIFO Registers, offset: 0x80
  713. RXFR2 : longword; // *< DSPI Receive FIFO Registers, offset: 0x84
  714. RXFR3 : longword; // *< DSPI Receive FIFO Registers, offset: 0x88
  715. end;
  716. const
  717. SPI0_BASE = $4002C000;
  718. var
  719. SPI0 : TSPI_Registers absolute SPI0_BASE;
  720. type
  721. TTSI_Registers = record
  722. GENCS : longword; // *< General Control and Status Register, offset: 0x0
  723. SCANC : longword; // *< SCAN Control Register, offset: 0x4
  724. PEN : longword; // *< Pin Enable Register, offset: 0x8
  725. WUCNTR : longword; // *< Wake-Up Channel Counter Register, offset: 0xC
  726. RESERVED_0 : array[0..239] of byte;
  727. CNTR1 : longword; // *< Counter Register, offset: 0x100
  728. CNTR3 : longword; // *< Counter Register, offset: 0x104
  729. CNTR5 : longword; // *< Counter Register, offset: 0x108
  730. CNTR7 : longword; // *< Counter Register, offset: 0x10C
  731. CNTR9 : longword; // *< Counter Register, offset: 0x110
  732. CNTR11 : longword; // *< Counter Register, offset: 0x114
  733. CNTR13 : longword; // *< Counter Register, offset: 0x118
  734. CNTR15 : longword; // *< Counter Register, offset: 0x11C
  735. THRESHOLD : longword; // *< Low Power Channel Threshold Register, offset: 0x120
  736. end;
  737. const
  738. TSI0_BASE = $40045000;
  739. var
  740. TSI0 : TTSI_Registers absolute TSI0_BASE;
  741. type
  742. TUART_Registers = record
  743. BDH : byte; // *< UART Baud Rate Registers:High, offset: 0x0
  744. BDL : byte; // *< UART Baud Rate Registers: Low, offset: 0x1
  745. C1 : byte; // *< UART Control Register 1, offset: 0x2
  746. C2 : byte; // *< UART Control Register 2, offset: 0x3
  747. S1 : byte; // *< UART Status Register 1, offset: 0x4
  748. S2 : byte; // *< UART Status Register 2, offset: 0x5
  749. C3 : byte; // *< UART Control Register 3, offset: 0x6
  750. D : byte; // *< UART Data Register, offset: 0x7
  751. MA1 : byte; // *< UART Match Address Registers 1, offset: 0x8
  752. MA2 : byte; // *< UART Match Address Registers 2, offset: 0x9
  753. C4 : byte; // *< UART Control Register 4, offset: 0xA
  754. C5 : byte; // *< UART Control Register 5, offset: 0xB
  755. ED : byte; // *< UART Extended Data Register, offset: 0xC
  756. MODEM : byte; // *< UART Modem Register, offset: 0xD
  757. IR : byte; // *< UART Infrared Register, offset: 0xE
  758. RESERVED_0 : array[0..0] of byte;
  759. PFIFO : byte; // *< UART FIFO Parameters, offset: 0x10
  760. CFIFO : byte; // *< UART FIFO Control Register, offset: 0x11
  761. SFIFO : byte; // *< UART FIFO Status Register, offset: 0x12
  762. TWFIFO : byte; // *< UART FIFO Transmit Watermark, offset: 0x13
  763. TCFIFO : byte; // *< UART FIFO Transmit Count, offset: 0x14
  764. RWFIFO : byte; // *< UART FIFO Receive Watermark, offset: 0x15
  765. RCFIFO : byte; // *< UART FIFO Receive Count, offset: 0x16
  766. RESERVED_1 : array[0..0] of byte;
  767. C7816 : byte; // *< UART 7816 Control Register, offset: 0x18
  768. IE7816 : byte; // *< UART 7816 Interrupt Enable Register, offset: 0x19
  769. IS7816 : byte; // *< UART 7816 Interrupt Status Register, offset: 0x1A
  770. WP7816_T_TYPE0 : byte; // *< UART 7816 Wait Parameter Register, offset: 0x1B
  771. WN7816 : byte; // *< UART 7816 Wait N Register, offset: 0x1C
  772. WF7816 : byte; // *< UART 7816 Wait FD Register, offset: 0x1D
  773. ET7816 : byte; // *< UART 7816 Error Threshold Register, offset: 0x1E
  774. TL7816 : byte; // *< UART 7816 Transmit Length Register, offset: 0x1F
  775. RESERVED_2 : array[0..0] of byte;
  776. C6 : byte; // *< UART CEA709.1-B Control Register 6, offset: 0x21
  777. PCTH : byte; // *< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22
  778. PCTL : byte; // *< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23
  779. B1T : byte; // *< UART CEA709.1-B Beta1 Timer, offset: 0x24
  780. SDTH : byte; // *< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25
  781. SDTL : byte; // *< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26
  782. PRE : byte; // *< UART CEA709.1-B Preamble, offset: 0x27
  783. TPL : byte; // *< UART CEA709.1-B Transmit Packet Length, offset: 0x28
  784. IE : byte; // *< UART CEA709.1-B Interrupt Enable Register, offset: 0x29
  785. WB : byte; // *< UART CEA709.1-B WBASE, offset: 0x2A
  786. S3 : byte; // *< UART CEA709.1-B Status Register, offset: 0x2B
  787. S4 : byte; // *< UART CEA709.1-B Status Register, offset: 0x2C
  788. RPL : byte; // *< UART CEA709.1-B Received Packet Length, offset: 0x2D
  789. RPREL : byte; // *< UART CEA709.1-B Received Preamble Length, offset: 0x2E
  790. CPW : byte; // *< UART CEA709.1-B Collision Pulse Width, offset: 0x2F
  791. RIDT : byte; // *< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30
  792. TIDT : byte; // *< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31
  793. end;
  794. const
  795. UART0_BASE = $4006A000;
  796. var
  797. UART0 : TUART_Registers absolute UART0_BASE;
  798. const
  799. UART1_BASE = $4006B000;
  800. var
  801. UART1 : TUART_Registers absolute UART1_BASE;
  802. const
  803. UART2_BASE = $4006C000;
  804. var
  805. UART2 : TUART_Registers absolute UART2_BASE;
  806. type
  807. TUSB_ENDPOINT = record
  808. ENDPT : byte; // *< Endpoint Control Register, array offset: 0xC0, array step: 0x4
  809. RESERVED_0 : array[0..2] of byte;
  810. end;
  811. TUSB_Registers = record
  812. PERID : byte; // *< Peripheral ID Register, offset: 0x0
  813. RESERVED_0 : array[0..2] of byte;
  814. IDCOMP : byte; // *< Peripheral ID Complement Register, offset: 0x4
  815. RESERVED_1 : array[0..2] of byte;
  816. REV : byte; // *< Peripheral Revision Register, offset: 0x8
  817. RESERVED_2 : array[0..2] of byte;
  818. ADDINFO : byte; // *< Peripheral Additional Info Register, offset: 0xC
  819. RESERVED_3 : array[0..2] of byte;
  820. OTGISTAT : byte; // *< OTG Interrupt Status Register, offset: 0x10
  821. RESERVED_4 : array[0..2] of byte;
  822. OTGICR : byte; // *< OTG Interrupt Control Register, offset: 0x14
  823. RESERVED_5 : array[0..2] of byte;
  824. OTGSTAT : byte; // *< OTG Status Register, offset: 0x18
  825. RESERVED_6 : array[0..2] of byte;
  826. OTGCTL : byte; // *< OTG Control Register, offset: 0x1C
  827. RESERVED_7 : array[0..98] of byte;
  828. ISTAT : byte; // *< Interrupt Status Register, offset: 0x80
  829. RESERVED_8 : array[0..2] of byte;
  830. INTEN : byte; // *< Interrupt Enable Register, offset: 0x84
  831. RESERVED_9 : array[0..2] of byte;
  832. ERRSTAT : byte; // *< Error Interrupt Status Register, offset: 0x88
  833. RESERVED_10 : array[0..2] of byte;
  834. ERREN : byte; // *< Error Interrupt Enable Register, offset: 0x8C
  835. RESERVED_11 : array[0..2] of byte;
  836. STAT : byte; // *< Status Register, offset: 0x90
  837. RESERVED_12 : array[0..2] of byte;
  838. CTL : byte; // *< Control Register, offset: 0x94
  839. RESERVED_13 : array[0..2] of byte;
  840. ADDR : byte; // *< Address Register, offset: 0x98
  841. RESERVED_14 : array[0..2] of byte;
  842. BDTPAGE1 : byte; // *< BDT Page Register 1, offset: 0x9C
  843. RESERVED_15 : array[0..2] of byte;
  844. FRMNUML : byte; // *< Frame Number Register Low, offset: 0xA0
  845. RESERVED_16 : array[0..2] of byte;
  846. FRMNUMH : byte; // *< Frame Number Register High, offset: 0xA4
  847. RESERVED_17 : array[0..2] of byte;
  848. TOKEN : byte; // *< Token Register, offset: 0xA8
  849. RESERVED_18 : array[0..2] of byte;
  850. SOFTHLD : byte; // *< SOF Threshold Register, offset: 0xAC
  851. RESERVED_19 : array[0..2] of byte;
  852. BDTPAGE2 : byte; // *< BDT Page Register 2, offset: 0xB0
  853. RESERVED_20 : array[0..2] of byte;
  854. BDTPAGE3 : byte; // *< BDT Page Register 3, offset: 0xB4
  855. RESERVED_21 : array[0..10] of byte;
  856. ENDPOINT : array[0..15] of TUSB_ENDPOINT;
  857. USBCTRL : byte; // *< USB Control Register, offset: 0x100
  858. RESERVED_22 : array[0..2] of byte;
  859. OBSERVE : byte; // *< USB OTG Observe Register, offset: 0x104
  860. RESERVED_23 : array[0..2] of byte;
  861. CONTROL : byte; // *< USB OTG Control Register, offset: 0x108
  862. RESERVED_24 : array[0..2] of byte;
  863. USBTRC0 : byte; // *< USB Transceiver Control Register 0, offset: 0x10C
  864. RESERVED_25 : array[0..6] of byte;
  865. USBFRMADJUST : byte; // *< Frame Adjust Register, offset: 0x114
  866. end;
  867. const
  868. USB0_BASE = $40072000;
  869. var
  870. USB0 : TUSB_Registers absolute USB0_BASE;
  871. type
  872. TUSBDCD_Registers = record
  873. CONTROL : longword; // *< Control Register, offset: 0x0
  874. CLOCK : longword; // *< Clock Register, offset: 0x4
  875. STATUS : longword; // *< Status Register, offset: 0x8
  876. RESERVED_0 : array[0..3] of byte;
  877. TIMER0 : longword; // *< TIMER0 Register, offset: 0x10
  878. TIMER1 : longword; // *< , offset: 0x14
  879. TIMER2 : longword; // *< , offset: 0x18
  880. end;
  881. const
  882. USBDCD_BASE = $40035000;
  883. var
  884. USBDCD : TUSBDCD_Registers absolute USBDCD_BASE;
  885. type
  886. TVREF_Registers = record
  887. TRM : byte; // *< VREF Trim Register, offset: 0x0
  888. SC : byte; // *< VREF Status and Control Register, offset: 0x1
  889. end;
  890. const
  891. VREF_BASE = $40074000;
  892. var
  893. VREF : TVREF_Registers absolute VREF_BASE;
  894. type
  895. TWDOG_Registers = record
  896. STCTRLH : word; // *< Watchdog Status and Control Register High, offset: 0x0
  897. STCTRLL : word; // *< Watchdog Status and Control Register Low, offset: 0x2
  898. TOVALH : word; // *< Watchdog Time-out Value Register High, offset: 0x4
  899. TOVALL : word; // *< Watchdog Time-out Value Register Low, offset: 0x6
  900. WINH : word; // *< Watchdog Window Register High, offset: 0x8
  901. WINL : word; // *< Watchdog Window Register Low, offset: 0xA
  902. REFRESH : word; // *< Watchdog Refresh Register, offset: 0xC
  903. UNLOCK : word; // *< Watchdog Unlock Register, offset: 0xE
  904. TMROUTH : word; // *< Watchdog Timer Output Register High, offset: 0x10
  905. TMROUTL : word; // *< Watchdog Timer Output Register Low, offset: 0x12
  906. RSTCNT : word; // *< Watchdog Reset Count Register, offset: 0x14
  907. PRESC : word; // *< Watchdog Prescaler Register, offset: 0x16
  908. end;
  909. const
  910. WDOG_BASE = $40052000;
  911. var
  912. WDOG : TWDOG_Registers absolute WDOG_BASE;
  913. implementation
  914. procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
  915. procedure MemoryManagement_interrupt; external name 'MemoryManagement_interrupt';
  916. procedure BusFault_interrupt; external name 'BusFault_interrupt';
  917. procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
  918. procedure SVCall_interrupt; external name 'SVCall_interrupt';
  919. procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
  920. procedure PendSV_interrupt; external name 'PendSV_interrupt';
  921. procedure SysTick_interrupt; external name 'SysTick_interrupt';
  922. procedure DMA0_interrupt; external name 'DMA0_interrupt';
  923. procedure DMA1_interrupt; external name 'DMA1_interrupt';
  924. procedure DMA2_interrupt; external name 'DMA2_interrupt';
  925. procedure DMA3_interrupt; external name 'DMA3_interrupt';
  926. procedure DMA_Error_interrupt; external name 'DMA_Error_interrupt';
  927. procedure RESERVED21_interrupt; external name 'RESERVED21_interrupt';
  928. procedure FTFL_interrupt; external name 'FTFL_interrupt';
  929. procedure Read_Collision_interrupt; external name 'Read_Collision_interrupt';
  930. procedure LVD_LVW_interrupt; external name 'LVD_LVW_interrupt';
  931. procedure LLW_interrupt; external name 'LLW_interrupt';
  932. procedure Watchdog_interrupt; external name 'Watchdog_interrupt';
  933. procedure I2C0_interrupt; external name 'I2C0_interrupt';
  934. procedure SPI0_interrupt; external name 'SPI0_interrupt';
  935. procedure I2S0_Tx_interrupt; external name 'I2S0_Tx_interrupt';
  936. procedure I2S0_Rx_interrupt; external name 'I2S0_Rx_interrupt';
  937. procedure UART0_LON_interrupt; external name 'UART0_LON_interrupt';
  938. procedure UART0_RX_TX_interrupt; external name 'UART0_RX_TX_interrupt';
  939. procedure UART0_ERR_interrupt; external name 'UART0_ERR_interrupt';
  940. procedure UART1_RX_TX_interrupt; external name 'UART1_RX_TX_interrupt';
  941. procedure UART1_ERR_interrupt; external name 'UART1_ERR_interrupt';
  942. procedure UART2_RX_TX_interrupt; external name 'UART2_RX_TX_interrupt';
  943. procedure UART2_ERR_interrupt; external name 'UART2_ERR_interrupt';
  944. procedure ADC0_interrupt; external name 'ADC0_interrupt';
  945. procedure CMP0_interrupt; external name 'CMP0_interrupt';
  946. procedure CMP1_interrupt; external name 'CMP1_interrupt';
  947. procedure FTM0_interrupt; external name 'FTM0_interrupt';
  948. procedure FTM1_interrupt; external name 'FTM1_interrupt';
  949. procedure CMT_interrupt; external name 'CMT_interrupt';
  950. procedure RTC_interrupt; external name 'RTC_interrupt';
  951. procedure RTC_Seconds_interrupt; external name 'RTC_Seconds_interrupt';
  952. procedure PIT0_interrupt; external name 'PIT0_interrupt';
  953. procedure PIT1_interrupt; external name 'PIT1_interrupt';
  954. procedure PIT2_interrupt; external name 'PIT2_interrupt';
  955. procedure PIT3_interrupt; external name 'PIT3_interrupt';
  956. procedure PDB0_interrupt; external name 'PDB0_interrupt';
  957. procedure USB0_interrupt; external name 'USB0_interrupt';
  958. procedure USBDCD_interrupt; external name 'USBDCD_interrupt';
  959. procedure TSI0_interrupt; external name 'TSI0_interrupt';
  960. procedure MCG_interrupt; external name 'MCG_interrupt';
  961. procedure LPTimer_interrupt; external name 'LPTimer_interrupt';
  962. procedure PORTA_interrupt; external name 'PORTA_interrupt';
  963. procedure PORTB_interrupt; external name 'PORTB_interrupt';
  964. procedure PORTC_interrupt; external name 'PORTC_interrupt';
  965. procedure PORTD_interrupt; external name 'PORTD_interrupt';
  966. procedure PORTE_interrupt; external name 'PORTE_interrupt';
  967. procedure SWI_interrupt; external name 'SWI_interrupt';
  968. {$i cortexm4f_start.inc}
  969. procedure FlashConfiguration; assembler; nostackframe;
  970. label flash_conf;
  971. asm
  972. .section ".flash_config.flash_conf"
  973. flash_conf:
  974. .byte 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF
  975. .text
  976. end;
  977. procedure LowLevelStartup; assembler; nostackframe; [public, alias: '_LOWLEVELSTART'];
  978. asm
  979. // Unlock watchdog
  980. ldr r0, .LWDOG_BASE
  981. movw r1, #50464
  982. strh r1, [r0, #0xE]
  983. movw r1, #55592
  984. strh r1, [r0, #0xE]
  985. nop
  986. nop
  987. // Disable watchdog for now
  988. movs r1, #0
  989. strh r1, [r0, #0]
  990. b Startup
  991. .LWDOG_BASE:
  992. .long 0x40052000
  993. end;
  994. procedure Vectors; assembler; nostackframe;
  995. label interrupt_vectors;
  996. asm
  997. .section ".init.interrupt_vectors"
  998. interrupt_vectors:
  999. .long _stack_top
  1000. .long LowLevelStartup
  1001. .long NonMaskableInt_interrupt
  1002. .long 0
  1003. .long MemoryManagement_interrupt
  1004. .long BusFault_interrupt
  1005. .long UsageFault_interrupt
  1006. .long 0
  1007. .long 0
  1008. .long 0
  1009. .long 0
  1010. .long SVCall_interrupt
  1011. .long DebugMonitor_interrupt
  1012. .long 0
  1013. .long PendSV_interrupt
  1014. .long SysTick_interrupt
  1015. .long DMA0_interrupt
  1016. .long DMA1_interrupt
  1017. .long DMA2_interrupt
  1018. .long DMA3_interrupt
  1019. .long DMA_Error_interrupt
  1020. .long RESERVED21_interrupt
  1021. .long FTFL_interrupt
  1022. .long Read_Collision_interrupt
  1023. .long LVD_LVW_interrupt
  1024. .long LLW_interrupt
  1025. .long Watchdog_interrupt
  1026. .long I2C0_interrupt
  1027. .long SPI0_interrupt
  1028. .long I2S0_Tx_interrupt
  1029. .long I2S0_Rx_interrupt
  1030. .long UART0_LON_interrupt
  1031. .long UART0_RX_TX_interrupt
  1032. .long UART0_ERR_interrupt
  1033. .long UART1_RX_TX_interrupt
  1034. .long UART1_ERR_interrupt
  1035. .long UART2_RX_TX_interrupt
  1036. .long UART2_ERR_interrupt
  1037. .long ADC0_interrupt
  1038. .long CMP0_interrupt
  1039. .long CMP1_interrupt
  1040. .long FTM0_interrupt
  1041. .long FTM1_interrupt
  1042. .long CMT_interrupt
  1043. .long RTC_interrupt
  1044. .long RTC_Seconds_interrupt
  1045. .long PIT0_interrupt
  1046. .long PIT1_interrupt
  1047. .long PIT2_interrupt
  1048. .long PIT3_interrupt
  1049. .long PDB0_interrupt
  1050. .long USB0_interrupt
  1051. .long USBDCD_interrupt
  1052. .long TSI0_interrupt
  1053. .long MCG_interrupt
  1054. .long LPTimer_interrupt
  1055. .long PORTA_interrupt
  1056. .long PORTB_interrupt
  1057. .long PORTC_interrupt
  1058. .long PORTD_interrupt
  1059. .long PORTE_interrupt
  1060. .long SWI_interrupt
  1061. .weak NonMaskableInt_interrupt
  1062. .weak MemoryManagement_interrupt
  1063. .weak BusFault_interrupt
  1064. .weak UsageFault_interrupt
  1065. .weak SVCall_interrupt
  1066. .weak DebugMonitor_interrupt
  1067. .weak PendSV_interrupt
  1068. .weak SysTick_interrupt
  1069. .weak DMA0_interrupt
  1070. .weak DMA1_interrupt
  1071. .weak DMA2_interrupt
  1072. .weak DMA3_interrupt
  1073. .weak DMA_Error_interrupt
  1074. .weak RESERVED21_interrupt
  1075. .weak FTFL_interrupt
  1076. .weak Read_Collision_interrupt
  1077. .weak LVD_LVW_interrupt
  1078. .weak LLW_interrupt
  1079. .weak Watchdog_interrupt
  1080. .weak I2C0_interrupt
  1081. .weak SPI0_interrupt
  1082. .weak I2S0_Tx_interrupt
  1083. .weak I2S0_Rx_interrupt
  1084. .weak UART0_LON_interrupt
  1085. .weak UART0_RX_TX_interrupt
  1086. .weak UART0_ERR_interrupt
  1087. .weak UART1_RX_TX_interrupt
  1088. .weak UART1_ERR_interrupt
  1089. .weak UART2_RX_TX_interrupt
  1090. .weak UART2_ERR_interrupt
  1091. .weak ADC0_interrupt
  1092. .weak CMP0_interrupt
  1093. .weak CMP1_interrupt
  1094. .weak FTM0_interrupt
  1095. .weak FTM1_interrupt
  1096. .weak CMT_interrupt
  1097. .weak RTC_interrupt
  1098. .weak RTC_Seconds_interrupt
  1099. .weak PIT0_interrupt
  1100. .weak PIT1_interrupt
  1101. .weak PIT2_interrupt
  1102. .weak PIT3_interrupt
  1103. .weak PDB0_interrupt
  1104. .weak USB0_interrupt
  1105. .weak USBDCD_interrupt
  1106. .weak TSI0_interrupt
  1107. .weak MCG_interrupt
  1108. .weak LPTimer_interrupt
  1109. .weak PORTA_interrupt
  1110. .weak PORTB_interrupt
  1111. .weak PORTC_interrupt
  1112. .weak PORTD_interrupt
  1113. .weak PORTE_interrupt
  1114. .weak SWI_interrupt
  1115. .set NonMaskableInt_interrupt, HaltProc
  1116. .set MemoryManagement_interrupt, HaltProc
  1117. .set BusFault_interrupt, HaltProc
  1118. .set UsageFault_interrupt, HaltProc
  1119. .set SVCall_interrupt, HaltProc
  1120. .set DebugMonitor_interrupt, HaltProc
  1121. .set PendSV_interrupt, HaltProc
  1122. .set SysTick_interrupt, HaltProc
  1123. .set DMA0_interrupt, HaltProc
  1124. .set DMA1_interrupt, HaltProc
  1125. .set DMA2_interrupt, HaltProc
  1126. .set DMA3_interrupt, HaltProc
  1127. .set DMA_Error_interrupt, HaltProc
  1128. .set RESERVED21_interrupt, HaltProc
  1129. .set FTFL_interrupt, HaltProc
  1130. .set Read_Collision_interrupt, HaltProc
  1131. .set LVD_LVW_interrupt, HaltProc
  1132. .set LLW_interrupt, HaltProc
  1133. .set Watchdog_interrupt, HaltProc
  1134. .set I2C0_interrupt, HaltProc
  1135. .set SPI0_interrupt, HaltProc
  1136. .set I2S0_Tx_interrupt, HaltProc
  1137. .set I2S0_Rx_interrupt, HaltProc
  1138. .set UART0_LON_interrupt, HaltProc
  1139. .set UART0_RX_TX_interrupt, HaltProc
  1140. .set UART0_ERR_interrupt, HaltProc
  1141. .set UART1_RX_TX_interrupt, HaltProc
  1142. .set UART1_ERR_interrupt, HaltProc
  1143. .set UART2_RX_TX_interrupt, HaltProc
  1144. .set UART2_ERR_interrupt, HaltProc
  1145. .set ADC0_interrupt, HaltProc
  1146. .set CMP0_interrupt, HaltProc
  1147. .set CMP1_interrupt, HaltProc
  1148. .set FTM0_interrupt, HaltProc
  1149. .set FTM1_interrupt, HaltProc
  1150. .set CMT_interrupt, HaltProc
  1151. .set RTC_interrupt, HaltProc
  1152. .set RTC_Seconds_interrupt, HaltProc
  1153. .set PIT0_interrupt, HaltProc
  1154. .set PIT1_interrupt, HaltProc
  1155. .set PIT2_interrupt, HaltProc
  1156. .set PIT3_interrupt, HaltProc
  1157. .set PDB0_interrupt, HaltProc
  1158. .set USB0_interrupt, HaltProc
  1159. .set USBDCD_interrupt, HaltProc
  1160. .set TSI0_interrupt, HaltProc
  1161. .set MCG_interrupt, HaltProc
  1162. .set LPTimer_interrupt, HaltProc
  1163. .set PORTA_interrupt, HaltProc
  1164. .set PORTB_interrupt, HaltProc
  1165. .set PORTC_interrupt, HaltProc
  1166. .set PORTD_interrupt, HaltProc
  1167. .set PORTE_interrupt, HaltProc
  1168. .set SWI_interrupt, HaltProc
  1169. .text
  1170. end;
  1171. end.